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 132 <a href="#nested-classes">Data Structures</a>  </div>
 133   <div class="headertitle"><div class="title">Auxiliary Control Register (ACTLR)<div class="ingroups"><a class="el" href="group__CMSIS__core__register.html">Core Register Access</a></div></div></div>
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 136
 137 <p>The ACTLR provides IMPLEMENTATION DEFINED configuration and control options.
 138 <a href="#details">More...</a></p>
 139 <table class="memberdecls">
 140 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="groups" name="groups"></a>
 141 Content</h2></td></tr>
 142 <tr class="memitem:group__CMSIS__ACTLR__BITS"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html">ACTLR Bits</a></td></tr>
 143 <tr class="memdesc:group__CMSIS__ACTLR__BITS"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit position and mask macros. <br /></td></tr>
 144 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
 145 </table><table class="memberdecls">
 146 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="nested-classes" name="nested-classes"></a>
 147 Data Structures</h2></td></tr>
 148 <tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structACTLR__Type.html">ACTLR_Type</a></td></tr>
 149 <tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit field declaration for ACTLR layout.  <a href="structACTLR__Type.html#details">More...</a><br /></td></tr>
 150 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
 151 </table>
 152 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
 153 <p>The ACTLR characteristics are differs between various Armv7-A implementations.</p>
 154 <p><b>Cortex-A5</b></p>
 155 <table class="markdownTable">
 156 <tr class="markdownTableHead">
 157 <th class="markdownTableHeadLeft">Bits   </th><th class="markdownTableHeadLeft">Name   </th><th class="markdownTableHeadLeft">Function    </th></tr>
 158 <tr class="markdownTableRowOdd">
 159 <td class="markdownTableBodyLeft">[31:29]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
 160 <tr class="markdownTableRowEven">
 161 <td class="markdownTableBodyLeft">[28]   </td><td class="markdownTableBodyLeft">DBDI   </td><td class="markdownTableBodyLeft">Disable Branch Dual Issue    </td></tr>
 162 <tr class="markdownTableRowOdd">
 163 <td class="markdownTableBodyLeft">[27:19]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
 164 <tr class="markdownTableRowEven">
 165 <td class="markdownTableBodyLeft">[18]   </td><td class="markdownTableBodyLeft">BTDIS   </td><td class="markdownTableBodyLeft">Disable indirect Branch Target Address Cache (BTAC).    </td></tr>
 166 <tr class="markdownTableRowOdd">
 167 <td class="markdownTableBodyLeft">[17]   </td><td class="markdownTableBodyLeft">RSDIS   </td><td class="markdownTableBodyLeft">Disable return stack operation.    </td></tr>
 168 <tr class="markdownTableRowEven">
 169 <td class="markdownTableBodyLeft">[16:15]   </td><td class="markdownTableBodyLeft">BP   </td><td class="markdownTableBodyLeft">Branch prediction policy.    </td></tr>
 170 <tr class="markdownTableRowOdd">
 171 <td class="markdownTableBodyLeft">[14:13]   </td><td class="markdownTableBodyLeft">L1PCTL   </td><td class="markdownTableBodyLeft">L1 Data prefetch control.    </td></tr>
 172 <tr class="markdownTableRowEven">
 173 <td class="markdownTableBodyLeft">[12]   </td><td class="markdownTableBodyLeft">RADIS   </td><td class="markdownTableBodyLeft">Disable Data Cache read-allocate mode.    </td></tr>
 174 <tr class="markdownTableRowOdd">
 175 <td class="markdownTableBodyLeft">[11]   </td><td class="markdownTableBodyLeft">DWBST   </td><td class="markdownTableBodyLeft">Disable AXI data write bursts to Normal memory.    </td></tr>
 176 <tr class="markdownTableRowEven">
 177 <td class="markdownTableBodyLeft">[10]   </td><td class="markdownTableBodyLeft">DODMBS   </td><td class="markdownTableBodyLeft">Disable optimized data memory barrier behavior.    </td></tr>
 178 <tr class="markdownTableRowOdd">
 179 <td class="markdownTableBodyLeft">[9:8]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
 180 <tr class="markdownTableRowEven">
 181 <td class="markdownTableBodyLeft">[7]   </td><td class="markdownTableBodyLeft">EXCL   </td><td class="markdownTableBodyLeft">Exclusive L1/L2 cache control.    </td></tr>
 182 <tr class="markdownTableRowOdd">
 183 <td class="markdownTableBodyLeft">[6]   </td><td class="markdownTableBodyLeft">SMP   </td><td class="markdownTableBodyLeft">Enables coherent requests to the processor.    </td></tr>
 184 <tr class="markdownTableRowEven">
 185 <td class="markdownTableBodyLeft">[5:1]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
 186 <tr class="markdownTableRowOdd">
 187 <td class="markdownTableBodyLeft">[0]   </td><td class="markdownTableBodyLeft">FW   </td><td class="markdownTableBodyLeft">Cache and TLB maintenance broadcast.   </td></tr>
 188 </table>
 189 <p><b>Cortex-A7</b></p>
 190 <table class="markdownTable">
 191 <tr class="markdownTableHead">
 192 <th class="markdownTableHeadLeft">Bits   </th><th class="markdownTableHeadLeft">Name   </th><th class="markdownTableHeadLeft">Function    </th></tr>
 193 <tr class="markdownTableRowOdd">
 194 <td class="markdownTableBodyLeft">[31:29]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
 195 <tr class="markdownTableRowEven">
 196 <td class="markdownTableBodyLeft">[28]   </td><td class="markdownTableBodyLeft">DDI   </td><td class="markdownTableBodyLeft">Disable Dual Issue    </td></tr>
 197 <tr class="markdownTableRowOdd">
 198 <td class="markdownTableBodyLeft">[27:16]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
 199 <tr class="markdownTableRowEven">
 200 <td class="markdownTableBodyLeft">[15]   </td><td class="markdownTableBodyLeft">DDVM   </td><td class="markdownTableBodyLeft">Disable Distributed Virtual Memory transactions.    </td></tr>
 201 <tr class="markdownTableRowOdd">
 202 <td class="markdownTableBodyLeft">[14:13]   </td><td class="markdownTableBodyLeft">L1PCTL   </td><td class="markdownTableBodyLeft">L1 Data prefetch control.    </td></tr>
 203 <tr class="markdownTableRowEven">
 204 <td class="markdownTableBodyLeft">[12]   </td><td class="markdownTableBodyLeft">L1RADIS   </td><td class="markdownTableBodyLeft">L1 Data Cache read-allocate mode disable.    </td></tr>
 205 <tr class="markdownTableRowOdd">
 206 <td class="markdownTableBodyLeft">[11]   </td><td class="markdownTableBodyLeft">L2RADIS   </td><td class="markdownTableBodyLeft">L2 Data Cache read-allocate mode disable.    </td></tr>
 207 <tr class="markdownTableRowEven">
 208 <td class="markdownTableBodyLeft">[10]   </td><td class="markdownTableBodyLeft">DODMBS   </td><td class="markdownTableBodyLeft">Disable optimized data memory barrier behavior.    </td></tr>
 209 <tr class="markdownTableRowOdd">
 210 <td class="markdownTableBodyLeft">[9:7]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
 211 <tr class="markdownTableRowEven">
 212 <td class="markdownTableBodyLeft">[6]   </td><td class="markdownTableBodyLeft">SMP   </td><td class="markdownTableBodyLeft">Enables coherent requests to the processor.    </td></tr>
 213 <tr class="markdownTableRowOdd">
 214 <td class="markdownTableBodyLeft">[5:0]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.   </td></tr>
 215 </table>
 216 <p><b>Cortex-A9</b></p>
 217 <table class="markdownTable">
 218 <tr class="markdownTableHead">
 219 <th class="markdownTableHeadLeft">Bits   </th><th class="markdownTableHeadLeft">Name   </th><th class="markdownTableHeadLeft">Function    </th></tr>
 220 <tr class="markdownTableRowOdd">
 221 <td class="markdownTableBodyLeft">[31:10]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
 222 <tr class="markdownTableRowEven">
 223 <td class="markdownTableBodyLeft">[9]   </td><td class="markdownTableBodyLeft">PARITY   </td><td class="markdownTableBodyLeft">Support for parity checking, if implemented.    </td></tr>
 224 <tr class="markdownTableRowOdd">
 225 <td class="markdownTableBodyLeft">[8]   </td><td class="markdownTableBodyLeft">AOW   </td><td class="markdownTableBodyLeft">Enable allocation in one cache way only.    </td></tr>
 226 <tr class="markdownTableRowEven">
 227 <td class="markdownTableBodyLeft">[7]   </td><td class="markdownTableBodyLeft">EXCL   </td><td class="markdownTableBodyLeft">Exclusive L1/L2 cache control.    </td></tr>
 228 <tr class="markdownTableRowOdd">
 229 <td class="markdownTableBodyLeft">[6]   </td><td class="markdownTableBodyLeft">SMP   </td><td class="markdownTableBodyLeft">Enables coherent requests to the processor.    </td></tr>
 230 <tr class="markdownTableRowEven">
 231 <td class="markdownTableBodyLeft">[5:4]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
 232 <tr class="markdownTableRowOdd">
 233 <td class="markdownTableBodyLeft">[3]   </td><td class="markdownTableBodyLeft">WFLZM   </td><td class="markdownTableBodyLeft">Enable write full line of zeros modea.    </td></tr>
 234 <tr class="markdownTableRowEven">
 235 <td class="markdownTableBodyLeft">[2]   </td><td class="markdownTableBodyLeft">L1PE   </td><td class="markdownTableBodyLeft">Dside prefetch.    </td></tr>
 236 <tr class="markdownTableRowOdd">
 237 <td class="markdownTableBodyLeft">[1]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
 238 <tr class="markdownTableRowEven">
 239 <td class="markdownTableBodyLeft">[0]   </td><td class="markdownTableBodyLeft">FW   </td><td class="markdownTableBodyLeft">Cache and TLB maintenance broadcast.   </td></tr>
 240 </table>
 241 <p>Consider using __get_ACTLR and __set_ACTRL to access ACTRL register. </p>
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