2 # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
3 #----------------------------------------------------------------------------------------------
4 armcortexm7ct.vfp-present=0 # (bool , init-time) default = '1' : Set whether the model has VFP support
5 armcortexm7ct.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
6 armcortexm7ct.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF]
7 armcortexm7ct.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls
8 armcortexm7ct.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF]
9 armcortexm7ct.semihosting-heap_limit=0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]
10 armcortexm7ct.semihosting-stack_base=0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]
11 armcortexm7ct.semihosting-stack_limit=0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]
12 armcortexm7ct.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access.
13 armcortexm7ct.NUM_MPU_REGION=0x10 # (int , init-time) default = '0x10' : Number of MPU regions : [0x0..0x10]
14 armcortexm7ct.NUM_IRQ=0x20 # (int , init-time) default = '0x20' : Number of user interrupts : [0x1..0xF0]
15 armcortexm7ct.TRC=1 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included
16 armcortexm7ct.LVL_WIDTH=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8]
17 armcortexm7ct.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode
18 armcortexm7ct.INITVTOR=0x0 # (int , init-time) default = '0x0' : vector-table offset at reset : [0x0..0xFFFFFF80]
19 armcortexm7ct.min_sync_level=0x0 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
20 armcortexm7ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
21 armcortexm7ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
22 armcortexm7ct.master_id=0x0 # (int , init-time) default = '0x0' : Master ID presented in bus transactions : [0x0..0xFFFFFFFF]
23 armcortexm7ct.DP_FLOAT=1 # (bool , init-time) default = '1' : Support 8-byte floats
24 armcortexm7ct.scheduler_mode=0x0 # (int , init-time) default = '0x0' : Control the interleaving of instructions in this processor (0=default long quantum, 1=low latency mode, short quantum and signal checking, 2=lock-breaking mode, long quantum with additional context switches near load-exclusive instructions, 3=ISSCompare) : [0x0..0x3]
25 armcortexm7ct.has_writebuffer=0 # (bool , init-time) default = '0' : Implement write accesses buffering before L1 cache. May affect ext_abort behaviour.
26 armcortexm7ct.dcache-size=0x8000 # (int , init-time) default = '0x8000' : L1 D-cache size in bytes : [0x0..0x100000]
27 armcortexm7ct.dcache-ways=0x4 # (int , init-time) default = '0x4' : L1 D-cache ways (sets are implicit from size) : [0x1..0x40]
28 armcortexm7ct.icache-size=0x8000 # (int , init-time) default = '0x8000' : L1 I-cache size in bytes : [0x0..0x100000]
29 armcortexm7ct.icache-ways=0x2 # (int , init-time) default = '0x2' : L1 I-cache ways (sets are implicit from size) : [0x1..0x40]
30 armcortexm7ct.itcm_size=0x100 # (int , init-time) default = '0x100' : ITCM size in KB : [0x0..0x4000]
31 armcortexm7ct.dtcm_size=0x100 # (int , init-time) default = '0x100' : DTCM size in KB : [0x0..0x4000]
32 armcortexm7ct.itcm_enable=0 # (bool , init-time) default = '0' : Enable ITCM at reset
33 armcortexm7ct.dtcm_enable=0 # (bool , init-time) default = '0' : Enable DTCM at reset
34 armcortexm7ct.duplicate_CADI_TCM_writes=0 # (bool , init-time) default = '0' : CADI writes to TCMs are also sent to downstream memory at same addresses (for validation platforms)
35 armcortexm7ct.dcache-state_modelled=0 # (bool , run-time ) default = '0' : Set whether D-cache has stateful implementation
36 armcortexm7ct.icache-state_modelled=0 # (bool , run-time ) default = '0' : Set whether I-cache has stateful implementation
37 armcortexm7ct.DBGLVL=0x1 # (int , init-time) default = '0x1' : 0: 2 DWT, 4 FPB; 1: 4 DWT, 8 FPB comparators : [0x0..0x1]
38 armcortexm7ct.WIC=1 # (bool , init-time) default = '1' : Include support for WIC-mode deep sleep
39 fvp_mps2.SCC_ID.Variant=0x0 # (int , init-time) default = '0x0' : SCC_ID[23:20], X in the FGPA version 'rXpY' : [0x0..0xF]
40 fvp_mps2.SCC_ID.Revision=0x1 # (int , init-time) default = '0x1' : SCC_ID[3:0], Y in the FGPA version 'rXpY' : [0x0..0xF]
41 fvp_mps2.iotss_systemcontrol.cpu0wait=0 # (bool , init-time) default = '0' : Whether to hold cpu0 in reset at boot
42 fvp_mps2.iotss_systemcontrol.cpu1wait=1 # (bool , init-time) default = '1' : Whether to hold cpu1 in reset at boot
43 fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:Original MPS2 ; 1:IoT Kit (cut-down SSE-200) ; 2:Full SSE-200 : [0x0..0x2]
44 fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb
45 fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '1' : Disable Memory gating logic
46 fvp_mps2.NSC_CFG_0=0 # (bool , init-time) default = '0' : Whether 0x10000000..0x1FFFFFFF is non-secure-callable
47 fvp_mps2.NSC_CFG_1=0 # (bool , init-time) default = '0' : Whether 0x30000000..0x3FFFFFFF is non-secure-callable
48 fvp_mps2.APBPPCEXP_DIS0=0x0 # (int , init-time) default = '0x0' : Disables support for individual bits on the APBNSPPCEXP0 and APBPPPCEXP0 buses : [0x0..0xFFFF]
49 fvp_mps2.APBPPCEXP_DIS1=0x0 # (int , init-time) default = '0x0' : Disables support for individual bits on the APBNSPPCEXP1 and APBPPPCEXP1 buses : [0x0..0xFFFF]
50 fvp_mps2.APBPPCEXP_DIS2=0x0 # (int , init-time) default = '0x0' : Disables support for individual bits on the APBNSPPCEXP2 and APBPPPCEXP2 buses : [0x0..0xFFFF]
51 fvp_mps2.APBPPCEXP_DIS3=0x0 # (int , init-time) default = '0x0' : Disables support for individual bits on the APBNSPPCEXP3 and APBPPPCEXP3 buses : [0x0..0xFFFF]
52 fvp_mps2.AHBPPCEXP_DIS0=0x0 # (int , init-time) default = '0x0' : Disables support for individual bits on the AHBNSPPCEXP0 and AHBPPPCEXP0 buses : [0x0..0xFFFF]
53 fvp_mps2.AHBPPCEXP_DIS1=0x0 # (int , init-time) default = '0x0' : Disables support for individual bits on the AHBNSPPCEXP1 and AHBPPPCEXP1 buses : [0x0..0xFFFF]
54 fvp_mps2.AHBPPCEXP_DIS2=0x0 # (int , init-time) default = '0x0' : Disables support for individual bits on the AHBNSPPCEXP2 and AHBPPPCEXP2 buses : [0x0..0xFFFF]
55 fvp_mps2.AHBPPCEXP_DIS3=0x0 # (int , init-time) default = '0x0' : Disables support for individual bits on the AHBNSPPCEXP3 and AHBPPPCEXP3 buses : [0x0..0xFFFF]
56 fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
57 fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
58 fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
59 fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
60 fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
61 fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
62 fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
63 fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
64 fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
65 fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
66 fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
67 fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
68 fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation.
69 fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation
70 fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name)
71 fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls.
72 fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
73 fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
74 fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
75 fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
76 fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
77 fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
78 fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
79 fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
80 fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
81 fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
82 fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
83 fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
84 fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
85 fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
86 fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
87 fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
88 fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
89 fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
90 fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
91 fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
92 fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
93 fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
94 fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
95 fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
96 fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
97 fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
98 fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
99 fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
100 fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
101 fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
102 fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
103 fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
104 fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
105 fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
106 fvp_mps2.stub0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
107 fvp_mps2.stub1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
108 fvp_mps2.stub_i2c1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
109 fvp_mps2.stub_i2s.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
110 fvp_mps2.stub_spi0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
111 fvp_mps2.stub_spi2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
112 fvp_mps2.expansion_warning_memory.abort_on_reads=0 # (bool , init-time) default = '0' : Abort on reads (read 0 if false)
113 fvp_mps2.expansion_warning_memory.abort_on_writes=0 # (bool , init-time) default = '0' : Abort on writes (ignore if false)
114 fvp_mps2.expansion_warning_memory.read_data=0x0 # (int , init-time) default = '0x0' : Data to return on reads, if not aborting
115 fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled
116 fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:4e:b4" # (string, init-time) default = '00:02:f7:ef:4e:b4' : Host/model MAC address
117 fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode
118 fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface
119 fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking
120 fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking
121 fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking
122 fvp_mps2.sse200.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
123 fvp_mps2.sse200.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
124 fvp_mps2.sse200.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31]
125 fvp_mps2.sse200.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31]
126 fvp_mps2.sse200.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported
127 fvp_mps2.sse200.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported
128 fvp_mps2.sse200.apb_ppc_iotss_subsystem0.NONSEC_MASK=0x0 # (int , init-time) default = '0x0' : 16-bit wide mask for security checking of ports: 0 = check, 1 = mask : [0x0..0x1]
129 fvp_mps2.sse200.apb_ppc_iotss_subsystem0.PORTx_ENABLE=0xFFFF # (int , init-time) default = '0xFFFF' : Enable (1) or disable (0) port x (where x is between 0-15): enable = 1, disable = 0 : [0x0..0xFFFF]
130 fvp_mps2.sse200.apb_ppc_iotss_subsystem1.NONSEC_MASK=0x0 # (int , init-time) default = '0x0' : 16-bit wide mask for security checking of ports: 0 = check, 1 = mask : [0x0..0x1]
131 fvp_mps2.sse200.apb_ppc_iotss_subsystem1.PORTx_ENABLE=0xFFFF # (int , init-time) default = '0xFFFF' : Enable (1) or disable (0) port x (where x is between 0-15): enable = 1, disable = 0 : [0x0..0xFFFF]
132 fvp_mps2.sse200.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
133 fvp_mps2.sse200.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
134 fvp_mps2.sse200.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
135 fvp_mps2.sse200.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
136 fvp_mps2.sse200.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
137 fvp_mps2.sse200.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
138 fvp_mps2.sse200.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
139 fvp_mps2.sse200.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
140 fvp_mps2.sse200.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
141 fvp_mps2.sse200.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
142 fvp_mps2.sse200.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
143 fvp_mps2.sse200.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
144 fvp_mps2.sse200.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
145 fvp_mps2.sse200.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
146 fvp_mps2.sse200.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
147 fvp_mps2.sse200.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
148 fvp_mps2.sse200.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
149 fvp_mps2.sse200.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
150 fvp_mps2.sse200.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
151 fvp_mps2.sse200.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
152 fvp_mps2.sse200.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
153 fvp_mps2.sse200.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
154 fvp_mps2.sse200.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
155 fvp_mps2.sse200.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF]
156 fvp_mps2.sse200.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
157 fvp_mps2.sse200.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
158 fvp_mps2.sse200.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
159 fvp_mps2.sse200.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
160 fvp_mps2.sse200.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
161 fvp_mps2.sse200.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
162 fvp_mps2.sse200.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
163 fvp_mps2.sse200.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
164 fvp_mps2.sse200.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
165 fvp_mps2.sse200.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
166 fvp_mps2.sse200.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
167 fvp_mps2.sse200.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
168 fvp_mps2.sse200.bus_error_warning_memory.read_data=0x0 # (int , init-time) default = '0x0' : Data to return on reads, if not aborting
169 fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component
170 fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
171 fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
172 fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
173 fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
174 fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
175 fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
176 fvp_mps2.mps2_secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31]
177 fvp_mps2.mps2_secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31]
178 fvp_mps2.mps2_secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported
179 fvp_mps2.mps2_secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported
180 fvp_mps2.mps2_secure_control_register_block.APBPPCEXP_DIS0=0x0 # (int , init-time) default = '0x0' : Disables support for individual bits on the APBNSPPCEXP0 and APBPPPCEXP0 buses : [0x0..0xFFFF]
181 fvp_mps2.mps2_secure_control_register_block.APBPPCEXP_DIS1=0x0 # (int , init-time) default = '0x0' : Disables support for individual bits on the APBNSPPCEXP1 and APBPPPCEXP1 buses : [0x0..0xFFFF]
182 fvp_mps2.mps2_secure_control_register_block.APBPPCEXP_DIS2=0x0 # (int , init-time) default = '0x0' : Disables support for individual bits on the APBNSPPCEXP2 and APBPPPCEXP2 buses : [0x0..0xFFFF]
183 fvp_mps2.mps2_secure_control_register_block.APBPPCEXP_DIS3=0x0 # (int , init-time) default = '0x0' : Disables support for individual bits on the APBNSPPCEXP3 and APBPPPCEXP3 buses : [0x0..0xFFFF]
184 fvp_mps2.mps2_secure_control_register_block.AHBPPCEXP_DIS0=0x0 # (int , init-time) default = '0x0' : Disables support for individual bits on the AHBNSPPCEXP0 and AHBPPPCEXP0 buses : [0x0..0xFFFF]
185 fvp_mps2.mps2_secure_control_register_block.AHBPPCEXP_DIS1=0x0 # (int , init-time) default = '0x0' : Disables support for individual bits on the AHBNSPPCEXP1 and AHBPPPCEXP1 buses : [0x0..0xFFFF]
186 fvp_mps2.mps2_secure_control_register_block.AHBPPCEXP_DIS2=0x0 # (int , init-time) default = '0x0' : Disables support for individual bits on the AHBNSPPCEXP2 and AHBPPPCEXP2 buses : [0x0..0xFFFF]
187 fvp_mps2.mps2_secure_control_register_block.AHBPPCEXP_DIS3=0x0 # (int , init-time) default = '0x0' : Disables support for individual bits on the AHBNSPPCEXP3 and AHBPPPCEXP3 buses : [0x0..0xFFFF]
188 fvp_mps2.ahb_ppc_iotss_expansion0.NONSEC_MASK=0x0 # (int , init-time) default = '0x0' : 16-bit wide mask for security checking of ports: 0 = check, 1 = mask : [0x0..0x1]
189 fvp_mps2.ahb_ppc_iotss_expansion1.NONSEC_MASK=0x0 # (int , init-time) default = '0x0' : 16-bit wide mask for security checking of ports: 0 = check, 1 = mask : [0x0..0x1]
190 fvp_mps2.apb_ppc_iotss_expansion0.NONSEC_MASK=0x0 # (int , init-time) default = '0x0' : 16-bit wide mask for security checking of ports: 0 = check, 1 = mask : [0x0..0x1]
191 fvp_mps2.apb_ppc_iotss_expansion1.NONSEC_MASK=0x0 # (int , init-time) default = '0x0' : 16-bit wide mask for security checking of ports: 0 = check, 1 = mask : [0x0..0x1]
192 fvp_mps2.apb_ppc_iotss_expansion2.NONSEC_MASK=0x0 # (int , init-time) default = '0x0' : 16-bit wide mask for security checking of ports: 0 = check, 1 = mask : [0x0..0x1]
193 fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component
194 fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
195 fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
196 fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
197 fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
198 fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
199 fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
200 fvp_mps2.exclusive_monitor_psram_iotss.enable_component=1 # (bool , init-time) default = '1' : Enable component
201 fvp_mps2.exclusive_monitor_psram_iotss.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
202 fvp_mps2.exclusive_monitor_psram_iotss.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
203 fvp_mps2.exclusive_monitor_psram_iotss.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
204 fvp_mps2.exclusive_monitor_psram_iotss.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
205 fvp_mps2.exclusive_monitor_psram_iotss.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
206 fvp_mps2.exclusive_monitor_psram_iotss.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
207 fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component
208 fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
209 fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
210 fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
211 fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
212 fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
213 fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
214 fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component
215 fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
216 fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
217 fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
218 fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
219 fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
220 fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
221 fvp_mps2.mps2_exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component
222 fvp_mps2.mps2_exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
223 fvp_mps2.mps2_exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
224 fvp_mps2.mps2_exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
225 fvp_mps2.mps2_exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
226 fvp_mps2.mps2_exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
227 fvp_mps2.mps2_exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
228 fvp_mps2.mps2_exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component
229 fvp_mps2.mps2_exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
230 fvp_mps2.mps2_exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
231 fvp_mps2.mps2_exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
232 fvp_mps2.mps2_exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
233 fvp_mps2.mps2_exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
234 fvp_mps2.mps2_exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
235 fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
236 fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
237 fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
238 fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
239 fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
240 fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
241 fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
242 fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
243 fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
244 fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
245 fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
246 fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
247 fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
248 fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
249 fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
250 fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
251 fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
252 fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
253 fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
254 fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
255 default_ahb_slave.read_data=0x0 # (int , init-time) default = '0x0' : Data to return on reads, if not aborting
256 #----------------------------------------------------------------------------------------------
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