begriffs open source - cmsis/blob - main/Core_A/html/group__CMSIS__IFSR__BITS.html

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  46    <div id="projectname">CMSIS-Core (Cortex-A)
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  55    <div id="projectbrief">CMSIS-Core support for Cortex-A processor-based devices</div>
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 126 <div class="header">
 127   <div class="summary">
 128 <a href="#define-members">Macros</a>  </div>
 129   <div class="headertitle"><div class="title">IFSR Bits<div class="ingroups"><a class="el" href="group__CMSIS__core__register.html">Core Register Access</a> &raquo; <a class="el" href="group__CMSIS__IFSR.html">Instruction Fault Status Register (IFSR)</a></div></div></div>
 130 </div><!--header-->
 131 <div class="contents">
 132
 133 <p>Bit position and mask macros.
 134 <a href="#details">More...</a></p>
 135 <table class="memberdecls">
 136 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a>
 137 Macros</h2></td></tr>
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 139 <tr class="memdesc:gafb3d593ec56834b6a265744efd6340a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">IFSR: ExT Position.  <br /></td></tr>
 140 <tr class="separator:gafb3d593ec56834b6a265744efd6340a8"><td class="memSeparator" colspan="2">&#160;</td></tr>
 141 <tr class="memitem:gab0083a1d82b370a7e5208e39267bda22"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#gab0083a1d82b370a7e5208e39267bda22">IFSR_ExT_Msk</a>&#160;&#160;&#160;(1UL &lt;&lt; <a class="el" href="group__CMSIS__IFSR__BITS.html#gafb3d593ec56834b6a265744efd6340a8">IFSR_ExT_Pos</a>)</td></tr>
 142 <tr class="memdesc:gab0083a1d82b370a7e5208e39267bda22"><td class="mdescLeft">&#160;</td><td class="mdescRight">IFSR: ExT Mask.  <br /></td></tr>
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 148 <tr class="memdesc:ga20639ca32a866d7b021e455b7a5d24c6"><td class="mdescLeft">&#160;</td><td class="mdescRight">IFSR: LPAE Mask.  <br /></td></tr>
 149 <tr class="separator:ga20639ca32a866d7b021e455b7a5d24c6"><td class="memSeparator" colspan="2">&#160;</td></tr>
 150 <tr class="memitem:ga9ecf4e123cfee3f0a19898a822fc0f62"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#ga9ecf4e123cfee3f0a19898a822fc0f62">IFSR_FS1_Pos</a>&#160;&#160;&#160;10U</td></tr>
 151 <tr class="memdesc:ga9ecf4e123cfee3f0a19898a822fc0f62"><td class="mdescLeft">&#160;</td><td class="mdescRight">IFSR: FS1 Position.  <br /></td></tr>
 152 <tr class="separator:ga9ecf4e123cfee3f0a19898a822fc0f62"><td class="memSeparator" colspan="2">&#160;</td></tr>
 153 <tr class="memitem:ga6fc93a02fbd1c968c70786a84428fca6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#ga6fc93a02fbd1c968c70786a84428fca6">IFSR_FS1_Msk</a>&#160;&#160;&#160;(1UL &lt;&lt; <a class="el" href="group__CMSIS__IFSR__BITS.html#ga9ecf4e123cfee3f0a19898a822fc0f62">IFSR_FS1_Pos</a>)</td></tr>
 154 <tr class="memdesc:ga6fc93a02fbd1c968c70786a84428fca6"><td class="mdescLeft">&#160;</td><td class="mdescRight">IFSR: FS1 Mask.  <br /></td></tr>
 155 <tr class="separator:ga6fc93a02fbd1c968c70786a84428fca6"><td class="memSeparator" colspan="2">&#160;</td></tr>
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 157 <tr class="memdesc:ga487c29da2f2d648f149c4346f3093f72"><td class="mdescLeft">&#160;</td><td class="mdescRight">IFSR: FS0 Position.  <br /></td></tr>
 158 <tr class="separator:ga487c29da2f2d648f149c4346f3093f72"><td class="memSeparator" colspan="2">&#160;</td></tr>
 159 <tr class="memitem:gaa17676ff0276b0fe93f92010fe35f6b8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#gaa17676ff0276b0fe93f92010fe35f6b8">IFSR_FS0_Msk</a>&#160;&#160;&#160;(0xFUL &lt;&lt; <a class="el" href="group__CMSIS__IFSR__BITS.html#ga487c29da2f2d648f149c4346f3093f72">IFSR_FS0_Pos</a>)</td></tr>
 160 <tr class="memdesc:gaa17676ff0276b0fe93f92010fe35f6b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">IFSR: FS0 Mask.  <br /></td></tr>
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 163 <tr class="memdesc:ga64ec6d573ec1efe1d6c36100ad1cd09d"><td class="mdescLeft">&#160;</td><td class="mdescRight">IFSR: STATUS Position.  <br /></td></tr>
 164 <tr class="separator:ga64ec6d573ec1efe1d6c36100ad1cd09d"><td class="memSeparator" colspan="2">&#160;</td></tr>
 165 <tr class="memitem:gaf74c1045a32a2d4de7ea6f0dbcf0d1b3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#gaf74c1045a32a2d4de7ea6f0dbcf0d1b3">IFSR_STATUS_Msk</a>&#160;&#160;&#160;(0x3FUL &lt;&lt; <a class="el" href="group__CMSIS__IFSR__BITS.html#ga64ec6d573ec1efe1d6c36100ad1cd09d">IFSR_STATUS_Pos</a>)</td></tr>
 166 <tr class="memdesc:gaf74c1045a32a2d4de7ea6f0dbcf0d1b3"><td class="mdescLeft">&#160;</td><td class="mdescRight">IFSR: STATUS Mask.  <br /></td></tr>
 167 <tr class="separator:gaf74c1045a32a2d4de7ea6f0dbcf0d1b3"><td class="memSeparator" colspan="2">&#160;</td></tr>
 168 </table>
 169 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
 170 <h2 class="groupheader">Macro Definition Documentation</h2>
 171 <a id="gab0083a1d82b370a7e5208e39267bda22" name="gab0083a1d82b370a7e5208e39267bda22"></a>
 172 <h2 class="memtitle"><span class="permalink"><a href="#gab0083a1d82b370a7e5208e39267bda22">&#9670;&#160;</a></span>IFSR_ExT_Msk</h2>
 173
 174 <div class="memitem">
 175 <div class="memproto">
 176       <table class="memname">
 177         <tr>
 178           <td class="memname">#define IFSR_ExT_Msk&#160;&#160;&#160;(1UL &lt;&lt; <a class="el" href="group__CMSIS__IFSR__BITS.html#gafb3d593ec56834b6a265744efd6340a8">IFSR_ExT_Pos</a>)</td>
 179         </tr>
 180       </table>
 181 </div><div class="memdoc">
 182
 183 </div>
 184 </div>
 185 <a id="gafb3d593ec56834b6a265744efd6340a8" name="gafb3d593ec56834b6a265744efd6340a8"></a>
 186 <h2 class="memtitle"><span class="permalink"><a href="#gafb3d593ec56834b6a265744efd6340a8">&#9670;&#160;</a></span>IFSR_ExT_Pos</h2>
 187
 188 <div class="memitem">
 189 <div class="memproto">
 190       <table class="memname">
 191         <tr>
 192           <td class="memname">#define IFSR_ExT_Pos&#160;&#160;&#160;12U</td>
 193         </tr>
 194       </table>
 195 </div><div class="memdoc">
 196
 197 </div>
 198 </div>
 199 <a id="gaa17676ff0276b0fe93f92010fe35f6b8" name="gaa17676ff0276b0fe93f92010fe35f6b8"></a>
 200 <h2 class="memtitle"><span class="permalink"><a href="#gaa17676ff0276b0fe93f92010fe35f6b8">&#9670;&#160;</a></span>IFSR_FS0_Msk</h2>
 201
 202 <div class="memitem">
 203 <div class="memproto">
 204       <table class="memname">
 205         <tr>
 206           <td class="memname">#define IFSR_FS0_Msk&#160;&#160;&#160;(0xFUL &lt;&lt; <a class="el" href="group__CMSIS__IFSR__BITS.html#ga487c29da2f2d648f149c4346f3093f72">IFSR_FS0_Pos</a>)</td>
 207         </tr>
 208       </table>
 209 </div><div class="memdoc">
 210
 211 </div>
 212 </div>
 213 <a id="ga487c29da2f2d648f149c4346f3093f72" name="ga487c29da2f2d648f149c4346f3093f72"></a>
 214 <h2 class="memtitle"><span class="permalink"><a href="#ga487c29da2f2d648f149c4346f3093f72">&#9670;&#160;</a></span>IFSR_FS0_Pos</h2>
 215
 216 <div class="memitem">
 217 <div class="memproto">
 218       <table class="memname">
 219         <tr>
 220           <td class="memname">#define IFSR_FS0_Pos&#160;&#160;&#160;0U</td>
 221         </tr>
 222       </table>
 223 </div><div class="memdoc">
 224
 225 </div>
 226 </div>
 227 <a id="ga6fc93a02fbd1c968c70786a84428fca6" name="ga6fc93a02fbd1c968c70786a84428fca6"></a>
 228 <h2 class="memtitle"><span class="permalink"><a href="#ga6fc93a02fbd1c968c70786a84428fca6">&#9670;&#160;</a></span>IFSR_FS1_Msk</h2>
 229
 230 <div class="memitem">
 231 <div class="memproto">
 232       <table class="memname">
 233         <tr>
 234           <td class="memname">#define IFSR_FS1_Msk&#160;&#160;&#160;(1UL &lt;&lt; <a class="el" href="group__CMSIS__IFSR__BITS.html#ga9ecf4e123cfee3f0a19898a822fc0f62">IFSR_FS1_Pos</a>)</td>
 235         </tr>
 236       </table>
 237 </div><div class="memdoc">
 238
 239 </div>
 240 </div>
 241 <a id="ga9ecf4e123cfee3f0a19898a822fc0f62" name="ga9ecf4e123cfee3f0a19898a822fc0f62"></a>
 242 <h2 class="memtitle"><span class="permalink"><a href="#ga9ecf4e123cfee3f0a19898a822fc0f62">&#9670;&#160;</a></span>IFSR_FS1_Pos</h2>
 243
 244 <div class="memitem">
 245 <div class="memproto">
 246       <table class="memname">
 247         <tr>
 248           <td class="memname">#define IFSR_FS1_Pos&#160;&#160;&#160;10U</td>
 249         </tr>
 250       </table>
 251 </div><div class="memdoc">
 252
 253 </div>
 254 </div>
 255 <a id="ga20639ca32a866d7b021e455b7a5d24c6" name="ga20639ca32a866d7b021e455b7a5d24c6"></a>
 256 <h2 class="memtitle"><span class="permalink"><a href="#ga20639ca32a866d7b021e455b7a5d24c6">&#9670;&#160;</a></span>IFSR_LPAE_Msk</h2>
 257
 258 <div class="memitem">
 259 <div class="memproto">
 260       <table class="memname">
 261         <tr>
 262           <td class="memname">#define IFSR_LPAE_Msk&#160;&#160;&#160;(0x1UL &lt;&lt; <a class="el" href="group__CMSIS__IFSR__BITS.html#gadfd49185eeb102fc69e0a0d28fd2c4a4">IFSR_LPAE_Pos</a>)</td>
 263         </tr>
 264       </table>
 265 </div><div class="memdoc">
 266
 267 </div>
 268 </div>
 269 <a id="gadfd49185eeb102fc69e0a0d28fd2c4a4" name="gadfd49185eeb102fc69e0a0d28fd2c4a4"></a>
 270 <h2 class="memtitle"><span class="permalink"><a href="#gadfd49185eeb102fc69e0a0d28fd2c4a4">&#9670;&#160;</a></span>IFSR_LPAE_Pos</h2>
 271
 272 <div class="memitem">
 273 <div class="memproto">
 274       <table class="memname">
 275         <tr>
 276           <td class="memname">#define IFSR_LPAE_Pos&#160;&#160;&#160;9U</td>
 277         </tr>
 278       </table>
 279 </div><div class="memdoc">
 280
 281 </div>
 282 </div>
 283 <a id="gaf74c1045a32a2d4de7ea6f0dbcf0d1b3" name="gaf74c1045a32a2d4de7ea6f0dbcf0d1b3"></a>
 284 <h2 class="memtitle"><span class="permalink"><a href="#gaf74c1045a32a2d4de7ea6f0dbcf0d1b3">&#9670;&#160;</a></span>IFSR_STATUS_Msk</h2>
 285
 286 <div class="memitem">
 287 <div class="memproto">
 288       <table class="memname">
 289         <tr>
 290           <td class="memname">#define IFSR_STATUS_Msk&#160;&#160;&#160;(0x3FUL &lt;&lt; <a class="el" href="group__CMSIS__IFSR__BITS.html#ga64ec6d573ec1efe1d6c36100ad1cd09d">IFSR_STATUS_Pos</a>)</td>
 291         </tr>
 292       </table>
 293 </div><div class="memdoc">
 294
 295 </div>
 296 </div>
 297 <a id="ga64ec6d573ec1efe1d6c36100ad1cd09d" name="ga64ec6d573ec1efe1d6c36100ad1cd09d"></a>
 298 <h2 class="memtitle"><span class="permalink"><a href="#ga64ec6d573ec1efe1d6c36100ad1cd09d">&#9670;&#160;</a></span>IFSR_STATUS_Pos</h2>
 299
 300 <div class="memitem">
 301 <div class="memproto">
 302       <table class="memname">
 303         <tr>
 304           <td class="memname">#define IFSR_STATUS_Pos&#160;&#160;&#160;0U</td>
 305         </tr>
 306       </table>
 307 </div><div class="memdoc">
 308
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