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  46    <div id="projectname">CMSIS-Core (Cortex-A)
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  55    <div id="projectbrief">CMSIS-Core support for Cortex-A processor-based devices</div>
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 130   <div class="headertitle"><div class="title">Device Header File &lt;device.h&gt; </div></div>
 131 </div><!--header-->
 132 <div class="contents">
 133 <div class="textblock"><p>The <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> contains the following sections that are device specific:</p><ul>
 134 <li><a class="el" href="device_h_pg.html#irqn_defs">Interrupt Number Definition</a> provides interrupt numbers (IRQn) for all exceptions and interrupts of the device.</li>
 135 <li><a class="el" href="device_h_pg.html#config_perifs">Configuration of the Processor and Core Peripherals</a> reflect the features of the device.</li>
 136 <li><a class="el" href="device_h_pg.html#access_perifs">Device Peripheral Access Layer</a> definitions for the <a class="el" href="group__peripheral__gr.html">Peripheral Access</a> to all device peripherals. It contains all data structures and the address mapping for device-specific peripherals.</li>
 137 <li><b>Access Functions for Peripherals (optioal)</b> provide additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device-specific library provided by the silicon vendor.</li>
 138 </ul>
 139 <h1><a class="anchor" id="irqn_defs"></a>
 140 Interrupt Number Definition</h1>
 141 <h1><a class="anchor" id="config_perifs"></a>
 142 Configuration of the Processor and Core Peripherals</h1>
 143 <h1><a class="anchor" id="access_perifs"></a>
 144 Device Peripheral Access Layer</h1>
 145 <p>The <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> contains the following sections that are device specific:</p><ul>
 146 <li><a class="el" href="device_h_pg.html#irqn_defs">Interrupt Number Definition</a> provides interrupt numbers (IRQn) for all exceptions and interrupts of the device.</li>
 147 <li><a class="el" href="device_h_pg.html#config_perifs">Configuration of the Processor and Core Peripherals</a> reflect the features of the device.</li>
 148 <li><a class="el" href="device_h_pg.html#access_perifs">Device Peripheral Access Layer</a> definitions for the <a class="el" href="group__peripheral__gr.html">Peripheral Access</a> to all device peripherals. It contains all data structures and the address mapping for device-specific peripherals.</li>
 149 <li><b>Access Functions for Peripherals (optional)</b> provide additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device-specific library provided by the silicon vendor.</li>
 150 </ul>
 151 <p><a href="modules.html"><b>Reference</b> </a> describes the standard features and functions of the <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> in detail.</p>
 152 <h1><a class="anchor" id="interrupt_number_sec"></a>
 153 Interrupt Number Definition</h1>
 154 <p><a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> contains the enumeration IRQn_Type that defines all exceptions and interrupts of the device. For devices implementing an Arm GIC these are defined as:</p><ul>
 155 <li>IRQn 0-15 represents software generated interrupts (SGI), local to each processor core.</li>
 156 <li>IRQn 16-31 represents private peripheral interrupts (PPI), local to each processor core.</li>
 157 <li>IRQn 32-1019 represents shared peripheral interrupts (SPI), routable to all processor cores.</li>
 158 <li>IRQn 1020-1023 represents special interrupts, refer to the GIC Architecture Specification.</li>
 159 </ul>
 160 <p><b>Example:</b> </p>
 161 <p>The following example shows the extension of the interrupt vector table for Cortex-A9 class device.</p>
 162 <div class="fragment"><div class="line"><span class="keyword">typedef</span> <span class="keyword">enum</span> IRQn</div>
 163 <div class="line">{</div>
 164 <div class="line"><span class="comment">/******  SGI Interrupts Numbers                 ****************************************/</span></div>
 165 <div class="line">  SGI0_IRQn            =  0,      </div>
 166 <div class="line">  SGI1_IRQn            =  1,</div>
 167 <div class="line">  SGI2_IRQn            =  2,</div>
 168 <div class="line">       :                  :</div>
 169 <div class="line">  SGI15_IRQn           = 15,</div>
 170 <div class="line"> </div>
 171 <div class="line"><span class="comment">/******  Cortex-A9 Processor Exceptions Numbers ****************************************/</span></div>
 172 <div class="line">  GlobalTimer_IRQn     = 27,        </div>
 173 <div class="line">  PrivTimer_IRQn       = 29,        </div>
 174 <div class="line">  PrivWatchdog_IRQn    = 30,        </div>
 175 <div class="line"><span class="comment">/******  Platform Exceptions Numbers ***************************************************/</span></div>
 176 <div class="line">  Watchdog_IRQn        = 32,        </div>
 177 <div class="line">  Timer0_IRQn          = 34,        </div>
 178 <div class="line">  Timer1_IRQn          = 35,        </div>
 179 <div class="line">  RTClock_IRQn         = 36,        </div>
 180 <div class="line">  UART0_IRQn           = 37,        </div>
 181 <div class="line">       :                  :</div>
 182 <div class="line">       :                  :</div>
 183 <div class="line">} IRQn_Type;</div>
 184 </div><!-- fragment --><h1><a class="anchor" id="core_config_sect"></a>
 185 Configuration of the Processor and Core Peripherals</h1>
 186 <p>The <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> configures the Cortex-A processor and the core peripherals with <em>#defines</em> that are set prior to including the file <b>core_&lt;cpu&gt;.h</b>.</p>
 187 <p>The following tables list the <em>#defines</em> along with the possible values for each processor core. If these <em>#defines</em> are missing default values are used.</p>
 188 <table class="cmtable">
 189 <tr>
 190 <th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
 191 <tr>
 192 <td>__CM0_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number)  </td></tr>
 193 <tr>
 194 <td>__CORTEX_A </td><td>5, 7, 9 </td><td>(n/a) </td><td>Core type number  </td></tr>
 195 <tr>
 196 <td>__FPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if an FPU is present or not  </td></tr>
 197 <tr>
 198 <td>__GIC_PRESENT </td><td>0 ..1  </td><td>Defines if an GIC is present or not </td><td>Core revision number ([15:8] revision number, [7:0] patch number)  </td></tr>
 199 <tr>
 200 <td>__TIM_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a private timer is present or not  </td></tr>
 201 <tr>
 202 <td>__L2C_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a level 2 cache controller is present or not  </td></tr>
 203 </table>
 204 <p><b>Example</b> </p>
 205 <p>The following code exemplifies the configuration of the Cortex-A9 Processor and Core Peripherals.</p>
 206 <div class="fragment"><div class="line"><span class="preprocessor">#define __CA_REV        0x0000U    </span></div>
 207 <div class="line"><span class="preprocessor">#define __CORTEX_A           9U    </span></div>
 208 <div class="line"><span class="preprocessor">#define __FPU_PRESENT        1U    </span></div>
 209 <div class="line"><span class="preprocessor">#define __GIC_PRESENT        1U    </span></div>
 210 <div class="line"><span class="preprocessor">#define __TIM_PRESENT        0U    </span></div>
 211 <div class="line"><span class="preprocessor">#define __L2C_PRESENT        0U    </span></div>
 212 <div class="line">:</div>
 213 <div class="line">:</div>
 214 <div class="line"><span class="preprocessor">#include &quot;<a class="code" href="core__ca_8h.html">core_ca.h</a>&quot;</span>               <span class="comment">/* Cortex-A processor and core peripherals       */</span></div>
 215 <div class="ttc" id="acore__ca_8h_html"><div class="ttname"><a href="core__ca_8h.html">core_ca.h</a></div><div class="ttdoc">CMSIS Cortex-A Core Peripheral Access Layer Header File.</div></div>
 216 </div><!-- fragment --><h1><a class="anchor" id="core_version_sect"></a>
 217 CMSIS Version and Processor Information</h1>
 218 <p>Defines in the core_<em>cpu</em>.h file identify the version of the CMSIS-Core-A and the processor used. The following shows the defines in the various core_<em>cpu</em>.h files that may be used in the <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> to verify a minimum version or ensure that the right processor core is used.</p>
 219 <div class="fragment"><div class="line"><span class="preprocessor">#define __CA_CMSIS_VERSION_MAIN  (5U)                                 </span><span class="comment">/* [31:16] CMSIS Core main version */</span><span class="preprocessor"></span></div>
 220 <div class="line"><span class="preprocessor">#define __CA_CMSIS_VERSION_SUB   (0U)                                 </span><span class="comment">/* [15:0]  CMSIS Core sub version */</span><span class="preprocessor"></span></div>
 221 <div class="line"><span class="preprocessor">#define __CA_CMSIS_VERSION       ((__CA_CMSIS_VERSION_MAIN &lt;&lt; 16U) | \</span></div>
 222 <div class="line"><span class="preprocessor">                                   __CA_CMSIS_VERSION_SUB          )  </span><span class="comment">/* CMSIS Core version number */</span><span class="preprocessor"></span></div>
 223 </div><!-- fragment --><h1><a class="anchor" id="device_access"></a>
 224 Device Peripheral Access Layer</h1>
 225 <p>The <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> contains for each peripheral:</p><ul>
 226 <li>Register Layout Typedef</li>
 227 <li>Base Address</li>
 228 <li>Access Definitions</li>
 229 </ul>
 230 <p>The section <a class="el" href="group__peripheral__gr.html">Peripheral Access</a> shows examples for peripheral definitions.</p>
 231 <h1><a class="anchor" id="device_h_sec"></a>
 232 Device.h Template File</h1>
 233 <p>The silicon vendor needs to extend the Device.h template file with the CMSIS features described above. In addition the <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> may contain functions to access device-specific peripherals. The <a class="el" href="system_c_pg.html#system_Device_h_sec">system_Device.h Template File</a> which is provided as part of the CMSIS specification is shown below.</p>
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