begriffs open source - cmsis/blob - main/DAP/html/index.html

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  46    <div id="projectname">CMSIS-DAP
  47    </div>
  48    <div id="projectbrief">Interface Firmware for CoreSight Debug Access Port</div>
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 123   <div class="headertitle"><div class="title">CMSIS-DAP </div></div>
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 125 <div class="contents">
 126 <div class="textblock"><p><a class="anchor" id="mainpage"></a> <b>CMSIS-DAP</b> is a <b>protocol</b> specification and an open-source <b>firmware</b> implementation that provides standardized access to the CoreSight Debug Access Port (<a href="https://developer.arm.com/documentation/102585/0000/what-is-a-debug-access-port">DAP</a>) available on many Arm Cortex processors as part of the <a href="https://developer.arm.com/ip-products/system-ip/coresight-debug-and-trace">CoreSight Debug and Trace</a> functionality.</p>
 127 <div class="image">
 128 <img src="cmsis_dap_interface.png" alt=""/>
 129 <div class="caption">
 130 Overview of CMSIS-DAP</div></div>
 131     <p>CMSIS-DAP supports target devices that contain one or more Cortex processors.</p>
 132 <p>A processor device exposes Debug Access Port (DAP) typically either with a 5-pin JTAG or with a 2-pin Serial Wired Debug (SWD) interface that is used as a physical communication with a debug unit.</p>
 133 <p>CMSIS-DAP provides the interface firmware for a debug unit that implements the communication between the debug port of the device and USB port. With it, a software debug tool that runs on a host computer can connect via USB and the debug unit to the device where the application firwmare gets executed.</p>
 134 <h1><a class="anchor" id="autotoc_md0"></a>
 135 Access to CMSIS-DAP</h1>
 136 <ul>
 137 <li><a href="https://github.com/ARM-software/CMSIS-DAP"><b>CMSIS-DAP GitHub Repo</b></a> provides the full source code.</li>
 138 <li><a href="https://arm-software.github.io/CMSIS-DAP/latest/"><b>CMSIS-DAP Documentation</b></a> describes the implemented functions in details.</li>
 139 </ul>
 140 <h1><a class="anchor" id="autotoc_md1"></a>
 141 Key Features and Benefits</h1>
 142 <ul>
 143 <li>Provides a standardized interface for debuggers. Interfaces to many standard debuggers is available.</li>
 144 <li>Access to CoreSight registers of all Cortex processor architectures (Cortex-A/R/M).</li>
 145 <li>Connects via 5-pin JTAG or 2-pin Serial Wire Debug (SWD).</li>
 146 <li>Supports multi-core debugging.</li>
 147 <li>Supports Serial Wire Output (SWO) of Cortex-M devices.</li>
 148 <li>Easy to deploy to debug units based on Cortex-M microcontrollers.</li>
 149 <li>Debug unit may be integrated on an evaluation board.</li>
 150 <li>Using USB bulk transfers avoids driver installation on host PC.</li>
 151 <li>Supports time-critical JTAG or SWD command execution.</li>
 152 <li>Supports Test Domain Timer for time measurement using the debug unit.</li>
 153 <li>Supports UART communication port, which can be routed to USB COM Port (optional) or native CMSIS-DAP commands. </li>
 154 </ul>
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