begriffs open source - cmsis/blob - main/Driver/html/group__nand__bus__mode__codes.html

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  46    <div id="projectname">CMSIS-Driver
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  55    <div id="projectbrief">Peripheral Interface for Middleware and Application Code</div>
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 129 <div class="header">
 130   <div class="summary">
 131 <a href="#define-members">Macros</a>  </div>
 132   <div class="headertitle"><div class="title">NAND Bus Modes<div class="ingroups"><a class="el" href="group__nand__interface__gr.html">NAND Interface</a> &raquo; <a class="el" href="group__nand__control__gr.html">NAND Control Codes</a></div></div></div>
 133 </div><!--header-->
 134 <div class="contents">
 135
 136 <p>Specify bus mode of the NAND interface.
 137 <a href="#details">More...</a></p>
 138 <table class="memberdecls">
 139 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a>
 140 Macros</h2></td></tr>
 141 <tr class="memitem:gac7743aeb6411b97f9fc6a24b556f4963"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gac7743aeb6411b97f9fc6a24b556f4963">ARM_NAND_BUS_SDR</a>&#160;&#160;&#160;(0x00UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#a372fc9b9cc1315046ceaffd6fd99e12c">ARM_NAND_BUS_INTERFACE_Pos</a>)</td></tr>
 142 <tr class="memdesc:gac7743aeb6411b97f9fc6a24b556f4963"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Interface: SDR (Single Data Rate) - Traditional interface (default)  <br /></td></tr>
 143 <tr class="separator:gac7743aeb6411b97f9fc6a24b556f4963"><td class="memSeparator" colspan="2">&#160;</td></tr>
 144 <tr class="memitem:ga82b8261b3d0d85881535adada318a7df"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga82b8261b3d0d85881535adada318a7df">ARM_NAND_BUS_DDR</a>&#160;&#160;&#160;(0x01UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#a372fc9b9cc1315046ceaffd6fd99e12c">ARM_NAND_BUS_INTERFACE_Pos</a>)</td></tr>
 145 <tr class="memdesc:ga82b8261b3d0d85881535adada318a7df"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Interface: NV-DDR (Double Data Rate)  <br /></td></tr>
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 148 <tr class="memdesc:ga13c102201d6021db184a2f068656c518"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Interface: NV-DDR2 (Double Data Rate)  <br /></td></tr>
 149 <tr class="separator:ga13c102201d6021db184a2f068656c518"><td class="memSeparator" colspan="2">&#160;</td></tr>
 150 <tr class="memitem:ga971e574ac412bbba445055e9afc384ba"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga971e574ac412bbba445055e9afc384ba">ARM_NAND_BUS_TIMING_MODE_0</a>&#160;&#160;&#160;(0x00UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#acc98e42d23656734c7f9a8a5421842d6">ARM_NAND_BUS_TIMING_MODE_Pos</a>)</td></tr>
 151 <tr class="memdesc:ga971e574ac412bbba445055e9afc384ba"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timing Mode 0 (default)  <br /></td></tr>
 152 <tr class="separator:ga971e574ac412bbba445055e9afc384ba"><td class="memSeparator" colspan="2">&#160;</td></tr>
 153 <tr class="memitem:ga475a339e929eca46e11bc8a7b330aa45"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga475a339e929eca46e11bc8a7b330aa45">ARM_NAND_BUS_TIMING_MODE_1</a>&#160;&#160;&#160;(0x01UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#acc98e42d23656734c7f9a8a5421842d6">ARM_NAND_BUS_TIMING_MODE_Pos</a>)</td></tr>
 154 <tr class="memdesc:ga475a339e929eca46e11bc8a7b330aa45"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timing Mode 1.  <br /></td></tr>
 155 <tr class="separator:ga475a339e929eca46e11bc8a7b330aa45"><td class="memSeparator" colspan="2">&#160;</td></tr>
 156 <tr class="memitem:gaed6154fb03b5516faf0bfd11d7a46309"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gaed6154fb03b5516faf0bfd11d7a46309">ARM_NAND_BUS_TIMING_MODE_2</a>&#160;&#160;&#160;(0x02UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#acc98e42d23656734c7f9a8a5421842d6">ARM_NAND_BUS_TIMING_MODE_Pos</a>)</td></tr>
 157 <tr class="memdesc:gaed6154fb03b5516faf0bfd11d7a46309"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timing Mode 2.  <br /></td></tr>
 158 <tr class="separator:gaed6154fb03b5516faf0bfd11d7a46309"><td class="memSeparator" colspan="2">&#160;</td></tr>
 159 <tr class="memitem:gacbc4e07e1af6ef0e4c656428e81464a9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gacbc4e07e1af6ef0e4c656428e81464a9">ARM_NAND_BUS_TIMING_MODE_3</a>&#160;&#160;&#160;(0x03UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#acc98e42d23656734c7f9a8a5421842d6">ARM_NAND_BUS_TIMING_MODE_Pos</a>)</td></tr>
 160 <tr class="memdesc:gacbc4e07e1af6ef0e4c656428e81464a9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timing Mode 3.  <br /></td></tr>
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 163 <tr class="memdesc:ga709d51a5215cd23ce2d85aec57141456"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timing Mode 4 (SDR EDO capable)  <br /></td></tr>
 164 <tr class="separator:ga709d51a5215cd23ce2d85aec57141456"><td class="memSeparator" colspan="2">&#160;</td></tr>
 165 <tr class="memitem:gaee3cad14ce2b8b9af69149bf74597791"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gaee3cad14ce2b8b9af69149bf74597791">ARM_NAND_BUS_TIMING_MODE_5</a>&#160;&#160;&#160;(0x05UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#acc98e42d23656734c7f9a8a5421842d6">ARM_NAND_BUS_TIMING_MODE_Pos</a>)</td></tr>
 166 <tr class="memdesc:gaee3cad14ce2b8b9af69149bf74597791"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timing Mode 5 (SDR EDO capable)  <br /></td></tr>
 167 <tr class="separator:gaee3cad14ce2b8b9af69149bf74597791"><td class="memSeparator" colspan="2">&#160;</td></tr>
 168 <tr class="memitem:ga4a3524e0eba994b3a66e06cde877f0f6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga4a3524e0eba994b3a66e06cde877f0f6">ARM_NAND_BUS_TIMING_MODE_6</a>&#160;&#160;&#160;(0x06UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#acc98e42d23656734c7f9a8a5421842d6">ARM_NAND_BUS_TIMING_MODE_Pos</a>)</td></tr>
 169 <tr class="memdesc:ga4a3524e0eba994b3a66e06cde877f0f6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timing Mode 6 (NV-DDR2 only)  <br /></td></tr>
 170 <tr class="separator:ga4a3524e0eba994b3a66e06cde877f0f6"><td class="memSeparator" colspan="2">&#160;</td></tr>
 171 <tr class="memitem:gaa63d75f5f2b48a7345a066d58de1bd23"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gaa63d75f5f2b48a7345a066d58de1bd23">ARM_NAND_BUS_TIMING_MODE_7</a>&#160;&#160;&#160;(0x07UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#acc98e42d23656734c7f9a8a5421842d6">ARM_NAND_BUS_TIMING_MODE_Pos</a>)</td></tr>
 172 <tr class="memdesc:gaa63d75f5f2b48a7345a066d58de1bd23"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timing Mode 7 (NV-DDR2 only)  <br /></td></tr>
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 174 <tr class="memitem:ga77348df5f5c2c96bcaeec60b6da02c1b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga77348df5f5c2c96bcaeec60b6da02c1b">ARM_NAND_BUS_DDR2_DO_WCYC_0</a>&#160;&#160;&#160;(0x00UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#a57b282c0818c87b79ea4f11d03cc4f3c">ARM_NAND_BUS_DDR2_DO_WCYC_Pos</a>)</td></tr>
 175 <tr class="memdesc:ga77348df5f5c2c96bcaeec60b6da02c1b"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Data Output Warm-up cycles: 0 (default)  <br /></td></tr>
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 177 <tr class="memitem:ga5839be0b4b2eb930ec039a3403b5e89e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga5839be0b4b2eb930ec039a3403b5e89e">ARM_NAND_BUS_DDR2_DO_WCYC_1</a>&#160;&#160;&#160;(0x01UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#a57b282c0818c87b79ea4f11d03cc4f3c">ARM_NAND_BUS_DDR2_DO_WCYC_Pos</a>)</td></tr>
 178 <tr class="memdesc:ga5839be0b4b2eb930ec039a3403b5e89e"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Data Output Warm-up cycles: 1.  <br /></td></tr>
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 181 <tr class="memdesc:ga10a1ef3be69bfa7e6cc657bee751a077"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Data Output Warm-up cycles: 2.  <br /></td></tr>
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 184 <tr class="memdesc:ga7f9e8416c4a4e20c4a04323e39f2100d"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Data Output Warm-up cycles: 4.  <br /></td></tr>
 185 <tr class="separator:ga7f9e8416c4a4e20c4a04323e39f2100d"><td class="memSeparator" colspan="2">&#160;</td></tr>
 186 <tr class="memitem:gaeee1853dea5e96cb19d2596cc0e70169"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gaeee1853dea5e96cb19d2596cc0e70169">ARM_NAND_BUS_DDR2_DI_WCYC_0</a>&#160;&#160;&#160;(0x00UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#aa80b898cdf665aa14ff0e181e4ff31f1">ARM_NAND_BUS_DDR2_DI_WCYC_Pos</a>)</td></tr>
 187 <tr class="memdesc:gaeee1853dea5e96cb19d2596cc0e70169"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Data Input Warm-up cycles: 0 (default)  <br /></td></tr>
 188 <tr class="separator:gaeee1853dea5e96cb19d2596cc0e70169"><td class="memSeparator" colspan="2">&#160;</td></tr>
 189 <tr class="memitem:ga42560a1f046e20cc4956276156c4ce25"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga42560a1f046e20cc4956276156c4ce25">ARM_NAND_BUS_DDR2_DI_WCYC_1</a>&#160;&#160;&#160;(0x01UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#aa80b898cdf665aa14ff0e181e4ff31f1">ARM_NAND_BUS_DDR2_DI_WCYC_Pos</a>)</td></tr>
 190 <tr class="memdesc:ga42560a1f046e20cc4956276156c4ce25"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Data Input Warm-up cycles: 1.  <br /></td></tr>
 191 <tr class="separator:ga42560a1f046e20cc4956276156c4ce25"><td class="memSeparator" colspan="2">&#160;</td></tr>
 192 <tr class="memitem:gaad2e7807292d84a5070143626f5c2756"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gaad2e7807292d84a5070143626f5c2756">ARM_NAND_BUS_DDR2_DI_WCYC_2</a>&#160;&#160;&#160;(0x02UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#aa80b898cdf665aa14ff0e181e4ff31f1">ARM_NAND_BUS_DDR2_DI_WCYC_Pos</a>)</td></tr>
 193 <tr class="memdesc:gaad2e7807292d84a5070143626f5c2756"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Data Input Warm-up cycles: 2.  <br /></td></tr>
 194 <tr class="separator:gaad2e7807292d84a5070143626f5c2756"><td class="memSeparator" colspan="2">&#160;</td></tr>
 195 <tr class="memitem:ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5">ARM_NAND_BUS_DDR2_DI_WCYC_4</a>&#160;&#160;&#160;(0x03UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#aa80b898cdf665aa14ff0e181e4ff31f1">ARM_NAND_BUS_DDR2_DI_WCYC_Pos</a>)</td></tr>
 196 <tr class="memdesc:ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Data Input Warm-up cycles: 4.  <br /></td></tr>
 197 <tr class="separator:ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5"><td class="memSeparator" colspan="2">&#160;</td></tr>
 198 <tr class="memitem:ga465ae06a6e097959620346304182e273"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga465ae06a6e097959620346304182e273">ARM_NAND_BUS_DDR2_VEN</a>&#160;&#160;&#160;(1UL &lt;&lt; 16)</td></tr>
 199 <tr class="memdesc:ga465ae06a6e097959620346304182e273"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Enable external VREFQ as reference.  <br /></td></tr>
 200 <tr class="separator:ga465ae06a6e097959620346304182e273"><td class="memSeparator" colspan="2">&#160;</td></tr>
 201 <tr class="memitem:gad38354e4a34adbf881afc7f89ff06e89"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gad38354e4a34adbf881afc7f89ff06e89">ARM_NAND_BUS_DDR2_CMPD</a>&#160;&#160;&#160;(1UL &lt;&lt; 17)</td></tr>
 202 <tr class="memdesc:gad38354e4a34adbf881afc7f89ff06e89"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Enable complementary DQS (DQS_c) signal.  <br /></td></tr>
 203 <tr class="separator:gad38354e4a34adbf881afc7f89ff06e89"><td class="memSeparator" colspan="2">&#160;</td></tr>
 204 <tr class="memitem:ga8a2d599082b9fe56cee1c6454bb3c6a1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga8a2d599082b9fe56cee1c6454bb3c6a1">ARM_NAND_BUS_DDR2_CMPR</a>&#160;&#160;&#160;(1UL &lt;&lt; 18)</td></tr>
 205 <tr class="memdesc:ga8a2d599082b9fe56cee1c6454bb3c6a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Enable complementary RE_n (RE_c) signal.  <br /></td></tr>
 206 <tr class="separator:ga8a2d599082b9fe56cee1c6454bb3c6a1"><td class="memSeparator" colspan="2">&#160;</td></tr>
 207 </table>
 208 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
 209 <p>Specify bus mode of the NAND interface. </p>
 210 <p>The defines can be used in the function <a class="el" href="group__nand__interface__gr.html#ga83061d6d53ffb148853efbc87a864607">ARM_NAND_Control</a> for the parameter <em>arg</em> and with the <a class="el" href="Driver__NAND_8h.html#a9b063c3078e86b50d4aa892518b2e2d8">ARM_NAND_BUS_MODE</a> as the <em>control</em> code. </p>
 211 <h2 class="groupheader">Macro Definition Documentation</h2>
 212 <a id="gac7743aeb6411b97f9fc6a24b556f4963" name="gac7743aeb6411b97f9fc6a24b556f4963"></a>
 213 <h2 class="memtitle"><span class="permalink"><a href="#gac7743aeb6411b97f9fc6a24b556f4963">&#9670;&#160;</a></span>ARM_NAND_BUS_SDR</h2>
 214
 215 <div class="memitem">
 216 <div class="memproto">
 217       <table class="memname">
 218         <tr>
 219           <td class="memname">#define ARM_NAND_BUS_SDR&#160;&#160;&#160;(0x00UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#a372fc9b9cc1315046ceaffd6fd99e12c">ARM_NAND_BUS_INTERFACE_Pos</a>)</td>
 220         </tr>
 221       </table>
 222 </div><div class="memdoc">
 223
 224 <p>Data Interface: SDR (Single Data Rate) - Traditional interface (default) </p>
 225
 226 </div>
 227 </div>
 228 <a id="ga82b8261b3d0d85881535adada318a7df" name="ga82b8261b3d0d85881535adada318a7df"></a>
 229 <h2 class="memtitle"><span class="permalink"><a href="#ga82b8261b3d0d85881535adada318a7df">&#9670;&#160;</a></span>ARM_NAND_BUS_DDR</h2>
 230
 231 <div class="memitem">
 232 <div class="memproto">
 233       <table class="memname">
 234         <tr>
 235           <td class="memname">#define ARM_NAND_BUS_DDR&#160;&#160;&#160;(0x01UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#a372fc9b9cc1315046ceaffd6fd99e12c">ARM_NAND_BUS_INTERFACE_Pos</a>)</td>
 236         </tr>
 237       </table>
 238 </div><div class="memdoc">
 239
 240 <p>Data Interface: NV-DDR (Double Data Rate) </p>
 241
 242 </div>
 243 </div>
 244 <a id="ga13c102201d6021db184a2f068656c518" name="ga13c102201d6021db184a2f068656c518"></a>
 245 <h2 class="memtitle"><span class="permalink"><a href="#ga13c102201d6021db184a2f068656c518">&#9670;&#160;</a></span>ARM_NAND_BUS_DDR2</h2>
 246
 247 <div class="memitem">
 248 <div class="memproto">
 249       <table class="memname">
 250         <tr>
 251           <td class="memname">#define ARM_NAND_BUS_DDR2&#160;&#160;&#160;(0x02UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#a372fc9b9cc1315046ceaffd6fd99e12c">ARM_NAND_BUS_INTERFACE_Pos</a>)</td>
 252         </tr>
 253       </table>
 254 </div><div class="memdoc">
 255
 256 <p>Data Interface: NV-DDR2 (Double Data Rate) </p>
 257
 258 </div>
 259 </div>
 260 <a id="ga971e574ac412bbba445055e9afc384ba" name="ga971e574ac412bbba445055e9afc384ba"></a>
 261 <h2 class="memtitle"><span class="permalink"><a href="#ga971e574ac412bbba445055e9afc384ba">&#9670;&#160;</a></span>ARM_NAND_BUS_TIMING_MODE_0</h2>
 262
 263 <div class="memitem">
 264 <div class="memproto">
 265       <table class="memname">
 266         <tr>
 267           <td class="memname">#define ARM_NAND_BUS_TIMING_MODE_0&#160;&#160;&#160;(0x00UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#acc98e42d23656734c7f9a8a5421842d6">ARM_NAND_BUS_TIMING_MODE_Pos</a>)</td>
 268         </tr>
 269       </table>
 270 </div><div class="memdoc">
 271
 272 <p>Timing Mode 0 (default) </p>
 273
 274 </div>
 275 </div>
 276 <a id="ga475a339e929eca46e11bc8a7b330aa45" name="ga475a339e929eca46e11bc8a7b330aa45"></a>
 277 <h2 class="memtitle"><span class="permalink"><a href="#ga475a339e929eca46e11bc8a7b330aa45">&#9670;&#160;</a></span>ARM_NAND_BUS_TIMING_MODE_1</h2>
 278
 279 <div class="memitem">
 280 <div class="memproto">
 281       <table class="memname">
 282         <tr>
 283           <td class="memname">#define ARM_NAND_BUS_TIMING_MODE_1&#160;&#160;&#160;(0x01UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#acc98e42d23656734c7f9a8a5421842d6">ARM_NAND_BUS_TIMING_MODE_Pos</a>)</td>
 284         </tr>
 285       </table>
 286 </div><div class="memdoc">
 287
 288 <p>Timing Mode 1. </p>
 289
 290 </div>
 291 </div>
 292 <a id="gaed6154fb03b5516faf0bfd11d7a46309" name="gaed6154fb03b5516faf0bfd11d7a46309"></a>
 293 <h2 class="memtitle"><span class="permalink"><a href="#gaed6154fb03b5516faf0bfd11d7a46309">&#9670;&#160;</a></span>ARM_NAND_BUS_TIMING_MODE_2</h2>
 294
 295 <div class="memitem">
 296 <div class="memproto">
 297       <table class="memname">
 298         <tr>
 299           <td class="memname">#define ARM_NAND_BUS_TIMING_MODE_2&#160;&#160;&#160;(0x02UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#acc98e42d23656734c7f9a8a5421842d6">ARM_NAND_BUS_TIMING_MODE_Pos</a>)</td>
 300         </tr>
 301       </table>
 302 </div><div class="memdoc">
 303
 304 <p>Timing Mode 2. </p>
 305
 306 </div>
 307 </div>
 308 <a id="gacbc4e07e1af6ef0e4c656428e81464a9" name="gacbc4e07e1af6ef0e4c656428e81464a9"></a>
 309 <h2 class="memtitle"><span class="permalink"><a href="#gacbc4e07e1af6ef0e4c656428e81464a9">&#9670;&#160;</a></span>ARM_NAND_BUS_TIMING_MODE_3</h2>
 310
 311 <div class="memitem">
 312 <div class="memproto">
 313       <table class="memname">
 314         <tr>
 315           <td class="memname">#define ARM_NAND_BUS_TIMING_MODE_3&#160;&#160;&#160;(0x03UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#acc98e42d23656734c7f9a8a5421842d6">ARM_NAND_BUS_TIMING_MODE_Pos</a>)</td>
 316         </tr>
 317       </table>
 318 </div><div class="memdoc">
 319
 320 <p>Timing Mode 3. </p>
 321
 322 </div>
 323 </div>
 324 <a id="ga709d51a5215cd23ce2d85aec57141456" name="ga709d51a5215cd23ce2d85aec57141456"></a>
 325 <h2 class="memtitle"><span class="permalink"><a href="#ga709d51a5215cd23ce2d85aec57141456">&#9670;&#160;</a></span>ARM_NAND_BUS_TIMING_MODE_4</h2>
 326
 327 <div class="memitem">
 328 <div class="memproto">
 329       <table class="memname">
 330         <tr>
 331           <td class="memname">#define ARM_NAND_BUS_TIMING_MODE_4&#160;&#160;&#160;(0x04UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#acc98e42d23656734c7f9a8a5421842d6">ARM_NAND_BUS_TIMING_MODE_Pos</a>)</td>
 332         </tr>
 333       </table>
 334 </div><div class="memdoc">
 335
 336 <p>Timing Mode 4 (SDR EDO capable) </p>
 337
 338 </div>
 339 </div>
 340 <a id="gaee3cad14ce2b8b9af69149bf74597791" name="gaee3cad14ce2b8b9af69149bf74597791"></a>
 341 <h2 class="memtitle"><span class="permalink"><a href="#gaee3cad14ce2b8b9af69149bf74597791">&#9670;&#160;</a></span>ARM_NAND_BUS_TIMING_MODE_5</h2>
 342
 343 <div class="memitem">
 344 <div class="memproto">
 345       <table class="memname">
 346         <tr>
 347           <td class="memname">#define ARM_NAND_BUS_TIMING_MODE_5&#160;&#160;&#160;(0x05UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#acc98e42d23656734c7f9a8a5421842d6">ARM_NAND_BUS_TIMING_MODE_Pos</a>)</td>
 348         </tr>
 349       </table>
 350 </div><div class="memdoc">
 351
 352 <p>Timing Mode 5 (SDR EDO capable) </p>
 353
 354 </div>
 355 </div>
 356 <a id="ga4a3524e0eba994b3a66e06cde877f0f6" name="ga4a3524e0eba994b3a66e06cde877f0f6"></a>
 357 <h2 class="memtitle"><span class="permalink"><a href="#ga4a3524e0eba994b3a66e06cde877f0f6">&#9670;&#160;</a></span>ARM_NAND_BUS_TIMING_MODE_6</h2>
 358
 359 <div class="memitem">
 360 <div class="memproto">
 361       <table class="memname">
 362         <tr>
 363           <td class="memname">#define ARM_NAND_BUS_TIMING_MODE_6&#160;&#160;&#160;(0x06UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#acc98e42d23656734c7f9a8a5421842d6">ARM_NAND_BUS_TIMING_MODE_Pos</a>)</td>
 364         </tr>
 365       </table>
 366 </div><div class="memdoc">
 367
 368 <p>Timing Mode 6 (NV-DDR2 only) </p>
 369
 370 </div>
 371 </div>
 372 <a id="gaa63d75f5f2b48a7345a066d58de1bd23" name="gaa63d75f5f2b48a7345a066d58de1bd23"></a>
 373 <h2 class="memtitle"><span class="permalink"><a href="#gaa63d75f5f2b48a7345a066d58de1bd23">&#9670;&#160;</a></span>ARM_NAND_BUS_TIMING_MODE_7</h2>
 374
 375 <div class="memitem">
 376 <div class="memproto">
 377       <table class="memname">
 378         <tr>
 379           <td class="memname">#define ARM_NAND_BUS_TIMING_MODE_7&#160;&#160;&#160;(0x07UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#acc98e42d23656734c7f9a8a5421842d6">ARM_NAND_BUS_TIMING_MODE_Pos</a>)</td>
 380         </tr>
 381       </table>
 382 </div><div class="memdoc">
 383
 384 <p>Timing Mode 7 (NV-DDR2 only) </p>
 385
 386 </div>
 387 </div>
 388 <a id="ga77348df5f5c2c96bcaeec60b6da02c1b" name="ga77348df5f5c2c96bcaeec60b6da02c1b"></a>
 389 <h2 class="memtitle"><span class="permalink"><a href="#ga77348df5f5c2c96bcaeec60b6da02c1b">&#9670;&#160;</a></span>ARM_NAND_BUS_DDR2_DO_WCYC_0</h2>
 390
 391 <div class="memitem">
 392 <div class="memproto">
 393       <table class="memname">
 394         <tr>
 395           <td class="memname">#define ARM_NAND_BUS_DDR2_DO_WCYC_0&#160;&#160;&#160;(0x00UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#a57b282c0818c87b79ea4f11d03cc4f3c">ARM_NAND_BUS_DDR2_DO_WCYC_Pos</a>)</td>
 396         </tr>
 397       </table>
 398 </div><div class="memdoc">
 399
 400 <p>DDR2 Data Output Warm-up cycles: 0 (default) </p>
 401
 402 </div>
 403 </div>
 404 <a id="ga5839be0b4b2eb930ec039a3403b5e89e" name="ga5839be0b4b2eb930ec039a3403b5e89e"></a>
 405 <h2 class="memtitle"><span class="permalink"><a href="#ga5839be0b4b2eb930ec039a3403b5e89e">&#9670;&#160;</a></span>ARM_NAND_BUS_DDR2_DO_WCYC_1</h2>
 406
 407 <div class="memitem">
 408 <div class="memproto">
 409       <table class="memname">
 410         <tr>
 411           <td class="memname">#define ARM_NAND_BUS_DDR2_DO_WCYC_1&#160;&#160;&#160;(0x01UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#a57b282c0818c87b79ea4f11d03cc4f3c">ARM_NAND_BUS_DDR2_DO_WCYC_Pos</a>)</td>
 412         </tr>
 413       </table>
 414 </div><div class="memdoc">
 415
 416 <p>DDR2 Data Output Warm-up cycles: 1. </p>
 417
 418 </div>
 419 </div>
 420 <a id="ga10a1ef3be69bfa7e6cc657bee751a077" name="ga10a1ef3be69bfa7e6cc657bee751a077"></a>
 421 <h2 class="memtitle"><span class="permalink"><a href="#ga10a1ef3be69bfa7e6cc657bee751a077">&#9670;&#160;</a></span>ARM_NAND_BUS_DDR2_DO_WCYC_2</h2>
 422
 423 <div class="memitem">
 424 <div class="memproto">
 425       <table class="memname">
 426         <tr>
 427           <td class="memname">#define ARM_NAND_BUS_DDR2_DO_WCYC_2&#160;&#160;&#160;(0x02UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#a57b282c0818c87b79ea4f11d03cc4f3c">ARM_NAND_BUS_DDR2_DO_WCYC_Pos</a>)</td>
 428         </tr>
 429       </table>
 430 </div><div class="memdoc">
 431
 432 <p>DDR2 Data Output Warm-up cycles: 2. </p>
 433
 434 </div>
 435 </div>
 436 <a id="ga7f9e8416c4a4e20c4a04323e39f2100d" name="ga7f9e8416c4a4e20c4a04323e39f2100d"></a>
 437 <h2 class="memtitle"><span class="permalink"><a href="#ga7f9e8416c4a4e20c4a04323e39f2100d">&#9670;&#160;</a></span>ARM_NAND_BUS_DDR2_DO_WCYC_4</h2>
 438
 439 <div class="memitem">
 440 <div class="memproto">
 441       <table class="memname">
 442         <tr>
 443           <td class="memname">#define ARM_NAND_BUS_DDR2_DO_WCYC_4&#160;&#160;&#160;(0x03UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#a57b282c0818c87b79ea4f11d03cc4f3c">ARM_NAND_BUS_DDR2_DO_WCYC_Pos</a>)</td>
 444         </tr>
 445       </table>
 446 </div><div class="memdoc">
 447
 448 <p>DDR2 Data Output Warm-up cycles: 4. </p>
 449
 450 </div>
 451 </div>
 452 <a id="gaeee1853dea5e96cb19d2596cc0e70169" name="gaeee1853dea5e96cb19d2596cc0e70169"></a>
 453 <h2 class="memtitle"><span class="permalink"><a href="#gaeee1853dea5e96cb19d2596cc0e70169">&#9670;&#160;</a></span>ARM_NAND_BUS_DDR2_DI_WCYC_0</h2>
 454
 455 <div class="memitem">
 456 <div class="memproto">
 457       <table class="memname">
 458         <tr>
 459           <td class="memname">#define ARM_NAND_BUS_DDR2_DI_WCYC_0&#160;&#160;&#160;(0x00UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#aa80b898cdf665aa14ff0e181e4ff31f1">ARM_NAND_BUS_DDR2_DI_WCYC_Pos</a>)</td>
 460         </tr>
 461       </table>
 462 </div><div class="memdoc">
 463
 464 <p>DDR2 Data Input Warm-up cycles: 0 (default) </p>
 465
 466 </div>
 467 </div>
 468 <a id="ga42560a1f046e20cc4956276156c4ce25" name="ga42560a1f046e20cc4956276156c4ce25"></a>
 469 <h2 class="memtitle"><span class="permalink"><a href="#ga42560a1f046e20cc4956276156c4ce25">&#9670;&#160;</a></span>ARM_NAND_BUS_DDR2_DI_WCYC_1</h2>
 470
 471 <div class="memitem">
 472 <div class="memproto">
 473       <table class="memname">
 474         <tr>
 475           <td class="memname">#define ARM_NAND_BUS_DDR2_DI_WCYC_1&#160;&#160;&#160;(0x01UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#aa80b898cdf665aa14ff0e181e4ff31f1">ARM_NAND_BUS_DDR2_DI_WCYC_Pos</a>)</td>
 476         </tr>
 477       </table>
 478 </div><div class="memdoc">
 479
 480 <p>DDR2 Data Input Warm-up cycles: 1. </p>
 481
 482 </div>
 483 </div>
 484 <a id="gaad2e7807292d84a5070143626f5c2756" name="gaad2e7807292d84a5070143626f5c2756"></a>
 485 <h2 class="memtitle"><span class="permalink"><a href="#gaad2e7807292d84a5070143626f5c2756">&#9670;&#160;</a></span>ARM_NAND_BUS_DDR2_DI_WCYC_2</h2>
 486
 487 <div class="memitem">
 488 <div class="memproto">
 489       <table class="memname">
 490         <tr>
 491           <td class="memname">#define ARM_NAND_BUS_DDR2_DI_WCYC_2&#160;&#160;&#160;(0x02UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#aa80b898cdf665aa14ff0e181e4ff31f1">ARM_NAND_BUS_DDR2_DI_WCYC_Pos</a>)</td>
 492         </tr>
 493       </table>
 494 </div><div class="memdoc">
 495
 496 <p>DDR2 Data Input Warm-up cycles: 2. </p>
 497
 498 </div>
 499 </div>
 500 <a id="ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5" name="ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5"></a>
 501 <h2 class="memtitle"><span class="permalink"><a href="#ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5">&#9670;&#160;</a></span>ARM_NAND_BUS_DDR2_DI_WCYC_4</h2>
 502
 503 <div class="memitem">
 504 <div class="memproto">
 505       <table class="memname">
 506         <tr>
 507           <td class="memname">#define ARM_NAND_BUS_DDR2_DI_WCYC_4&#160;&#160;&#160;(0x03UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#aa80b898cdf665aa14ff0e181e4ff31f1">ARM_NAND_BUS_DDR2_DI_WCYC_Pos</a>)</td>
 508         </tr>
 509       </table>
 510 </div><div class="memdoc">
 511
 512 <p>DDR2 Data Input Warm-up cycles: 4. </p>
 513
 514 </div>
 515 </div>
 516 <a id="ga465ae06a6e097959620346304182e273" name="ga465ae06a6e097959620346304182e273"></a>
 517 <h2 class="memtitle"><span class="permalink"><a href="#ga465ae06a6e097959620346304182e273">&#9670;&#160;</a></span>ARM_NAND_BUS_DDR2_VEN</h2>
 518
 519 <div class="memitem">
 520 <div class="memproto">
 521       <table class="memname">
 522         <tr>
 523           <td class="memname">#define ARM_NAND_BUS_DDR2_VEN&#160;&#160;&#160;(1UL &lt;&lt; 16)</td>
 524         </tr>
 525       </table>
 526 </div><div class="memdoc">
 527
 528 <p>DDR2 Enable external VREFQ as reference. </p>
 529
 530 </div>
 531 </div>
 532 <a id="gad38354e4a34adbf881afc7f89ff06e89" name="gad38354e4a34adbf881afc7f89ff06e89"></a>
 533 <h2 class="memtitle"><span class="permalink"><a href="#gad38354e4a34adbf881afc7f89ff06e89">&#9670;&#160;</a></span>ARM_NAND_BUS_DDR2_CMPD</h2>
 534
 535 <div class="memitem">
 536 <div class="memproto">
 537       <table class="memname">
 538         <tr>
 539           <td class="memname">#define ARM_NAND_BUS_DDR2_CMPD&#160;&#160;&#160;(1UL &lt;&lt; 17)</td>
 540         </tr>
 541       </table>
 542 </div><div class="memdoc">
 543
 544 <p>DDR2 Enable complementary DQS (DQS_c) signal. </p>
 545
 546 </div>
 547 </div>
 548 <a id="ga8a2d599082b9fe56cee1c6454bb3c6a1" name="ga8a2d599082b9fe56cee1c6454bb3c6a1"></a>
 549 <h2 class="memtitle"><span class="permalink"><a href="#ga8a2d599082b9fe56cee1c6454bb3c6a1">&#9670;&#160;</a></span>ARM_NAND_BUS_DDR2_CMPR</h2>
 550
 551 <div class="memitem">
 552 <div class="memproto">
 553       <table class="memname">
 554         <tr>
 555           <td class="memname">#define ARM_NAND_BUS_DDR2_CMPR&#160;&#160;&#160;(1UL &lt;&lt; 18)</td>
 556         </tr>
 557       </table>
 558 </div><div class="memdoc">
 559
 560 <p>DDR2 Enable complementary RE_n (RE_c) signal. </p>
 561
 562 </div>
 563 </div>
 564 </div><!-- contents -->
 565 </div><!-- doc-content -->
 566 <!-- start footer part -->
 567 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
 568   <ul>
 569     <li class="footer">
 570       <script type="text/javascript">
 571         <!--
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