begriffs open source - cmsis/blob - CMSIS/Driver/DriverTemplates/Driver_NAND.c

   1 /*
   2  * Copyright (c) 2013-2019 Arm Limited. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: Apache-2.0
   5  *
   6  * Licensed under the Apache License, Version 2.0 (the License); you may
   7  * not use this file except in compliance with the License.
   8  * You may obtain a copy of the License at
   9  *
  10  * www.apache.org/licenses/LICENSE-2.0
  11  *
  12  * Unless required by applicable law or agreed to in writing, software
  13  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  14  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  15  * See the License for the specific language governing permissions and
  16  * limitations under the License.
  17  */
  18
  19 #include "Driver_NAND.h"
  20
  21 #define ARM_NAND_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0)   /* driver version */
  22
  23 /* Driver Version */
  24 static const ARM_DRIVER_VERSION DriverVersion = {
  25   ARM_NAND_API_VERSION,
  26   ARM_NAND_DRV_VERSION
  27 };
  28
  29 /* Driver Capabilities */
  30 static const ARM_NAND_CAPABILITIES DriverCapabilities = {
  31   0,                 /* Signal Device Ready event (R/Bn rising edge)                        */
  32   0,                 /* Supports re-entrant operation (SendCommand/Address, Read/WriteData) */
  33   0,                 /* Supports Sequence operation (ExecuteSequence, AbortSequence)        */
  34   0,                 /* Supports VCC Power Supply Control                                   */
  35   0,                 /* Supports 1.8 VCC Power Supply                                       */
  36   0,                 /* Supports VCCQ I/O Power Supply Control                              */
  37   0,                 /* Supports 1.8 VCCQ I/O Power Supply                                  */
  38   0,                 /* Supports VPP High Voltage Power Supply Control                      */
  39   0,                 /* Supports WPn (Write Protect) Control                                */
  40   0,                 /* Number of CEn (Chip Enable) lines: ce_lines + 1                     */
  41   0,                 /* Supports manual CEn (Chip Enable) Control                           */
  42   0,                 /* Supports R/Bn (Ready/Busy) Monitoring                               */
  43   0,                 /* Supports 16-bit data                                                */
  44   0,                 /* Supports NV-DDR  Data Interface (ONFI)                              */
  45   0,                 /* Supports NV-DDR2 Data Interface (ONFI)                              */
  46   0,                 /* Fastest (highest) SDR     Timing Mode supported (ONFI)              */
  47   0,                 /* Fastest (highest) NV_DDR  Timing Mode supported (ONFI)              */
  48   0,                 /* Fastest (highest) NV_DDR2 Timing Mode supported (ONFI)              */
  49   0,                 /* Supports Driver Strength 2.0x = 18 Ohms                             */
  50   0,                 /* Supports Driver Strength 1.4x = 25 Ohms                             */
  51   0,                 /* Supports Driver Strength 0.7x = 50 Ohms                             */
  52 #if (ARM_NAND_API_VERSION > 0x201U)
  53   0                  /* Reserved (must be zero)                                             */
  54 #endif
  55 };
  56
  57 /* Exported functions */
  58
  59 static ARM_DRIVER_VERSION GetVersion (void) {
  60   return DriverVersion;
  61 }
  62
  63 static ARM_NAND_CAPABILITIES GetCapabilities (void) {
  64   return DriverCapabilities;
  65 }
  66
  67 static int32_t Initialize (ARM_NAND_SignalEvent_t cb_event) {
  68   (void)cb_event;
  69   return ARM_DRIVER_ERROR_UNSUPPORTED;
  70 }
  71
  72 static int32_t Uninitialize (void) {
  73   return ARM_DRIVER_ERROR_UNSUPPORTED;
  74 }
  75
  76 static int32_t PowerControl (ARM_POWER_STATE state) {
  77
  78   switch ((int32_t)state) {
  79     case ARM_POWER_OFF:
  80       return ARM_DRIVER_ERROR_UNSUPPORTED;
  81
  82     case ARM_POWER_LOW:
  83       return ARM_DRIVER_ERROR_UNSUPPORTED;
  84
  85     case ARM_POWER_FULL:
  86       return ARM_DRIVER_ERROR_UNSUPPORTED;
  87
  88     default:
  89       return ARM_DRIVER_ERROR_UNSUPPORTED;
  90   }
  91   return ARM_DRIVER_OK;
  92 }
  93
  94 static int32_t DevicePower (uint32_t voltage) {
  95   (void)voltage;
  96   return ARM_DRIVER_ERROR_UNSUPPORTED;
  97 }
  98
  99 static int32_t WriteProtect (uint32_t dev_num, bool enable) {
 100   (void)dev_num; (void)enable;
 101   return ARM_DRIVER_ERROR_UNSUPPORTED;
 102 }
 103
 104 static int32_t ChipEnable (uint32_t dev_num, bool enable) {
 105   (void)dev_num; (void)enable;
 106   return ARM_DRIVER_ERROR_UNSUPPORTED;
 107 }
 108
 109 static int32_t GetDeviceBusy (uint32_t dev_num) {
 110   (void)dev_num;
 111   return ARM_DRIVER_ERROR_UNSUPPORTED;
 112 }
 113
 114 static int32_t SendCommand (uint32_t dev_num, uint8_t cmd) {
 115   (void)dev_num; (void)cmd;
 116   return ARM_DRIVER_ERROR_UNSUPPORTED;
 117 }
 118
 119 static int32_t SendAddress (uint32_t dev_num, uint8_t addr) {
 120   (void)dev_num; (void)addr;
 121   return ARM_DRIVER_ERROR_UNSUPPORTED;
 122 }
 123
 124 static int32_t ReadData (uint32_t dev_num, void *data, uint32_t cnt, uint32_t mode) {
 125   (void)dev_num; (void)data; (void)cnt; (void)mode;
 126   return ARM_DRIVER_ERROR_UNSUPPORTED;
 127 }
 128
 129 static int32_t WriteData (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode) {
 130   (void)dev_num; (void)data; (void)cnt; (void)mode;
 131   return ARM_DRIVER_ERROR_UNSUPPORTED;
 132 }
 133
 134 static int32_t ExecuteSequence (uint32_t dev_num, uint32_t code, uint32_t cmd,
 135                                 uint32_t addr_col, uint32_t addr_row,
 136                                 void *data, uint32_t data_cnt,
 137                                 uint8_t *status, uint32_t *count) {
 138   (void)dev_num; (void)code; (void)cmd;
 139   (void)addr_col; (void)addr_row;
 140   (void)data; (void)data_cnt;
 141   (void)status; (void)count;
 142
 143   return ARM_DRIVER_ERROR_UNSUPPORTED;
 144 }
 145
 146 static int32_t AbortSequence (uint32_t dev_num) {
 147   (void)dev_num;
 148
 149   return ARM_DRIVER_ERROR_UNSUPPORTED;
 150 }
 151
 152 static int32_t Control (uint32_t dev_num, uint32_t control, uint32_t arg) {
 153
 154   switch (control) {
 155     case ARM_NAND_BUS_MODE:
 156       return ARM_DRIVER_ERROR_UNSUPPORTED;
 157
 158     case ARM_NAND_BUS_DATA_WIDTH:
 159       return ARM_DRIVER_ERROR_UNSUPPORTED;
 160
 161     case ARM_NAND_DEVICE_READY_EVENT:
 162       return ARM_DRIVER_ERROR_UNSUPPORTED;
 163
 164     default:
 165       return ARM_DRIVER_ERROR_UNSUPPORTED;
 166   }
 167
 168   return ARM_DRIVER_ERROR;
 169 }
 170
 171 static ARM_NAND_STATUS GetStatus (uint32_t dev_num) {
 172   (void)dev_num;
 173
 174   stat.busy      = 0U;
 175   stat.ecc_error = 0U;
 176
 177   return stat;
 178 }
 179
 180 static int32_t InquireECC (int32_t index, ARM_NAND_ECC_INFO *info) {
 181   (void)index; (void)info;
 182   return ARM_DRIVER_ERROR_UNSUPPORTED;
 183 }
 184
 185 /* NAND Driver Control Block */
 186 extern
 187 ARM_DRIVER_NAND Driver_NAND_(NAND_DRIVER);
 188 ARM_DRIVER_NAND Driver_NAND_(NAND_DRIVER) = {
 189   GetVersion,
 190   GetCapabilities,
 191   Initialize,
 192   Uninitialize,
 193   PowerControl,
 194   DevicePower,
 195   WriteProtect,
 196   ChipEnable,
 197   GetDeviceBusy,
 198   SendCommand,
 199   SendAddress,
 200   ReadData,
 201   WriteData,
 202   ExecuteSequence,
 203   AbortSequence,
 204   Control,
 205   GetStatus,
 206   InquireECC
 207 };