begriffs open source - cmsis/blob - main/Core_A/group__CMSIS__CPSR__M.html

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 126 <div class="header">
 127   <div class="summary">
 128 <a href="#define-members">Macros</a>  </div>
 129   <div class="headertitle"><div class="title">CPSR M field values<div class="ingroups"><a class="el" href="group__CMSIS__core__register.html">Core Register Access</a> &raquo; <a class="el" href="group__CMSIS__CPSR.html">Current Program Status Register (CPSR)</a></div></div></div>
 130 </div><!--header-->
 131 <div class="contents">
 132
 133 <p>Valid values for CPSR M field.
 134 <a href="#details">More...</a></p>
 135 <table class="memberdecls">
 136 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a>
 137 Macros</h2></td></tr>
 138 <tr class="memitem:gad716a0ee4dc815f0f01e1339d6511a4e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#gad716a0ee4dc815f0f01e1339d6511a4e">CPSR_M_USR</a>&#160;&#160;&#160;0x10U</td></tr>
 139 <tr class="memdesc:gad716a0ee4dc815f0f01e1339d6511a4e"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPSR: M User mode (PL0)  <br /></td></tr>
 140 <tr class="separator:gad716a0ee4dc815f0f01e1339d6511a4e"><td class="memSeparator" colspan="2">&#160;</td></tr>
 141 <tr class="memitem:ga868ef12e003f541f90a613ca7f6ada74"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#ga868ef12e003f541f90a613ca7f6ada74">CPSR_M_FIQ</a>&#160;&#160;&#160;0x11U</td></tr>
 142 <tr class="memdesc:ga868ef12e003f541f90a613ca7f6ada74"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPSR: M Fast Interrupt mode (PL1)  <br /></td></tr>
 143 <tr class="separator:ga868ef12e003f541f90a613ca7f6ada74"><td class="memSeparator" colspan="2">&#160;</td></tr>
 144 <tr class="memitem:gada3f31a773f7fc7bf6567d598cf3a1db"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#gada3f31a773f7fc7bf6567d598cf3a1db">CPSR_M_IRQ</a>&#160;&#160;&#160;0x12U</td></tr>
 145 <tr class="memdesc:gada3f31a773f7fc7bf6567d598cf3a1db"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPSR: M Interrupt mode (PL1)  <br /></td></tr>
 146 <tr class="separator:gada3f31a773f7fc7bf6567d598cf3a1db"><td class="memSeparator" colspan="2">&#160;</td></tr>
 147 <tr class="memitem:ga5afcb85bd2968acc2b09cb9d99c531ad"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#ga5afcb85bd2968acc2b09cb9d99c531ad">CPSR_M_SVC</a>&#160;&#160;&#160;0x13U</td></tr>
 148 <tr class="memdesc:ga5afcb85bd2968acc2b09cb9d99c531ad"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPSR: M Supervisor mode (PL1)  <br /></td></tr>
 149 <tr class="separator:ga5afcb85bd2968acc2b09cb9d99c531ad"><td class="memSeparator" colspan="2">&#160;</td></tr>
 150 <tr class="memitem:ga69d734db93f67899b4bffcf62f80f098"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#ga69d734db93f67899b4bffcf62f80f098">CPSR_M_MON</a>&#160;&#160;&#160;0x16U</td></tr>
 151 <tr class="memdesc:ga69d734db93f67899b4bffcf62f80f098"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPSR: M Monitor mode (PL1)  <br /></td></tr>
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 153 <tr class="memitem:gac8c0a99a21ef256f5d3115595a845bfa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#gac8c0a99a21ef256f5d3115595a845bfa">CPSR_M_ABT</a>&#160;&#160;&#160;0x17U</td></tr>
 154 <tr class="memdesc:gac8c0a99a21ef256f5d3115595a845bfa"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPSR: M Abort mode (PL1)  <br /></td></tr>
 155 <tr class="separator:gac8c0a99a21ef256f5d3115595a845bfa"><td class="memSeparator" colspan="2">&#160;</td></tr>
 156 <tr class="memitem:ga002c78f542ca5c5fdd02d2aeee9f6988"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#ga002c78f542ca5c5fdd02d2aeee9f6988">CPSR_M_HYP</a>&#160;&#160;&#160;0x1AU</td></tr>
 157 <tr class="memdesc:ga002c78f542ca5c5fdd02d2aeee9f6988"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPSR: M Hypervisor mode (PL2)  <br /></td></tr>
 158 <tr class="separator:ga002c78f542ca5c5fdd02d2aeee9f6988"><td class="memSeparator" colspan="2">&#160;</td></tr>
 159 <tr class="memitem:ga07d4f42d6971c2f0cc25872008ddf5ef"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#ga07d4f42d6971c2f0cc25872008ddf5ef">CPSR_M_UND</a>&#160;&#160;&#160;0x1BU</td></tr>
 160 <tr class="memdesc:ga07d4f42d6971c2f0cc25872008ddf5ef"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPSR: M Undefined mode (PL1)  <br /></td></tr>
 161 <tr class="separator:ga07d4f42d6971c2f0cc25872008ddf5ef"><td class="memSeparator" colspan="2">&#160;</td></tr>
 162 <tr class="memitem:gaa0a3996ce096cd205bce34f90b10912c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#gaa0a3996ce096cd205bce34f90b10912c">CPSR_M_SYS</a>&#160;&#160;&#160;0x1FU</td></tr>
 163 <tr class="memdesc:gaa0a3996ce096cd205bce34f90b10912c"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPSR: M System mode (PL1)  <br /></td></tr>
 164 <tr class="separator:gaa0a3996ce096cd205bce34f90b10912c"><td class="memSeparator" colspan="2">&#160;</td></tr>
 165 </table>
 166 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
 167 <p>Valid values for CPSR M field. </p>
 168 <p>The M field can contain one of these values which indicates the current processor mode. </p>
 169 <h2 class="groupheader">Macro Definition Documentation</h2>
 170 <a id="gac8c0a99a21ef256f5d3115595a845bfa" name="gac8c0a99a21ef256f5d3115595a845bfa"></a>
 171 <h2 class="memtitle"><span class="permalink"><a href="#gac8c0a99a21ef256f5d3115595a845bfa">&#9670;&#160;</a></span>CPSR_M_ABT</h2>
 172
 173 <div class="memitem">
 174 <div class="memproto">
 175       <table class="memname">
 176         <tr>
 177           <td class="memname">#define CPSR_M_ABT&#160;&#160;&#160;0x17U</td>
 178         </tr>
 179       </table>
 180 </div><div class="memdoc">
 181
 182 <p>CPSR: M Abort mode (PL1) </p>
 183 <p>Abort mode is the default mode to which a Data Abort exception or Prefetch Abort exception is taken. </p>
 184
 185 </div>
 186 </div>
 187 <a id="ga868ef12e003f541f90a613ca7f6ada74" name="ga868ef12e003f541f90a613ca7f6ada74"></a>
 188 <h2 class="memtitle"><span class="permalink"><a href="#ga868ef12e003f541f90a613ca7f6ada74">&#9670;&#160;</a></span>CPSR_M_FIQ</h2>
 189
 190 <div class="memitem">
 191 <div class="memproto">
 192       <table class="memname">
 193         <tr>
 194           <td class="memname">#define CPSR_M_FIQ&#160;&#160;&#160;0x11U</td>
 195         </tr>
 196       </table>
 197 </div><div class="memdoc">
 198
 199 <p>CPSR: M Fast Interrupt mode (PL1) </p>
 200 <p>FIQ mode is the default mode to which an FIQ interrupt is taken. </p>
 201
 202 </div>
 203 </div>
 204 <a id="ga002c78f542ca5c5fdd02d2aeee9f6988" name="ga002c78f542ca5c5fdd02d2aeee9f6988"></a>
 205 <h2 class="memtitle"><span class="permalink"><a href="#ga002c78f542ca5c5fdd02d2aeee9f6988">&#9670;&#160;</a></span>CPSR_M_HYP</h2>
 206
 207 <div class="memitem">
 208 <div class="memproto">
 209       <table class="memname">
 210         <tr>
 211           <td class="memname">#define CPSR_M_HYP&#160;&#160;&#160;0x1AU</td>
 212         </tr>
 213       </table>
 214 </div><div class="memdoc">
 215
 216 <p>CPSR: M Hypervisor mode (PL2) </p>
 217 <p>Hyp mode is the Non-secure PL2 mode, implemented as part of the Virtualization Extensions. Hyp mode is entered on taking an exception from Non-secure state that must be taken to PL2. </p>
 218
 219 </div>
 220 </div>
 221 <a id="gada3f31a773f7fc7bf6567d598cf3a1db" name="gada3f31a773f7fc7bf6567d598cf3a1db"></a>
 222 <h2 class="memtitle"><span class="permalink"><a href="#gada3f31a773f7fc7bf6567d598cf3a1db">&#9670;&#160;</a></span>CPSR_M_IRQ</h2>
 223
 224 <div class="memitem">
 225 <div class="memproto">
 226       <table class="memname">
 227         <tr>
 228           <td class="memname">#define CPSR_M_IRQ&#160;&#160;&#160;0x12U</td>
 229         </tr>
 230       </table>
 231 </div><div class="memdoc">
 232
 233 <p>CPSR: M Interrupt mode (PL1) </p>
 234 <p>IRQ mode is the default mode to which an IRQ interrupt is taken. </p>
 235
 236 </div>
 237 </div>
 238 <a id="ga69d734db93f67899b4bffcf62f80f098" name="ga69d734db93f67899b4bffcf62f80f098"></a>
 239 <h2 class="memtitle"><span class="permalink"><a href="#ga69d734db93f67899b4bffcf62f80f098">&#9670;&#160;</a></span>CPSR_M_MON</h2>
 240
 241 <div class="memitem">
 242 <div class="memproto">
 243       <table class="memname">
 244         <tr>
 245           <td class="memname">#define CPSR_M_MON&#160;&#160;&#160;0x16U</td>
 246         </tr>
 247       </table>
 248 </div><div class="memdoc">
 249
 250 <p>CPSR: M Monitor mode (PL1) </p>
 251 <p>Monitor mode is the mode to which a Secure Monitor Call exception is taken. </p>
 252
 253 </div>
 254 </div>
 255 <a id="ga5afcb85bd2968acc2b09cb9d99c531ad" name="ga5afcb85bd2968acc2b09cb9d99c531ad"></a>
 256 <h2 class="memtitle"><span class="permalink"><a href="#ga5afcb85bd2968acc2b09cb9d99c531ad">&#9670;&#160;</a></span>CPSR_M_SVC</h2>
 257
 258 <div class="memitem">
 259 <div class="memproto">
 260       <table class="memname">
 261         <tr>
 262           <td class="memname">#define CPSR_M_SVC&#160;&#160;&#160;0x13U</td>
 263         </tr>
 264       </table>
 265 </div><div class="memdoc">
 266
 267 <p>CPSR: M Supervisor mode (PL1) </p>
 268 <p>Supervisor mode is the default mode to which a Supervisor Call exception is taken. </p>
 269
 270 </div>
 271 </div>
 272 <a id="gaa0a3996ce096cd205bce34f90b10912c" name="gaa0a3996ce096cd205bce34f90b10912c"></a>
 273 <h2 class="memtitle"><span class="permalink"><a href="#gaa0a3996ce096cd205bce34f90b10912c">&#9670;&#160;</a></span>CPSR_M_SYS</h2>
 274
 275 <div class="memitem">
 276 <div class="memproto">
 277       <table class="memname">
 278         <tr>
 279           <td class="memname">#define CPSR_M_SYS&#160;&#160;&#160;0x1FU</td>
 280         </tr>
 281       </table>
 282 </div><div class="memdoc">
 283
 284 <p>CPSR: M System mode (PL1) </p>
 285 <p>Software executing in System mode executes at PL1. System mode has the same registers available as User mode, and is not entered by any exception. </p>
 286
 287 </div>
 288 </div>
 289 <a id="ga07d4f42d6971c2f0cc25872008ddf5ef" name="ga07d4f42d6971c2f0cc25872008ddf5ef"></a>
 290 <h2 class="memtitle"><span class="permalink"><a href="#ga07d4f42d6971c2f0cc25872008ddf5ef">&#9670;&#160;</a></span>CPSR_M_UND</h2>
 291
 292 <div class="memitem">
 293 <div class="memproto">
 294       <table class="memname">
 295         <tr>
 296           <td class="memname">#define CPSR_M_UND&#160;&#160;&#160;0x1BU</td>
 297         </tr>
 298       </table>
 299 </div><div class="memdoc">
 300
 301 <p>CPSR: M Undefined mode (PL1) </p>
 302 <p>Undefined mode is the default mode to which an instruction-related exception, including any attempt to execute an UNDEFINED instruction, is taken. </p>
 303
 304 </div>
 305 </div>
 306 <a id="gad716a0ee4dc815f0f01e1339d6511a4e" name="gad716a0ee4dc815f0f01e1339d6511a4e"></a>
 307 <h2 class="memtitle"><span class="permalink"><a href="#gad716a0ee4dc815f0f01e1339d6511a4e">&#9670;&#160;</a></span>CPSR_M_USR</h2>
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 313           <td class="memname">#define CPSR_M_USR&#160;&#160;&#160;0x10U</td>
 314         </tr>
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 317
 318 <p>CPSR: M User mode (PL0) </p>
 319 <p>An operating system runs applications in User mode to restrict the use of system resources. Software executing in User mode executes at PL0. Execution in User mode is sometimes described as unprivileged execution. </p>
 320
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