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52 <div id="projectbrief">CMSIS-Core support for Cortex-A processor-based devices</div>
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127 <div class="summary">
128 <a href="#define-members">Macros</a> </div>
129 <div class="headertitle"><div class="title">SCTLR Bits<div class="ingroups"><a class="el" href="group__CMSIS__core__register.html">Core Register Access</a> » <a class="el" href="group__CMSIS__SCTLR.html">System Control Register (SCTLR)</a></div></div></div>
131 <div class="contents">
133 <p>Bit position and mask macros.
134 <a href="#details">More...</a></p>
135 <table class="memberdecls">
136 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a>
137 Macros</h2></td></tr>
138 <tr class="memitem:gab0a611e2359e04624379e1ddd4dc64b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gab0a611e2359e04624379e1ddd4dc64b1">SCTLR_TE_Pos</a>   30U</td></tr>
139 <tr class="memdesc:gab0a611e2359e04624379e1ddd4dc64b1"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: TE Position. <br /></td></tr>
140 <tr class="separator:gab0a611e2359e04624379e1ddd4dc64b1"><td class="memSeparator" colspan="2"> </td></tr>
141 <tr class="memitem:ga4a68d6660c76951ada2541ceaf040b3b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga4a68d6660c76951ada2541ceaf040b3b">SCTLR_TE_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gab0a611e2359e04624379e1ddd4dc64b1">SCTLR_TE_Pos</a>)</td></tr>
142 <tr class="memdesc:ga4a68d6660c76951ada2541ceaf040b3b"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: TE Mask. <br /></td></tr>
143 <tr class="separator:ga4a68d6660c76951ada2541ceaf040b3b"><td class="memSeparator" colspan="2"> </td></tr>
144 <tr class="memitem:ga4ac80ef4db2641dc9e6e8df0825a151e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga4ac80ef4db2641dc9e6e8df0825a151e">SCTLR_AFE_Pos</a>   29U</td></tr>
145 <tr class="memdesc:ga4ac80ef4db2641dc9e6e8df0825a151e"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: AFE Position. <br /></td></tr>
146 <tr class="separator:ga4ac80ef4db2641dc9e6e8df0825a151e"><td class="memSeparator" colspan="2"> </td></tr>
147 <tr class="memitem:ga9016d6e50562d2584c1f1a95bde1e957"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga9016d6e50562d2584c1f1a95bde1e957">SCTLR_AFE_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga4ac80ef4db2641dc9e6e8df0825a151e">SCTLR_AFE_Pos</a>)</td></tr>
148 <tr class="memdesc:ga9016d6e50562d2584c1f1a95bde1e957"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: AFE Mask. <br /></td></tr>
149 <tr class="separator:ga9016d6e50562d2584c1f1a95bde1e957"><td class="memSeparator" colspan="2"> </td></tr>
150 <tr class="memitem:gaf76fa48119363f9b88c2c8f5b74e0a04"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gaf76fa48119363f9b88c2c8f5b74e0a04">SCTLR_TRE_Pos</a>   28U</td></tr>
151 <tr class="memdesc:gaf76fa48119363f9b88c2c8f5b74e0a04"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: TRE Position. <br /></td></tr>
152 <tr class="separator:gaf76fa48119363f9b88c2c8f5b74e0a04"><td class="memSeparator" colspan="2"> </td></tr>
153 <tr class="memitem:gab0481eb9812a4908601cb20c8ae84918"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gab0481eb9812a4908601cb20c8ae84918">SCTLR_TRE_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gaf76fa48119363f9b88c2c8f5b74e0a04">SCTLR_TRE_Pos</a>)</td></tr>
154 <tr class="memdesc:gab0481eb9812a4908601cb20c8ae84918"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: TRE Mask. <br /></td></tr>
155 <tr class="separator:gab0481eb9812a4908601cb20c8ae84918"><td class="memSeparator" colspan="2"> </td></tr>
156 <tr class="memitem:gac1cf872c51ed0baa6ed23e26c1ed35a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gac1cf872c51ed0baa6ed23e26c1ed35a9">SCTLR_NMFI_Pos</a>   27U</td></tr>
157 <tr class="memdesc:gac1cf872c51ed0baa6ed23e26c1ed35a9"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: NMFI Position. <br /></td></tr>
158 <tr class="separator:gac1cf872c51ed0baa6ed23e26c1ed35a9"><td class="memSeparator" colspan="2"> </td></tr>
159 <tr class="memitem:gab92a3bd63ad9ac3d408e1b615bedc279"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gab92a3bd63ad9ac3d408e1b615bedc279">SCTLR_NMFI_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gac1cf872c51ed0baa6ed23e26c1ed35a9">SCTLR_NMFI_Pos</a>)</td></tr>
160 <tr class="memdesc:gab92a3bd63ad9ac3d408e1b615bedc279"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: NMFI Mask. <br /></td></tr>
161 <tr class="separator:gab92a3bd63ad9ac3d408e1b615bedc279"><td class="memSeparator" colspan="2"> </td></tr>
162 <tr class="memitem:ga0baec19421bd41277c5d8783c59942fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga0baec19421bd41277c5d8783c59942fa">SCTLR_EE_Pos</a>   25U</td></tr>
163 <tr class="memdesc:ga0baec19421bd41277c5d8783c59942fa"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: EE Position. <br /></td></tr>
164 <tr class="separator:ga0baec19421bd41277c5d8783c59942fa"><td class="memSeparator" colspan="2"> </td></tr>
165 <tr class="memitem:ga8d95cd61bc40dc77f8855f40c797d044"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga8d95cd61bc40dc77f8855f40c797d044">SCTLR_EE_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga0baec19421bd41277c5d8783c59942fa">SCTLR_EE_Pos</a>)</td></tr>
166 <tr class="memdesc:ga8d95cd61bc40dc77f8855f40c797d044"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: EE Mask. <br /></td></tr>
167 <tr class="separator:ga8d95cd61bc40dc77f8855f40c797d044"><td class="memSeparator" colspan="2"> </td></tr>
168 <tr class="memitem:ga1372b569553a0740d881e24c0be7334f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga1372b569553a0740d881e24c0be7334f">SCTLR_VE_Pos</a>   24U</td></tr>
169 <tr class="memdesc:ga1372b569553a0740d881e24c0be7334f"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: VE Position. <br /></td></tr>
170 <tr class="separator:ga1372b569553a0740d881e24c0be7334f"><td class="memSeparator" colspan="2"> </td></tr>
171 <tr class="memitem:gad94a7feadba850299a68c56e39c0b274"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gad94a7feadba850299a68c56e39c0b274">SCTLR_VE_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga1372b569553a0740d881e24c0be7334f">SCTLR_VE_Pos</a>)</td></tr>
172 <tr class="memdesc:gad94a7feadba850299a68c56e39c0b274"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: VE Mask. <br /></td></tr>
173 <tr class="separator:gad94a7feadba850299a68c56e39c0b274"><td class="memSeparator" colspan="2"> </td></tr>
174 <tr class="memitem:gaa0431730d7ce929db03d8accee558e17"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gaa0431730d7ce929db03d8accee558e17">SCTLR_U_Pos</a>   22U</td></tr>
175 <tr class="memdesc:gaa0431730d7ce929db03d8accee558e17"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: U Position. <br /></td></tr>
176 <tr class="separator:gaa0431730d7ce929db03d8accee558e17"><td class="memSeparator" colspan="2"> </td></tr>
177 <tr class="memitem:gaa047daa7ab35b5ad5dd238c7377a232f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gaa047daa7ab35b5ad5dd238c7377a232f">SCTLR_U_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gaa0431730d7ce929db03d8accee558e17">SCTLR_U_Pos</a>)</td></tr>
178 <tr class="memdesc:gaa047daa7ab35b5ad5dd238c7377a232f"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: U Mask. <br /></td></tr>
179 <tr class="separator:gaa047daa7ab35b5ad5dd238c7377a232f"><td class="memSeparator" colspan="2"> </td></tr>
180 <tr class="memitem:gad88d563fa9a8b09fe36702a5329b0360"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gad88d563fa9a8b09fe36702a5329b0360">SCTLR_FI_Pos</a>   21U</td></tr>
181 <tr class="memdesc:gad88d563fa9a8b09fe36702a5329b0360"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: FI Position. <br /></td></tr>
182 <tr class="separator:gad88d563fa9a8b09fe36702a5329b0360"><td class="memSeparator" colspan="2"> </td></tr>
183 <tr class="memitem:ga316b80925b88fe3b88ec46a55655b0bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga316b80925b88fe3b88ec46a55655b0bc">SCTLR_FI_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gad88d563fa9a8b09fe36702a5329b0360">SCTLR_FI_Pos</a>)</td></tr>
184 <tr class="memdesc:ga316b80925b88fe3b88ec46a55655b0bc"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: FI Mask. <br /></td></tr>
185 <tr class="separator:ga316b80925b88fe3b88ec46a55655b0bc"><td class="memSeparator" colspan="2"> </td></tr>
186 <tr class="memitem:ga7c7d88f3db4de438ddd069cf3fbc88b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga7c7d88f3db4de438ddd069cf3fbc88b3">SCTLR_UWXN_Pos</a>   20U</td></tr>
187 <tr class="memdesc:ga7c7d88f3db4de438ddd069cf3fbc88b3"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: UWXN Position. <br /></td></tr>
188 <tr class="separator:ga7c7d88f3db4de438ddd069cf3fbc88b3"><td class="memSeparator" colspan="2"> </td></tr>
189 <tr class="memitem:gab834e64e0da7c2a98d747ce73252c199"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gab834e64e0da7c2a98d747ce73252c199">SCTLR_UWXN_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga7c7d88f3db4de438ddd069cf3fbc88b3">SCTLR_UWXN_Pos</a>)</td></tr>
190 <tr class="memdesc:gab834e64e0da7c2a98d747ce73252c199"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: UWXN Mask. <br /></td></tr>
191 <tr class="separator:gab834e64e0da7c2a98d747ce73252c199"><td class="memSeparator" colspan="2"> </td></tr>
192 <tr class="memitem:gaf145654986fd6d014136580ad279d256"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gaf145654986fd6d014136580ad279d256">SCTLR_WXN_Pos</a>   19U</td></tr>
193 <tr class="memdesc:gaf145654986fd6d014136580ad279d256"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: WXN Position. <br /></td></tr>
194 <tr class="separator:gaf145654986fd6d014136580ad279d256"><td class="memSeparator" colspan="2"> </td></tr>
195 <tr class="memitem:ga510b03214d135f15ad3c5d41ec20a291"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga510b03214d135f15ad3c5d41ec20a291">SCTLR_WXN_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gaf145654986fd6d014136580ad279d256">SCTLR_WXN_Pos</a>)</td></tr>
196 <tr class="memdesc:ga510b03214d135f15ad3c5d41ec20a291"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: WXN Mask. <br /></td></tr>
197 <tr class="separator:ga510b03214d135f15ad3c5d41ec20a291"><td class="memSeparator" colspan="2"> </td></tr>
198 <tr class="memitem:ga316882abba6c9cdd31dbbd7ba46c9f52"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga316882abba6c9cdd31dbbd7ba46c9f52">SCTLR_HA_Pos</a>   17U</td></tr>
199 <tr class="memdesc:ga316882abba6c9cdd31dbbd7ba46c9f52"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: HA Position. <br /></td></tr>
200 <tr class="separator:ga316882abba6c9cdd31dbbd7ba46c9f52"><td class="memSeparator" colspan="2"> </td></tr>
201 <tr class="memitem:ga6830e9bf54a6b548f329ac047f59c179"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga6830e9bf54a6b548f329ac047f59c179">SCTLR_HA_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga316882abba6c9cdd31dbbd7ba46c9f52">SCTLR_HA_Pos</a>)</td></tr>
202 <tr class="memdesc:ga6830e9bf54a6b548f329ac047f59c179"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: HA Mask. <br /></td></tr>
203 <tr class="separator:ga6830e9bf54a6b548f329ac047f59c179"><td class="memSeparator" colspan="2"> </td></tr>
204 <tr class="memitem:ga86e5b78ba8f818061644688db75ddc64"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga86e5b78ba8f818061644688db75ddc64">SCTLR_RR_Pos</a>   14U</td></tr>
205 <tr class="memdesc:ga86e5b78ba8f818061644688db75ddc64"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: RR Position. <br /></td></tr>
206 <tr class="separator:ga86e5b78ba8f818061644688db75ddc64"><td class="memSeparator" colspan="2"> </td></tr>
207 <tr class="memitem:ga1ff9e6766c7e1ca312b025bf34d384bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga1ff9e6766c7e1ca312b025bf34d384bc">SCTLR_RR_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga86e5b78ba8f818061644688db75ddc64">SCTLR_RR_Pos</a>)</td></tr>
208 <tr class="memdesc:ga1ff9e6766c7e1ca312b025bf34d384bc"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: RR Mask. <br /></td></tr>
209 <tr class="separator:ga1ff9e6766c7e1ca312b025bf34d384bc"><td class="memSeparator" colspan="2"> </td></tr>
210 <tr class="memitem:ga57778fd6afbe5b4fe8d8ea828acf833d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga57778fd6afbe5b4fe8d8ea828acf833d">SCTLR_V_Pos</a>   13U</td></tr>
211 <tr class="memdesc:ga57778fd6afbe5b4fe8d8ea828acf833d"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: V Position. <br /></td></tr>
212 <tr class="separator:ga57778fd6afbe5b4fe8d8ea828acf833d"><td class="memSeparator" colspan="2"> </td></tr>
213 <tr class="memitem:gaf84f3f15bf6917acdc5b5a4ad661ac11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gaf84f3f15bf6917acdc5b5a4ad661ac11">SCTLR_V_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga57778fd6afbe5b4fe8d8ea828acf833d">SCTLR_V_Pos</a>)</td></tr>
214 <tr class="memdesc:gaf84f3f15bf6917acdc5b5a4ad661ac11"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: V Mask. <br /></td></tr>
215 <tr class="separator:gaf84f3f15bf6917acdc5b5a4ad661ac11"><td class="memSeparator" colspan="2"> </td></tr>
216 <tr class="memitem:gaaaa818a1da51059bd979f0e768ebcc7c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gaaaa818a1da51059bd979f0e768ebcc7c">SCTLR_I_Pos</a>   12U</td></tr>
217 <tr class="memdesc:gaaaa818a1da51059bd979f0e768ebcc7c"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: I Position. <br /></td></tr>
218 <tr class="separator:gaaaa818a1da51059bd979f0e768ebcc7c"><td class="memSeparator" colspan="2"> </td></tr>
219 <tr class="memitem:gab3cc0744fb07127e3c0f18cba9d51666"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gab3cc0744fb07127e3c0f18cba9d51666">SCTLR_I_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gaaaa818a1da51059bd979f0e768ebcc7c">SCTLR_I_Pos</a>)</td></tr>
220 <tr class="memdesc:gab3cc0744fb07127e3c0f18cba9d51666"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: I Mask. <br /></td></tr>
221 <tr class="separator:gab3cc0744fb07127e3c0f18cba9d51666"><td class="memSeparator" colspan="2"> </td></tr>
222 <tr class="memitem:gaa0eade648c9a34de891af0e6f47857dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gaa0eade648c9a34de891af0e6f47857dd">SCTLR_Z_Pos</a>   11U</td></tr>
223 <tr class="memdesc:gaa0eade648c9a34de891af0e6f47857dd"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: Z Position. <br /></td></tr>
224 <tr class="separator:gaa0eade648c9a34de891af0e6f47857dd"><td class="memSeparator" colspan="2"> </td></tr>
225 <tr class="memitem:ga12a05acdcb8db6e99970f26206d3067c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga12a05acdcb8db6e99970f26206d3067c">SCTLR_Z_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gaa0eade648c9a34de891af0e6f47857dd">SCTLR_Z_Pos</a>)</td></tr>
226 <tr class="memdesc:ga12a05acdcb8db6e99970f26206d3067c"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: Z Mask. <br /></td></tr>
227 <tr class="separator:ga12a05acdcb8db6e99970f26206d3067c"><td class="memSeparator" colspan="2"> </td></tr>
228 <tr class="memitem:ga3290be0882c1493bca9a0db6b4d0bff8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga3290be0882c1493bca9a0db6b4d0bff8">SCTLR_SW_Pos</a>   10U</td></tr>
229 <tr class="memdesc:ga3290be0882c1493bca9a0db6b4d0bff8"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: SW Position. <br /></td></tr>
230 <tr class="separator:ga3290be0882c1493bca9a0db6b4d0bff8"><td class="memSeparator" colspan="2"> </td></tr>
231 <tr class="memitem:gae4074aefcf01786fe199c82e273271b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gae4074aefcf01786fe199c82e273271b8">SCTLR_SW_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga3290be0882c1493bca9a0db6b4d0bff8">SCTLR_SW_Pos</a>)</td></tr>
232 <tr class="memdesc:gae4074aefcf01786fe199c82e273271b8"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: SW Mask. <br /></td></tr>
233 <tr class="separator:gae4074aefcf01786fe199c82e273271b8"><td class="memSeparator" colspan="2"> </td></tr>
234 <tr class="memitem:ga5f185efbe1a9eb5738b2573f076a0859"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga5f185efbe1a9eb5738b2573f076a0859">SCTLR_B_Pos</a>   7U</td></tr>
235 <tr class="memdesc:ga5f185efbe1a9eb5738b2573f076a0859"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: B Position. <br /></td></tr>
236 <tr class="separator:ga5f185efbe1a9eb5738b2573f076a0859"><td class="memSeparator" colspan="2"> </td></tr>
237 <tr class="memitem:ga4853d6f9ccbf919fcdadb0b2a5913cc6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga4853d6f9ccbf919fcdadb0b2a5913cc6">SCTLR_B_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga5f185efbe1a9eb5738b2573f076a0859">SCTLR_B_Pos</a>)</td></tr>
238 <tr class="memdesc:ga4853d6f9ccbf919fcdadb0b2a5913cc6"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: B Mask. <br /></td></tr>
239 <tr class="separator:ga4853d6f9ccbf919fcdadb0b2a5913cc6"><td class="memSeparator" colspan="2"> </td></tr>
240 <tr class="memitem:gace284f69e1a810957665adf0cb2e4b2b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gace284f69e1a810957665adf0cb2e4b2b">SCTLR_CP15BEN_Pos</a>   5U</td></tr>
241 <tr class="memdesc:gace284f69e1a810957665adf0cb2e4b2b"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: CP15BEN Position. <br /></td></tr>
242 <tr class="separator:gace284f69e1a810957665adf0cb2e4b2b"><td class="memSeparator" colspan="2"> </td></tr>
243 <tr class="memitem:ga5541a6a63db4d4d233b8f57b1d46fbac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga5541a6a63db4d4d233b8f57b1d46fbac">SCTLR_CP15BEN_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gace284f69e1a810957665adf0cb2e4b2b">SCTLR_CP15BEN_Pos</a>)</td></tr>
244 <tr class="memdesc:ga5541a6a63db4d4d233b8f57b1d46fbac"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: CP15BEN Mask. <br /></td></tr>
245 <tr class="separator:ga5541a6a63db4d4d233b8f57b1d46fbac"><td class="memSeparator" colspan="2"> </td></tr>
246 <tr class="memitem:ga8a0394c5147b8212767087e3421deffa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga8a0394c5147b8212767087e3421deffa">SCTLR_C_Pos</a>   2U</td></tr>
247 <tr class="memdesc:ga8a0394c5147b8212767087e3421deffa"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: C Position. <br /></td></tr>
248 <tr class="separator:ga8a0394c5147b8212767087e3421deffa"><td class="memSeparator" colspan="2"> </td></tr>
249 <tr class="memitem:ga2be72788d984153ded81711e20fd2d33"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga2be72788d984153ded81711e20fd2d33">SCTLR_C_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga8a0394c5147b8212767087e3421deffa">SCTLR_C_Pos</a>)</td></tr>
250 <tr class="memdesc:ga2be72788d984153ded81711e20fd2d33"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: C Mask. <br /></td></tr>
251 <tr class="separator:ga2be72788d984153ded81711e20fd2d33"><td class="memSeparator" colspan="2"> </td></tr>
252 <tr class="memitem:ga0d667a307e974515ebc15b5249f34146"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga0d667a307e974515ebc15b5249f34146">SCTLR_A_Pos</a>   1U</td></tr>
253 <tr class="memdesc:ga0d667a307e974515ebc15b5249f34146"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: A Position. <br /></td></tr>
254 <tr class="separator:ga0d667a307e974515ebc15b5249f34146"><td class="memSeparator" colspan="2"> </td></tr>
255 <tr class="memitem:ga678c919832272745678213e55211e741"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga678c919832272745678213e55211e741">SCTLR_A_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga0d667a307e974515ebc15b5249f34146">SCTLR_A_Pos</a>)</td></tr>
256 <tr class="memdesc:ga678c919832272745678213e55211e741"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: A Mask. <br /></td></tr>
257 <tr class="separator:ga678c919832272745678213e55211e741"><td class="memSeparator" colspan="2"> </td></tr>
258 <tr class="memitem:ga88e34078fa8cf719aab6f53f138c9810"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga88e34078fa8cf719aab6f53f138c9810">SCTLR_M_Pos</a>   0U</td></tr>
259 <tr class="memdesc:ga88e34078fa8cf719aab6f53f138c9810"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: M Position. <br /></td></tr>
260 <tr class="separator:ga88e34078fa8cf719aab6f53f138c9810"><td class="memSeparator" colspan="2"> </td></tr>
261 <tr class="memitem:gaf460824cdbf549bd914aa79762572e8e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gaf460824cdbf549bd914aa79762572e8e">SCTLR_M_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga88e34078fa8cf719aab6f53f138c9810">SCTLR_M_Pos</a>)</td></tr>
262 <tr class="memdesc:gaf460824cdbf549bd914aa79762572e8e"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: M Mask. <br /></td></tr>
263 <tr class="separator:gaf460824cdbf549bd914aa79762572e8e"><td class="memSeparator" colspan="2"> </td></tr>
265 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
266 <p>Bit position and mask macros. </p>
267 <h2 class="groupheader">Macro Definition Documentation</h2>
268 <a id="ga678c919832272745678213e55211e741" name="ga678c919832272745678213e55211e741"></a>
269 <h2 class="memtitle"><span class="permalink"><a href="#ga678c919832272745678213e55211e741">◆ </a></span>SCTLR_A_Msk</h2>
271 <div class="memitem">
272 <div class="memproto">
273 <table class="memname">
275 <td class="memname">#define SCTLR_A_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga0d667a307e974515ebc15b5249f34146">SCTLR_A_Pos</a>)</td>
278 </div><div class="memdoc">
280 <p>SCTLR: A Mask. </p>
284 <a id="ga0d667a307e974515ebc15b5249f34146" name="ga0d667a307e974515ebc15b5249f34146"></a>
285 <h2 class="memtitle"><span class="permalink"><a href="#ga0d667a307e974515ebc15b5249f34146">◆ </a></span>SCTLR_A_Pos</h2>
287 <div class="memitem">
288 <div class="memproto">
289 <table class="memname">
291 <td class="memname">#define SCTLR_A_Pos   1U</td>
294 </div><div class="memdoc">
296 <p>SCTLR: A Position. </p>
300 <a id="ga9016d6e50562d2584c1f1a95bde1e957" name="ga9016d6e50562d2584c1f1a95bde1e957"></a>
301 <h2 class="memtitle"><span class="permalink"><a href="#ga9016d6e50562d2584c1f1a95bde1e957">◆ </a></span>SCTLR_AFE_Msk</h2>
303 <div class="memitem">
304 <div class="memproto">
305 <table class="memname">
307 <td class="memname">#define SCTLR_AFE_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga4ac80ef4db2641dc9e6e8df0825a151e">SCTLR_AFE_Pos</a>)</td>
310 </div><div class="memdoc">
312 <p>SCTLR: AFE Mask. </p>
316 <a id="ga4ac80ef4db2641dc9e6e8df0825a151e" name="ga4ac80ef4db2641dc9e6e8df0825a151e"></a>
317 <h2 class="memtitle"><span class="permalink"><a href="#ga4ac80ef4db2641dc9e6e8df0825a151e">◆ </a></span>SCTLR_AFE_Pos</h2>
319 <div class="memitem">
320 <div class="memproto">
321 <table class="memname">
323 <td class="memname">#define SCTLR_AFE_Pos   29U</td>
326 </div><div class="memdoc">
328 <p>SCTLR: AFE Position. </p>
332 <a id="ga4853d6f9ccbf919fcdadb0b2a5913cc6" name="ga4853d6f9ccbf919fcdadb0b2a5913cc6"></a>
333 <h2 class="memtitle"><span class="permalink"><a href="#ga4853d6f9ccbf919fcdadb0b2a5913cc6">◆ </a></span>SCTLR_B_Msk</h2>
335 <div class="memitem">
336 <div class="memproto">
337 <table class="memname">
339 <td class="memname">#define SCTLR_B_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga5f185efbe1a9eb5738b2573f076a0859">SCTLR_B_Pos</a>)</td>
342 </div><div class="memdoc">
344 <p>SCTLR: B Mask. </p>
348 <a id="ga5f185efbe1a9eb5738b2573f076a0859" name="ga5f185efbe1a9eb5738b2573f076a0859"></a>
349 <h2 class="memtitle"><span class="permalink"><a href="#ga5f185efbe1a9eb5738b2573f076a0859">◆ </a></span>SCTLR_B_Pos</h2>
351 <div class="memitem">
352 <div class="memproto">
353 <table class="memname">
355 <td class="memname">#define SCTLR_B_Pos   7U</td>
358 </div><div class="memdoc">
360 <p>SCTLR: B Position. </p>
364 <a id="ga2be72788d984153ded81711e20fd2d33" name="ga2be72788d984153ded81711e20fd2d33"></a>
365 <h2 class="memtitle"><span class="permalink"><a href="#ga2be72788d984153ded81711e20fd2d33">◆ </a></span>SCTLR_C_Msk</h2>
367 <div class="memitem">
368 <div class="memproto">
369 <table class="memname">
371 <td class="memname">#define SCTLR_C_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga8a0394c5147b8212767087e3421deffa">SCTLR_C_Pos</a>)</td>
374 </div><div class="memdoc">
376 <p>SCTLR: C Mask. </p>
380 <a id="ga8a0394c5147b8212767087e3421deffa" name="ga8a0394c5147b8212767087e3421deffa"></a>
381 <h2 class="memtitle"><span class="permalink"><a href="#ga8a0394c5147b8212767087e3421deffa">◆ </a></span>SCTLR_C_Pos</h2>
383 <div class="memitem">
384 <div class="memproto">
385 <table class="memname">
387 <td class="memname">#define SCTLR_C_Pos   2U</td>
390 </div><div class="memdoc">
392 <p>SCTLR: C Position. </p>
396 <a id="ga5541a6a63db4d4d233b8f57b1d46fbac" name="ga5541a6a63db4d4d233b8f57b1d46fbac"></a>
397 <h2 class="memtitle"><span class="permalink"><a href="#ga5541a6a63db4d4d233b8f57b1d46fbac">◆ </a></span>SCTLR_CP15BEN_Msk</h2>
399 <div class="memitem">
400 <div class="memproto">
401 <table class="memname">
403 <td class="memname">#define SCTLR_CP15BEN_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gace284f69e1a810957665adf0cb2e4b2b">SCTLR_CP15BEN_Pos</a>)</td>
406 </div><div class="memdoc">
408 <p>SCTLR: CP15BEN Mask. </p>
412 <a id="gace284f69e1a810957665adf0cb2e4b2b" name="gace284f69e1a810957665adf0cb2e4b2b"></a>
413 <h2 class="memtitle"><span class="permalink"><a href="#gace284f69e1a810957665adf0cb2e4b2b">◆ </a></span>SCTLR_CP15BEN_Pos</h2>
415 <div class="memitem">
416 <div class="memproto">
417 <table class="memname">
419 <td class="memname">#define SCTLR_CP15BEN_Pos   5U</td>
422 </div><div class="memdoc">
424 <p>SCTLR: CP15BEN Position. </p>
428 <a id="ga8d95cd61bc40dc77f8855f40c797d044" name="ga8d95cd61bc40dc77f8855f40c797d044"></a>
429 <h2 class="memtitle"><span class="permalink"><a href="#ga8d95cd61bc40dc77f8855f40c797d044">◆ </a></span>SCTLR_EE_Msk</h2>
431 <div class="memitem">
432 <div class="memproto">
433 <table class="memname">
435 <td class="memname">#define SCTLR_EE_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga0baec19421bd41277c5d8783c59942fa">SCTLR_EE_Pos</a>)</td>
438 </div><div class="memdoc">
440 <p>SCTLR: EE Mask. </p>
444 <a id="ga0baec19421bd41277c5d8783c59942fa" name="ga0baec19421bd41277c5d8783c59942fa"></a>
445 <h2 class="memtitle"><span class="permalink"><a href="#ga0baec19421bd41277c5d8783c59942fa">◆ </a></span>SCTLR_EE_Pos</h2>
447 <div class="memitem">
448 <div class="memproto">
449 <table class="memname">
451 <td class="memname">#define SCTLR_EE_Pos   25U</td>
454 </div><div class="memdoc">
456 <p>SCTLR: EE Position. </p>
460 <a id="ga316b80925b88fe3b88ec46a55655b0bc" name="ga316b80925b88fe3b88ec46a55655b0bc"></a>
461 <h2 class="memtitle"><span class="permalink"><a href="#ga316b80925b88fe3b88ec46a55655b0bc">◆ </a></span>SCTLR_FI_Msk</h2>
463 <div class="memitem">
464 <div class="memproto">
465 <table class="memname">
467 <td class="memname">#define SCTLR_FI_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gad88d563fa9a8b09fe36702a5329b0360">SCTLR_FI_Pos</a>)</td>
470 </div><div class="memdoc">
472 <p>SCTLR: FI Mask. </p>
476 <a id="gad88d563fa9a8b09fe36702a5329b0360" name="gad88d563fa9a8b09fe36702a5329b0360"></a>
477 <h2 class="memtitle"><span class="permalink"><a href="#gad88d563fa9a8b09fe36702a5329b0360">◆ </a></span>SCTLR_FI_Pos</h2>
479 <div class="memitem">
480 <div class="memproto">
481 <table class="memname">
483 <td class="memname">#define SCTLR_FI_Pos   21U</td>
486 </div><div class="memdoc">
488 <p>SCTLR: FI Position. </p>
492 <a id="ga6830e9bf54a6b548f329ac047f59c179" name="ga6830e9bf54a6b548f329ac047f59c179"></a>
493 <h2 class="memtitle"><span class="permalink"><a href="#ga6830e9bf54a6b548f329ac047f59c179">◆ </a></span>SCTLR_HA_Msk</h2>
495 <div class="memitem">
496 <div class="memproto">
497 <table class="memname">
499 <td class="memname">#define SCTLR_HA_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga316882abba6c9cdd31dbbd7ba46c9f52">SCTLR_HA_Pos</a>)</td>
502 </div><div class="memdoc">
504 <p>SCTLR: HA Mask. </p>
508 <a id="ga316882abba6c9cdd31dbbd7ba46c9f52" name="ga316882abba6c9cdd31dbbd7ba46c9f52"></a>
509 <h2 class="memtitle"><span class="permalink"><a href="#ga316882abba6c9cdd31dbbd7ba46c9f52">◆ </a></span>SCTLR_HA_Pos</h2>
511 <div class="memitem">
512 <div class="memproto">
513 <table class="memname">
515 <td class="memname">#define SCTLR_HA_Pos   17U</td>
518 </div><div class="memdoc">
520 <p>SCTLR: HA Position. </p>
524 <a id="gab3cc0744fb07127e3c0f18cba9d51666" name="gab3cc0744fb07127e3c0f18cba9d51666"></a>
525 <h2 class="memtitle"><span class="permalink"><a href="#gab3cc0744fb07127e3c0f18cba9d51666">◆ </a></span>SCTLR_I_Msk</h2>
527 <div class="memitem">
528 <div class="memproto">
529 <table class="memname">
531 <td class="memname">#define SCTLR_I_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gaaaa818a1da51059bd979f0e768ebcc7c">SCTLR_I_Pos</a>)</td>
534 </div><div class="memdoc">
536 <p>SCTLR: I Mask. </p>
540 <a id="gaaaa818a1da51059bd979f0e768ebcc7c" name="gaaaa818a1da51059bd979f0e768ebcc7c"></a>
541 <h2 class="memtitle"><span class="permalink"><a href="#gaaaa818a1da51059bd979f0e768ebcc7c">◆ </a></span>SCTLR_I_Pos</h2>
543 <div class="memitem">
544 <div class="memproto">
545 <table class="memname">
547 <td class="memname">#define SCTLR_I_Pos   12U</td>
550 </div><div class="memdoc">
552 <p>SCTLR: I Position. </p>
556 <a id="gaf460824cdbf549bd914aa79762572e8e" name="gaf460824cdbf549bd914aa79762572e8e"></a>
557 <h2 class="memtitle"><span class="permalink"><a href="#gaf460824cdbf549bd914aa79762572e8e">◆ </a></span>SCTLR_M_Msk</h2>
559 <div class="memitem">
560 <div class="memproto">
561 <table class="memname">
563 <td class="memname">#define SCTLR_M_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga88e34078fa8cf719aab6f53f138c9810">SCTLR_M_Pos</a>)</td>
566 </div><div class="memdoc">
568 <p>SCTLR: M Mask. </p>
572 <a id="ga88e34078fa8cf719aab6f53f138c9810" name="ga88e34078fa8cf719aab6f53f138c9810"></a>
573 <h2 class="memtitle"><span class="permalink"><a href="#ga88e34078fa8cf719aab6f53f138c9810">◆ </a></span>SCTLR_M_Pos</h2>
575 <div class="memitem">
576 <div class="memproto">
577 <table class="memname">
579 <td class="memname">#define SCTLR_M_Pos   0U</td>
582 </div><div class="memdoc">
584 <p>SCTLR: M Position. </p>
588 <a id="gab92a3bd63ad9ac3d408e1b615bedc279" name="gab92a3bd63ad9ac3d408e1b615bedc279"></a>
589 <h2 class="memtitle"><span class="permalink"><a href="#gab92a3bd63ad9ac3d408e1b615bedc279">◆ </a></span>SCTLR_NMFI_Msk</h2>
591 <div class="memitem">
592 <div class="memproto">
593 <table class="memname">
595 <td class="memname">#define SCTLR_NMFI_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gac1cf872c51ed0baa6ed23e26c1ed35a9">SCTLR_NMFI_Pos</a>)</td>
598 </div><div class="memdoc">
600 <p>SCTLR: NMFI Mask. </p>
604 <a id="gac1cf872c51ed0baa6ed23e26c1ed35a9" name="gac1cf872c51ed0baa6ed23e26c1ed35a9"></a>
605 <h2 class="memtitle"><span class="permalink"><a href="#gac1cf872c51ed0baa6ed23e26c1ed35a9">◆ </a></span>SCTLR_NMFI_Pos</h2>
607 <div class="memitem">
608 <div class="memproto">
609 <table class="memname">
611 <td class="memname">#define SCTLR_NMFI_Pos   27U</td>
614 </div><div class="memdoc">
616 <p>SCTLR: NMFI Position. </p>
620 <a id="ga1ff9e6766c7e1ca312b025bf34d384bc" name="ga1ff9e6766c7e1ca312b025bf34d384bc"></a>
621 <h2 class="memtitle"><span class="permalink"><a href="#ga1ff9e6766c7e1ca312b025bf34d384bc">◆ </a></span>SCTLR_RR_Msk</h2>
623 <div class="memitem">
624 <div class="memproto">
625 <table class="memname">
627 <td class="memname">#define SCTLR_RR_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga86e5b78ba8f818061644688db75ddc64">SCTLR_RR_Pos</a>)</td>
630 </div><div class="memdoc">
632 <p>SCTLR: RR Mask. </p>
636 <a id="ga86e5b78ba8f818061644688db75ddc64" name="ga86e5b78ba8f818061644688db75ddc64"></a>
637 <h2 class="memtitle"><span class="permalink"><a href="#ga86e5b78ba8f818061644688db75ddc64">◆ </a></span>SCTLR_RR_Pos</h2>
639 <div class="memitem">
640 <div class="memproto">
641 <table class="memname">
643 <td class="memname">#define SCTLR_RR_Pos   14U</td>
646 </div><div class="memdoc">
648 <p>SCTLR: RR Position. </p>
652 <a id="gae4074aefcf01786fe199c82e273271b8" name="gae4074aefcf01786fe199c82e273271b8"></a>
653 <h2 class="memtitle"><span class="permalink"><a href="#gae4074aefcf01786fe199c82e273271b8">◆ </a></span>SCTLR_SW_Msk</h2>
655 <div class="memitem">
656 <div class="memproto">
657 <table class="memname">
659 <td class="memname">#define SCTLR_SW_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga3290be0882c1493bca9a0db6b4d0bff8">SCTLR_SW_Pos</a>)</td>
662 </div><div class="memdoc">
664 <p>SCTLR: SW Mask. </p>
668 <a id="ga3290be0882c1493bca9a0db6b4d0bff8" name="ga3290be0882c1493bca9a0db6b4d0bff8"></a>
669 <h2 class="memtitle"><span class="permalink"><a href="#ga3290be0882c1493bca9a0db6b4d0bff8">◆ </a></span>SCTLR_SW_Pos</h2>
671 <div class="memitem">
672 <div class="memproto">
673 <table class="memname">
675 <td class="memname">#define SCTLR_SW_Pos   10U</td>
678 </div><div class="memdoc">
680 <p>SCTLR: SW Position. </p>
684 <a id="ga4a68d6660c76951ada2541ceaf040b3b" name="ga4a68d6660c76951ada2541ceaf040b3b"></a>
685 <h2 class="memtitle"><span class="permalink"><a href="#ga4a68d6660c76951ada2541ceaf040b3b">◆ </a></span>SCTLR_TE_Msk</h2>
687 <div class="memitem">
688 <div class="memproto">
689 <table class="memname">
691 <td class="memname">#define SCTLR_TE_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gab0a611e2359e04624379e1ddd4dc64b1">SCTLR_TE_Pos</a>)</td>
694 </div><div class="memdoc">
696 <p>SCTLR: TE Mask. </p>
700 <a id="gab0a611e2359e04624379e1ddd4dc64b1" name="gab0a611e2359e04624379e1ddd4dc64b1"></a>
701 <h2 class="memtitle"><span class="permalink"><a href="#gab0a611e2359e04624379e1ddd4dc64b1">◆ </a></span>SCTLR_TE_Pos</h2>
703 <div class="memitem">
704 <div class="memproto">
705 <table class="memname">
707 <td class="memname">#define SCTLR_TE_Pos   30U</td>
710 </div><div class="memdoc">
712 <p>SCTLR: TE Position. </p>
716 <a id="gab0481eb9812a4908601cb20c8ae84918" name="gab0481eb9812a4908601cb20c8ae84918"></a>
717 <h2 class="memtitle"><span class="permalink"><a href="#gab0481eb9812a4908601cb20c8ae84918">◆ </a></span>SCTLR_TRE_Msk</h2>
719 <div class="memitem">
720 <div class="memproto">
721 <table class="memname">
723 <td class="memname">#define SCTLR_TRE_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gaf76fa48119363f9b88c2c8f5b74e0a04">SCTLR_TRE_Pos</a>)</td>
726 </div><div class="memdoc">
728 <p>SCTLR: TRE Mask. </p>
732 <a id="gaf76fa48119363f9b88c2c8f5b74e0a04" name="gaf76fa48119363f9b88c2c8f5b74e0a04"></a>
733 <h2 class="memtitle"><span class="permalink"><a href="#gaf76fa48119363f9b88c2c8f5b74e0a04">◆ </a></span>SCTLR_TRE_Pos</h2>
735 <div class="memitem">
736 <div class="memproto">
737 <table class="memname">
739 <td class="memname">#define SCTLR_TRE_Pos   28U</td>
742 </div><div class="memdoc">
744 <p>SCTLR: TRE Position. </p>
748 <a id="gaa047daa7ab35b5ad5dd238c7377a232f" name="gaa047daa7ab35b5ad5dd238c7377a232f"></a>
749 <h2 class="memtitle"><span class="permalink"><a href="#gaa047daa7ab35b5ad5dd238c7377a232f">◆ </a></span>SCTLR_U_Msk</h2>
751 <div class="memitem">
752 <div class="memproto">
753 <table class="memname">
755 <td class="memname">#define SCTLR_U_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gaa0431730d7ce929db03d8accee558e17">SCTLR_U_Pos</a>)</td>
758 </div><div class="memdoc">
760 <p>SCTLR: U Mask. </p>
764 <a id="gaa0431730d7ce929db03d8accee558e17" name="gaa0431730d7ce929db03d8accee558e17"></a>
765 <h2 class="memtitle"><span class="permalink"><a href="#gaa0431730d7ce929db03d8accee558e17">◆ </a></span>SCTLR_U_Pos</h2>
767 <div class="memitem">
768 <div class="memproto">
769 <table class="memname">
771 <td class="memname">#define SCTLR_U_Pos   22U</td>
774 </div><div class="memdoc">
776 <p>SCTLR: U Position. </p>
780 <a id="gab834e64e0da7c2a98d747ce73252c199" name="gab834e64e0da7c2a98d747ce73252c199"></a>
781 <h2 class="memtitle"><span class="permalink"><a href="#gab834e64e0da7c2a98d747ce73252c199">◆ </a></span>SCTLR_UWXN_Msk</h2>
783 <div class="memitem">
784 <div class="memproto">
785 <table class="memname">
787 <td class="memname">#define SCTLR_UWXN_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga7c7d88f3db4de438ddd069cf3fbc88b3">SCTLR_UWXN_Pos</a>)</td>
790 </div><div class="memdoc">
792 <p>SCTLR: UWXN Mask. </p>
796 <a id="ga7c7d88f3db4de438ddd069cf3fbc88b3" name="ga7c7d88f3db4de438ddd069cf3fbc88b3"></a>
797 <h2 class="memtitle"><span class="permalink"><a href="#ga7c7d88f3db4de438ddd069cf3fbc88b3">◆ </a></span>SCTLR_UWXN_Pos</h2>
799 <div class="memitem">
800 <div class="memproto">
801 <table class="memname">
803 <td class="memname">#define SCTLR_UWXN_Pos   20U</td>
806 </div><div class="memdoc">
808 <p>SCTLR: UWXN Position. </p>
812 <a id="gaf84f3f15bf6917acdc5b5a4ad661ac11" name="gaf84f3f15bf6917acdc5b5a4ad661ac11"></a>
813 <h2 class="memtitle"><span class="permalink"><a href="#gaf84f3f15bf6917acdc5b5a4ad661ac11">◆ </a></span>SCTLR_V_Msk</h2>
815 <div class="memitem">
816 <div class="memproto">
817 <table class="memname">
819 <td class="memname">#define SCTLR_V_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga57778fd6afbe5b4fe8d8ea828acf833d">SCTLR_V_Pos</a>)</td>
822 </div><div class="memdoc">
824 <p>SCTLR: V Mask. </p>
828 <a id="ga57778fd6afbe5b4fe8d8ea828acf833d" name="ga57778fd6afbe5b4fe8d8ea828acf833d"></a>
829 <h2 class="memtitle"><span class="permalink"><a href="#ga57778fd6afbe5b4fe8d8ea828acf833d">◆ </a></span>SCTLR_V_Pos</h2>
831 <div class="memitem">
832 <div class="memproto">
833 <table class="memname">
835 <td class="memname">#define SCTLR_V_Pos   13U</td>
838 </div><div class="memdoc">
840 <p>SCTLR: V Position. </p>
844 <a id="gad94a7feadba850299a68c56e39c0b274" name="gad94a7feadba850299a68c56e39c0b274"></a>
845 <h2 class="memtitle"><span class="permalink"><a href="#gad94a7feadba850299a68c56e39c0b274">◆ </a></span>SCTLR_VE_Msk</h2>
847 <div class="memitem">
848 <div class="memproto">
849 <table class="memname">
851 <td class="memname">#define SCTLR_VE_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga1372b569553a0740d881e24c0be7334f">SCTLR_VE_Pos</a>)</td>
854 </div><div class="memdoc">
856 <p>SCTLR: VE Mask. </p>
860 <a id="ga1372b569553a0740d881e24c0be7334f" name="ga1372b569553a0740d881e24c0be7334f"></a>
861 <h2 class="memtitle"><span class="permalink"><a href="#ga1372b569553a0740d881e24c0be7334f">◆ </a></span>SCTLR_VE_Pos</h2>
863 <div class="memitem">
864 <div class="memproto">
865 <table class="memname">
867 <td class="memname">#define SCTLR_VE_Pos   24U</td>
870 </div><div class="memdoc">
872 <p>SCTLR: VE Position. </p>
876 <a id="ga510b03214d135f15ad3c5d41ec20a291" name="ga510b03214d135f15ad3c5d41ec20a291"></a>
877 <h2 class="memtitle"><span class="permalink"><a href="#ga510b03214d135f15ad3c5d41ec20a291">◆ </a></span>SCTLR_WXN_Msk</h2>
879 <div class="memitem">
880 <div class="memproto">
881 <table class="memname">
883 <td class="memname">#define SCTLR_WXN_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gaf145654986fd6d014136580ad279d256">SCTLR_WXN_Pos</a>)</td>
886 </div><div class="memdoc">
888 <p>SCTLR: WXN Mask. </p>
892 <a id="gaf145654986fd6d014136580ad279d256" name="gaf145654986fd6d014136580ad279d256"></a>
893 <h2 class="memtitle"><span class="permalink"><a href="#gaf145654986fd6d014136580ad279d256">◆ </a></span>SCTLR_WXN_Pos</h2>
895 <div class="memitem">
896 <div class="memproto">
897 <table class="memname">
899 <td class="memname">#define SCTLR_WXN_Pos   19U</td>
902 </div><div class="memdoc">
904 <p>SCTLR: WXN Position. </p>
908 <a id="ga12a05acdcb8db6e99970f26206d3067c" name="ga12a05acdcb8db6e99970f26206d3067c"></a>
909 <h2 class="memtitle"><span class="permalink"><a href="#ga12a05acdcb8db6e99970f26206d3067c">◆ </a></span>SCTLR_Z_Msk</h2>
911 <div class="memitem">
912 <div class="memproto">
913 <table class="memname">
915 <td class="memname">#define SCTLR_Z_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gaa0eade648c9a34de891af0e6f47857dd">SCTLR_Z_Pos</a>)</td>
918 </div><div class="memdoc">
920 <p>SCTLR: Z Mask. </p>
924 <a id="gaa0eade648c9a34de891af0e6f47857dd" name="gaa0eade648c9a34de891af0e6f47857dd"></a>
925 <h2 class="memtitle"><span class="permalink"><a href="#gaa0eade648c9a34de891af0e6f47857dd">◆ </a></span>SCTLR_Z_Pos</h2>
927 <div class="memitem">
928 <div class="memproto">
929 <table class="memname">
931 <td class="memname">#define SCTLR_Z_Pos   11U</td>
934 </div><div class="memdoc">
936 <p>SCTLR: Z Position. </p>
940 </div><!-- contents -->
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