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   1 # Revision History {#core_revisionHistory}
   2
   3 CMSIS-Core (M) component is maintained with its own versioning that gets offically updated upon releases of the [CMSIS Software Pack](../General/cmsis_pack.html).
   4
   5 The table below provides information about the changes delivered with specific versions of CMSIS-Core (M).
   6
   7 <table class="cmtable" summary="Revision History">
   8     <tr>
   9       <th>Version</th>
  10       <th>Description</th>
  11     </tr>
  12     <tr>
  13       <td>V5.7.0</td>
  14       <td>
  15         <ul>
  16           <li>Added: Added new compiler macros \ref __ALIAS and \ref __NO_INIT</li>
  17         </ul>
  18       </td>
  19     </tr>
  20     <tr>
  21       <td>V5.6.0</td>
  22       <td>
  23         <ul>
  24           <li>Added: Arm Cortex-M85 cpu support</li>
  25           <li>Added: Arm China Star-MC1 cpu support</li>
  26           <li>Updated: system_ARMCM55.c</li>
  27         </ul>
  28       </td>
  29     </tr>
  30     <tr>
  31       <td>V5.5.0</td>
  32       <td>
  33         <ul>
  34           <li>Updated GCC LinkerDescription, GCC Assembler startup</li>
  35           <li>Added ARMv8-M Stack Sealing (to linker, startup) for toolchain ARM, GCC</li>
  36           <li>Changed C-Startup to default Startup.</li>
  37           </li>
  38             Updated Armv8-M Assembler startup to use GAS syntax<br>
  39             Note: Updating existing projects may need manual user interaction!
  40           </li>
  41         </ul>
  42       </td>
  43     </tr>
  44     <tr>
  45       <td>V5.4.0</td>
  46       <td>
  47         <ul>
  48           <li>Added: Cortex-M55 cpu support</li>
  49           <li>Enhanced: MVE support for Armv8.1-MML</li>
  50           <li>Fixed: Device config define checks</li>
  51           <li>Added: \ref cache_functions_m7 for Armv7-M and later</li>
  52         </ul>
  53       </td>
  54     </tr>
  55     <tr>
  56       <td>V5.3.0</td>
  57       <td>
  58         <ul>
  59           <li>Added: Provisions for compiler-independent C startup code.</li>
  60         </ul>
  61       </td>
  62     </tr>
  63     <tr>
  64       <td>V5.2.1</td>
  65       <td>
  66         <ul>
  67           <li>Fixed: Compilation issue in cmsis_armclang_ltm.h introduced in 5.2.0</li>
  68         </ul>
  69       </td>
  70     </tr>
  71     <tr>
  72       <td>V5.2.0</td>
  73       <td>
  74         <ul>
  75           <li>Added: Cortex-M35P support.</li>
  76           <li>Added: Cortex-M1 support.
  77           <li>Added: Armv8.1 architecture support.
  78           <li>Added: \ref __RESTRICT and \ref __STATIC_FORCEINLINE compiler control macros.
  79         </ul>
  80       </td>
  81     </tr>
  82     <tr>
  83       <td>V5.1.2</td>
  84       <td>
  85         <ul>
  86           <li>Removed using get/set built-ins FPSCR in GCC >= 7.2 due to shortcomings.</li>
  87           <li>Added __NO_RETURN to  __NVIC_SystemReset() to silence compiler warnings.</li>
  88           <li>Added support for Cortex-M1 (beta).</li>
  89           <li>Removed usage of register keyword.</li>
  90           <li>Added defines for EXC_RETURN, FNC_RETURN and integrity signature values.</li>
  91           <li>Enhanced MPUv7 API with defines for memory access attributes.</li>
  92         </ul>
  93       </td>
  94     </tr>
  95     <tr>
  96       <td>V5.1.1</td>
  97       <td>
  98         <ul>
  99           <li>Aligned MSPLIM and PSPLIM access functions along supported compilers.</li>
 100         </ul>
 101       </td>
 102     </tr>
 103     <tr>
 104       <td>V5.1.0</td>
 105       <td>
 106         <ul>
 107           <li>Added MPU Functions for ARMv8-M for Cortex-M23/M33.</li>
 108           <li>Moved __SSAT and __USAT intrinsics to CMSIS-Core.</li>
 109           <li>Aligned __REV, __REV16 and __REVSH intrinsics along supported compilers.</li>
 110         </ul>
 111       </td>
 112     </tr>
 113     <tr>
 114       <td>V5.0.2</td>
 115       <td>
 116         <ul>
 117           <li>Added macros  \ref \__UNALIGNED_UINT16_READ,  \ref \__UNALIGNED_UINT16_WRITE.</li>
 118           <li>Added macros  \ref \__UNALIGNED_UINT32_READ,  \ref \__UNALIGNED_UINT32_WRITE.</li>
 119           <li>Deprecated macro __UNALIGNED_UINT32.</li>
 120           <li>Changed \ref version_control_gr macros to be core agnostic.</li>
 121           <li>Added \ref mpu_functions for Cortex-M0+/M3/M4/M7.</li>
 122         </ul>
 123       </td>
 124     </tr>
 125     <tr>
 126       <td>V5.0.1</td>
 127       <td>
 128         <ul>
 129           <li>Added: macro \ref \__PACKED_STRUCT.</li>
 130           <li>Added: uVisor support.</li>
 131         </ul>
 132       </td>
 133     </tr>
 134     <tr>
 135       <td>V5.00</td>
 136       <td>
 137         <ul>
 138           <li>Added: Cortex-M23, Cortex-M33 support.</li>
 139           <li>Added: macro __SAU_PRESENT with __SAU_REGION_PRESENT.</li>
 140           <li>Replaced: macro __SAU_PRESENT with __SAU_REGION_PRESENT.</li>
 141           <li>Reworked: SAU register and functions.</li>
 142           <li>Added: macro \ref \__ALIGNED.</li>
 143           <li>Updated: function \ref SCB_EnableICache.</li>
 144           <li>Added: cmsis_compiler.h with compiler specific CMSIS macros, functions, instructions.</li>
 145           <li>Added: macro \ref \__PACKED.</li>
 146           <li>Updated: compiler specific include files.</li>
 147           <li>Updated: core dependant include files.</li>
 148           <li>Removed: deprecated files core_cmfunc.h, core_cminstr.h, core_cmsimd.h.</li>
 149         </ul>
 150       </td>
 151     </tr>
 152     <tr>
 153       <td>V5.00<br>Beta 6</td>
 154       <td>
 155         <ul>
 156           <li>Added: SCB_CFSR register bit definitions.</li>
 157           <li>Added: function \ref NVIC_GetEnableIRQ.</li>
 158           <li>Updated: core instruction macros \ref \__NOP, \ref \__WFI, \ref \__WFE, \ref \__SEV for toolchain GCC.</li>
 159         </ul>
 160       </td>
 161     </tr>
 162     <tr>
 163       <td>V5.00<br>Beta 5</td>
 164       <td>
 165         <ul>
 166           <li>Moved: DSP libraries from CMSIS/DSP/Lib to CMSIS/Lib.</li>
 167           <li>Added: DSP libraries build projects to CMSIS pack.</li>
 168         </ul>
 169       </td>
 170     </tr>
 171     <tr>
 172       <td>V5.00<br>Beta 4</td>
 173       <td>
 174         <ul>
 175           <li>Updated: ARMv8M device files.</li>
 176           <li>Corrected: ARMv8MBL interrupts.</li>
 177           <li>Reworked: NVIC functions.</li>
 178         </ul>
 179       </td>
 180     </tr>
 181     <tr>
 182       <td>V5.00<br>Beta 2</td>
 183       <td>
 184         <ul>
 185           <li>Changed: ARMv8M SAU regions to 8.</li>
 186           <li>Changed: moved function \ref TZ_SAU_Setup to file partition_&lt;device&gt;.h.</li>
 187           <li>Changed: license under Apache-2.0.</li>
 188           <li>Added: check if macro is defined before use.</li>
 189           <li>Corrected: function \ref SCB_DisableDCache.</li>
 190           <li>Corrected: macros \ref \_VAL2FLD, \ref \_FLD2VAL.</li>
 191           <li>Added: NVIC function virtualization with macros \ref CMSIS_NVIC_VIRTUAL and \ref CMSIS_VECTAB_VIRTUAL.</li>
 192         </ul>
 193       </td>
 194     </tr>
 195     <tr>
 196       <td>V5.00<br>Beta 1</td>
 197       <td>
 198         <ul>
 199           <li>Renamed: cmsis_armcc_V6.h to cmsis_armclang.h.</li>
 200           <li>Renamed: core\_*.h to lower case.</li>
 201           <li>Added: function \ref SCB_GetFPUType to all CMSIS cores.</li>
 202           <li>Added: ARMv8-M support.</li>
 203         </ul>
 204       </td>
 205     </tr>
 206     <tr>
 207       <td>V4.30</td>
 208       <td>
 209         <ul>
 210           <li>Corrected: DoxyGen function parameter comments.</li>
 211           <li>Corrected: IAR toolchain: removed for \ref NVIC_SystemReset the attribute(noreturn).</li>
 212           <li>Corrected: GCC toolchain: suppressed irrelevant compiler warnings.</li>
 213           <li>Added: Support files for Arm Compiler v6 (cmsis_armcc_v6.h).</li>
 214         </ul>
 215       </td>
 216     </tr>
 217     <tr>
 218       <td>V4.20</td>
 219       <td>
 220         <ul>
 221           <li>Corrected: MISRA-C:2004 violations.</li>
 222           <li>Corrected: predefined macro for TI CCS Compiler.</li>
 223           <li>Corrected: function \ref __SHADD16 in arm_math.h.</li>
 224           <li>Updated: cache functions for Cortex-M7.</li>
 225           <li>Added: macros \ref _VAL2FLD, \ref _FLD2VAL to core\_*.h.</li>
 226           <li>Updated: functions \ref __QASX, \ref __QSAX, \ref __SHASX, \ref __SHSAX.</li>
 227           <li>Corrected: potential bug in function \ref __SHADD16.</li>
 228         </ul>
 229       </td>
 230     </tr>
 231     <tr>
 232       <td>V4.10</td>
 233       <td>
 234         <ul>
 235           <li>Corrected: MISRA-C:2004 violations.</li>
 236           <li>Corrected: intrinsic functions \ref __DSB, \ref __DMB, \ref __ISB.</li>
 237           <li>Corrected: register definitions for ITCMCR register.</li>
 238           <li>Corrected: register definitions for \ref CONTROL_Type register.</li>
 239           <li>Added: functions \ref SCB_GetFPUType, \ref SCB_InvalidateDCache_by_Addr to core_cm7.h.</li>
 240           <li>Added: register definitions for \ref APSR_Type, \ref IPSR_Type, \ref xPSR_Type register.</li>
 241           <li>Added: \ref __set_BASEPRI_MAX function to core_cmFunc.h.</li>
 242           <li>Added: intrinsic functions \ref __RBIT, \ref __CLZ  for Cortex-M0/CortexM0+.</li>
 243         </ul>
 244       </td>
 245     </tr>
 246     <tr>
 247       <td>V4.00</td>
 248       <td>
 249         <ul>
 250           <li>Added: Cortex-M7 support.</li>
 251           <li>Added: intrinsic functions for \ref __RRX, \ref __LDRBT, \ref __LDRHT, \ref __LDRT, \ref __STRBT, \ref __STRHT, and \ref __STRT</li>
 252         </ul>
 253       </td>
 254     </tr>
 255     <tr>
 256       <td>V3.40</td>
 257       <td>
 258        <ul>
 259          <li>Corrected: C++ include guard settings.</li>
 260        </ul>
 261      </td>
 262     </tr>
 263     <tr>
 264       <td>V3.30</td>
 265       <td>
 266         <ul>
 267           <li>Added: COSMIC tool chain support.</li>
 268           <li>Corrected: GCC __SMLALDX instruction intrinsic for Cortex-M4.</li>
 269           <li>Corrected: GCC __SMLALD instruction intrinsic for Cortex-M4.</li>
 270           <li>Corrected: GCC/CLang warnings.</li>
 271         </ul>
 272       </td>
 273     </tr>
 274     <tr>
 275       <td>V3.20</td>
 276       <td>
 277         <ul>
 278           <li>Added: \ref __BKPT instruction intrinsic.</li>
 279           <li>Added: \ref __SMMLA instruction intrinsic for Cortex-M4.</li>
 280           <li>Corrected: \ref ITM_SendChar.</li>
 281           <li>Corrected: \ref __enable_irq, \ref __disable_irq and inline assembly for GCC Compiler.</li>
 282           <li>Corrected: \ref NVIC_GetPriority and VTOR_TBLOFF for Cortex-M0/M0+, SC000.</li>
 283           <li>Corrected: rework of in-line assembly functions to remove potential compiler warnings.</li>
 284         </ul>
 285       </td>
 286     </tr>
 287     <tr>
 288       <td>V3.01</td>
 289       <td>
 290        <ul>
 291          <li>Added support for Cortex-M0+ processor.</li>
 292        </ul>
 293      </td>
 294     </tr>
 295     <tr>
 296       <td>V3.00</td>
 297       <td>
 298         <ul>
 299           <li>Added support for GNU GCC ARM Embedded Compiler.</li>
 300           <li>Added function \ref __ROR.</li>
 301           <li>Added \ref regMap_pg for TPIU, DWT.</li>
 302           <li>Added support for \ref core_config_sect "SC000 and SC300 processors".</li>
 303           <li>Corrected \ref ITM_SendChar function.</li>
 304           <li>Corrected the functions \ref __STREXB, \ref __STREXH, \ref __STREXW for the GNU GCC compiler section.</li>
 305           <li>Documentation restructured.</li>
 306         </ul>
 307       </td>
 308     </tr>
 309     <tr>
 310       <td>V2.10</td>
 311       <td>
 312         <ul>
 313           <li>Updated documentation.</li>
 314           <li>Updated CMSIS core include files.</li>
 315           <li>Changed CMSIS/Device folder structure.</li>
 316           <li>Added support for Cortex-M0, Cortex-M4 w/o FPU to CMSIS DSP library.</li>
 317           <li>Reworked CMSIS DSP library examples.</li>
 318         </ul>
 319       </td>
 320     </tr>
 321     <tr>
 322       <td>V2.00</td>
 323       <td>
 324        <ul>
 325          <li>Added support for Cortex-M4 processor.</li>
 326        </ul>
 327      </td>
 328     </tr>
 329     <tr>
 330       <td>V1.30</td>
 331       <td>
 332         <ul>
 333           <li>Reworked Startup Concept.</li>
 334           <li>Added additional Debug Functionality.</li>
 335           <li>Changed folder structure.</li>
 336           <li>Added doxygen comments.</li>
 337           <li>Added definitions for bit.</li>
 338         </ul>
 339       </td>
 340     </tr>
 341     <tr>
 342       <td>V1.01</td>
 343       <td>
 344        <ul>
 345          <li>Added support for Cortex-M0 processor.</li>
 346        </ul>
 347       </td>
 348     </tr>
 349     <tr>
 350       <td>V1.01</td>
 351       <td>
 352        <ul>
 353          <li>Added intrinsic functions for \ref __LDREXB, \ref __LDREXH, \ref __LDREXW, \ref __STREXB, \ref __STREXH, \ref __STREXW, and \ref __CLREX</li>
 354        </ul>
 355      </td>
 356     </tr>
 357     <tr>
 358       <td>V1.00</td>
 359       <td>
 360        <ul>
 361          <li>Initial Release for Cortex-M3 processor.</li>
 362        </ul>
 363      </td>
 364     </tr>
 365 </table>