begriffs open source - cmsis/blob - v6.1.0-rc1/Core_A/mem_h_pg.html

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  43    <div id="projectname">CMSIS-Core (Cortex-A)
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 127   <div class="headertitle"><div class="title">Memory Configuration Files mem_&lt;device&gt;.h </div></div>
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 129 <div class="contents">
 130 <div class="textblock"><pre class="fragment">/**************************************************************************//**
 131  * @file     mem_&lt;Device&gt;.h
 132  * @brief    CMSIS Cortex-A Memory base and size definitions (used in scatter file)
 133  * @version  V1.00
 134  * @date     10. January 2018
 135  ******************************************************************************/
 136 /*
 137  * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 138  *
 139  * SPDX-License-Identifier: Apache-2.0
 140  *
 141  * Licensed under the Apache License, Version 2.0 (the License); you may
 142  * not use this file except in compliance with the License.
 143  * You may obtain a copy of the License at
 144  *
 145  * www.apache.org/licenses/LICENSE-2.0
 146  *
 147  * Unless required by applicable law or agreed to in writing, software
 148  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 149  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 150  * See the License for the specific language governing permissions and
 151  * limitations under the License.
 152  */
 153
 154 #ifndef MEM_&lt;Device&gt;_H   /* ToDo: replace '&lt;Device&gt;' with your device name */
 155 #define MEM_&lt;Device&gt;_H
 156
 157 /*----------------------------------------------------------------------------
 158   User Stack &amp; Heap size definition
 159  *----------------------------------------------------------------------------*/
 160 /*
 161 //-------- &lt;&lt;&lt; Use Configuration Wizard in Context Menu &gt;&gt;&gt; ------------------
 162 */
 163
 164 /*--------------------- ROM Configuration ------------------------------------
 165 //
 166 // &lt;h&gt; ROM Configuration
 167 //   &lt;o0&gt; ROM Base Address &lt;0x0-0xFFFFFFFF:8&gt;
 168 //   &lt;o1&gt; ROM Size (in Bytes) &lt;0x0-0xFFFFFFFF:8&gt;
 169 // &lt;/h&gt;
 170  *----------------------------------------------------------------------------*/
 171 #define __ROM_BASE       0x80000000
 172 #define __ROM_SIZE       0x00200000
 173
 174 /*--------------------- RAM Configuration -----------------------------------
 175 // &lt;h&gt; RAM Configuration
 176 //   &lt;o0&gt; RAM Base Address    &lt;0x0-0xFFFFFFFF:8&gt;
 177 //   &lt;o1&gt; RAM Total Size (in Bytes) &lt;0x0-0xFFFFFFFF:8&gt;
 178 //   &lt;o2&gt; RW_DATA Size (in Bytes) &lt;0x0-0xFFFFFFFF:8&gt;
 179 //   &lt;o3&gt; ZI_DATA Size (in Bytes) &lt;0x0-0xFFFFFFFF:8&gt;
 180 //   &lt;h&gt; Stack / Heap Configuration
 181 //     &lt;o4&gt;  Stack Size (in Bytes) &lt;0x0-0xFFFFFFFF:8&gt;
 182 //     &lt;o5&gt;  Heap Size (in Bytes) &lt;0x0-0xFFFFFFFF:8&gt;
 183 //     &lt;h&gt; Exceptional Modes
 184 //       &lt;o6&gt; UND Stack Size (in Bytes) &lt;0x0-0xFFFFFFFF:8&gt;
 185 //       &lt;o7&gt; ABT Stack Size (in Bytes) &lt;0x0-0xFFFFFFFF:8&gt;
 186 //       &lt;o8&gt; SVC Stack Size (in Bytes) &lt;0x0-0xFFFFFFFF:8&gt;
 187 //       &lt;o9&gt; IRQ Stack Size (in Bytes) &lt;0x0-0xFFFFFFFF:8&gt;
 188 //       &lt;o10&gt; FIQ Stack Size (in Bytes) &lt;0x0-0xFFFFFFFF:8&gt;
 189 //     &lt;/h&gt;
 190 //   &lt;/h&gt;
 191 // &lt;/h&gt;
 192  *----------------------------------------------------------------------------*/
 193 #define __RAM_BASE       0x80200000
 194 #define __RAM_SIZE       0x00200000
 195
 196 #define __RW_DATA_SIZE   0x00100000
 197 #define __ZI_DATA_SIZE   0x000F0000
 198
 199 #define __STACK_SIZE     0x00001000
 200 #define __HEAP_SIZE      0x00008000
 201
 202 #define __UND_STACK_SIZE 0x00000100
 203 #define __ABT_STACK_SIZE 0x00000100
 204 #define __SVC_STACK_SIZE 0x00000100
 205 #define __IRQ_STACK_SIZE 0x00000100
 206 #define __FIQ_STACK_SIZE 0x00000100
 207
 208 /*----------------------------------------------------------------------------*/
 209
 210 /*--------------------- TTB Configuration ------------------------------------
 211 //
 212 // &lt;h&gt; TTB Configuration
 213 //   &lt;o0&gt; TTB Base Address &lt;0x0-0xFFFFFFFF:8&gt;
 214 //   &lt;o1&gt; TTB Size (in Bytes) &lt;0x0-0xFFFFFFFF:8&gt;
 215 // &lt;/h&gt;
 216  *----------------------------------------------------------------------------*/
 217 #define __TTB_BASE       0x80500000
 218 #define __TTB_SIZE       0x00004000
 219
 220 #endif /* MEM_&lt;Device&gt;_H */
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