begriffs open source - cmsis/blob - v6.1.0-rc1/Core_A/rev_histCoreA.html

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  43    <div id="projectname">CMSIS-Core (Cortex-A)
  44    &#160;<span id="projectnumber"><script type="text/javascript">
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  52    <div id="projectbrief">CMSIS-Core support for Cortex-A processor-based devices</div>
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 127   <div class="headertitle"><div class="title">Revision History </div></div>
 128 </div><!--header-->
 129 <div class="contents">
 130 <div class="textblock"><p><a class="anchor" id="md_src_history"></a> CMSIS-Core(A) component is maintaned with own versioning that gets incremented together with the <a href="../General/cmsis_pack.html">CMSIS Software Pack</a> releases.</p>
 131 <p>The table below provides information about the changes delivered with specific versions of CMSIS-Core(A) updates.</p>
 132 <table class="cmtable" summary="Revision History">
 133 <tr>
 134 <th>Version </th><th>Description  </th></tr>
 135 <tr>
 136 <td>V6.1.0 </td><td><ul>
 137 <li>
 138 Added support for Cortex-M52 </li>
 139 <li>
 140 Added deprecated CoreDebug symbols for CMSIS 5 compatibility </li>
 141 <li>
 142 Added define CMSIS_DISABLE_DEPRECATED to hide deprecated symbols </li>
 143 </ul>
 144 </td></tr>
 145 <tr>
 146 <td>V6.0.0 </td><td><ul>
 147 <li>
 148 Core(M) and Core(A) joined into single Core component </li>
 149 <li>
 150 Core header files reworked, aligned with TRMs </li>
 151 <li>
 152 Previously deprecated features removed </li>
 153 <li>
 154 Dropped support for Arm Compiler 5 </li>
 155 </ul>
 156 </td></tr>
 157 <tr>
 158 <td>V1.2.1 </td><td><ul>
 159 <li>
 160 Bugfixes for Cortex-A32 </li>
 161 </ul>
 162 </td></tr>
 163 <tr>
 164 <td>V1.2.0 </td><td><ul>
 165 <li>
 166 Fixed <a class="el" href="group__GIC__functions.html#ga18fbddf7f3594df141c97f61a71da47c">GIC_SetPendingIRQ</a> to use GICD_SGIR instead of GICD_SPENDSGIR for compliance with all GIC specification versions. </li>
 167 <li>
 168 Added missing DSP intrinsics. </li>
 169 <li>
 170 Reworked assembly intrinsics: volatile, barriers and clobbers. </li>
 171 </ul>
 172 </td></tr>
 173 <tr>
 174 <td>V1.1.4 </td><td><ul>
 175 <li>
 176 Fixed <a class="el" href="group__FPU__functions.html#ga1e4728985ee8b4fa89cc01c032f69565" title="Enable Floating Point Unit.">__FPU_Enable()</a>. </li>
 177 </ul>
 178 </td></tr>
 179 <tr>
 180 <td>V1.1.3 </td><td><ul>
 181 <li>
 182 Fixed <a class="el" href="group__CMSIS__Core__RegAccFunctions.html#ga7009688fca7a35b5e3ba6cf11cc74869" title="Get USR/SYS Stack Pointer.">__get_SP_usr()</a> / <a class="el" href="group__CMSIS__Core__RegAccFunctions.html#gaabb67304694380b52a86cdc77efdfbf9" title="Set USR/SYS Stack Pointer.">__set_SP_usr()</a> for ArmClang. </li>
 183 <li>
 184 Fixed zero argument handling in <a class="el" href="group__CMSIS__Core__InstructionInterface.html#ga90884c591ac5d73d6069334eba9d6c02" title="Count leading zeros.">__CLZ()</a> . </li>
 185 </ul>
 186 </td></tr>
 187 <tr>
 188 <td>V1.1.2 </td><td><ul>
 189 <li>
 190 Removed using get/set built-ins FPSCR in GCC &gt;= 7.2 due to shortcomings. </li>
 191 <li>
 192 Fixed co-processor register access macros for Arm Compiler 5. </li>
 193 </ul>
 194 </td></tr>
 195 <tr>
 196 <td>V1.1.1 </td><td><ul>
 197 <li>
 198 Refactored L1 cache maintenance to be compiler agnostic. </li>
 199 </ul>
 200 </td></tr>
 201 <tr>
 202 <td>V1.1.0 </td><td><ul>
 203 <li>
 204 Added compiler_iccarm.h for IAR compiler. </li>
 205 <li>
 206 Added missing core access functions for Arm Compiler 5. </li>
 207 <li>
 208 Aligned access function to coprocessor 15. </li>
 209 <li>
 210 Additional generic Timer functions. </li>
 211 <li>
 212 Bug fixes and minor enhancements. </li>
 213 </ul>
 214 </td></tr>
 215 <tr>
 216 <td>V1.0.0 </td><td>Initial Release for Cortex-A5/A7/A9 processors.  </td></tr>
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