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 126 <div><div class="header">
 127   <div class="headertitle"><div class="title">TrustZone setup: partition_&lt;Device&gt;.h </div></div>
 128 </div><!--header-->
 129 <div class="contents">
 130 <div class="textblock"><p><a class="anchor" id="md_src_core_partition_device_h"></a> The TrustZone header file contains the initial setup of the TrustZone hardware in an Armv8-M system.</p>
 131 <p>This file implements the function <a class="el" href="group__sau__trustzone__functions.html#ga6093bc5939ea8924fbcfdffb8f0553f1">TZ_SAU_Setup</a> that is called from <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">SystemInit</a>. It uses settings in these files:</p>
 132 <ul>
 133 <li><a class="el" href="partition_h_pg.html">partition_&lt;Device&gt;.h</a> that defines the initial system configuration and during SystemInit in Secure state.</li>
 134 <li><a class="el" href="partition_h_pg.html#partition_gen_h_pg">partition_gen.h</a> that contains SAU region and interrupt target assignments. This file may be generated using <a href="../Zone/index.html">CMSIS-Zone</a>.</li>
 135 </ul>
 136 <blockquote class="doxtable">
 137 <p>&zwj;<b>Note</b></p><ul>
 138 <li><a class="el" href="partition_h_pg.html#partition_gen_h_pg">partition_gen.h</a> is optional and can be generated using <a href="../Zone/index.html">CMSIS-Zone</a>. In previous versions of CMSIS-Core(M) this settings were part of <a class="el" href="partition_h_pg.html">partition_&lt;Device&gt;.h</a>. </li>
 139 </ul>
 140 </blockquote>
 141 <p>The <a class="el" href="partition_h_pg.html">partition_&lt;Device&gt;.h</a> file contains the following configuration settings for:</p>
 142 <ul>
 143 <li><a class="el" href="partition_h_pg.html#sau_ctrlregister_sec">SAU CTRL register settings</a> provides settings for the SAU CTRL register.</li>
 144 <li><a class="el" href="partition_h_pg.html#sau_sleepexception_sec">Configuration of Sleep and Exception behaviour</a> provides device-specific deep-sleep and exception settings.</li>
 145 <li><a class="el" href="partition_h_pg.html#sau_fpu_sec">Configuration of Floating Point Unit</a> defines the usage of the Floating Point Unit in secure and non-secure state.</li>
 146 </ul>
 147 <p>The <a class="el" href="partition_h_pg.html">partition_&lt;Device&gt;.h</a> file includes the <a class="el" href="partition_h_pg.html#partition_gen_h_pg">partition_gen.h</a> file with configuration settings for:</p>
 148 <ul>
 149 <li><a class="el" href="partition_h_pg.html#sau_regions_sect">Configuration of the SAU Address Regions</a> provides configuration of the SAU Address Regions.</li>
 150 <li><a class="el" href="partition_h_pg.html#sau_interrupttarget_sec">Configuration of Interrupt Target settings</a> provides device-specific interrupt target settings.</li>
 151 </ul>
 152 <h1><a class="anchor" id="sau_ctrlregister_sec"></a>
 153 SAU CTRL register settings</h1>
 154 <table class="cmtable">
 155 <tr>
 156 <th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
 157 <tr>
 158 <td>SAU_INIT_CTRL </td><td>0 .. 1 </td><td>0 </td><td>Initialize SAU CTRL register or not<ul>
 159 <li>0: do not initialize SAU CTRL register</li>
 160 <li>1: initialize SAU CTRL register  </li>
 161 </ul>
 162 </td></tr>
 163 <tr>
 164 <td>SAU_INIT_CTRL_ENABLE </td><td>0 .. 1 </td><td>0 </td><td>enable/disable the SAU<ul>
 165 <li>0: disable SAU</li>
 166 <li>1: enable SAU  </li>
 167 </ul>
 168 </td></tr>
 169 <tr>
 170 <td>SAU_INIT_CTRL_ALLNS </td><td>0 .. 1 </td><td>0 </td><td>value for SAU_CTRL register bit ALLNS<ul>
 171 <li>0: all Memory is Secure</li>
 172 <li>1: all Memory is Non-Secure  </li>
 173 </ul>
 174 </td></tr>
 175 </table>
 176 <h1><a class="anchor" id="sau_sleepexception_sec"></a>
 177 Configuration of Sleep and Exception behaviour</h1>
 178 <table class="cmtable">
 179 <tr>
 180 <th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
 181 <tr>
 182 <td>SCB_CSR_AIRCR_INIT </td><td>0 .. 1 </td><td>1 </td><td>Setup behaviour of Sleep and Exception Handling<ul>
 183 <li>0: not setup of CSR and AIRCR registers; the values below are not relevant</li>
 184 <li>1: setup of CSR and AIRCR registers with values below  </li>
 185 </ul>
 186 </td></tr>
 187 <tr>
 188 <td>CSR_INIT_DEEPSLEEPS_VAL </td><td>0 .. 1 </td><td>1 </td><td>value for SCB_CSR register bit DEEPSLEEPS<ul>
 189 <li>0: Deep Sleep can be enabled by Secure and Non-Secure state</li>
 190 <li>1: Deep Sleep can be enabled by Secure state only  </li>
 191 </ul>
 192 </td></tr>
 193 <tr>
 194 <td>AIRCR_INIT_SYSRESETREQS_VAL </td><td>0 .. 1 </td><td>1 </td><td>value for SCB_AIRCR register bit SYSRESETREQS<ul>
 195 <li>0: System reset request accessible from Secure and Non-Secure state</li>
 196 <li>1: System reset request accessible from Secure state only  </li>
 197 </ul>
 198 </td></tr>
 199 <tr>
 200 <td>AIRCR_INIT_PRIS_VAL </td><td>0 .. 1 </td><td>1 </td><td>value for SCB_AIRCR register bit PRIS<ul>
 201 <li>0: Priority of Non-Secure exceptions is Not altered</li>
 202 <li>1: Priority of Non-Secure exceptions is Lowered to 0x80-0xFF  </li>
 203 </ul>
 204 </td></tr>
 205 <tr>
 206 <td>AIRCR_INIT_BFHFNMINS_VAL </td><td>0 .. 1 </td><td>0 </td><td>value for SCB_AIRCR register bit BFHFNMINS<ul>
 207 <li>0: BusFault, HardFault, and NMI target are Secure state</li>
 208 <li>1: BusFault, HardFault, and NMI target are Non-Secure state  </li>
 209 </ul>
 210 </td></tr>
 211 </table>
 212 <h1><a class="anchor" id="sau_fpu_sec"></a>
 213 Configuration of Floating Point Unit</h1>
 214 <table class="cmtable">
 215 <tr>
 216 <th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
 217 <tr>
 218 <td>TZ_FPU_NS_USAGE </td><td>0 .. 1 </td><td>1 </td><td>Setup behaviour of Floating Point Unit<ul>
 219 <li>0: not setup of NSACR and FPCCR registers; the values below are not relevant</li>
 220 <li>1: setup of NSACR and FPCCR registers with values below  </li>
 221 </ul>
 222 </td></tr>
 223 <tr>
 224 <td>SCB_NSACR_CP10_11_VAL </td><td>0 or 3 </td><td>3 </td><td>Floating Point Unit usage (Value for SCB-&gt;NSACR register bits CP10, CP11)<ul>
 225 <li>0: Secure state only</li>
 226 <li>3: Secure and Non-Secure state  </li>
 227 </ul>
 228 </td></tr>
 229 <tr>
 230 <td>FPU_FPCCR_TS_VAL </td><td>0 .. 1 </td><td>0 </td><td>Treat floating-point registers as Secure (value for FPU-&gt;FPCCR register bit TS)<ul>
 231 <li>0: Disable</li>
 232 <li>1: Enabled  </li>
 233 </ul>
 234 </td></tr>
 235 <tr>
 236 <td>FPU_FPCCR_CLRONRETS_VAL </td><td>0 .. 1 </td><td>0 </td><td>Clear on return (CLRONRET) accessibility (Value for FPU-&gt;FPCCR register bit CLRONRETS)<ul>
 237 <li>0: Secure and Non-Secure state</li>
 238 <li>1: Secure state only  </li>
 239 </ul>
 240 </td></tr>
 241 <tr>
 242 <td>FPU_FPCCR_CLRONRET_VAL </td><td>0 .. 1 </td><td>1 </td><td>Clear floating-point caller saved registers on exception return (Value for FPU-&gt;FPCCR register bit CLRONRET)<ul>
 243 <li>0: Disabled</li>
 244 <li>1: Enabled  </li>
 245 </ul>
 246 </td></tr>
 247 </table>
 248 <h1><a class="anchor" id="partition_gen_h_pg"></a>
 249 Region/ISR setup: partition_gen.h</h1>
 250 <p>The <a class="el" href="partition_h_pg.html#partition_gen_h_pg">partition_gen.h</a> header file can be generated using <a href="../Zone/index.html">CMSIS-Zone</a>.</p>
 251 <p>The <a class="el" href="partition_h_pg.html">partition_&lt;Device&gt;.h</a> file includes the <a class="el" href="partition_h_pg.html">partition_gen.h</a> file with configuration settings for:</p>
 252 <ul>
 253 <li><a class="el" href="partition_h_pg.html#sau_regions_sect">Configuration of the SAU Address Regions</a> provides configuration of the SAU Address Regions.</li>
 254 <li><a class="el" href="partition_h_pg.html#sau_interrupttarget_sec">Configuration of Interrupt Target settings</a> provides device-specific interrupt target settings.</li>
 255 </ul>
 256 <blockquote class="doxtable">
 257 <p>&zwj;<b>Note</b></p><ul>
 258 <li>In previous versions of CMSIS-Core(M) the above settings were part of <a class="el" href="partition_h_pg.html">partition_&lt;Device&gt;.h</a> </li>
 259 </ul>
 260 </blockquote>
 261 <h2><a class="anchor" id="sau_regions_sect"></a>
 262 Configuration of the SAU Address Regions</h2>
 263 <table class="cmtable">
 264 <tr>
 265 <th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
 266 <tr>
 267 <td>SAU_REGIONS_MAX </td><td>0 .. tbd </td><td>8 </td><td>maximum number of SAU regions  </td></tr>
 268 <tr>
 269 <td>SAU_INIT_REGION&lt;number&gt; </td><td>0 .. 1 </td><td>0 </td><td>initialize SAU region or not<ul>
 270 <li>0: do not initialize SAU region</li>
 271 <li>1: initialize SAU region  </li>
 272 </ul>
 273 </td></tr>
 274 <tr>
 275 <td>SAU_INIT_START&lt;number&gt; </td><td>0x00000000 .. 0xFFFFFFE0<br  />
 276  [in steps of 32] </td><td>0x00000000 </td><td>region start address  </td></tr>
 277 <tr>
 278 <td>SAU_INIT_END&lt;number&gt; </td><td>0x00000000 .. 0xFFFFFFE0<br  />
 279  [in steps of 32] </td><td>0x00000000 </td><td>region start address  </td></tr>
 280 <tr>
 281 <td>SAU_INIT_NSC&lt;number&gt; </td><td>0 .. 1 </td><td>0 </td><td>SAU region attribute<ul>
 282 <li>0: Non-Secure</li>
 283 <li>1: Secure, Non-Secure callable  </li>
 284 </ul>
 285 </td></tr>
 286 </table>
 287 <p>The range of &lt;number&gt; is from 0 .. SAU_REGIONS_MAX. A set of these macros must exist for each &lt;number&gt;.</p>
 288 <p>The following example shows a set of SAU region macros.</p>
 289 <div class="fragment"><div class="line"><span class="preprocessor">#define SAU_REGIONS_MAX   8                 </span><span class="comment">/* Max. number of SAU regions */</span><span class="preprocessor"></span></div>
 290 <div class="line"> </div>
 291 <div class="line"><span class="preprocessor">#define SAU_INIT_REGION0    1</span></div>
 292 <div class="line"><span class="preprocessor">#define SAU_INIT_START0     0x00000000      </span><span class="comment">/* start address of SAU region 0 */</span><span class="preprocessor"></span></div>
 293 <div class="line"><span class="preprocessor">#define SAU_INIT_END0       0x001FFFE0      </span><span class="comment">/* end address of SAU region 0 */</span><span class="preprocessor"></span></div>
 294 <div class="line"><span class="preprocessor">#define SAU_INIT_NSC0       1</span></div>
 295 <div class="line"> </div>
 296 <div class="line"><span class="preprocessor">#define SAU_INIT_REGION1    1</span></div>
 297 <div class="line"><span class="preprocessor">#define SAU_INIT_START1     0x00200000      </span><span class="comment">/* start address of SAU region 1 */</span><span class="preprocessor"></span></div>
 298 <div class="line"><span class="preprocessor">#define SAU_INIT_END1       0x003FFFE0      </span><span class="comment">/* end address of SAU region 1 */</span><span class="preprocessor"></span></div>
 299 <div class="line"><span class="preprocessor">#define SAU_INIT_NSC1       0</span></div>
 300 <div class="line"> </div>
 301 <div class="line"><span class="preprocessor">#define SAU_INIT_REGION2    1</span></div>
 302 <div class="line"><span class="preprocessor">#define SAU_INIT_START2     0x20200000      </span><span class="comment">/* start address of SAU region 2 */</span><span class="preprocessor"></span></div>
 303 <div class="line"><span class="preprocessor">#define SAU_INIT_END2       0x203FFFE0      </span><span class="comment">/* end address of SAU region 2 */</span><span class="preprocessor"></span></div>
 304 <div class="line"><span class="preprocessor">#define SAU_INIT_NSC2       0</span></div>
 305 <div class="line"> </div>
 306 <div class="line"><span class="preprocessor">#define SAU_INIT_REGION3    1</span></div>
 307 <div class="line"><span class="preprocessor">#define SAU_INIT_START3     0x40000000      </span><span class="comment">/* start address of SAU region 3 */</span><span class="preprocessor"></span></div>
 308 <div class="line"><span class="preprocessor">#define SAU_INIT_END3       0x40040000      </span><span class="comment">/* end address of SAU region 3 */</span><span class="preprocessor"></span></div>
 309 <div class="line"><span class="preprocessor">#define SAU_INIT_NSC3       0</span></div>
 310 <div class="line"> </div>
 311 <div class="line"><span class="preprocessor">#define SAU_INIT_REGION4    0</span></div>
 312 <div class="line"><span class="preprocessor">#define SAU_INIT_START4     0x00000000      </span><span class="comment">/* start address of SAU region 4 */</span><span class="preprocessor"></span></div>
 313 <div class="line"><span class="preprocessor">#define SAU_INIT_END4       0x00000000      </span><span class="comment">/* end address of SAU region 4 */</span><span class="preprocessor"></span></div>
 314 <div class="line"><span class="preprocessor">#define SAU_INIT_NSC4       0</span></div>
 315 <div class="line"> </div>
 316 <div class="line"><span class="preprocessor">#define SAU_INIT_REGION5    0</span></div>
 317 <div class="line"><span class="preprocessor">#define SAU_INIT_START5     0x00000000      </span><span class="comment">/* start address of SAU region 5 */</span><span class="preprocessor"></span></div>
 318 <div class="line"><span class="preprocessor">#define SAU_INIT_END5       0x00000000      </span><span class="comment">/* end address of SAU region 5 */</span><span class="preprocessor"></span></div>
 319 <div class="line"><span class="preprocessor">#define SAU_INIT_NSC5       0</span></div>
 320 <div class="line"> </div>
 321 <div class="line"><span class="preprocessor">#define SAU_INIT_REGION6    0</span></div>
 322 <div class="line"><span class="preprocessor">#define SAU_INIT_START6     0x00000000      </span><span class="comment">/* start address of SAU region 6 */</span><span class="preprocessor"></span></div>
 323 <div class="line"><span class="preprocessor">#define SAU_INIT_END6       0x00000000      </span><span class="comment">/* end address of SAU region 6 */</span><span class="preprocessor"></span></div>
 324 <div class="line"><span class="preprocessor">#define SAU_INIT_NSC6       0</span></div>
 325 <div class="line"> </div>
 326 <div class="line"><span class="preprocessor">#define SAU_INIT_REGION7    0</span></div>
 327 <div class="line"><span class="preprocessor">#define SAU_INIT_START7     0x00000000      </span><span class="comment">/* start address of SAU region 7 */</span><span class="preprocessor"></span></div>
 328 <div class="line"><span class="preprocessor">#define SAU_INIT_END7       0x00000000      </span><span class="comment">/* end address of SAU region 7 */</span><span class="preprocessor"></span></div>
 329 <div class="line"><span class="preprocessor">#define SAU_INIT_NSC7       0</span></div>
 330 </div><!-- fragment --><h2><a class="anchor" id="sau_interrupttarget_sec"></a>
 331 Configuration of Interrupt Target settings</h2>
 332 <p>Each interrupt has a configuration bit that defines the execution in Secure or Non-secure state. The Non-Secure interrupts have a separate vector table. Refer to <a class="el" href="using_TrustZone_pg.html#Model_TrustZone">Programmers Model with TrustZone</a> for more information.</p>
 333 <table class="cmtable">
 334 <tr>
 335 <th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
 336 <tr>
 337 <td>NVIC_INIT_ITNS&lt;number&gt; </td><td>0x00000000 .. 0xFFFFFFFF<br  />
 338  [each bit represents an interrupt] </td><td>0x00000000 </td><td>Interrupt vector target<ul>
 339 <li>0: Secure state</li>
 340 <li>1: Non-Secure state  </li>
 341 </ul>
 342 </td></tr>
 343 </table>
 344 <p>The range of &lt;number&gt; is 0 .. (&lt;number of external interrupts&gt; + 31) / 32.</p>
 345 <p>The following example shows the configuration for a maximum of 64 external interrupts.</p>
 346 <div class="fragment"><div class="line"><span class="preprocessor">#define NVIC_INIT_ITNS0      0x0000122B</span></div>
 347 <div class="line"><span class="preprocessor">#define NVIC_INIT_ITNS1      0x0000003A</span></div>
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