begriffs open source - cmsis/blob - CMSIS/CoreValidation/Tests/Cortex-M33/IAR/CV_Config.h

   1 /*-----------------------------------------------------------------------------
   2  *      Name:         CV_Config.h
   3  *      Purpose:      CV Config header
   4  *----------------------------------------------------------------------------
   5  *      Copyright (c) 2017 - 2018 Arm Limited. All rights reserved.
   6  *----------------------------------------------------------------------------*/
   7 #ifndef __CV_CONFIG_H
   8 #define __CV_CONFIG_H
   9
  10 #include "RTE_Components.h"
  11 #include CMSIS_device_header
  12
  13 #define RTE_CV_COREINSTR 1
  14 #define RTE_CV_COREFUNC  1
  15 #define RTE_CV_CORESIMD  1
  16 #define RTE_CV_MPUFUNC   __MPU_PRESENT
  17
  18 //-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
  19
  20 // <h> Common Test Settings
  21 // <o> Print Output Format <0=> Plain Text <1=> XML
  22 // <i> Set the test results output format to plain text or XML
  23 #ifndef PRINT_XML_REPORT
  24 #define PRINT_XML_REPORT            1
  25 #endif
  26 // <o> Buffer size for assertions results
  27 // <i> Set the buffer size for assertions results buffer
  28 #define BUFFER_ASSERTIONS           128U
  29 // </h>
  30
  31 // <h> Disable Test Cases
  32 // <i> Uncheck to disable an individual test case
  33 // <q0> TC_CoreInstr_NOP
  34 #define TC_COREINSTR_NOP_EN                        1
  35 // <q0> TC_CoreInstr_SEV
  36 #define TC_COREINSTR_SEV_EN                        1
  37 // <q0> TC_CoreInstr_BKPT
  38 #define TC_COREINSTR_BKPT_EN                       1
  39 // <q0> TC_CoreInstr_ISB
  40 #define TC_COREINSTR_ISB_EN                        1
  41 // <q0> TC_CoreInstr_DSB
  42 #define TC_COREINSTR_DSB_EN                        1
  43 // <q0> TC_CoreInstr_DMB
  44 #define TC_COREINSTR_DMB_EN                        1
  45 // <q0> TC_CoreInstr_WFI
  46 #define TC_COREINSTR_WFI_EN                        0
  47 // <q0> TC_CoreInstr_WFE
  48 #define TC_COREINSTR_WFE_EN                        0
  49
  50 // <q0> TC_CoreInstr_REV
  51 #define TC_COREINSTR_REV_EN                        1
  52 // <q0> TC_CoreInstr_REV16
  53 #define TC_COREINSTR_REV16_EN                      1
  54 // <q0> TC_CoreInstr_REVSH
  55 #define TC_COREINSTR_REVSH_EN                      1
  56 // <q0> TC_CoreInstr_ROR
  57 #define TC_COREINSTR_ROR_EN                        1
  58 // <q0> TC_CoreInstr_RBIT
  59 #define TC_COREINSTR_RBIT_EN                       1
  60 // <q0> TC_CoreInstr_CLZ
  61 #define TC_COREINSTR_CLZ_EN                        1
  62 // <q0> TC_CoreInstr_SSAT
  63 #define TC_COREINSTR_SSAT_EN                       1
  64 // <q0> TC_CoreInstr_USAT
  65 #define TC_COREINSTR_USAT_EN                       1
  66 // <q0> TC_CoreInstr_RRX
  67 #define TC_COREINSTR_RRX_EN                        1
  68 // <q0> TC_CoreInstr_LoadStoreExlusive
  69 #define TC_COREINSTR_LOADSTOREEXCLUSIVE_EN         1
  70 // <q0> TC_CoreInstr_LoadStoreUnpriv
  71 #define TC_COREINSTR_LOADSTOREUNPRIV_EN            1
  72 // <q0> TC_CoreInstr_LoadStoreAcquire
  73 #define TC_COREINSTR_LOADSTOREACQUIRE_EN           1
  74 // <q0> TC_CoreInstr_LoadStoreAcquireExclusive
  75 #define TC_COREINSTR_LOADSTOREACQUIREEXCLUSIVE_EN  1
  76
  77 // <q0> TC_CoreSimd_SatAddSub
  78 #define TC_CORESIMD_SATADDSUB_EN                   1
  79 // <q0> TC_CoreSimd_ParSat16
  80 #define TC_CORESIMD_PARSAT16_EN                    1
  81 // <q0> TC_CoreSimd_PackUnpack
  82 #define TC_CORESIMD_PACKUNPACK_EN                  1
  83 // <q0> TC_CoreSimd_ParSel
  84 #define TC_CORESIMD_PARSEL_EN                      1
  85 // <q0> TC_CoreSimd_ParAddSub8
  86 #define TC_CORESIMD_PARADDSUB8_EN                  1
  87 // <q0> TC_CoreSimd_AbsDif8
  88 #define TC_CORESIMD_ABSDIF8_EN                     1
  89 // <q0> TC_CoreSimd_ParAddSub16
  90 #define TC_CORESIMD_PARADDSUB16_EN                 1
  91 // <q0> TC_CoreSimd_ParMul16
  92 #define TC_CORESIMD_PARMUL16_EN                    1
  93 // <q0> TC_CoreSimd_Pack16
  94 #define TC_CORESIMD_PACK16_EN                      1
  95 // <q0> TC_CoreSimd_MulAcc32
  96 #define TC_CORESIMD_MULACC32_EN                    1
  97
  98 // <q0> TC_CoreFunc_EnDisIRQ
  99 #define TC_COREFUNC_ENDISIRQ_EN                    1
 100 // <q0> TC_CoreFunc_IRQPrio
 101 #define TC_COREFUNC_IRQPRIO_EN                     1
 102 // <q0> TC_CoreFunc_EncDecIRQPrio
 103 #define TC_COREFUNC_ENCDECIRQPRIO_EN               1
 104 // <q0> TC_CoreFunc_IRQVect
 105 #define TC_COREFUNC_IRQVECT_EN                     1
 106 // <q0> TC_CoreFunc_Control
 107 #define TC_COREFUNC_CONTROL_EN                     1
 108 // <q0> TC_CoreFunc_IPSR
 109 #define TC_COREFUNC_IPSR_EN                        1
 110 // <q0> TC_CoreFunc_APSR
 111 #define TC_COREFUNC_APSR_EN                        1
 112 // <q0> TC_CoreFunc_PSP
 113 #define TC_COREFUNC_PSP_EN                         1
 114 // <q0> TC_CoreFunc_MSP
 115 #define TC_COREFUNC_MSP_EN                         1
 116
 117 // <q0> TC_CoreFunc_PSPLIM
 118 #define TC_COREFUNC_PSPLIM_EN                      1
 119 // <q0> TC_CoreFunc_PSPLIM_NS
 120 #define TC_COREFUNC_PSPLIM_NS_EN                   1
 121 // <q0> TC_CoreFunc_MSPLIM
 122 #define TC_COREFUNC_MSPLIM_EN                      1
 123 // <q0> TC_CoreFunc_MSPLIM_NS
 124 #define TC_COREFUNC_MSPLIM_NS_EN                   1
 125 // <q0> TC_CoreFunc_PRIMASK
 126 #define TC_COREFUNC_PRIMASK_EN                     1
 127 // <q0> TC_CoreFunc_FAULTMASK
 128 #define TC_COREFUNC_FAULTMASK_EN                   1
 129 // <q0> TC_CoreFunc_BASEPRI
 130 #define TC_COREFUNC_BASEPRI_EN                     1
 131 // <q0> TC_CoreFunc_FPUType
 132 #define TC_COREFUNC_FPUTYPE_EN                     1
 133 // <q0> TC_CoreFunc_FPSCR
 134 #define TC_COREFUNC_FPSCR_EN                       1
 135
 136
 137 // <q0> TC_MPU_SetClear
 138 #define TC_MPU_SETCLEAR_EN                         1
 139 // <q0> TC_MPU_Load
 140 #define TC_MPU_LOAD_EN                             1
 141
 142 // </h>
 143
 144 #endif /* __CV_CONFIG_H */
 145