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   1 # Revision History {#rev_histCoreA}
   2
   3 CMSIS-Core(A) component is maintaned with own versioning that gets incremented together with the [CMSIS Software Pack](../General/cmsis_pack.html) releases.
   4
   5 The table below provides information about the changes delivered with specific versions of CMSIS-Core(A) updates.
   6
   7 <table class="cmtable" summary="Revision History">
   8     <tr>
   9       <th>Version</th>
  10       <th>Description</th>
  11     </tr>
  12     <tr>
  13       <td>V6.1.0</td>
  14       <td>
  15         <ul>
  16           <li>Added support for Cortex-M52</li>
  17           <li>Added deprecated CoreDebug symbols for CMSIS 5 compatibility</li>
  18           <li>Added define CMSIS_DISABLE_DEPRECATED to hide deprecated symbols</li>
  19         </ul>
  20       </td>
  21     </tr>    <tr>
  22       <td>V6.0.0</td>
  23       <td>
  24         <ul>
  25           <li>Core(M) and Core(A) joined into single Core component</li>
  26           <li>Core header files reworked, aligned with TRMs</li>
  27           <li>Previously deprecated features removed</li>
  28           <li>Dropped support for Arm Compiler 5</li>
  29         </ul>
  30       </td>
  31     </tr>
  32     <tr>
  33       <td>V1.2.1</td>
  34       <td>
  35         <ul>
  36           <li>Bugfixes for Cortex-A32</li>
  37         </ul>
  38       </td>
  39     </tr>
  40     <tr>
  41       <td>V1.2.0</td>
  42       <td>
  43         <ul>
  44           <li>Fixed \ref GIC_SetPendingIRQ to use GICD_SGIR instead of GICD_SPENDSGIR
  45               for compliance with all GIC specification versions.</li>
  46           <li>Added missing DSP intrinsics.</li>
  47           <li>Reworked assembly intrinsics: volatile, barriers and clobbers.</li>
  48         </ul>
  49       </td>
  50     </tr>
  51     <tr>
  52       <td>V1.1.4</td>
  53       <td>
  54         <ul>
  55           <li>Fixed __FPU_Enable().</li>
  56         </ul>
  57       </td>
  58     </tr>
  59     <tr>
  60       <td>V1.1.3</td>
  61       <td>
  62         <ul>
  63           <li>Fixed __get_SP_usr() / __set_SP_usr() for ArmClang.</li>
  64           <li>Fixed zero argument handling in __CLZ() .</li>
  65         </ul>
  66       </td>
  67     </tr>
  68     <tr>
  69       <td>V1.1.2</td>
  70       <td>
  71         <ul>
  72           <li>Removed using get/set built-ins FPSCR in GCC >= 7.2 due to shortcomings.</li>
  73           <li>Fixed co-processor register access macros for Arm Compiler 5.</li>
  74         </ul>
  75       </td>
  76     </tr>
  77     <tr>
  78       <td>V1.1.1</td>
  79       <td>
  80         <ul>
  81           <li>Refactored L1 cache maintenance to be compiler agnostic.</li>
  82         </ul>
  83       </td>
  84     </tr>
  85     <tr>
  86       <td>V1.1.0</td>
  87       <td>
  88         <ul>
  89           <li>Added compiler_iccarm.h for IAR compiler.</li>
  90           <li>Added missing core access functions for Arm Compiler 5.</li>
  91           <li>Aligned access function to coprocessor 15.</li>
  92           <li>Additional generic Timer functions.</li>
  93           <li>Bug fixes and minor enhancements.</li>
  94         </ul>
  95       </td>
  96     </tr>
  97     <tr>
  98       <td>V1.0.0</td>
  99       <td>Initial Release for Cortex-A5/A7/A9 processors.</td>
 100     </tr>
 101 </table>