begriffs open source - cmsis/blob - ARM.CMSIS.pdsc

   1 <?xml version="1.0" encoding="UTF-8"?>
   2
   3 <package schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="PACK.xsd">
   4   <name>CMSIS</name>
   5   <description>CMSIS (Cortex Microcontroller Software Interface Standard)</description>
   6   <vendor>ARM</vendor>
   7   <!-- <license>license.txt</license> -->
   8   <url>http://www.keil.com/pack/</url>
   9
  10   <releases>
  11     <release version="5.3.1-dev7">
  12       Generic Arm Device:
  13        - Reworked ARM device support files.
  14        - Updated RTOS2 examples.
  15     </release>
  16     <release version="5.3.1-dev6">
  17       Utilities:
  18       - updated SVDConv and PackChk for Win32 and Linux
  19     </release>
  20     <release version="5.3.1-dev5">
  21       Aligned pack structure with repository.
  22       The following folders are deprecated:
  23       - CMSIS/Include/
  24       - CMSIS/DSP_Lib/
  25     </release>
  26     <release version="5.3.1-dev4">
  27       CMSIS-RTOS2:
  28         - API 2.1.3 (see revision history for details)
  29     </release>
  30     <release version="5.3.1-dev3">
  31       RTX5 (Cortex-A): updated exception handling
  32     </release>
  33     <release version="5.3.1-dev2">
  34       CMSIS-RTOS2:
  35         - RTX 5.4.0 (see revision history for details)
  36     </release>
  37     <release version="5.3.1-dev1">
  38       CMSIS-Core(M): 5.1.2 (see revision history for details)
  39       CMSIS-Core(A): 1.1.2 (see revision history for details)
  40       CMSIS-RTOS2:
  41         - RTX 5.3.1 (see revision history for details)
  42       CMSIS-Driver:
  43         - Flash Driver API V2.2.0
  44     </release>
  45     <release version="5.3.1-dev0">
  46       Patch release scheduled for after EW18.
  47     </release>
  48     <release version="5.3.0" date="2018-02-22">
  49       Updated Arm company brand.
  50       CMSIS-Core(M): 5.1.1 (see revision history for details)
  51       CMSIS-Core(A): 1.1.1 (see revision history for details)
  52       CMSIS-DAP: 2.0.0 (see revision history for details)
  53       CMSIS-NN: 1.0.0
  54         - Initial contribution of the bare metal Neural Network Library.
  55       CMSIS-RTOS2:
  56         - RTX 5.3.0 (see revision history for details)
  57         - OS Tick API 1.0.1
  58     </release>
  59     <release version="5.2.0" date="2017-11-16">
  60       CMSIS-Core(M): 5.1.0 (see revision history for details)
  61         - Added MPU Functions for ARMv8-M for Cortex-M23/M33.
  62         - Added compiler_iccarm.h to replace compiler_iar.h shipped with the compiler.
  63       CMSIS-Core(A): 1.1.0 (see revision history for details)
  64         - Added compiler_iccarm.h.
  65         - Added additional access functions for physical timer.
  66       CMSIS-DAP: 1.2.0 (see revision history for details)
  67       CMSIS-DSP: 1.5.2 (see revision history for details)
  68       CMSIS-Driver: 2.6.0 (see revision history for details)
  69         - CAN Driver API V1.2.0
  70         - NAND Driver API V2.3.0
  71       CMSIS-RTOS:
  72         - RTX: added variant for Infineon XMC4 series affected by PMU_CM.001 errata.
  73       CMSIS-RTOS2:
  74         - API 2.1.2 (see revision history for details)
  75         - RTX 5.2.3 (see revision history for details)
  76       Devices:
  77         - Added GCC startup and linker script for Cortex-A9.
  78         - Added device ARMCM0plus_MPU for Cortex-M0+ with MPU.
  79         - Added IAR startup code for Cortex-A9
  80     </release>
  81     <release version="5.1.1" date="2017-09-19">
  82       CMSIS-RTOS2:
  83       - RTX 5.2.1 (see revision history for details)
  84     </release>
  85     <release version="5.1.0" date="2017-08-04">
  86       CMSIS-Core(M): 5.0.2 (see revision history for details)
  87       - Changed Version Control macros to be core agnostic.
  88       - Added MPU Functions for ARMv7-M for Cortex-M0+/M3/M4/M7.
  89       CMSIS-Core(A): 1.0.0 (see revision history for details)
  90       - Initial release
  91       - IRQ Controller API 1.0.0
  92       CMSIS-Driver: 2.05 (see revision history for details)
  93       - All typedefs related to status have been made volatile.
  94       CMSIS-RTOS2:
  95       - API 2.1.1 (see revision history for details)
  96       - RTX 5.2.0 (see revision history for details)
  97       - OS Tick API 1.0.0
  98       CMSIS-DSP: 1.5.2 (see revision history for details)
  99       - Fixed GNU Compiler specific diagnostics.
 100       CMSIS-PACK: 1.5.0 (see revision history for details)
 101       - added System Description File (*.SDF) Format
 102       CMSIS-Zone: 0.0.1 (Preview)
 103       - Initial specification draft
 104     </release>
 105     <release version="5.0.1" date="2017-02-03">
 106       Package Description:
 107       - added taxonomy for Cclass RTOS
 108       CMSIS-RTOS2:
 109       - API 2.1   (see revision history for details)
 110       - RTX 5.1.0 (see revision history for details)
 111       CMSIS-Core: 5.0.1 (see revision history for details)
 112       - Added __PACKED_STRUCT macro
 113       - Added uVisior support
 114       - Updated cmsis_armcc.h: corrected macro __ARM_ARCH_6M__
 115       - Updated template for secure main function (main_s.c)
 116       - Updated template for Context Management for ARMv8-M TrustZone (tz_context.c)
 117       CMSIS-DSP: 1.5.1 (see revision history for details)
 118       - added ARMv8M DSP libraries.
 119       CMSIS-PACK:1.4.9 (see revision history for details)
 120       - added Pack Index File specification and schema file
 121     </release>
 122     <release version="5.0.0" date="2016-11-11">
 123       Changed open source license to Apache 2.0
 124       CMSIS_Core:
 125        - Added support for Cortex-M23 and Cortex-M33.
 126        - Added ARMv8-M device configurations for mainline and baseline.
 127        - Added CMSE support and thread context management for TrustZone for ARMv8-M
 128        - Added cmsis_compiler.h to unify compiler behaviour.
 129        - Updated function SCB_EnableICache (for Cortex-M7).
 130        - Added functions: NVIC_GetEnableIRQ, SCB_GetFPUType
 131       CMSIS-RTOS:
 132         - bug fix in RTX 4.82 (see revision history for details)
 133       CMSIS-RTOS2:
 134         - new API including compatibility layer to CMSIS-RTOS
 135         - reference implementation based on RTX5
 136         - supports all Cortex-M variants including TrustZone for ARMv8-M
 137       CMSIS-SVD:
 138        - reworked SVD format documentation
 139        - removed SVD file database documentation as SVD files are distributed in packs
 140        - updated SVDConv for Win32 and Linux
 141       CMSIS-DSP:
 142        - Moved DSP libraries from CMSIS/DSP/Lib to CMSIS/Lib.
 143        - Added DSP libraries build projects to CMSIS pack.
 144     </release>
 145     <release version="4.5.0" date="2015-10-28">
 146       - CMSIS-Core     4.30.0  (see revision history for details)
 147       - CMSIS-DAP      1.1.0   (unchanged)
 148       - CMSIS-Driver   2.04.0  (see revision history for details)
 149       - CMSIS-DSP      1.4.7   (no source code change [still labeled 1.4.5], see revision history for details)
 150       - CMSIS-PACK     1.4.1   (see revision history for details)
 151       - CMSIS-RTOS     4.80.0  Restored time delay parameter 'millisec' old behavior (prior V4.79) for software compatibility. (see revision history for details)
 152       - CMSIS-SVD      1.3.1   (see revision history for details)
 153     </release>
 154     <release version="4.4.0" date="2015-09-11">
 155       - CMSIS-Core     4.20   (see revision history for details)
 156       - CMSIS-DSP      1.4.6  (no source code change [still labeled 1.4.5], see revision history for details)
 157       - CMSIS-PACK     1.4.0  (adding memory attributes, algorithm style)
 158       - CMSIS-Driver   2.03.0 (adding CAN [Controller Area Network] API)
 159       - CMSIS-RTOS
 160         -- API         1.02   (unchanged)
 161         -- RTX         4.79   (see revision history for details)
 162       - CMSIS-SVD      1.3.0  (see revision history for details)
 163       - CMSIS-DAP      1.1.0  (extended with SWO support)
 164     </release>
 165     <release version="4.3.0" date="2015-03-20">
 166       - CMSIS-Core     4.10   (Cortex-M7 extended Cache Maintenance functions)
 167       - CMSIS-DSP      1.4.5  (see revision history for details)
 168       - CMSIS-Driver   2.02   (adding SAI (Serial Audio Interface) API)
 169       - CMSIS-PACK     1.3.3  (Semantic Versioning, Generator extensions)
 170       - CMSIS-RTOS
 171         -- API         1.02   (unchanged)
 172         -- RTX         4.78   (see revision history for details)
 173       - CMSIS-SVD      1.2    (unchanged)
 174     </release>
 175     <release version="4.2.0" date="2014-09-24">
 176       Adding Cortex-M7 support
 177       - CMSIS-Core     4.00  (Cortex-M7 support, corrected C++ include guards in core header files)
 178       - CMSIS-DSP      1.4.4 (Cortex-M7 support and corrected out of bound issues)
 179       - CMSIS-PACK     1.3.1 (Cortex-M7 updates, clarification, corrected batch files in Tutorial)
 180       - CMSIS-SVD      1.2   (Cortex-M7 extensions)
 181       - CMSIS-RTOS RTX 4.75  (see revision history for details)
 182     </release>
 183     <release version="4.1.1" date="2014-06-30">
 184       - fixed conditions preventing the inclusion of the DSP library in projects for Infineon XMC4000 series devices
 185     </release>
 186     <release version="4.1.0" date="2014-06-12">
 187       - CMSIS-Driver   2.02  (incompatible update)
 188       - CMSIS-Pack     1.3   (see revision history for details)
 189       - CMSIS-DSP      1.4.2 (unchanged)
 190       - CMSIS-Core     3.30  (unchanged)
 191       - CMSIS-RTOS RTX 4.74  (unchanged)
 192       - CMSIS-RTOS API 1.02  (unchanged)
 193       - CMSIS-SVD      1.10  (unchanged)
 194       PACK:
 195       - removed G++ specific files from PACK
 196       - added Component Startup variant "C Startup"
 197       - added Pack Checking Utility
 198       - updated conditions to reflect tool-chain dependency
 199       - added Taxonomy for Graphics
 200       - updated Taxonomy for unified drivers from "Drivers" to "CMSIS Drivers"
 201     </release>
 202     <release version="4.0.0">
 203       - CMSIS-Driver   2.00  Preliminary (incompatible update)
 204       - CMSIS-Pack     1.1   Preliminary
 205       - CMSIS-DSP      1.4.2 (see revision history for details)
 206       - CMSIS-Core     3.30  (see revision history for details)
 207       - CMSIS-RTOS RTX 4.74  (see revision history for details)
 208       - CMSIS-RTOS API 1.02  (unchanged)
 209       - CMSIS-SVD      1.10  (unchanged)
 210     </release>
 211     <release version="3.20.4">
 212       - CMSIS-RTOS 4.74 (see revision history for details)
 213       - PACK Extensions (Boards, Device Features, Flash Programming, Generators, Configuration Wizard). Schema version 1.1.
 214     </release>
 215     <release version="3.20.3">
 216       - CMSIS-Driver API Version 1.10 ARM prefix added (incompatible change)
 217       - CMSIS-RTOS 4.73 (see revision history for details)
 218     </release>
 219     <release version="3.20.2">
 220       - CMSIS-Pack documentation has been added
 221       - CMSIS-Drivers header and documentation have been added to PACK
 222       - CMSIS-CORE, CMSIS-DSP, CMSIS-RTOS API and CMSIS-SVD remain unchanged
 223     </release>
 224     <release version="3.20.1">
 225       - CMSIS-RTOS Keil RTX V4.72 has been added to PACK
 226       - CMSIS-CORE, CMSIS-DSP, CMSIS-RTOS API and CMSIS-SVD remain unchanged
 227     </release>
 228     <release version="3.20.0">
 229       The software portions that are deployed in the application program are now under a BSD license which allows usage
 230       of CMSIS components in any commercial or open source projects.  The Pack Description file Arm.CMSIS.pdsc describes the use cases
 231       The individual components have been update as listed below:
 232       - CMSIS-CORE adds functions for setting breakpoints, supports the latest GCC Compiler, and contains several corrections.
 233       - CMSIS-DSP library is optimized for more performance and contains several bug fixes.
 234       - CMSIS-RTOS API is extended with capabilities for short timeouts, Kernel initialization, and prepared for a C++ interface.
 235       - CMSIS-SVD is unchanged.
 236     </release>
 237   </releases>
 238
 239   <taxonomy>
 240     <description Cclass="Board Support">Generic Interfaces for Evaluation and Development Boards</description>
 241     <description Cclass="CMSIS" doc="CMSIS/Documentation/General/html/index.html">Cortex Microcontroller Software Interface Components</description>
 242     <description Cclass="Device" doc="CMSIS/Documentation/Core/html/index.html">Startup, System Setup</description>
 243     <description Cclass="CMSIS Driver" doc="CMSIS/Documentation/Driver/html/index.html">Unified Device Drivers compliant to CMSIS-Driver Specifications</description>
 244     <description Cclass="File System">File Drive Support and File System</description>
 245     <description Cclass="Graphics">Graphical User Interface</description>
 246     <description Cclass="Network">Network Stack using Internet Protocols</description>
 247     <description Cclass="USB">Universal Serial Bus Stack</description>
 248     <description Cclass="Compiler">Compiler Software Extensions</description>
 249     <description Cclass="RTOS">Real-time Operating System</description>
 250   </taxonomy>
 251
 252   <devices>
 253     <!-- ******************************  Cortex-M0  ****************************** -->
 254     <family Dfamily="ARM Cortex M0" Dvendor="ARM:82">
 255       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/index.html" title="Cortex-M0 Device Generic Users Guide"/>
 256       <description>
 257 The Cortex-M0 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 258 - simple, easy-to-use programmers model
 259 - highly efficient ultra-low power operation
 260 - excellent code density
 261 - deterministic, high-performance interrupt handling
 262 - upward compatibility with the rest of the Cortex-M processor family.
 263       </description>
 264       <!-- debug svd="Device/ARM/SVD/ARMCM0.svd"/ SVD files do not contain any peripheral -->
 265       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 266       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 267       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 268
 269       <device Dname="ARMCM0">
 270         <processor Dcore="Cortex-M0" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
 271         <compile header="Device/ARM/ARMCM0/Include/ARMCM0.h" define="ARMCM0"/>
 272       </device>
 273     </family>
 274
 275     <!-- ******************************  Cortex-M0P  ****************************** -->
 276     <family Dfamily="ARM Cortex M0 plus" Dvendor="ARM:82">
 277       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0662b/index.html" title="Cortex-M0+ Device Generic Users Guide"/>
 278       <description>
 279 The Cortex-M0+ processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 280 - simple, easy-to-use programmers model
 281 - highly efficient ultra-low power operation
 282 - excellent code density
 283 - deterministic, high-performance interrupt handling
 284 - upward compatibility with the rest of the Cortex-M processor family.
 285       </description>
 286       <!-- debug svd="Device/ARM/SVD/ARMCM0P.svd"/ SVD files do not contain any peripheral -->
 287       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 288       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 289       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 290
 291       <device Dname="ARMCM0P">
 292         <processor Dcore="Cortex-M0+" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
 293         <compile header="Device/ARM/ARMCM0plus/Include/ARMCM0plus.h" define="ARMCM0P"/>
 294       </device>
 295
 296       <device Dname="ARMCM0P_MPU">
 297         <processor Dcore="Cortex-M0+" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 298         <compile header="Device/ARM/ARMCM0plus/Include/ARMCM0plus_MPU.h" define="ARMCM0P_MPU"/>
 299       </device>
 300     </family>
 301
 302     <!-- ******************************  Cortex-M3  ****************************** -->
 303     <family Dfamily="ARM Cortex M3" Dvendor="ARM:82">
 304       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/index.html" title="Cortex-M3 Device Generic Users Guide"/>
 305       <description>
 306 The Cortex-M3 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 307 - simple, easy-to-use programmers model
 308 - highly efficient ultra-low power operation
 309 - excellent code density
 310 - deterministic, high-performance interrupt handling
 311 - upward compatibility with the rest of the Cortex-M processor family.
 312       </description>
 313       <!-- debug svd="Device/ARM/SVD/ARMCM3.svd"/ SVD files do not contain any peripheral -->
 314       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 315       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 316       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 317
 318       <device Dname="ARMCM3">
 319         <processor Dcore="Cortex-M3" DcoreVersion="r2p1" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 320         <compile header="Device/ARM/ARMCM3/Include/ARMCM3.h" define="ARMCM3"/>
 321       </device>
 322     </family>
 323
 324     <!-- ******************************  Cortex-M4  ****************************** -->
 325     <family Dfamily="ARM Cortex M4" Dvendor="ARM:82">
 326       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/index.html" title="Cortex-M4 Device Generic Users Guide"/>
 327       <description>
 328 The Cortex-M4 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 329 - simple, easy-to-use programmers model
 330 - highly efficient ultra-low power operation
 331 - excellent code density
 332 - deterministic, high-performance interrupt handling
 333 - upward compatibility with the rest of the Cortex-M processor family.
 334       </description>
 335       <!-- debug svd="Device/ARM/SVD/ARMCM4.svd"/ SVD files do not contain any peripheral -->
 336       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 337       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 338       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 339
 340       <device Dname="ARMCM4">
 341         <processor Dcore="Cortex-M4" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 342         <compile header="Device/ARM/ARMCM4/Include/ARMCM4.h"    define="ARMCM4"/>
 343       </device>
 344
 345       <device Dname="ARMCM4_FP">
 346         <processor Dcore="Cortex-M4" DcoreVersion="r0p1" Dfpu="SP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 347         <compile header="Device/ARM/ARMCM4/Include/ARMCM4_FP.h" define="ARMCM4_FP"/>
 348       </device>
 349     </family>
 350
 351     <!-- ******************************  Cortex-M7  ****************************** -->
 352     <family Dfamily="ARM Cortex M7" Dvendor="ARM:82">
 353       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0646b/index.html" title="Cortex-M7 Device Generic Users Guide"/>
 354       <description>
 355 The Cortex-M7 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 356 - simple, easy-to-use programmers model
 357 - highly efficient ultra-low power operation
 358 - excellent code density
 359 - deterministic, high-performance interrupt handling
 360 - upward compatibility with the rest of the Cortex-M processor family.
 361       </description>
 362       <!-- debug svd="Device/ARM/SVD/ARMCM7.svd"/ SVD files do not contain any peripheral -->
 363       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 364       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 365       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 366
 367       <device Dname="ARMCM7">
 368         <processor Dcore="Cortex-M7" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 369         <compile header="Device/ARM/ARMCM7/Include/ARMCM7.h" define="ARMCM7"/>
 370       </device>
 371
 372       <device Dname="ARMCM7_SP">
 373         <processor Dcore="Cortex-M7" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 374         <compile header="Device/ARM/ARMCM7/Include/ARMCM7_SP.h" define="ARMCM7_SP"/>
 375       </device>
 376
 377       <device Dname="ARMCM7_DP">
 378         <processor Dcore="Cortex-M7" DcoreVersion="r0p0" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 379         <compile header="Device/ARM/ARMCM7/Include/ARMCM7_DP.h" define="ARMCM7_DP"/>
 380       </device>
 381     </family>
 382
 383     <!-- ******************************  Cortex-M23  ********************** -->
 384     <family Dfamily="ARM Cortex M23" Dvendor="ARM:82">
 385       <!--book name="Device/ARM/Documents/??_dgug.pdf"       title="?? Device Generic Users Guide"/-->
 386       <description>
 387 The Arm Cortex-M23 is based on the Armv8-M baseline architecture.
 388 It is the smallest and most energy efficient Arm processor with Arm TrustZone technology.
 389 Cortex-M23 is the ideal processor for constrained embedded applications requiring efficient security.
 390       </description>
 391       <!-- debug svd="Device/ARM/SVD/ARMCM23.svd"/ SVD files do not contain any peripheral -->
 392       <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
 393       <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
 394       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 395       <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
 396       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 397
 398       <device Dname="ARMCM23">
 399         <processor Dcore="Cortex-M23" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
 400         <compile header="Device/ARM/ARMCM23/Include/ARMCM23.h" define="ARMCM23"/>
 401       </device>
 402
 403       <device Dname="ARMCM23_TZ">
 404         <processor Dcore="Cortex-M23" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 405         <compile header="Device/ARM/ARMCM23/Include/ARMCM23_TZ.h" define="ARMCM23_TZ"/>
 406       </device>
 407     </family>
 408
 409     <!-- ******************************  Cortex-M33  ****************************** -->
 410     <family Dfamily="ARM Cortex M33" Dvendor="ARM:82">
 411       <!--book name="Device/ARM/Documents/??_dgug.pdf"       title="?? Device Generic Users Guide"/-->
 412       <description>
 413 The Arm Cortex-M33 is the most configurable of all Cortex-M processors. It is a full featured microcontroller
 414 class processor based on the Armv8-M mainline architecture with Arm TrustZone security.
 415       </description>
 416       <!-- debug svd="Device/ARM/SVD/ARMCM33.svd"/ SVD files do not contain any peripheral -->
 417       <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
 418       <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
 419       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 420       <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
 421       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"          default="1"/-->
 422
 423       <device Dname="ARMCM33">
 424         <processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
 425         <description>
 426           no DSP Instructions, no Floating Point Unit, no TrustZone
 427         </description>
 428         <compile header="Device/ARM/ARMCM33/Include/ARMCM33.h" define="ARMCM33"/>
 429       </device>
 430
 431       <device Dname="ARMCM33_TZ">
 432         <processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 433         <description>
 434           no DSP Instructions, no Floating Point Unit, TrustZone
 435         </description>
 436         <compile header="Device/ARM/ARMCM33/Include/ARMCM33_TZ.h" define="ARMCM33_TZ"/>
 437       </device>
 438
 439       <device Dname="ARMCM33_DSP_FP">
 440         <processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
 441         <description>
 442           DSP Instructions, Single Precision Floating Point Unit, no TrustZone
 443         </description>
 444         <compile header="Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP.h" define="ARMCM33_DSP_FP"/>
 445       </device>
 446
 447       <device Dname="ARMCM33_DSP_FP_TZ">
 448         <processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 449         <description>
 450           DSP Instructions, Single Precision Floating Point Unit, TrustZone
 451         </description>
 452         <compile header="Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h" define="ARMCM33_DSP_FP_TZ"/>
 453       </device>
 454     </family>
 455
 456     <!-- ******************************  ARMSC000  ****************************** -->
 457     <family Dfamily="ARM SC000" Dvendor="ARM:82">
 458       <description>
 459 The Arm SC000 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including:
 460 - simple, easy-to-use programmers model
 461 - highly efficient ultra-low power operation
 462 - excellent code density
 463 - deterministic, high-performance interrupt handling
 464       </description>
 465       <!-- debug svd="Device/ARM/SVD/ARMSC000.svd"/ SVD files do not contain any peripheral -->
 466       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 467       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 468       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 469
 470       <device Dname="ARMSC000">
 471         <processor Dcore="SC000" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
 472         <compile header="Device/ARM/ARMSC000/Include/ARMSC000.h" define="ARMSC000"/>
 473       </device>
 474     </family>
 475
 476     <!-- ******************************  ARMSC300  ****************************** -->
 477     <family Dfamily="ARM SC300" Dvendor="ARM:82">
 478       <description>
 479 The ARM SC300 processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including:
 480 - simple, easy-to-use programmers model
 481 - highly efficient ultra-low power operation
 482 - excellent code density
 483 - deterministic, high-performance interrupt handling
 484       </description>
 485       <!-- debug svd="Device/ARM/SVD/ARMSC300.svd"/ SVD files do not contain any peripheral -->
 486       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 487       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 488       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 489
 490       <device Dname="ARMSC300">
 491         <processor Dcore="SC300" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
 492         <compile header="Device/ARM/ARMSC300/Include/ARMSC300.h" define="ARMSC300"/>
 493       </device>
 494     </family>
 495
 496     <!-- ******************************  ARMv8-M Baseline  ********************** -->
 497     <family Dfamily="ARMv8-M Baseline" Dvendor="ARM:82">
 498       <!--book name="Device/ARM/Documents/ARMv8MBL_dgug.pdf"       title="ARMv8MBL Device Generic Users Guide"/-->
 499       <description>
 500 Armv8-M Baseline based device with TrustZone
 501       </description>
 502       <!-- debug svd="Device/ARM/SVD/ARMv8MBL.svd"/ SVD files do not contain any peripheral -->
 503       <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
 504       <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
 505       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 506       <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
 507       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 508
 509       <device Dname="ARMv8MBL">
 510         <processor Dcore="ARMV8MBL" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 511         <compile header="Device/ARM/ARMv8MBL/Include/ARMv8MBL.h" define="ARMv8MBL"/>
 512       </device>
 513     </family>
 514
 515     <!-- ******************************  ARMv8-M Mainline  ****************************** -->
 516     <family Dfamily="ARMv8-M Mainline" Dvendor="ARM:82">
 517       <!--book name="Device/ARM/Documents/ARMv8MML_dgug.pdf"       title="ARMv8MML Device Generic Users Guide"/-->
 518       <description>
 519 Armv8-M Mainline based device with TrustZone
 520       </description>
 521       <!-- debug svd="Device/ARM/SVD/ARMv8MML.svd"/ SVD files do not contain any peripheral -->
 522       <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
 523       <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
 524       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 525       <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
 526       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 527
 528       <device Dname="ARMv8MML">
 529         <processor Dcore="ARMV8MML" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 530         <description>
 531           no DSP Instructions, no Floating Point Unit, TrustZone
 532         </description>
 533         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML.h" define="ARMv8MML"/>
 534       </device>
 535
 536       <device Dname="ARMv8MML_DSP">
 537         <processor Dcore="ARMV8MML" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 538         <description>
 539           DSP Instructions, no Floating Point Unit, TrustZone
 540         </description>
 541         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DSP.h" define="ARMv8MML_DSP"/>
 542       </device>
 543
 544       <device Dname="ARMv8MML_SP">
 545         <processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 546         <description>
 547           no DSP Instructions, Single Precision Floating Point Unit, TrustZone
 548         </description>
 549         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_SP.h" define="ARMv8MML_SP"/>
 550       </device>
 551
 552       <device Dname="ARMv8MML_DSP_SP">
 553         <processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 554         <description>
 555           DSP Instructions, Single Precision Floating Point Unit, TrustZone
 556         </description>
 557         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_SP.h" define="ARMv8MML_DSP_SP"/>
 558       </device>
 559
 560       <device Dname="ARMv8MML_DP">
 561         <processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="DP_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 562         <description>
 563           no DSP Instructions, Double Precision Floating Point Unit, TrustZone
 564         </description>
 565         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DP.h" define="ARMv8MML_DP"/>
 566       </device>
 567
 568       <device Dname="ARMv8MML_DSP_DP">
 569         <processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="DP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 570         <description>
 571           DSP Instructions, Double Precision Floating Point Unit, TrustZone
 572         </description>
 573         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h" define="ARMv8MML_DSP_DP"/>
 574       </device>
 575     </family>
 576
 577     <!-- ******************************  Cortex-A5  ****************************** -->
 578     <family Dfamily="ARM Cortex A5" Dvendor="ARM:82">
 579       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0433c/index.html" title="Cortex-A5 Technical Reference Manual"/>
 580       <description>
 581 The Arm Cortex-A5 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full
 582 virtual memory capabilities. The Cortex-A5 processor implements the Armv7-A architecture profile and can execute 32-bit
 583 Arm instructions and 16-bit and 32-bit Thumb instructions. The Cortex-A5 is the smallest member of the Cortex-A processor family.
 584       </description>
 585
 586       <memory id="IROM1"                                start="0x80000000" size="0x00200000" startup="1" default="1"/>
 587       <memory id="IRAM1"                                start="0x80200000" size="0x00200000" init   ="0" default="1"/>
 588
 589       <device Dname="ARMCA5">
 590         <processor Dcore="Cortex-A5" DcoreVersion="r0p1" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable"/>
 591         <compile header="Device/ARM/ARMCA5/Include/ARMCA5.h" define="ARMCA5"/>
 592       </device>
 593     </family>
 594
 595     <!-- ******************************  Cortex-A7  ****************************** -->
 596     <family Dfamily="ARM Cortex A7" Dvendor="ARM:82">
 597       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/index.html" title="Cortex-A7 MPCore Technical Reference Manual"/>
 598       <description>
 599 The Cortex-A7 MPCore processor is a high-performance, low-power processor that implements the Armv7-A architecture.
 600 The Cortex-A7 MPCore processor has one to four processors in a single multiprocessor device with a L1 cache subsystem,
 601 an optional integrated GIC, and an optional L2 cache controller.
 602       </description>
 603
 604       <memory id="IROM1"                                start="0x80000000" size="0x00200000" startup="1" default="1"/>
 605       <memory id="IRAM1"                                start="0x80200000" size="0x00200000" init   ="0" default="1"/>
 606
 607       <device Dname="ARMCA7">
 608         <processor Dcore="Cortex-A7" DcoreVersion="r0p5" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable"/>
 609         <compile header="Device/ARM/ARMCA7/Include/ARMCA7.h" define="ARMCA7"/>
 610       </device>
 611     </family>
 612
 613     <!-- ******************************  Cortex-A9  ****************************** -->
 614     <family Dfamily="ARM Cortex A9" Dvendor="ARM:82">
 615       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.100511_0401_10_en/index.html" title="Cortex-A9 Technical Reference Manual"/>
 616       <description>
 617 The Cortex-A9 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full virtual memory capabilities.
 618 The Cortex-A9 processor implements the Armv7-A architecture and runs 32-bit Arm instructions, 16-bit and 32-bit Thumb instructions,
 619 and 8-bit Java bytecodes in Jazelle state.
 620       </description>
 621
 622       <memory id="IROM1"                                start="0x80000000" size="0x00200000" startup="1" default="1"/>
 623       <memory id="IRAM1"                                start="0x80200000" size="0x00200000" init   ="0" default="1"/>
 624
 625       <device Dname="ARMCA9">
 626         <processor Dcore="Cortex-A9" DcoreVersion="r4p1" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable"/>
 627         <compile header="Device/ARM/ARMCA9/Include/ARMCA9.h" define="ARMCA9"/>
 628       </device>
 629     </family>
 630   </devices>
 631
 632
 633   <apis>
 634     <!-- CMSIS Device API -->
 635     <api Cclass="Device" Cgroup="IRQ Controller" Capiversion="1.0.0" exclusive="1">
 636       <description>Device interrupt controller interface</description>
 637       <files>
 638         <file category="header" name="CMSIS/Core_A/Include/irq_ctrl.h"/>
 639       </files>
 640     </api>
 641     <api Cclass="Device" Cgroup="OS Tick" Capiversion="1.0.1" exclusive="1">
 642       <description>RTOS Kernel system tick timer interface</description>
 643       <files>
 644         <file category="header" name="CMSIS/RTOS2/Include/os_tick.h"/>
 645       </files>
 646     </api>
 647     <!-- CMSIS-RTOS API -->
 648     <api Cclass="CMSIS" Cgroup="RTOS" Capiversion="1.0.0" exclusive="1">
 649       <description>CMSIS-RTOS API for Cortex-M, SC000, and SC300</description>
 650       <files>
 651         <file category="doc" name="CMSIS/Documentation/RTOS/html/index.html"/>
 652       </files>
 653     </api>
 654     <api Cclass="CMSIS" Cgroup="RTOS2" Capiversion="2.1.3" exclusive="1">
 655       <description>CMSIS-RTOS API for Cortex-M, SC000, and SC300</description>
 656       <files>
 657         <file category="doc" name="CMSIS/Documentation/RTOS2/html/index.html"/>
 658         <file category="header" name="CMSIS/RTOS2/Include/cmsis_os2.h"/>
 659       </files>
 660     </api>
 661     <!-- CMSIS Driver API -->
 662     <api Cclass="CMSIS Driver" Cgroup="USART" Capiversion="2.3.0" exclusive="0">
 663       <description>USART Driver API for Cortex-M</description>
 664       <files>
 665         <file category="doc" name="CMSIS/Documentation/Driver/html/group__usart__interface__gr.html" />
 666         <file category="header" name="CMSIS/Driver/Include/Driver_USART.h" />
 667       </files>
 668     </api>
 669     <api Cclass="CMSIS Driver" Cgroup="SPI" Capiversion="2.2.0" exclusive="0">
 670       <description>SPI Driver API for Cortex-M</description>
 671       <files>
 672         <file category="doc" name="CMSIS/Documentation/Driver/html/group__spi__interface__gr.html" />
 673         <file category="header" name="CMSIS/Driver/Include/Driver_SPI.h" />
 674       </files>
 675     </api>
 676     <api Cclass="CMSIS Driver" Cgroup="SAI" Capiversion="1.1.0" exclusive="0">
 677       <description>SAI Driver API for Cortex-M</description>
 678       <files>
 679         <file category="doc" name="CMSIS/Documentation/Driver/html/group__sai__interface__gr.html"/>
 680         <file category="header" name="CMSIS/Driver/Include/Driver_SAI.h" />
 681       </files>
 682     </api>
 683     <api Cclass="CMSIS Driver" Cgroup="I2C" Capiversion="2.3.0" exclusive="0">
 684       <description>I2C Driver API for Cortex-M</description>
 685       <files>
 686         <file category="doc" name="CMSIS/Documentation/Driver/html/group__i2c__interface__gr.html"/>
 687         <file category="header" name="CMSIS/Driver/Include/Driver_I2C.h" />
 688       </files>
 689     </api>
 690     <api Cclass="CMSIS Driver" Cgroup="CAN" Capiversion="1.2.0" exclusive="0">
 691       <description>CAN Driver API for Cortex-M</description>
 692       <files>
 693         <file category="doc" name="CMSIS/Documentation/Driver/html/group__can__interface__gr.html"/>
 694         <file category="header" name="CMSIS/Driver/Include/Driver_CAN.h" />
 695       </files>
 696     </api>
 697     <api Cclass="CMSIS Driver" Cgroup="Flash" Capiversion="2.2.0" exclusive="0">
 698       <description>Flash Driver API for Cortex-M</description>
 699       <files>
 700         <file category="doc" name="CMSIS/Documentation/Driver/html/group__flash__interface__gr.html" />
 701         <file category="header" name="CMSIS/Driver/Include/Driver_Flash.h" />
 702       </files>
 703     </api>
 704     <api Cclass="CMSIS Driver" Cgroup="MCI" Capiversion="2.3.0" exclusive="0">
 705       <description>MCI Driver API for Cortex-M</description>
 706       <files>
 707         <file category="doc" name="CMSIS/Documentation/Driver/html/group__mci__interface__gr.html" />
 708         <file category="header" name="CMSIS/Driver/Include/Driver_MCI.h" />
 709       </files>
 710     </api>
 711     <api Cclass="CMSIS Driver" Cgroup="NAND" Capiversion="2.3.0" exclusive="0">
 712       <description>NAND Flash Driver API for Cortex-M</description>
 713       <files>
 714         <file category="doc" name="CMSIS/Documentation/Driver/html/group__nand__interface__gr.html" />
 715         <file category="header" name="CMSIS/Driver/Include/Driver_NAND.h" />
 716       </files>
 717     </api>
 718     <api Cclass="CMSIS Driver" Cgroup="Ethernet" Capiversion="2.1.0" exclusive="0">
 719       <description>Ethernet MAC and PHY Driver API for Cortex-M</description>
 720       <files>
 721         <file category="doc" name="CMSIS/Documentation/Driver/html/group__eth__interface__gr.html" />
 722         <file category="header" name="CMSIS/Driver/Include/Driver_ETH_MAC.h" />
 723         <file category="header" name="CMSIS/Driver/Include/Driver_ETH_PHY.h" />
 724       </files>
 725     </api>
 726     <api Cclass="CMSIS Driver" Cgroup="Ethernet MAC" Capiversion="2.1.0" exclusive="0">
 727       <description>Ethernet MAC Driver API for Cortex-M</description>
 728       <files>
 729         <file category="doc" name="CMSIS/Documentation/Driver/html/group__eth__mac__interface__gr.html" />
 730         <file category="header" name="CMSIS/Driver/Include/Driver_ETH_MAC.h" />
 731       </files>
 732     </api>
 733     <api Cclass="CMSIS Driver" Cgroup="Ethernet PHY" Capiversion="2.1.0" exclusive="0">
 734       <description>Ethernet PHY Driver API for Cortex-M</description>
 735       <files>
 736         <file category="doc" name="CMSIS/Documentation/Driver/html/group__eth__phy__interface__gr.html" />
 737         <file category="header" name="CMSIS/Driver/Include/Driver_ETH_PHY.h" />
 738       </files>
 739     </api>
 740     <api Cclass="CMSIS Driver" Cgroup="USB Device" Capiversion="2.2.0" exclusive="0">
 741       <description>USB Device Driver API for Cortex-M</description>
 742       <files>
 743         <file category="doc" name="CMSIS/Documentation/Driver/html/group__usbd__interface__gr.html" />
 744         <file category="header" name="CMSIS/Driver/Include/Driver_USBD.h" />
 745       </files>
 746     </api>
 747     <api Cclass="CMSIS Driver" Cgroup="USB Host" Capiversion="2.2.0" exclusive="0">
 748       <description>USB Host Driver API for Cortex-M</description>
 749       <files>
 750         <file category="doc" name="CMSIS/Documentation/Driver/html/group__usbh__interface__gr.html" />
 751         <file category="header" name="CMSIS/Driver/Include/Driver_USBH.h" />
 752       </files>
 753     </api>
 754   </apis>
 755
 756   <!-- conditions are dependency rules that can apply to a component or an individual file -->
 757   <conditions>
 758     <!-- compiler -->
 759     <condition id="ARMCC6">
 760       <accept Tcompiler="ARMCC" Toptions="AC6"/>
 761       <accept Tcompiler="ARMCC" Toptions="AC6LTO"/>
 762     </condition>
 763     <condition id="ARMCC5">
 764       <require Tcompiler="ARMCC" Toptions="AC5"/>
 765     </condition>
 766     <condition id="ARMCC">
 767       <require Tcompiler="ARMCC"/>
 768     </condition>
 769     <condition id="GCC">
 770       <require Tcompiler="GCC"/>
 771     </condition>
 772     <condition id="IAR">
 773       <require Tcompiler="IAR"/>
 774     </condition>
 775     <condition id="ARMCC GCC">
 776       <accept Tcompiler="ARMCC"/>
 777       <accept Tcompiler="GCC"/>
 778     </condition>
 779     <condition id="ARMCC GCC IAR">
 780       <accept Tcompiler="ARMCC"/>
 781       <accept Tcompiler="GCC"/>
 782       <accept Tcompiler="IAR"/>
 783     </condition>
 784
 785     <!-- Arm architecture -->
 786     <condition id="ARMv6-M Device">
 787       <description>Armv6-M architecture based device</description>
 788       <accept Dcore="Cortex-M0"/>
 789       <accept Dcore="Cortex-M0+"/>
 790       <accept Dcore="SC000"/>
 791     </condition>
 792     <condition id="ARMv7-M Device">
 793       <description>Armv7-M architecture based device</description>
 794       <accept Dcore="Cortex-M3"/>
 795       <accept Dcore="Cortex-M4"/>
 796       <accept Dcore="Cortex-M7"/>
 797       <accept Dcore="SC300"/>
 798     </condition>
 799     <condition id="ARMv8-M Device">
 800       <description>Armv8-M architecture based device</description>
 801       <accept Dcore="ARMV8MBL"/>
 802       <accept Dcore="ARMV8MML"/>
 803       <accept Dcore="Cortex-M23"/>
 804       <accept Dcore="Cortex-M33"/>
 805     </condition>
 806     <condition id="ARMv8-M TZ Device">
 807       <description>Armv8-M architecture based device with TrustZone</description>
 808       <require condition="ARMv8-M Device"/>
 809       <require Dtz="TZ"/>
 810     </condition>
 811     <condition id="ARMv6_7-M Device">
 812       <description>Armv6_7-M architecture based device</description>
 813       <accept condition="ARMv6-M Device"/>
 814       <accept condition="ARMv7-M Device"/>
 815     </condition>
 816     <condition id="ARMv6_7_8-M Device">
 817       <description>Armv6_7_8-M architecture based device</description>
 818       <accept condition="ARMv6-M Device"/>
 819       <accept condition="ARMv7-M Device"/>
 820       <accept condition="ARMv8-M Device"/>
 821     </condition>
 822     <condition id="ARMv7-A Device">
 823       <description>Armv7-A architecture based device</description>
 824       <accept Dcore="Cortex-A5"/>
 825       <accept Dcore="Cortex-A7"/>
 826       <accept Dcore="Cortex-A9"/>
 827     </condition>
 828
 829     <!-- ARM core -->
 830     <condition id="CM0">
 831       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device</description>
 832       <accept Dcore="Cortex-M0"/>
 833       <accept Dcore="Cortex-M0+"/>
 834       <accept Dcore="SC000"/>
 835     </condition>
 836     <condition id="CM3">
 837       <description>Cortex-M3 or SC300 processor based device</description>
 838       <accept Dcore="Cortex-M3"/>
 839       <accept Dcore="SC300"/>
 840     </condition>
 841     <condition id="CM4">
 842       <description>Cortex-M4 processor based device</description>
 843       <require Dcore="Cortex-M4" Dfpu="NO_FPU"/>
 844     </condition>
 845     <condition id="CM4_FP">
 846       <description>Cortex-M4 processor based device using Floating Point Unit</description>
 847       <accept Dcore="Cortex-M4" Dfpu="FPU"/>
 848       <accept Dcore="Cortex-M4" Dfpu="SP_FPU"/>
 849       <accept Dcore="Cortex-M4" Dfpu="DP_FPU"/>
 850     </condition>
 851     <condition id="CM7">
 852       <description>Cortex-M7 processor based device</description>
 853       <require Dcore="Cortex-M7" Dfpu="NO_FPU"/>
 854     </condition>
 855     <condition id="CM7_FP">
 856       <description>Cortex-M7 processor based device using Floating Point Unit</description>
 857       <accept Dcore="Cortex-M7" Dfpu="SP_FPU"/>
 858       <accept Dcore="Cortex-M7" Dfpu="DP_FPU"/>
 859     </condition>
 860     <condition id="CM7_SP">
 861       <description>Cortex-M7 processor based device using Floating Point Unit (SP)</description>
 862       <require Dcore="Cortex-M7" Dfpu="SP_FPU"/>
 863     </condition>
 864     <condition id="CM7_DP">
 865       <description>Cortex-M7 processor based device using Floating Point Unit (DP)</description>
 866       <require Dcore="Cortex-M7" Dfpu="DP_FPU"/>
 867     </condition>
 868     <condition id="CM23">
 869       <description>Cortex-M23 processor based device</description>
 870       <require Dcore="Cortex-M23"/>
 871     </condition>
 872     <condition id="CM33">
 873       <description>Cortex-M33 processor based device</description>
 874       <require Dcore="Cortex-M33" Dfpu="NO_FPU"/>
 875     </condition>
 876     <condition id="CM33_FP">
 877       <description>Cortex-M33 processor based device using Floating Point Unit</description>
 878       <require Dcore="Cortex-M33" Dfpu="SP_FPU"/>
 879     </condition>
 880     <condition id="ARMv8MBL">
 881       <description>Armv8-M Baseline processor based device</description>
 882       <require Dcore="ARMV8MBL"/>
 883     </condition>
 884     <condition id="ARMv8MML">
 885       <description>Armv8-M Mainline processor based device</description>
 886       <require Dcore="ARMV8MML" Dfpu="NO_FPU"/>
 887     </condition>
 888     <condition id="ARMv8MML_FP">
 889       <description>Armv8-M Mainline processor based device using Floating Point Unit</description>
 890       <accept Dcore="ARMV8MML" Dfpu="SP_FPU"/>
 891       <accept Dcore="ARMV8MML" Dfpu="DP_FPU"/>
 892     </condition>
 893
 894     <condition id="CM33_NODSP_NOFPU">
 895       <description>CM33, no DSP, no FPU</description>
 896       <require Dcore="Cortex-M33" Ddsp="NO_DSP" Dfpu="NO_FPU"/>
 897     </condition>
 898     <condition id="CM33_DSP_NOFPU">
 899       <description>CM33, DSP, no FPU</description>
 900       <require Dcore="Cortex-M33" Ddsp="DSP" Dfpu="NO_FPU"/>
 901     </condition>
 902     <condition id="CM33_NODSP_SP">
 903       <description>CM33, no DSP, SP FPU</description>
 904       <require Dcore="Cortex-M33" Ddsp="NO_DSP" Dfpu="SP_FPU"/>
 905     </condition>
 906     <condition id="CM33_DSP_SP">
 907       <description>CM33, DSP, SP FPU</description>
 908       <require Dcore="Cortex-M33" Ddsp="DSP" Dfpu="SP_FPU"/>
 909     </condition>
 910
 911     <condition id="ARMv8MML_NODSP_NOFPU">
 912       <description>Armv8-M Mainline, no DSP, no FPU</description>
 913       <require Dcore="ARMV8MML" Ddsp="NO_DSP" Dfpu="NO_FPU"/>
 914     </condition>
 915     <condition id="ARMv8MML_DSP_NOFPU">
 916       <description>Armv8-M Mainline, DSP, no FPU</description>
 917       <require Dcore="ARMV8MML" Ddsp="DSP" Dfpu="NO_FPU"/>
 918     </condition>
 919     <condition id="ARMv8MML_NODSP_SP">
 920       <description>Armv8-M Mainline, no DSP, SP FPU</description>
 921       <require Dcore="ARMV8MML" Ddsp="NO_DSP" Dfpu="SP_FPU"/>
 922     </condition>
 923     <condition id="ARMv8MML_DSP_SP">
 924       <description>Armv8-M Mainline, DSP, SP FPU</description>
 925       <require Dcore="ARMV8MML" Ddsp="DSP" Dfpu="SP_FPU"/>
 926     </condition>
 927
 928     <condition id="CA5_CA9">
 929       <description>Cortex-A5 or Cortex-A9 processor based device</description>
 930       <accept Dcore="Cortex-A5"/>
 931       <accept Dcore="Cortex-A9"/>
 932     </condition>
 933
 934     <condition id="CA7">
 935       <description>Cortex-A7 processor based device</description>
 936       <accept Dcore="Cortex-A7"/>
 937     </condition>
 938
 939     <!-- ARMCC compiler -->
 940     <condition id="CA_ARMCC5">
 941       <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the Arm Compiler 5</description>
 942       <require condition="ARMv7-A Device"/>
 943       <require condition="ARMCC5"/>
 944     </condition>
 945     <condition id="CA_ARMCC6">
 946       <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the Arm Compiler 6</description>
 947       <require condition="ARMv7-A Device"/>
 948       <require condition="ARMCC6"/>
 949     </condition>
 950
 951     <condition id="CM0_ARMCC">
 952       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device for the Arm Compiler</description>
 953       <require condition="CM0"/>
 954       <require Tcompiler="ARMCC"/>
 955     </condition>
 956     <condition id="CM0_LE_ARMCC">
 957       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the Arm Compiler</description>
 958       <require condition="CM0_ARMCC"/>
 959       <require Dendian="Little-endian"/>
 960     </condition>
 961     <condition id="CM0_BE_ARMCC">
 962       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the Arm Compiler</description>
 963       <require condition="CM0_ARMCC"/>
 964       <require Dendian="Big-endian"/>
 965     </condition>
 966
 967     <condition id="CM3_ARMCC">
 968       <description>Cortex-M3 or SC300 processor based device for the Arm Compiler</description>
 969       <require condition="CM3"/>
 970       <require Tcompiler="ARMCC"/>
 971     </condition>
 972     <condition id="CM3_LE_ARMCC">
 973       <description>Cortex-M3 or SC300 processor based device in little endian mode for the Arm Compiler</description>
 974       <require condition="CM3_ARMCC"/>
 975       <require Dendian="Little-endian"/>
 976     </condition>
 977     <condition id="CM3_BE_ARMCC">
 978       <description>Cortex-M3 or SC300 processor based device in big endian mode for the Arm Compiler</description>
 979       <require condition="CM3_ARMCC"/>
 980       <require Dendian="Big-endian"/>
 981     </condition>
 982
 983     <condition id="CM4_ARMCC">
 984       <description>Cortex-M4 processor based device for the Arm Compiler</description>
 985       <require condition="CM4"/>
 986       <require Tcompiler="ARMCC"/>
 987     </condition>
 988     <condition id="CM4_LE_ARMCC">
 989       <description>Cortex-M4 processor based device in little endian mode for the Arm Compiler</description>
 990       <require condition="CM4_ARMCC"/>
 991       <require Dendian="Little-endian"/>
 992     </condition>
 993     <condition id="CM4_BE_ARMCC">
 994       <description>Cortex-M4 processor based device in big endian mode for the Arm Compiler</description>
 995       <require condition="CM4_ARMCC"/>
 996       <require Dendian="Big-endian"/>
 997     </condition>
 998
 999     <condition id="CM4_FP_ARMCC">
1000       <description>Cortex-M4 processor based device using Floating Point Unit for the Arm Compiler</description>
1001       <require condition="CM4_FP"/>
1002       <require Tcompiler="ARMCC"/>
1003     </condition>
1004     <condition id="CM4_FP_LE_ARMCC">
1005       <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
1006       <require condition="CM4_FP_ARMCC"/>
1007       <require Dendian="Little-endian"/>
1008     </condition>
1009     <condition id="CM4_FP_BE_ARMCC">
1010       <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
1011       <require condition="CM4_FP_ARMCC"/>
1012       <require Dendian="Big-endian"/>
1013     </condition>
1014
1015     <condition id="CM7_ARMCC">
1016       <description>Cortex-M7 processor based device for the Arm Compiler</description>
1017       <require condition="CM7"/>
1018       <require Tcompiler="ARMCC"/>
1019     </condition>
1020     <condition id="CM7_LE_ARMCC">
1021       <description>Cortex-M7 processor based device in little endian mode for the Arm Compiler</description>
1022       <require condition="CM7_ARMCC"/>
1023       <require Dendian="Little-endian"/>
1024     </condition>
1025     <condition id="CM7_BE_ARMCC">
1026       <description>Cortex-M7 processor based device in big endian mode for the Arm Compiler</description>
1027       <require condition="CM7_ARMCC"/>
1028       <require Dendian="Big-endian"/>
1029     </condition>
1030
1031     <condition id="CM7_FP_ARMCC">
1032       <description>Cortex-M7 processor based device using Floating Point Unit for the Arm Compiler</description>
1033       <require condition="CM7_FP"/>
1034       <require Tcompiler="ARMCC"/>
1035     </condition>
1036     <condition id="CM7_FP_LE_ARMCC">
1037       <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
1038       <require condition="CM7_FP_ARMCC"/>
1039       <require Dendian="Little-endian"/>
1040     </condition>
1041     <condition id="CM7_FP_BE_ARMCC">
1042       <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
1043       <require condition="CM7_FP_ARMCC"/>
1044       <require Dendian="Big-endian"/>
1045     </condition>
1046
1047     <condition id="CM7_SP_ARMCC">
1048       <description>Cortex-M7 processor based device using Floating Point Unit (SP) for the Arm Compiler</description>
1049       <require condition="CM7_SP"/>
1050       <require Tcompiler="ARMCC"/>
1051     </condition>
1052     <condition id="CM7_SP_LE_ARMCC">
1053       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the Arm Compiler</description>
1054       <require condition="CM7_SP_ARMCC"/>
1055       <require Dendian="Little-endian"/>
1056     </condition>
1057     <condition id="CM7_SP_BE_ARMCC">
1058       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the Arm Compiler</description>
1059       <require condition="CM7_SP_ARMCC"/>
1060       <require Dendian="Big-endian"/>
1061     </condition>
1062
1063     <condition id="CM7_DP_ARMCC">
1064       <description>Cortex-M7 processor based device using Floating Point Unit (DP) for the Arm Compiler</description>
1065       <require condition="CM7_DP"/>
1066       <require Tcompiler="ARMCC"/>
1067     </condition>
1068     <condition id="CM7_DP_LE_ARMCC">
1069       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the Arm Compiler</description>
1070       <require condition="CM7_DP_ARMCC"/>
1071       <require Dendian="Little-endian"/>
1072     </condition>
1073     <condition id="CM7_DP_BE_ARMCC">
1074       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the Arm Compiler</description>
1075       <require condition="CM7_DP_ARMCC"/>
1076       <require Dendian="Big-endian"/>
1077     </condition>
1078
1079     <condition id="CM23_ARMCC">
1080       <description>Cortex-M23 processor based device for the Arm Compiler</description>
1081       <require condition="CM23"/>
1082       <require Tcompiler="ARMCC"/>
1083     </condition>
1084     <condition id="CM23_LE_ARMCC">
1085       <description>Cortex-M23 processor based device in little endian mode for the Arm Compiler</description>
1086       <require condition="CM23_ARMCC"/>
1087       <require Dendian="Little-endian"/>
1088     </condition>
1089     <condition id="CM23_BE_ARMCC">
1090       <description>Cortex-M23 processor based device in big endian mode for the Arm Compiler</description>
1091       <require condition="CM23_ARMCC"/>
1092       <require Dendian="Big-endian"/>
1093     </condition>
1094
1095     <condition id="CM33_ARMCC">
1096       <description>Cortex-M33 processor based device for the Arm Compiler</description>
1097       <require condition="CM33"/>
1098       <require Tcompiler="ARMCC"/>
1099     </condition>
1100     <condition id="CM33_LE_ARMCC">
1101       <description>Cortex-M33 processor based device in little endian mode for the Arm Compiler</description>
1102       <require condition="CM33_ARMCC"/>
1103       <require Dendian="Little-endian"/>
1104     </condition>
1105     <condition id="CM33_BE_ARMCC">
1106       <description>Cortex-M33 processor based device in big endian mode for the Arm Compiler</description>
1107       <require condition="CM33_ARMCC"/>
1108       <require Dendian="Big-endian"/>
1109     </condition>
1110
1111     <condition id="CM33_FP_ARMCC">
1112       <description>Cortex-M33 processor based device using Floating Point Unit for the Arm Compiler</description>
1113       <require condition="CM33_FP"/>
1114       <require Tcompiler="ARMCC"/>
1115     </condition>
1116     <condition id="CM33_FP_LE_ARMCC">
1117       <description>Cortex-M33 processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
1118       <require condition="CM33_FP_ARMCC"/>
1119       <require Dendian="Little-endian"/>
1120     </condition>
1121     <condition id="CM33_FP_BE_ARMCC">
1122       <description>Cortex-M33 processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
1123       <require condition="CM33_FP_ARMCC"/>
1124       <require Dendian="Big-endian"/>
1125     </condition>
1126
1127     <condition id="CM33_NODSP_NOFPU_ARMCC">
1128       <description>Cortex-M33 processor, no DSP, no FPU, Arm Compiler</description>
1129       <require condition="CM33_NODSP_NOFPU"/>
1130       <require Tcompiler="ARMCC"/>
1131     </condition>
1132     <condition id="CM33_DSP_NOFPU_ARMCC">
1133       <description>Cortex-M33 processor, DSP, no FPU, Arm Compiler</description>
1134       <require condition="CM33_DSP_NOFPU"/>
1135       <require Tcompiler="ARMCC"/>
1136     </condition>
1137     <condition id="CM33_NODSP_SP_ARMCC">
1138       <description>Cortex-M33 processor, no DSP, SP FPU, Arm Compiler</description>
1139       <require condition="CM33_NODSP_SP"/>
1140       <require Tcompiler="ARMCC"/>
1141     </condition>
1142     <condition id="CM33_DSP_SP_ARMCC">
1143       <description>Cortex-M33 processor, DSP, SP FPU, Arm Compiler</description>
1144       <require condition="CM33_DSP_SP"/>
1145       <require Tcompiler="ARMCC"/>
1146     </condition>
1147     <condition id="CM33_NODSP_NOFPU_LE_ARMCC">
1148       <description>Cortex-M33 processor, little endian, no DSP, no FPU, Arm Compiler</description>
1149       <require condition="CM33_NODSP_NOFPU_ARMCC"/>
1150       <require Dendian="Little-endian"/>
1151     </condition>
1152     <condition id="CM33_DSP_NOFPU_LE_ARMCC">
1153       <description>Cortex-M33 processor, little endian, DSP, no FPU, Arm Compiler</description>
1154       <require condition="CM33_DSP_NOFPU_ARMCC"/>
1155       <require Dendian="Little-endian"/>
1156     </condition>
1157     <condition id="CM33_NODSP_SP_LE_ARMCC">
1158       <description>Cortex-M33 processor, little endian, no DSP, SP FPU, Arm Compiler</description>
1159       <require condition="CM33_NODSP_SP_ARMCC"/>
1160       <require Dendian="Little-endian"/>
1161     </condition>
1162     <condition id="CM33_DSP_SP_LE_ARMCC">
1163       <description>Cortex-M33 processor, little endian, DSP, SP FPU, Arm Compiler</description>
1164       <require condition="CM33_DSP_SP_ARMCC"/>
1165       <require Dendian="Little-endian"/>
1166     </condition>
1167
1168     <condition id="ARMv8MBL_ARMCC">
1169       <description>Armv8-M Baseline processor based device for the Arm Compiler</description>
1170       <require condition="ARMv8MBL"/>
1171       <require Tcompiler="ARMCC"/>
1172     </condition>
1173     <condition id="ARMv8MBL_LE_ARMCC">
1174       <description>Armv8-M Baseline processor based device in little endian mode for the Arm Compiler</description>
1175       <require condition="ARMv8MBL_ARMCC"/>
1176       <require Dendian="Little-endian"/>
1177     </condition>
1178     <condition id="ARMv8MBL_BE_ARMCC">
1179       <description>Armv8-M Baseline processor based device in big endian mode for the Arm Compiler</description>
1180       <require condition="ARMv8MBL_ARMCC"/>
1181       <require Dendian="Big-endian"/>
1182     </condition>
1183
1184     <condition id="ARMv8MML_ARMCC">
1185       <description>Armv8-M Mainline processor based device for the Arm Compiler</description>
1186       <require condition="ARMv8MML"/>
1187       <require Tcompiler="ARMCC"/>
1188     </condition>
1189     <condition id="ARMv8MML_LE_ARMCC">
1190       <description>Armv8-M Mainline processor based device in little endian mode for the Arm Compiler</description>
1191       <require condition="ARMv8MML_ARMCC"/>
1192       <require Dendian="Little-endian"/>
1193     </condition>
1194     <condition id="ARMv8MML_BE_ARMCC">
1195       <description>Armv8-M Mainline processor based device in big endian mode for the Arm Compiler</description>
1196       <require condition="ARMv8MML_ARMCC"/>
1197       <require Dendian="Big-endian"/>
1198     </condition>
1199
1200     <condition id="ARMv8MML_FP_ARMCC">
1201       <description>Armv8-M Mainline processor based device using Floating Point Unit for the Arm Compiler</description>
1202       <require condition="ARMv8MML_FP"/>
1203       <require Tcompiler="ARMCC"/>
1204     </condition>
1205     <condition id="ARMv8MML_FP_LE_ARMCC">
1206       <description>Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
1207       <require condition="ARMv8MML_FP_ARMCC"/>
1208       <require Dendian="Little-endian"/>
1209     </condition>
1210     <condition id="ARMv8MML_FP_BE_ARMCC">
1211       <description>Armv8-M Mainline processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
1212       <require condition="ARMv8MML_FP_ARMCC"/>
1213       <require Dendian="Big-endian"/>
1214     </condition>
1215
1216     <condition id="ARMv8MML_NODSP_NOFPU_ARMCC">
1217       <description>Armv8-M Mainline, no DSP, no FPU, Arm Compiler</description>
1218       <require condition="ARMv8MML_NODSP_NOFPU"/>
1219       <require Tcompiler="ARMCC"/>
1220     </condition>
1221     <condition id="ARMv8MML_DSP_NOFPU_ARMCC">
1222       <description>Armv8-M Mainline, DSP, no FPU, Arm Compiler</description>
1223       <require condition="ARMv8MML_DSP_NOFPU"/>
1224       <require Tcompiler="ARMCC"/>
1225     </condition>
1226     <condition id="ARMv8MML_NODSP_SP_ARMCC">
1227       <description>Armv8-M Mainline, no DSP, SP FPU, Arm Compiler</description>
1228       <require condition="ARMv8MML_NODSP_SP"/>
1229       <require Tcompiler="ARMCC"/>
1230     </condition>
1231     <condition id="ARMv8MML_DSP_SP_ARMCC">
1232       <description>Armv8-M Mainline, DSP, SP FPU, Arm Compiler</description>
1233       <require condition="ARMv8MML_DSP_SP"/>
1234       <require Tcompiler="ARMCC"/>
1235     </condition>
1236     <condition id="ARMv8MML_NODSP_NOFPU_LE_ARMCC">
1237       <description>Armv8-M Mainline, little endian, no DSP, no FPU, Arm Compiler</description>
1238       <require condition="ARMv8MML_NODSP_NOFPU_ARMCC"/>
1239       <require Dendian="Little-endian"/>
1240     </condition>
1241     <condition id="ARMv8MML_DSP_NOFPU_LE_ARMCC">
1242       <description>Armv8-M Mainline, little endian, DSP, no FPU, Arm Compiler</description>
1243       <require condition="ARMv8MML_DSP_NOFPU_ARMCC"/>
1244       <require Dendian="Little-endian"/>
1245     </condition>
1246     <condition id="ARMv8MML_NODSP_SP_LE_ARMCC">
1247       <description>Armv8-M Mainline, little endian, no DSP, SP FPU, Arm Compiler</description>
1248       <require condition="ARMv8MML_NODSP_SP_ARMCC"/>
1249       <require Dendian="Little-endian"/>
1250     </condition>
1251     <condition id="ARMv8MML_DSP_SP_LE_ARMCC">
1252       <description>Armv8-M Mainline, little endian, DSP, SP FPU, Arm Compiler</description>
1253       <require condition="ARMv8MML_DSP_SP_ARMCC"/>
1254       <require Dendian="Little-endian"/>
1255     </condition>
1256
1257     <!-- GCC compiler -->
1258     <condition id="CA_GCC">
1259       <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the GCC Compiler</description>
1260       <require condition="ARMv7-A Device"/>
1261       <require Tcompiler="GCC"/>
1262     </condition>
1263
1264     <condition id="CM0_GCC">
1265       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device for the GCC Compiler</description>
1266       <require condition="CM0"/>
1267       <require Tcompiler="GCC"/>
1268     </condition>
1269     <condition id="CM0_LE_GCC">
1270       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the GCC Compiler</description>
1271       <require condition="CM0_GCC"/>
1272       <require Dendian="Little-endian"/>
1273     </condition>
1274     <condition id="CM0_BE_GCC">
1275       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the GCC Compiler</description>
1276       <require condition="CM0_GCC"/>
1277       <require Dendian="Big-endian"/>
1278     </condition>
1279
1280     <condition id="CM3_GCC">
1281       <description>Cortex-M3 or SC300 processor based device for the GCC Compiler</description>
1282       <require condition="CM3"/>
1283       <require Tcompiler="GCC"/>
1284     </condition>
1285     <condition id="CM3_LE_GCC">
1286       <description>Cortex-M3 or SC300 processor based device in little endian mode for the GCC Compiler</description>
1287       <require condition="CM3_GCC"/>
1288       <require Dendian="Little-endian"/>
1289     </condition>
1290     <condition id="CM3_BE_GCC">
1291       <description>Cortex-M3 or SC300 processor based device in big endian mode for the GCC Compiler</description>
1292       <require condition="CM3_GCC"/>
1293       <require Dendian="Big-endian"/>
1294     </condition>
1295
1296     <condition id="CM4_GCC">
1297       <description>Cortex-M4 processor based device for the GCC Compiler</description>
1298       <require condition="CM4"/>
1299       <require Tcompiler="GCC"/>
1300     </condition>
1301     <condition id="CM4_LE_GCC">
1302       <description>Cortex-M4 processor based device in little endian mode for the GCC Compiler</description>
1303       <require condition="CM4_GCC"/>
1304       <require Dendian="Little-endian"/>
1305     </condition>
1306     <condition id="CM4_BE_GCC">
1307       <description>Cortex-M4 processor based device in big endian mode for the GCC Compiler</description>
1308       <require condition="CM4_GCC"/>
1309       <require Dendian="Big-endian"/>
1310     </condition>
1311
1312     <condition id="CM4_FP_GCC">
1313       <description>Cortex-M4 processor based device using Floating Point Unit for the GCC Compiler</description>
1314       <require condition="CM4_FP"/>
1315       <require Tcompiler="GCC"/>
1316     </condition>
1317     <condition id="CM4_FP_LE_GCC">
1318       <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
1319       <require condition="CM4_FP_GCC"/>
1320       <require Dendian="Little-endian"/>
1321     </condition>
1322     <condition id="CM4_FP_BE_GCC">
1323       <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
1324       <require condition="CM4_FP_GCC"/>
1325       <require Dendian="Big-endian"/>
1326     </condition>
1327
1328     <condition id="CM7_GCC">
1329       <description>Cortex-M7 processor based device for the GCC Compiler</description>
1330       <require condition="CM7"/>
1331       <require Tcompiler="GCC"/>
1332     </condition>
1333     <condition id="CM7_LE_GCC">
1334       <description>Cortex-M7 processor based device in little endian mode for the GCC Compiler</description>
1335       <require condition="CM7_GCC"/>
1336       <require Dendian="Little-endian"/>
1337     </condition>
1338     <condition id="CM7_BE_GCC">
1339       <description>Cortex-M7 processor based device in big endian mode for the GCC Compiler</description>
1340       <require condition="CM7_GCC"/>
1341       <require Dendian="Big-endian"/>
1342     </condition>
1343
1344     <condition id="CM7_FP_GCC">
1345       <description>Cortex-M7 processor based device using Floating Point Unit for the GCC Compiler</description>
1346       <require condition="CM7_FP"/>
1347       <require Tcompiler="GCC"/>
1348     </condition>
1349     <condition id="CM7_FP_LE_GCC">
1350       <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
1351       <require condition="CM7_FP_GCC"/>
1352       <require Dendian="Little-endian"/>
1353     </condition>
1354     <condition id="CM7_FP_BE_GCC">
1355       <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
1356       <require condition="CM7_FP_GCC"/>
1357       <require Dendian="Big-endian"/>
1358     </condition>
1359
1360     <condition id="CM7_SP_GCC">
1361       <description>Cortex-M7 processor based device using Floating Point Unit (SP) for the GCC Compiler</description>
1362       <require condition="CM7_SP"/>
1363       <require Tcompiler="GCC"/>
1364     </condition>
1365     <condition id="CM7_SP_LE_GCC">
1366       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the GCC Compiler</description>
1367       <require condition="CM7_SP_GCC"/>
1368       <require Dendian="Little-endian"/>
1369     </condition>
1370     <condition id="CM7_SP_BE_GCC">
1371       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the GCC Compiler</description>
1372       <require condition="CM7_SP_GCC"/>
1373       <require Dendian="Big-endian"/>
1374     </condition>
1375
1376     <condition id="CM7_DP_GCC">
1377       <description>Cortex-M7 processor based device using Floating Point Unit (DP) for the GCC Compiler</description>
1378       <require condition="CM7_DP"/>
1379       <require Tcompiler="GCC"/>
1380     </condition>
1381     <condition id="CM7_DP_LE_GCC">
1382       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the GCC Compiler</description>
1383       <require condition="CM7_DP_GCC"/>
1384       <require Dendian="Little-endian"/>
1385     </condition>
1386     <condition id="CM7_DP_BE_GCC">
1387       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the GCC Compiler</description>
1388       <require condition="CM7_DP_GCC"/>
1389       <require Dendian="Big-endian"/>
1390     </condition>
1391
1392     <condition id="CM23_GCC">
1393       <description>Cortex-M23 processor based device for the GCC Compiler</description>
1394       <require condition="CM23"/>
1395       <require Tcompiler="GCC"/>
1396     </condition>
1397     <condition id="CM23_LE_GCC">
1398       <description>Cortex-M23 processor based device in little endian mode for the GCC Compiler</description>
1399       <require condition="CM23_GCC"/>
1400       <require Dendian="Little-endian"/>
1401     </condition>
1402     <condition id="CM23_BE_GCC">
1403       <description>Cortex-M23 processor based device in big endian mode for the GCC Compiler</description>
1404       <require condition="CM23_GCC"/>
1405       <require Dendian="Big-endian"/>
1406     </condition>
1407
1408     <condition id="CM33_GCC">
1409       <description>Cortex-M33 processor based device for the GCC Compiler</description>
1410       <require condition="CM33"/>
1411       <require Tcompiler="GCC"/>
1412     </condition>
1413     <condition id="CM33_LE_GCC">
1414       <description>Cortex-M33 processor based device in little endian mode for the GCC Compiler</description>
1415       <require condition="CM33_GCC"/>
1416       <require Dendian="Little-endian"/>
1417     </condition>
1418     <condition id="CM33_BE_GCC">
1419       <description>Cortex-M33 processor based device in big endian mode for the GCC Compiler</description>
1420       <require condition="CM33_GCC"/>
1421       <require Dendian="Big-endian"/>
1422     </condition>
1423
1424     <condition id="CM33_FP_GCC">
1425       <description>Cortex-M33 processor based device using Floating Point Unit for the GCC Compiler</description>
1426       <require condition="CM33_FP"/>
1427       <require Tcompiler="GCC"/>
1428     </condition>
1429     <condition id="CM33_FP_LE_GCC">
1430       <description>Cortex-M33 processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
1431       <require condition="CM33_FP_GCC"/>
1432       <require Dendian="Little-endian"/>
1433     </condition>
1434     <condition id="CM33_FP_BE_GCC">
1435       <description>Cortex-M33 processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
1436       <require condition="CM33_FP_GCC"/>
1437       <require Dendian="Big-endian"/>
1438     </condition>
1439
1440     <condition id="CM33_NODSP_NOFPU_GCC">
1441       <description>CM33, no DSP, no FPU, GCC Compiler</description>
1442       <require condition="CM33_NODSP_NOFPU"/>
1443       <require Tcompiler="GCC"/>
1444     </condition>
1445     <condition id="CM33_DSP_NOFPU_GCC">
1446       <description>CM33, DSP, no FPU, GCC Compiler</description>
1447       <require condition="CM33_DSP_NOFPU"/>
1448       <require Tcompiler="GCC"/>
1449     </condition>
1450     <condition id="CM33_NODSP_SP_GCC">
1451       <description>CM33, no DSP, SP FPU, GCC Compiler</description>
1452       <require condition="CM33_NODSP_SP"/>
1453       <require Tcompiler="GCC"/>
1454     </condition>
1455     <condition id="CM33_DSP_SP_GCC">
1456       <description>CM33, DSP, SP FPU, GCC Compiler</description>
1457       <require condition="CM33_DSP_SP"/>
1458       <require Tcompiler="GCC"/>
1459     </condition>
1460     <condition id="CM33_NODSP_NOFPU_LE_GCC">
1461       <description>CM33, little endian, no DSP, no FPU, GCC Compiler</description>
1462       <require condition="CM33_NODSP_NOFPU_GCC"/>
1463       <require Dendian="Little-endian"/>
1464     </condition>
1465     <condition id="CM33_DSP_NOFPU_LE_GCC">
1466       <description>CM33, little endian, DSP, no FPU, GCC Compiler</description>
1467       <require condition="CM33_DSP_NOFPU_GCC"/>
1468       <require Dendian="Little-endian"/>
1469     </condition>
1470     <condition id="CM33_NODSP_SP_LE_GCC">
1471       <description>CM33, little endian, no DSP, SP FPU, GCC Compiler</description>
1472       <require condition="CM33_NODSP_SP_GCC"/>
1473       <require Dendian="Little-endian"/>
1474     </condition>
1475     <condition id="CM33_DSP_SP_LE_GCC">
1476       <description>CM33, little endian, DSP, SP FPU, GCC Compiler</description>
1477       <require condition="CM33_DSP_SP_GCC"/>
1478       <require Dendian="Little-endian"/>
1479     </condition>
1480
1481     <condition id="ARMv8MBL_GCC">
1482       <description>Armv8-M Baseline processor based device for the GCC Compiler</description>
1483       <require condition="ARMv8MBL"/>
1484       <require Tcompiler="GCC"/>
1485     </condition>
1486     <condition id="ARMv8MBL_LE_GCC">
1487       <description>Armv8-M Baseline processor based device in little endian mode for the GCC Compiler</description>
1488       <require condition="ARMv8MBL_GCC"/>
1489       <require Dendian="Little-endian"/>
1490     </condition>
1491     <condition id="ARMv8MBL_BE_GCC">
1492       <description>Armv8-M Baseline processor based device in big endian mode for the GCC Compiler</description>
1493       <require condition="ARMv8MBL_GCC"/>
1494       <require Dendian="Big-endian"/>
1495     </condition>
1496
1497     <condition id="ARMv8MML_GCC">
1498       <description>Armv8-M Mainline processor based device for the GCC Compiler</description>
1499       <require condition="ARMv8MML"/>
1500       <require Tcompiler="GCC"/>
1501     </condition>
1502     <condition id="ARMv8MML_LE_GCC">
1503       <description>Armv8-M Mainline processor based device in little endian mode for the GCC Compiler</description>
1504       <require condition="ARMv8MML_GCC"/>
1505       <require Dendian="Little-endian"/>
1506     </condition>
1507     <condition id="ARMv8MML_BE_GCC">
1508       <description>Armv8-M Mainline processor based device in big endian mode for the GCC Compiler</description>
1509       <require condition="ARMv8MML_GCC"/>
1510       <require Dendian="Big-endian"/>
1511     </condition>
1512
1513     <condition id="ARMv8MML_FP_GCC">
1514       <description>Armv8-M Mainline processor based device using Floating Point Unit for the GCC Compiler</description>
1515       <require condition="ARMv8MML_FP"/>
1516       <require Tcompiler="GCC"/>
1517     </condition>
1518     <condition id="ARMv8MML_FP_LE_GCC">
1519       <description>Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
1520       <require condition="ARMv8MML_FP_GCC"/>
1521       <require Dendian="Little-endian"/>
1522     </condition>
1523     <condition id="ARMv8MML_FP_BE_GCC">
1524       <description>Armv8-M Mainline processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
1525       <require condition="ARMv8MML_FP_GCC"/>
1526       <require Dendian="Big-endian"/>
1527     </condition>
1528
1529     <condition id="ARMv8MML_NODSP_NOFPU_GCC">
1530       <description>Armv8-M Mainline, no DSP, no FPU, GCC Compiler</description>
1531       <require condition="ARMv8MML_NODSP_NOFPU"/>
1532       <require Tcompiler="GCC"/>
1533     </condition>
1534     <condition id="ARMv8MML_DSP_NOFPU_GCC">
1535       <description>Armv8-M Mainline, DSP, no FPU, GCC Compiler</description>
1536       <require condition="ARMv8MML_DSP_NOFPU"/>
1537       <require Tcompiler="GCC"/>
1538     </condition>
1539     <condition id="ARMv8MML_NODSP_SP_GCC">
1540       <description>Armv8-M Mainline, no DSP, SP FPU, GCC Compiler</description>
1541       <require condition="ARMv8MML_NODSP_SP"/>
1542       <require Tcompiler="GCC"/>
1543     </condition>
1544     <condition id="ARMv8MML_DSP_SP_GCC">
1545       <description>Armv8-M Mainline, DSP, SP FPU, GCC Compiler</description>
1546       <require condition="ARMv8MML_DSP_SP"/>
1547       <require Tcompiler="GCC"/>
1548     </condition>
1549     <condition id="ARMv8MML_NODSP_NOFPU_LE_GCC">
1550       <description>Armv8-M Mainline, little endian, no DSP, no FPU, GCC Compiler</description>
1551       <require condition="ARMv8MML_NODSP_NOFPU_GCC"/>
1552       <require Dendian="Little-endian"/>
1553     </condition>
1554     <condition id="ARMv8MML_DSP_NOFPU_LE_GCC">
1555       <description>Armv8-M Mainline, little endian, DSP, no FPU, GCC Compiler</description>
1556       <require condition="ARMv8MML_DSP_NOFPU_GCC"/>
1557       <require Dendian="Little-endian"/>
1558     </condition>
1559     <condition id="ARMv8MML_NODSP_SP_LE_GCC">
1560       <description>Armv8-M Mainline, little endian, no DSP, SP FPU, GCC Compiler</description>
1561       <require condition="ARMv8MML_NODSP_SP_GCC"/>
1562       <require Dendian="Little-endian"/>
1563     </condition>
1564     <condition id="ARMv8MML_DSP_SP_LE_GCC">
1565       <description>Armv8-M Mainline, little endian, DSP, SP FPU, GCC Compiler</description>
1566       <require condition="ARMv8MML_DSP_SP_GCC"/>
1567       <require Dendian="Little-endian"/>
1568     </condition>
1569
1570     <!-- IAR compiler -->
1571     <condition id="CA_IAR">
1572       <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the IAR Compiler</description>
1573       <require condition="ARMv7-A Device"/>
1574       <require Tcompiler="IAR"/>
1575     </condition>
1576
1577     <condition id="CM0_IAR">
1578       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device for the IAR Compiler</description>
1579       <require condition="CM0"/>
1580       <require Tcompiler="IAR"/>
1581     </condition>
1582     <condition id="CM0_LE_IAR">
1583       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the IAR Compiler</description>
1584       <require condition="CM0_IAR"/>
1585       <require Dendian="Little-endian"/>
1586     </condition>
1587     <condition id="CM0_BE_IAR">
1588       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the IAR Compiler</description>
1589       <require condition="CM0_IAR"/>
1590       <require Dendian="Big-endian"/>
1591     </condition>
1592
1593     <condition id="CM3_IAR">
1594       <description>Cortex-M3 or SC300 processor based device for the IAR Compiler</description>
1595       <require condition="CM3"/>
1596       <require Tcompiler="IAR"/>
1597     </condition>
1598     <condition id="CM3_LE_IAR">
1599       <description>Cortex-M3 or SC300 processor based device in little endian mode for the IAR Compiler</description>
1600       <require condition="CM3_IAR"/>
1601       <require Dendian="Little-endian"/>
1602     </condition>
1603     <condition id="CM3_BE_IAR">
1604       <description>Cortex-M3 or SC300 processor based device in big endian mode for the IAR Compiler</description>
1605       <require condition="CM3_IAR"/>
1606       <require Dendian="Big-endian"/>
1607     </condition>
1608
1609     <condition id="CM4_IAR">
1610       <description>Cortex-M4 processor based device for the IAR Compiler</description>
1611       <require condition="CM4"/>
1612       <require Tcompiler="IAR"/>
1613     </condition>
1614     <condition id="CM4_LE_IAR">
1615       <description>Cortex-M4 processor based device in little endian mode for the IAR Compiler</description>
1616       <require condition="CM4_IAR"/>
1617       <require Dendian="Little-endian"/>
1618     </condition>
1619     <condition id="CM4_BE_IAR">
1620       <description>Cortex-M4 processor based device in big endian mode for the IAR Compiler</description>
1621       <require condition="CM4_IAR"/>
1622       <require Dendian="Big-endian"/>
1623     </condition>
1624
1625     <condition id="CM4_FP_IAR">
1626       <description>Cortex-M4 processor based device using Floating Point Unit for the IAR Compiler</description>
1627       <require condition="CM4_FP"/>
1628       <require Tcompiler="IAR"/>
1629     </condition>
1630     <condition id="CM4_FP_LE_IAR">
1631       <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
1632       <require condition="CM4_FP_IAR"/>
1633       <require Dendian="Little-endian"/>
1634     </condition>
1635     <condition id="CM4_FP_BE_IAR">
1636       <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
1637       <require condition="CM4_FP_IAR"/>
1638       <require Dendian="Big-endian"/>
1639     </condition>
1640
1641     <condition id="CM7_IAR">
1642       <description>Cortex-M7 processor based device for the IAR Compiler</description>
1643       <require condition="CM7"/>
1644       <require Tcompiler="IAR"/>
1645     </condition>
1646     <condition id="CM7_LE_IAR">
1647       <description>Cortex-M7 processor based device in little endian mode for the IAR Compiler</description>
1648       <require condition="CM7_IAR"/>
1649       <require Dendian="Little-endian"/>
1650     </condition>
1651     <condition id="CM7_BE_IAR">
1652       <description>Cortex-M7 processor based device in big endian mode for the IAR Compiler</description>
1653       <require condition="CM7_IAR"/>
1654       <require Dendian="Big-endian"/>
1655     </condition>
1656
1657     <condition id="CM7_FP_IAR">
1658       <description>Cortex-M7 processor based device using Floating Point Unit for the IAR Compiler</description>
1659       <require condition="CM7_FP"/>
1660       <require Tcompiler="IAR"/>
1661     </condition>
1662     <condition id="CM7_FP_LE_IAR">
1663       <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
1664       <require condition="CM7_FP_IAR"/>
1665       <require Dendian="Little-endian"/>
1666     </condition>
1667     <condition id="CM7_FP_BE_IAR">
1668       <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
1669       <require condition="CM7_FP_IAR"/>
1670       <require Dendian="Big-endian"/>
1671     </condition>
1672
1673     <condition id="CM7_SP_IAR">
1674       <description>Cortex-M7 processor based device using Floating Point Unit (SP) for the IAR Compiler</description>
1675       <require condition="CM7_SP"/>
1676       <require Tcompiler="IAR"/>
1677     </condition>
1678     <condition id="CM7_SP_LE_IAR">
1679       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the IAR Compiler</description>
1680       <require condition="CM7_SP_IAR"/>
1681       <require Dendian="Little-endian"/>
1682     </condition>
1683     <condition id="CM7_SP_BE_IAR">
1684       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the IAR Compiler</description>
1685       <require condition="CM7_SP_IAR"/>
1686       <require Dendian="Big-endian"/>
1687     </condition>
1688
1689     <condition id="CM7_DP_IAR">
1690       <description>Cortex-M7 processor based device using Floating Point Unit (DP) for the IAR Compiler</description>
1691       <require condition="CM7_DP"/>
1692       <require Tcompiler="IAR"/>
1693     </condition>
1694     <condition id="CM7_DP_LE_IAR">
1695       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the IAR Compiler</description>
1696       <require condition="CM7_DP_IAR"/>
1697       <require Dendian="Little-endian"/>
1698     </condition>
1699     <condition id="CM7_DP_BE_IAR">
1700       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the IAR Compiler</description>
1701       <require condition="CM7_DP_IAR"/>
1702       <require Dendian="Big-endian"/>
1703     </condition>
1704
1705     <condition id="CM23_IAR">
1706       <description>Cortex-M23 processor based device for the IAR Compiler</description>
1707       <require condition="CM23"/>
1708       <require Tcompiler="IAR"/>
1709     </condition>
1710     <condition id="CM23_LE_IAR">
1711       <description>Cortex-M23 processor based device in little endian mode for the IAR Compiler</description>
1712       <require condition="CM23_IAR"/>
1713       <require Dendian="Little-endian"/>
1714     </condition>
1715     <condition id="CM23_BE_IAR">
1716       <description>Cortex-M23 processor based device in big endian mode for the IAR Compiler</description>
1717       <require condition="CM23_IAR"/>
1718       <require Dendian="Big-endian"/>
1719     </condition>
1720
1721     <condition id="CM33_IAR">
1722       <description>Cortex-M33 processor based device for the IAR Compiler</description>
1723       <require condition="CM33"/>
1724       <require Tcompiler="IAR"/>
1725     </condition>
1726     <condition id="CM33_LE_IAR">
1727       <description>Cortex-M33 processor based device in little endian mode for the IAR Compiler</description>
1728       <require condition="CM33_IAR"/>
1729       <require Dendian="Little-endian"/>
1730     </condition>
1731     <condition id="CM33_BE_IAR">
1732       <description>Cortex-M33 processor based device in big endian mode for the IAR Compiler</description>
1733       <require condition="CM33_IAR"/>
1734       <require Dendian="Big-endian"/>
1735     </condition>
1736
1737     <condition id="CM33_FP_IAR">
1738       <description>Cortex-M33 processor based device using Floating Point Unit for the IAR Compiler</description>
1739       <require condition="CM33_FP"/>
1740       <require Tcompiler="IAR"/>
1741     </condition>
1742     <condition id="CM33_FP_LE_IAR">
1743       <description>Cortex-M33 processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
1744       <require condition="CM33_FP_IAR"/>
1745       <require Dendian="Little-endian"/>
1746     </condition>
1747     <condition id="CM33_FP_BE_IAR">
1748       <description>Cortex-M33 processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
1749       <require condition="CM33_FP_IAR"/>
1750       <require Dendian="Big-endian"/>
1751     </condition>
1752
1753     <condition id="CM33_NODSP_NOFPU_IAR">
1754       <description>CM33, no DSP, no FPU, IAR Compiler</description>
1755       <require condition="CM33_NODSP_NOFPU"/>
1756       <require Tcompiler="IAR"/>
1757     </condition>
1758     <condition id="CM33_DSP_NOFPU_IAR">
1759       <description>CM33, DSP, no FPU, IAR Compiler</description>
1760       <require condition="CM33_DSP_NOFPU"/>
1761       <require Tcompiler="IAR"/>
1762     </condition>
1763     <condition id="CM33_NODSP_SP_IAR">
1764       <description>CM33, no DSP, SP FPU, IAR Compiler</description>
1765       <require condition="CM33_NODSP_SP"/>
1766       <require Tcompiler="IAR"/>
1767     </condition>
1768     <condition id="CM33_DSP_SP_IAR">
1769       <description>CM33, DSP, SP FPU, IAR Compiler</description>
1770       <require condition="CM33_DSP_SP"/>
1771       <require Tcompiler="IAR"/>
1772     </condition>
1773     <condition id="CM33_NODSP_NOFPU_LE_IAR">
1774       <description>CM33, little endian, no DSP, no FPU, IAR Compiler</description>
1775       <require condition="CM33_NODSP_NOFPU_IAR"/>
1776       <require Dendian="Little-endian"/>
1777     </condition>
1778     <condition id="CM33_DSP_NOFPU_LE_IAR">
1779       <description>CM33, little endian, DSP, no FPU, IAR Compiler</description>
1780       <require condition="CM33_DSP_NOFPU_IAR"/>
1781       <require Dendian="Little-endian"/>
1782     </condition>
1783     <condition id="CM33_NODSP_SP_LE_IAR">
1784       <description>CM33, little endian, no DSP, SP FPU, IAR Compiler</description>
1785       <require condition="CM33_NODSP_SP_IAR"/>
1786       <require Dendian="Little-endian"/>
1787     </condition>
1788     <condition id="CM33_DSP_SP_LE_IAR">
1789       <description>CM33, little endian, DSP, SP FPU, IAR Compiler</description>
1790       <require condition="CM33_DSP_SP_IAR"/>
1791       <require Dendian="Little-endian"/>
1792     </condition>
1793
1794     <condition id="ARMv8MBL_IAR">
1795       <description>Armv8-M Baseline processor based device for the IAR Compiler</description>
1796       <require condition="ARMv8MBL"/>
1797       <require Tcompiler="IAR"/>
1798     </condition>
1799     <condition id="ARMv8MBL_LE_IAR">
1800       <description>Armv8-M Baseline processor based device in little endian mode for the IAR Compiler</description>
1801       <require condition="ARMv8MBL_IAR"/>
1802       <require Dendian="Little-endian"/>
1803     </condition>
1804     <condition id="ARMv8MBL_BE_IAR">
1805       <description>Armv8-M Baseline processor based device in big endian mode for the IAR Compiler</description>
1806       <require condition="ARMv8MBL_IAR"/>
1807       <require Dendian="Big-endian"/>
1808     </condition>
1809
1810     <condition id="ARMv8MML_IAR">
1811       <description>Armv8-M Mainline processor based device for the IAR Compiler</description>
1812       <require condition="ARMv8MML"/>
1813       <require Tcompiler="IAR"/>
1814     </condition>
1815     <condition id="ARMv8MML_LE_IAR">
1816       <description>Armv8-M Mainline processor based device in little endian mode for the IAR Compiler</description>
1817       <require condition="ARMv8MML_IAR"/>
1818       <require Dendian="Little-endian"/>
1819     </condition>
1820     <condition id="ARMv8MML_BE_IAR">
1821       <description>Armv8-M Mainline processor based device in big endian mode for the IAR Compiler</description>
1822       <require condition="ARMv8MML_IAR"/>
1823       <require Dendian="Big-endian"/>
1824     </condition>
1825
1826     <condition id="ARMv8MML_FP_IAR">
1827       <description>Armv8-M Mainline processor based device using Floating Point Unit for the IAR Compiler</description>
1828       <require condition="ARMv8MML_FP"/>
1829       <require Tcompiler="IAR"/>
1830     </condition>
1831     <condition id="ARMv8MML_FP_LE_IAR">
1832       <description>Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
1833       <require condition="ARMv8MML_FP_IAR"/>
1834       <require Dendian="Little-endian"/>
1835     </condition>
1836     <condition id="ARMv8MML_FP_BE_IAR">
1837       <description>Armv8-M Mainline processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
1838       <require condition="ARMv8MML_FP_IAR"/>
1839       <require Dendian="Big-endian"/>
1840     </condition>
1841
1842     <condition id="ARMv8MML_NODSP_NOFPU_IAR">
1843       <description>Armv8-M Mainline, no DSP, no FPU, IAR Compiler</description>
1844       <require condition="ARMv8MML_NODSP_NOFPU"/>
1845       <require Tcompiler="IAR"/>
1846     </condition>
1847     <condition id="ARMv8MML_DSP_NOFPU_IAR">
1848       <description>Armv8-M Mainline, DSP, no FPU, IAR Compiler</description>
1849       <require condition="ARMv8MML_DSP_NOFPU"/>
1850       <require Tcompiler="IAR"/>
1851     </condition>
1852     <condition id="ARMv8MML_NODSP_SP_IAR">
1853       <description>Armv8-M Mainline, no DSP, SP FPU, IAR Compiler</description>
1854       <require condition="ARMv8MML_NODSP_SP"/>
1855       <require Tcompiler="IAR"/>
1856     </condition>
1857     <condition id="ARMv8MML_DSP_SP_IAR">
1858       <description>Armv8-M Mainline, DSP, SP FPU, IAR Compiler</description>
1859       <require condition="ARMv8MML_DSP_SP"/>
1860       <require Tcompiler="IAR"/>
1861     </condition>
1862     <condition id="ARMv8MML_NODSP_NOFPU_LE_IAR">
1863       <description>Armv8-M Mainline, little endian, no DSP, no FPU, IAR Compiler</description>
1864       <require condition="ARMv8MML_NODSP_NOFPU_IAR"/>
1865       <require Dendian="Little-endian"/>
1866     </condition>
1867     <condition id="ARMv8MML_DSP_NOFPU_LE_IAR">
1868       <description>Armv8-M Mainline, little endian, DSP, no FPU, IAR Compiler</description>
1869       <require condition="ARMv8MML_DSP_NOFPU_IAR"/>
1870       <require Dendian="Little-endian"/>
1871     </condition>
1872     <condition id="ARMv8MML_NODSP_SP_LE_IAR">
1873       <description>Armv8-M Mainline, little endian, no DSP, SP FPU, IAR Compiler</description>
1874       <require condition="ARMv8MML_NODSP_SP_IAR"/>
1875       <require Dendian="Little-endian"/>
1876     </condition>
1877     <condition id="ARMv8MML_DSP_SP_LE_IAR">
1878       <description>Armv8-M Mainline, little endian, DSP, SP FPU, IAR Compiler</description>
1879       <require condition="ARMv8MML_DSP_SP_IAR"/>
1880       <require Dendian="Little-endian"/>
1881     </condition>
1882
1883     <!-- conditions selecting single devices and CMSIS Core -->
1884     <!-- used for component startup, GCC version is used for C-Startup -->
1885     <condition id="ARMCM0 CMSIS">
1886       <description>Generic Arm Cortex-M0 device startup and depends on CMSIS Core</description>
1887       <require Dvendor="ARM:82" Dname="ARMCM0"/>
1888       <require Cclass="CMSIS" Cgroup="CORE"/>
1889     </condition>
1890     <condition id="ARMCM0 CMSIS GCC">
1891       <description>Generic ARM Cortex-M0 device startup and depends on CMSIS Core requiring GCC</description>
1892       <require condition="ARMCM0 CMSIS"/>
1893       <require condition="GCC"/>
1894     </condition>
1895
1896     <condition id="ARMCM0+ CMSIS">
1897       <description>Generic Arm Cortex-M0+ device startup and depends on CMSIS Core</description>
1898       <require Dvendor="ARM:82" Dname="ARMCM0P*"/>
1899       <require Cclass="CMSIS" Cgroup="CORE"/>
1900     </condition>
1901     <condition id="ARMCM0+ CMSIS GCC">
1902       <description>Generic Arm Cortex-M0+ device startup and depends CMSIS Core requiring GCC</description>
1903       <require condition="ARMCM0+ CMSIS"/>
1904       <require condition="GCC"/>
1905     </condition>
1906
1907     <condition id="ARMCM3 CMSIS">
1908       <description>Generic Arm Cortex-M3 device startup and depends on CMSIS Core</description>
1909       <require Dvendor="ARM:82" Dname="ARMCM3"/>
1910       <require Cclass="CMSIS" Cgroup="CORE"/>
1911     </condition>
1912     <condition id="ARMCM3 CMSIS GCC">
1913       <description>Generic Arm Cortex-M3 device startup and depends on CMSIS Core requiring GCC</description>
1914       <require condition="ARMCM3 CMSIS"/>
1915       <require condition="GCC"/>
1916     </condition>
1917
1918     <condition id="ARMCM4 CMSIS">
1919       <description>Generic Arm Cortex-M4 device startup and depends on CMSIS Core</description>
1920       <require Dvendor="ARM:82" Dname="ARMCM4*"/>
1921       <require Cclass="CMSIS" Cgroup="CORE"/>
1922     </condition>
1923     <condition id="ARMCM4 CMSIS GCC">
1924       <description>Generic Arm Cortex-M4 device startup and depends on CMSIS Core requiring GCC</description>
1925       <require condition="ARMCM4 CMSIS"/>
1926       <require condition="GCC"/>
1927     </condition>
1928
1929     <condition id="ARMCM7 CMSIS">
1930       <description>Generic Arm Cortex-M7 device startup and depends on CMSIS Core</description>
1931       <require Dvendor="ARM:82" Dname="ARMCM7*"/>
1932       <require Cclass="CMSIS" Cgroup="CORE"/>
1933     </condition>
1934     <condition id="ARMCM7 CMSIS GCC">
1935       <description>Generic Arm Cortex-M7 device startup and depends on CMSIS Core requiring GCC</description>
1936       <require condition="ARMCM7 CMSIS"/>
1937       <require condition="GCC"/>
1938     </condition>
1939
1940     <condition id="ARMCM23 CMSIS">
1941       <description>Generic Arm Cortex-M23 device startup and depends on CMSIS Core</description>
1942       <require Dvendor="ARM:82" Dname="ARMCM23*"/>
1943       <require Cclass="CMSIS" Cgroup="CORE"/>
1944     </condition>
1945     <condition id="ARMCM23 CMSIS GCC">
1946       <description>Generic Arm Cortex-M23 device startup and depends on CMSIS Core requiring GCC</description>
1947       <require condition="ARMCM23 CMSIS"/>
1948       <require condition="GCC"/>
1949     </condition>
1950
1951     <condition id="ARMCM33 CMSIS">
1952       <description>Generic Arm Cortex-M33 device startup and depends on CMSIS Core</description>
1953       <require Dvendor="ARM:82" Dname="ARMCM33*"/>
1954       <require Cclass="CMSIS" Cgroup="CORE"/>
1955     </condition>
1956     <condition id="ARMCM33 CMSIS GCC">
1957       <description>Generic Arm Cortex-M33 device startup and depends on CMSIS Core requiring GCC</description>
1958       <require condition="ARMCM33 CMSIS"/>
1959       <require condition="GCC"/>
1960     </condition>
1961
1962     <condition id="ARMSC000 CMSIS">
1963       <description>Generic Arm SC000 device startup and depends on CMSIS Core</description>
1964       <require Dvendor="ARM:82" Dname="ARMSC000"/>
1965       <require Cclass="CMSIS" Cgroup="CORE"/>
1966     </condition>
1967     <condition id="ARMSC000 CMSIS GCC">
1968       <description>Generic Arm SC000 device startup and depends on CMSIS Core requiring GCC</description>
1969       <require condition="ARMSC000 CMSIS"/>
1970       <require condition="GCC"/>
1971     </condition>
1972
1973     <condition id="ARMSC300 CMSIS">
1974       <description>Generic Arm SC300 device startup and depends on CMSIS Core</description>
1975       <require Dvendor="ARM:82" Dname="ARMSC300"/>
1976       <require Cclass="CMSIS" Cgroup="CORE"/>
1977     </condition>
1978     <condition id="ARMSC300 CMSIS GCC">
1979       <description>Generic Arm SC300 device startup and dependson CMSIS Core requiring GCC</description>
1980       <require condition="ARMSC300 CMSIS"/>
1981       <require condition="GCC"/>
1982     </condition>
1983
1984     <condition id="ARMv8MBL CMSIS">
1985       <description>Generic Armv8-M Baseline device startup and depends on CMSIS Core</description>
1986       <require Dvendor="ARM:82" Dname="ARMv8MBL"/>
1987       <require Cclass="CMSIS" Cgroup="CORE"/>
1988     </condition>
1989     <condition id="ARMv8MBL CMSIS GCC">
1990       <description>Generic Armv8-M Baseline device startup and depends on CMSIS Core requiring GCC</description>
1991       <require condition="ARMv8MBL CMSIS"/>
1992       <require condition="GCC"/>
1993     </condition>
1994
1995     <condition id="ARMv8MML CMSIS">
1996       <description>Generic Armv8-M Mainline device startup and depends on CMSIS Core</description>
1997       <require Dvendor="ARM:82" Dname="ARMv8MML*"/>
1998       <require Cclass="CMSIS" Cgroup="CORE"/>
1999     </condition>
2000     <condition id="ARMv8MML CMSIS GCC">
2001       <description>Generic Armv8-M Mainline device startup and depends on CMSIS Core requiring GCC</description>
2002       <require condition="ARMv8MML CMSIS"/>
2003       <require condition="GCC"/>
2004     </condition>
2005
2006     <condition id="ARMCA5 CMSIS">
2007       <description>Generic Arm Cortex-A5 device startup and depends on CMSIS Core</description>
2008       <require Dvendor="ARM:82" Dname="ARMCA5"/>
2009       <require Cclass="CMSIS" Cgroup="CORE"/>
2010     </condition>
2011
2012     <condition id="ARMCA7 CMSIS">
2013       <description>Generic Arm Cortex-A7 device startup and depends on CMSIS Core</description>
2014       <require Dvendor="ARM:82" Dname="ARMCA7"/>
2015       <require Cclass="CMSIS" Cgroup="CORE"/>
2016     </condition>
2017
2018     <condition id="ARMCA9 CMSIS">
2019       <description>Generic Arm Cortex-A9 device startup and depends on CMSIS Core</description>
2020       <require Dvendor="ARM:82" Dname="ARMCA9"/>
2021       <require Cclass="CMSIS" Cgroup="CORE"/>
2022     </condition>
2023
2024     <!-- CMSIS DSP -->
2025     <condition id="CMSIS DSP">
2026       <description>Components required for DSP</description>
2027       <require condition="ARMv6_7_8-M Device"/>
2028       <require condition="ARMCC GCC IAR"/>
2029       <require Cclass="CMSIS" Cgroup="CORE"/>
2030     </condition>
2031
2032     <!-- CMSIS NN -->
2033     <condition id="CMSIS NN">
2034       <description>Components required for NN</description>
2035       <require condition="CMSIS DSP"/>
2036     </condition>
2037
2038     <!-- RTOS RTX -->
2039     <condition id="RTOS RTX">
2040       <description>Components required for RTOS RTX</description>
2041       <require condition="ARMv6_7-M Device"/>
2042       <require condition="ARMCC GCC IAR"/>
2043       <require Cclass="Device" Cgroup="Startup"/>
2044       <deny    Cclass="CMSIS"  Cgroup="RTOS2" Csub="Keil RTX5"/>
2045     </condition>
2046     <condition id="RTOS RTX IFX">
2047       <description>Components required for RTOS RTX IFX</description>
2048       <require condition="ARMv6_7-M Device"/>
2049       <require condition="ARMCC GCC IAR"/>
2050       <require Dvendor="Infineon:7" Dname="XMC4*"/>
2051       <require Cclass="Device" Cgroup="Startup"/>
2052       <deny    Cclass="CMSIS"  Cgroup="RTOS2" Csub="Keil RTX5"/>
2053     </condition>
2054     <condition id="RTOS RTX5">
2055       <description>Components required for RTOS RTX5</description>
2056       <require condition="ARMv6_7_8-M Device"/>
2057       <require condition="ARMCC GCC IAR"/>
2058       <require Cclass="CMSIS"  Cgroup="RTOS2" Csub="Keil RTX5"/>
2059     </condition>
2060     <condition id="RTOS2 RTX5">
2061       <description>Components required for RTOS2 RTX5</description>
2062       <require condition="ARMv6_7_8-M Device"/>
2063       <require condition="ARMCC GCC IAR"/>
2064       <require Cclass="CMSIS"  Cgroup="CORE"/>
2065       <require Cclass="Device" Cgroup="Startup"/>
2066     </condition>
2067     <condition id="RTOS2 RTX5 v7-A">
2068       <description>Components required for RTOS2 RTX5 on Armv7-A</description>
2069       <require condition="ARMv7-A Device"/>
2070       <require condition="ARMCC GCC IAR"/>
2071       <require Cclass="CMSIS"  Cgroup="CORE"/>
2072       <require Cclass="Device" Cgroup="Startup"/>
2073       <require Cclass="Device" Cgroup="OS Tick"/>
2074       <require Cclass="Device" Cgroup="IRQ Controller"/>
2075     </condition>
2076     <condition id="RTOS2 RTX5 Lib">
2077       <description>Components required for RTOS2 RTX5 Library</description>
2078       <require condition="ARMv6_7_8-M Device"/>
2079       <require condition="ARMCC GCC IAR"/>
2080       <require Cclass="CMSIS"  Cgroup="CORE"/>
2081       <require Cclass="Device" Cgroup="Startup"/>
2082     </condition>
2083     <condition id="RTOS2 RTX5 NS">
2084       <description>Components required for RTOS2 RTX5 in Non-Secure Domain</description>
2085       <require condition="ARMv8-M TZ Device"/>
2086       <require condition="ARMCC GCC IAR"/>
2087       <require Cclass="CMSIS"  Cgroup="CORE"/>
2088       <require Cclass="Device" Cgroup="Startup"/>
2089     </condition>
2090
2091     <!-- OS Tick -->
2092     <condition id="OS Tick PTIM">
2093       <description>Components required for OS Tick Private Timer</description>
2094       <require condition="CA5_CA9"/>
2095       <require Cclass="Device" Cgroup="IRQ Controller"/>
2096     </condition>
2097
2098     <condition id="OS Tick GTIM">
2099       <description>Components required for OS Tick Generic Physical Timer</description>
2100       <require condition="CA7"/>
2101       <require Cclass="Device" Cgroup="IRQ Controller"/>
2102     </condition>
2103
2104   </conditions>
2105
2106   <components>
2107     <!-- CMSIS-Core component -->
2108     <component Cclass="CMSIS" Cgroup="CORE" Cversion="5.1.1"  condition="ARMv6_7_8-M Device" >
2109       <description>CMSIS-CORE for Cortex-M, SC000, SC300, ARMv8-M</description>
2110       <files>
2111         <!-- CPU independent -->
2112         <file category="doc"     name="CMSIS/Documentation/Core/html/index.html"/>
2113         <file category="include" name="CMSIS/Core/Include/"/>
2114         <file category="header"  name="CMSIS/Core/Include/tz_context.h" condition="ARMv8-M TZ Device"/>
2115         <!-- Code template -->
2116         <file category="sourceC" attr="template" condition="ARMv8-M TZ Device" name="CMSIS/Core/Template/ARMv8-M/main_s.c"     version="1.1.0" select="Secure mode 'main' module for ARMv8-M"/>
2117         <file category="sourceC" attr="template" condition="ARMv8-M TZ Device" name="CMSIS/Core/Template/ARMv8-M/tz_context.c" version="1.1.0" select="RTOS Context Management (TrustZone for ARMv8-M)" />
2118       </files>
2119     </component>
2120
2121     <component Cclass="CMSIS" Cgroup="CORE" Cversion="1.1.1"  condition="ARMv7-A Device" >
2122       <description>CMSIS-CORE for Cortex-A</description>
2123       <files>
2124         <!-- CPU independent -->
2125         <file category="doc"     name="CMSIS/Documentation/Core_A/html/index.html"/>
2126         <file category="include" name="CMSIS/Core_A/Include/"/>
2127       </files>
2128     </component>
2129
2130     <!-- CMSIS-Startup components -->
2131     <!-- Cortex-M0 -->
2132     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM0 CMSIS">
2133       <description>System and Startup for Generic Arm Cortex-M0 device</description>
2134       <files>
2135         <!-- include folder / device header file -->
2136         <file category="header"  name="Device/ARM/ARMCM0/Include/ARMCM0.h"/>
2137         <!-- startup / system file -->
2138         <file category="sourceAsm"    name="Device/ARM/ARMCM0/Source/ARM/startup_ARMCM0.s" version="1.0.0" attr="config" condition="ARMCC"/>
2139         <file category="sourceAsm"    name="Device/ARM/ARMCM0/Source/GCC/startup_ARMCM0.S" version="1.0.0" attr="config" condition="GCC"/>
2140         <file category="linkerScript" name="Device/ARM/ARMCM0/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2141         <file category="sourceAsm"    name="Device/ARM/ARMCM0/Source/IAR/startup_ARMCM0.s" version="1.0.0" attr="config" condition="IAR"/>
2142         <file category="sourceC"      name="Device/ARM/ARMCM0/Source/system_ARMCM0.c"      version="1.0.0" attr="config"/>
2143       </files>
2144     </component>
2145     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM0 CMSIS GCC">
2146       <description>System and Startup for Generic Arm Cortex-M0 device</description>
2147       <files>
2148         <!-- include folder / device header file -->
2149         <file category="header"  name="Device/ARM/ARMCM0/Include/ARMCM0.h"/>
2150         <!-- startup / system file -->
2151         <file category="sourceC"      name="Device/ARM/ARMCM0/Source/GCC/startup_ARMCM0.c" version="1.0.0" attr="config" condition="GCC"/>
2152         <file category="linkerScript" name="Device/ARM/ARMCM0/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2153         <file category="sourceC"      name="Device/ARM/ARMCM0/Source/system_ARMCM0.c"      version="1.0.0" attr="config"/>
2154       </files>
2155     </component>
2156
2157     <!-- Cortex-M0+ -->
2158     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM0+ CMSIS">
2159       <description>System and Startup for Generic Arm Cortex-M0+ device</description>
2160       <files>
2161         <!-- include folder / device header file -->
2162         <file category="header"  name="Device/ARM/ARMCM0plus/Include/ARMCM0plus.h"/>
2163         <!-- startup / system file -->
2164         <file category="sourceAsm"    name="Device/ARM/ARMCM0plus/Source/ARM/startup_ARMCM0plus.s" version="1.0.0" attr="config" condition="ARMCC"/>
2165         <file category="sourceAsm"    name="Device/ARM/ARMCM0plus/Source/GCC/startup_ARMCM0plus.S" version="1.0.0" attr="config" condition="GCC"/>
2166         <file category="linkerScript" name="Device/ARM/ARMCM0plus/Source/GCC/gcc_arm.ld"           version="1.0.0" attr="config" condition="GCC"/>
2167         <file category="sourceAsm"    name="Device/ARM/ARMCM0plus/Source/IAR/startup_ARMCM0plus.s" version="1.0.0" attr="config" condition="IAR"/>
2168         <file category="sourceC"      name="Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c"      version="1.0.0" attr="config"/>
2169       </files>
2170     </component>
2171     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM0+ CMSIS GCC">
2172       <description>System and Startup for Generic Arm Cortex-M0+ device</description>
2173       <files>
2174         <!-- include folder / device header file -->
2175         <file category="header"  name="Device/ARM/ARMCM0plus/Include/ARMCM0plus.h"/>
2176         <!-- startup / system file -->
2177         <file category="sourceC"      name="Device/ARM/ARMCM0plus/Source/GCC/startup_ARMCM0plus.c" version="1.0.0" attr="config" condition="GCC"/>
2178         <file category="linkerScript" name="Device/ARM/ARMCM0plus/Source/GCC/gcc_arm.ld"           version="1.0.0" attr="config" condition="GCC"/>
2179         <file category="sourceC"      name="Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c"      version="1.0.0" attr="config"/>
2180       </files>
2181     </component>
2182
2183     <!-- Cortex-M3 -->
2184     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM3 CMSIS">
2185       <description>System and Startup for Generic Arm Cortex-M3 device</description>
2186       <files>
2187         <!-- include folder / device header file -->
2188         <file category="header"  name="Device/ARM/ARMCM3/Include/ARMCM3.h"/>
2189         <!-- startup / system file -->
2190         <file category="sourceAsm"    name="Device/ARM/ARMCM3/Source/ARM/startup_ARMCM3.s" version="1.0.0" attr="config" condition="ARMCC"/>
2191         <file category="sourceAsm"    name="Device/ARM/ARMCM3/Source/GCC/startup_ARMCM3.S" version="1.0.0" attr="config" condition="GCC"/>
2192         <file category="linkerScript" name="Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2193         <file category="sourceAsm"    name="Device/ARM/ARMCM3/Source/IAR/startup_ARMCM3.s" version="1.0.0" attr="config" condition="IAR"/>
2194         <file category="sourceC"      name="Device/ARM/ARMCM3/Source/system_ARMCM3.c"      version="1.0.0" attr="config"/>
2195       </files>
2196     </component>
2197     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM3 CMSIS GCC">
2198       <description>System and Startup for Generic Arm Cortex-M3 device</description>
2199       <files>
2200         <!-- include folder / device header file -->
2201         <file category="header"  name="Device/ARM/ARMCM3/Include/ARMCM3.h"/>
2202         <!-- startup / system file -->
2203         <file category="sourceC"      name="Device/ARM/ARMCM3/Source/GCC/startup_ARMCM3.c" version="1.0.0" attr="config" condition="GCC"/>
2204         <file category="linkerScript" name="Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2205         <file category="sourceC"      name="Device/ARM/ARMCM3/Source/system_ARMCM3.c"      version="1.0.0" attr="config"/>
2206       </files>
2207     </component>
2208
2209     <!-- Cortex-M4 -->
2210     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM4 CMSIS">
2211       <description>System and Startup for Generic Arm Cortex-M4 device</description>
2212       <files>
2213         <!-- include folder / device header file -->
2214         <file category="include" name="Device/ARM/ARMCM4/Include/"/>
2215         <!-- startup / system file -->
2216         <file category="sourceAsm"    name="Device/ARM/ARMCM4/Source/ARM/startup_ARMCM4.s" version="1.0.0" attr="config" condition="ARMCC"/>
2217         <file category="sourceAsm"    name="Device/ARM/ARMCM4/Source/GCC/startup_ARMCM4.S" version="1.0.0" attr="config" condition="GCC"/>
2218         <file category="linkerScript" name="Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2219         <file category="sourceAsm"    name="Device/ARM/ARMCM4/Source/IAR/startup_ARMCM4.s" version="1.0.0" attr="config" condition="IAR"/>
2220         <file category="sourceC"      name="Device/ARM/ARMCM4/Source/system_ARMCM4.c"      version="1.0.0" attr="config"/>
2221       </files>
2222     </component>
2223     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM4 CMSIS GCC">
2224       <description>System and Startup for Generic Arm Cortex-M4 device</description>
2225       <files>
2226         <!-- include folder / device header file -->
2227         <file category="include" name="Device/ARM/ARMCM4/Include/"/>
2228         <!-- startup / system file -->
2229         <file category="sourceC"      name="Device/ARM/ARMCM4/Source/GCC/startup_ARMCM4.c" version="1.0.0" attr="config" condition="GCC"/>
2230         <file category="linkerScript" name="Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2231         <file category="sourceC"      name="Device/ARM/ARMCM4/Source/system_ARMCM4.c"      version="1.0.0" attr="config"/>
2232       </files>
2233     </component>
2234
2235     <!-- Cortex-M7 -->
2236     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM7 CMSIS">
2237       <description>System and Startup for Generic Arm Cortex-M7 device</description>
2238       <files>
2239         <!-- include folder / device header file -->
2240         <file category="include"  name="Device/ARM/ARMCM7/Include/"/>
2241         <!-- startup / system file -->
2242         <file category="sourceAsm"    name="Device/ARM/ARMCM7/Source/ARM/startup_ARMCM7.s" version="1.0.0" attr="config" condition="ARMCC"/>
2243         <file category="sourceAsm"    name="Device/ARM/ARMCM7/Source/GCC/startup_ARMCM7.S" version="1.0.0" attr="config" condition="GCC"/>
2244         <file category="linkerScript" name="Device/ARM/ARMCM7/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2245         <file category="sourceAsm"    name="Device/ARM/ARMCM7/Source/IAR/startup_ARMCM7.s" version="1.0.0" attr="config" condition="IAR"/>
2246         <file category="sourceC"      name="Device/ARM/ARMCM7/Source/system_ARMCM7.c"      version="1.0.0" attr="config"/>
2247       </files>
2248     </component>
2249     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM7 CMSIS GCC">
2250       <description>System and Startup for Generic Arm Cortex-M7 device</description>
2251       <files>
2252         <!-- include folder / device header file -->
2253         <file category="include"  name="Device/ARM/ARMCM7/Include/"/>
2254         <!-- startup / system file -->
2255         <file category="sourceC"      name="Device/ARM/ARMCM7/Source/GCC/startup_ARMCM7.c" version="1.0.0" attr="config" condition="GCC"/>
2256         <file category="linkerScript" name="Device/ARM/ARMCM7/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2257         <file category="sourceC"      name="Device/ARM/ARMCM7/Source/system_ARMCM7.c"      version="1.0.0" attr="config"/>
2258       </files>
2259     </component>
2260
2261     <!-- Cortex-M23 -->
2262     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.0" condition="ARMCM23 CMSIS">
2263       <description>System and Startup for Generic Arm Cortex-M23 device</description>
2264       <files>
2265         <!-- include folder / device header file -->
2266         <file category="include"      name="Device/ARM/ARMCM23/Include/"/>
2267         <!-- startup / system file -->
2268         <file category="sourceAsm"    name="Device/ARM/ARMCM23/Source/ARM/startup_ARMCM23.s" version="1.0.0" attr="config" condition="ARMCC"/>
2269         <file category="sourceAsm"    name="Device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.S" version="1.0.0" attr="config" condition="GCC"/>
2270         <file category="linkerScript" name="Device/ARM/ARMCM23/Source/GCC/gcc_arm.ld"        version="1.0.0" attr="config" condition="GCC"/>
2271         <file category="sourceAsm"    name="Device/ARM/ARMCM23/Source/IAR/startup_ARMCM23.s" version="1.0.0" attr="config" condition="IAR"/>
2272         <file category="sourceC"      name="Device/ARM/ARMCM23/Source/system_ARMCM23.c"      version="1.0.0" attr="config"/>
2273         <!-- SAU configuration -->
2274         <file category="header"       name="Device/ARM/ARMCM23/Include/Template/partition_ARMCM23.h" version="1.0.0" attr="config" condition="ARMv8-M TZ Device"/>
2275       </files>
2276     </component>
2277     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.0" condition="ARMCM23 CMSIS GCC">
2278       <description>System and Startup for Generic Arm Cortex-M23 device</description>
2279       <files>
2280         <!-- include folder / device header file -->
2281         <file category="include"  name="Device/ARM/ARMCM23/Include/"/>
2282         <!-- startup / system file -->
2283         <file category="sourceC"      name="Device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.c" version="1.0.0" attr="config" condition="GCC"/>
2284         <file category="linkerScript" name="Device/ARM/ARMCM23/Source/GCC/gcc_arm.ld"        version="1.0.0" attr="config" condition="GCC"/>
2285         <file category="sourceC"      name="Device/ARM/ARMCM23/Source/system_ARMCM23.c"      version="1.0.0" attr="config"/>
2286         <!-- SAU configuration -->
2287         <file category="header"       name="Device/ARM/ARMCM23/Include/Template/partition_ARMCM23.h" version="1.0.0" attr="config" condition="ARMv8-M TZ Device"/>
2288       </files>
2289     </component>
2290
2291     <!-- Cortex-M33 -->
2292     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.1.0" condition="ARMCM33 CMSIS">
2293       <description>System and Startup for Generic Arm Cortex-M33 device</description>
2294       <files>
2295         <!-- include folder / device header file -->
2296         <file category="include"      name="Device/ARM/ARMCM33/Include/"/>
2297         <!-- startup / system file -->
2298         <file category="sourceAsm"    name="Device/ARM/ARMCM33/Source/ARM/startup_ARMCM33.s"         version="1.0.0" attr="config" condition="ARMCC"/>
2299         <file category="sourceAsm"    name="Device/ARM/ARMCM33/Source/GCC/startup_ARMCM33.S"         version="1.0.0" attr="config" condition="GCC"/>
2300         <file category="linkerScript" name="Device/ARM/ARMCM33/Source/GCC/gcc_arm.ld"                version="1.0.0" attr="config" condition="GCC"/>
2301         <file category="sourceAsm"    name="Device/ARM/ARMCM33/Source/IAR/startup_ARMCM33.s"         version="1.0.0" attr="config" condition="IAR"/>
2302         <file category="sourceC"      name="Device/ARM/ARMCM33/Source/system_ARMCM33.c"              version="1.0.0" attr="config"/>
2303         <!-- SAU configuration -->
2304         <file category="header"       name="Device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2305       </files>
2306     </component>
2307     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.1.0" condition="ARMCM33 CMSIS GCC">
2308       <description>System and Startup for Generic Arm Cortex-M33 device</description>
2309       <files>
2310         <!-- include folder / device header file -->
2311         <file category="include"  name="Device/ARM/ARMCM33/Include/"/>
2312         <!-- startup / system file -->
2313         <file category="sourceC"      name="Device/ARM/ARMCM33/Source/GCC/startup_ARMCM33.c"         version="1.0.0" attr="config" condition="GCC"/>
2314         <file category="linkerScript" name="Device/ARM/ARMCM33/Source/GCC/gcc_arm.ld"                version="1.0.0" attr="config" condition="GCC"/>
2315         <file category="sourceC"      name="Device/ARM/ARMCM33/Source/system_ARMCM33.c"              version="1.0.0" attr="config"/>
2316         <!-- SAU configuration -->
2317         <file category="header"       name="Device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2318       </files>
2319     </component>
2320
2321     <!-- Cortex-SC000 -->
2322     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMSC000 CMSIS">
2323       <description>System and Startup for Generic Arm SC000 device</description>
2324       <files>
2325         <!-- include folder / device header file -->
2326         <file category="header"  name="Device/ARM/ARMSC000/Include/ARMSC000.h"/>
2327         <!-- startup / system file -->
2328         <file category="sourceAsm"    name="Device/ARM/ARMSC000/Source/ARM/startup_ARMSC000.s" version="1.0.0" attr="config" condition="ARMCC"/>
2329         <file category="sourceAsm"    name="Device/ARM/ARMSC000/Source/GCC/startup_ARMSC000.S" version="1.0.0" attr="config" condition="GCC"/>
2330         <file category="linkerScript" name="Device/ARM/ARMSC000/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2331         <file category="sourceAsm"    name="Device/ARM/ARMSC000/Source/IAR/startup_ARMSC000.s" version="1.0.0" attr="config" condition="IAR"/>
2332         <file category="sourceC"      name="Device/ARM/ARMSC000/Source/system_ARMSC000.c"      version="1.0.0" attr="config"/>
2333       </files>
2334     </component>
2335     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMSC000 CMSIS GCC">
2336       <description>System and Startup for Generic Arm SC000 device</description>
2337       <files>
2338         <!-- include folder / device header file -->
2339         <file category="header"  name="Device/ARM/ARMSC000/Include/ARMSC000.h"/>
2340         <!-- startup / system file -->
2341         <file category="sourceC"      name="Device/ARM/ARMSC000/Source/GCC/startup_ARMSC000.c" version="1.0.0" attr="config" condition="GCC"/>
2342         <file category="linkerScript" name="Device/ARM/ARMSC000/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2343         <file category="sourceC"      name="Device/ARM/ARMSC000/Source/system_ARMSC000.c"      version="1.0.0" attr="config"/>
2344       </files>
2345     </component>
2346
2347     <!-- Cortex-SC300 -->
2348     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMSC300 CMSIS">
2349       <description>System and Startup for Generic Arm SC300 device</description>
2350       <files>
2351         <!-- include folder / device header file -->
2352         <file category="header"  name="Device/ARM/ARMSC300/Include/ARMSC300.h"/>
2353         <!-- startup / system file -->
2354         <file category="sourceAsm"    name="Device/ARM/ARMSC300/Source/ARM/startup_ARMSC300.s" version="1.0.0" attr="config" condition="ARMCC"/>
2355         <file category="sourceAsm"    name="Device/ARM/ARMSC300/Source/GCC/startup_ARMSC300.S" version="1.0.0" attr="config" condition="GCC"/>
2356         <file category="linkerScript" name="Device/ARM/ARMSC300/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2357         <file category="sourceAsm"    name="Device/ARM/ARMSC300/Source/IAR/startup_ARMSC300.s" version="1.0.0" attr="config" condition="IAR"/>
2358         <file category="sourceC"      name="Device/ARM/ARMSC300/Source/system_ARMSC300.c"      version="1.0.0" attr="config"/>
2359       </files>
2360     </component>
2361     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMSC300 CMSIS GCC">
2362       <description>System and Startup for Generic Arm SC300 device</description>
2363       <files>
2364         <!-- include folder / device header file -->
2365         <file category="header"  name="Device/ARM/ARMSC300/Include/ARMSC300.h"/>
2366         <!-- startup / system file -->
2367         <file category="sourceC"      name="Device/ARM/ARMSC300/Source/GCC/startup_ARMSC300.c" version="1.0.0" attr="config" condition="GCC"/>
2368         <file category="linkerScript" name="Device/ARM/ARMSC300/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2369         <file category="sourceC"      name="Device/ARM/ARMSC300/Source/system_ARMSC300.c"      version="1.0.0" attr="config"/>
2370       </files>
2371     </component>
2372
2373     <!-- ARMv8MBL -->
2374     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.0" condition="ARMv8MBL CMSIS">
2375       <description>System and Startup for Generic Armv8-M Baseline device</description>
2376       <files>
2377         <!-- include folder / device header file -->
2378         <file category="include"      name="Device/ARM/ARMv8MBL/Include/"/>
2379         <!-- startup / system file -->
2380         <file category="sourceAsm"    name="Device/ARM/ARMv8MBL/Source/ARM/startup_ARMv8MBL.s" version="1.0.0" attr="config" condition="ARMCC"/>
2381         <file category="sourceAsm"    name="Device/ARM/ARMv8MBL/Source/GCC/startup_ARMv8MBL.S" version="1.0.0" attr="config" condition="GCC"/>
2382         <file category="linkerScript" name="Device/ARM/ARMv8MBL/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2383         <file category="sourceC"      name="Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c"      version="1.0.0" attr="config" condition="ARMCC GCC"/>
2384         <!-- SAU configuration -->
2385         <file category="header"       name="Device/ARM/ARMv8MBL/Include/Template/partition_ARMv8MBL.h" version="1.0.0" attr="config"/>
2386       </files>
2387     </component>
2388     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.0" condition="ARMv8MBL CMSIS GCC">
2389       <description>System and Startup for Generic Armv8-M Baseline device</description>
2390       <files>
2391         <!-- include folder / device header file -->
2392         <file category="include"  name="Device/ARM/ARMv8MBL/Include/"/>
2393         <!-- startup / system file -->
2394         <file category="sourceC"      name="Device/ARM/ARMv8MBL/Source/GCC/startup_ARMv8MBL.c" version="1.0.0" attr="config" condition="GCC"/>
2395         <file category="linkerScript" name="Device/ARM/ARMv8MBL/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2396         <file category="sourceC"      name="Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c"      version="1.0.0" attr="config"/>
2397         <!-- SAU configuration -->
2398         <file category="header"       name="Device/ARM/ARMv8MBL/Include/Template/partition_ARMv8MBL.h" version="1.0.0" attr="config" condition="ARMv8-M TZ Device"/>
2399       </files>
2400     </component>
2401
2402     <!-- ARMv8MML -->
2403     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.1.0" condition="ARMv8MML CMSIS">
2404       <description>System and Startup for Generic Armv8-M Mainline device</description>
2405       <files>
2406         <!-- include folder / device header file -->
2407         <file category="include"      name="Device/ARM/ARMv8MML/Include/"/>
2408         <!-- startup / system file -->
2409         <file category="sourceAsm"    name="Device/ARM/ARMv8MML/Source/ARM/startup_ARMv8MML.s"         version="1.0.0" attr="config" condition="ARMCC"/>
2410         <file category="sourceAsm"    name="Device/ARM/ARMv8MML/Source/GCC/startup_ARMv8MML.S"         version="1.0.0" attr="config" condition="GCC"/>
2411         <file category="linkerScript" name="Device/ARM/ARMv8MML/Source/GCC/gcc_arm.ld"                 version="1.0.0" attr="config" condition="GCC"/>
2412         <file category="sourceC"      name="Device/ARM/ARMv8MML/Source/system_ARMv8MML.c"              version="1.0.0" attr="config" condition="ARMCC GCC"/>
2413         <!-- SAU configuration -->
2414         <file category="header"       name="Device/ARM/ARMv8MML/Include/Template/partition_ARMv8MML.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2415       </files>
2416     </component>
2417     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.1.0" condition="ARMv8MML CMSIS GCC">
2418       <description>System and Startup for Generic Armv8-M Mainline device</description>
2419       <files>
2420         <!-- include folder / device header file -->
2421         <file category="include"      name="Device/ARM/ARMv8MML/Include/"/>
2422         <!-- startup / system file -->
2423         <file category="sourceC"      name="Device/ARM/ARMv8MML/Source/GCC/startup_ARMv8MML.c"         version="1.0.0" attr="config" condition="GCC"/>
2424         <file category="linkerScript" name="Device/ARM/ARMv8MML/Source/GCC/gcc_arm.ld"                 version="1.0.0" attr="config" condition="GCC"/>
2425         <file category="sourceC"      name="Device/ARM/ARMv8MML/Source/system_ARMv8MML.c"              version="1.0.0" attr="config"/>
2426         <!-- SAU configuration -->
2427         <file category="header"       name="Device/ARM/ARMv8MML/Include/Template/partition_ARMv8MML.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2428       </files>
2429     </component>
2430
2431     <!-- Cortex-A5 -->
2432     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.0" condition="ARMCA5 CMSIS">
2433       <description>System and Startup for Generic Arm Cortex-A5 device</description>
2434       <files>
2435         <!-- include folder / device header file -->
2436         <file category="include"      name="Device/ARM/ARMCA5/Include/"/>
2437         <!-- startup / system / mmu files -->
2438         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/AC5/startup_ARMCA5.c" version="1.0.0" attr="config" condition="ARMCC5"/>
2439         <file category="linkerScript" name="Device/ARM/ARMCA5/Source/AC5/ARMCA5.sct"       version="1.0.0" attr="config" condition="ARMCC5"/>
2440         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/AC6/startup_ARMCA5.c" version="1.0.0" attr="config" condition="ARMCC6"/>
2441         <file category="linkerScript" name="Device/ARM/ARMCA5/Source/AC6/ARMCA5.sct"       version="1.0.0" attr="config" condition="ARMCC6"/>
2442         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/GCC/startup_ARMCA5.c" version="1.0.0" attr="config" condition="GCC"/>
2443         <file category="other"        name="Device/ARM/ARMCA5/Source/GCC/ARMCA5.ld"        version="1.0.0" attr="config" condition="GCC"/>
2444         <file category="sourceAsm"    name="Device/ARM/ARMCA5/Source/IAR/startup_ARMCA5.s" version="1.0.0" attr="config" condition="IAR"/>
2445         <file category="linkerScript" name="Device/ARM/ARMCA5/Source/IAR/ARMCA5.icf"       version="1.0.0" attr="config" condition="IAR"/>
2446         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/system_ARMCA5.c"      version="1.0.0" attr="config"/>
2447         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/mmu_ARMCA5.c"         version="1.0.0" attr="config"/>
2448         <file category="header"       name="Device/ARM/ARMCA5/Include/system_ARMCA5.h"     version="1.0.0" attr="config"/>
2449         <file category="header"       name="Device/ARM/ARMCA5/Include/mem_ARMCA5.h"        version="1.0.0" attr="config"/>
2450
2451       </files>
2452     </component>
2453
2454     <!-- Cortex-A7 -->
2455     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.0" condition="ARMCA7 CMSIS">
2456       <description>System and Startup for Generic Arm Cortex-A7 device</description>
2457       <files>
2458         <!-- include folder / device header file -->
2459         <file category="include"      name="Device/ARM/ARMCA7/Include/"/>
2460         <!-- startup / system / mmu files -->
2461         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/AC5/startup_ARMCA7.c" version="1.0.0" attr="config" condition="ARMCC5"/>
2462         <file category="linkerScript" name="Device/ARM/ARMCA7/Source/AC5/ARMCA7.sct"       version="1.0.0" attr="config" condition="ARMCC5"/>
2463         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/AC6/startup_ARMCA7.c" version="1.0.0" attr="config" condition="ARMCC6"/>
2464         <file category="linkerScript" name="Device/ARM/ARMCA7/Source/AC6/ARMCA7.sct"       version="1.0.0" attr="config" condition="ARMCC6"/>
2465         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/GCC/startup_ARMCA7.c" version="1.0.0" attr="config" condition="GCC"/>
2466         <file category="other"        name="Device/ARM/ARMCA7/Source/GCC/ARMCA7.ld"        version="1.0.0" attr="config" condition="GCC"/>
2467         <file category="sourceAsm"    name="Device/ARM/ARMCA7/Source/IAR/startup_ARMCA7.s" version="1.0.0" attr="config" condition="IAR"/>
2468         <file category="linkerScript" name="Device/ARM/ARMCA7/Source/IAR/ARMCA7.icf"       version="1.0.0" attr="config" condition="IAR"/>
2469         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/system_ARMCA7.c"      version="1.0.0" attr="config"/>
2470         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/mmu_ARMCA7.c"         version="1.0.0" attr="config"/>
2471         <file category="header"       name="Device/ARM/ARMCA7/Include/system_ARMCA7.h"     version="1.0.0" attr="config"/>
2472         <file category="header"       name="Device/ARM/ARMCA7/Include/mem_ARMCA7.h"        version="1.0.0" attr="config"/>
2473       </files>
2474     </component>
2475
2476     <!-- Cortex-A9 -->
2477     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCA9 CMSIS">
2478       <description>System and Startup for Generic Arm Cortex-A9 device</description>
2479       <files>
2480         <!-- include folder / device header file -->
2481         <file category="include"  name="Device/ARM/ARMCA9/Include/"/>
2482         <!-- startup / system / mmu files -->
2483         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/AC5/startup_ARMCA9.c" version="1.0.0" attr="config" condition="ARMCC5"/>
2484         <file category="linkerScript" name="Device/ARM/ARMCA9/Source/AC5/ARMCA9.sct"       version="1.0.0" attr="config" condition="ARMCC5"/>
2485         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/AC6/startup_ARMCA9.c" version="1.0.0" attr="config" condition="ARMCC6"/>
2486         <file category="linkerScript" name="Device/ARM/ARMCA9/Source/AC6/ARMCA9.sct"       version="1.0.0" attr="config" condition="ARMCC6"/>
2487         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/GCC/startup_ARMCA9.c" version="1.0.0" attr="config" condition="GCC"/>
2488         <file category="other"        name="Device/ARM/ARMCA9/Source/GCC/ARMCA9.ld"        version="1.0.0" attr="config" condition="GCC"/>
2489         <file category="sourceAsm"    name="Device/ARM/ARMCA9/Source/IAR/startup_ARMCA9.s" version="1.0.0" attr="config" condition="IAR"/>
2490         <file category="linkerScript" name="Device/ARM/ARMCA9/Source/IAR/ARMCA9.icf"       version="1.0.0" attr="config" condition="IAR"/>
2491         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/system_ARMCA9.c"      version="1.0.0" attr="config"/>
2492         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/mmu_ARMCA9.c"         version="1.0.0" attr="config"/>
2493         <file category="header"       name="Device/ARM/ARMCA9/Include/system_ARMCA9.h"     version="1.0.0" attr="config"/>
2494         <file category="header"       name="Device/ARM/ARMCA9/Include/mem_ARMCA9.h"        version="1.0.0" attr="config"/>
2495       </files>
2496     </component>
2497
2498     <!-- IRQ Controller -->
2499     <component Cclass="Device" Cgroup="IRQ Controller" Csub="GIC" Capiversion="1.0.0" Cversion="1.0.1" condition="ARMv7-A Device">
2500       <description>IRQ Controller implementation using GIC</description>
2501       <files>
2502         <file category="sourceC" name="CMSIS/Core_A/Source/irq_ctrl_gic.c"/>
2503       </files>
2504     </component>
2505
2506     <!-- OS Tick -->
2507     <component Cclass="Device" Cgroup="OS Tick" Csub="Private Timer" Capiversion="1.0.1" Cversion="1.0.2" condition="OS Tick PTIM">
2508       <description>OS Tick implementation using Private Timer</description>
2509       <files>
2510         <file category="sourceC" name="CMSIS/RTOS2/Source/os_tick_ptim.c"/>
2511       </files>
2512     </component>
2513
2514     <component Cclass="Device" Cgroup="OS Tick" Csub="Generic Physical Timer" Capiversion="1.0.1" Cversion="1.0.1" condition="OS Tick GTIM">
2515       <description>OS Tick implementation using Generic Physical Timer</description>
2516       <files>
2517         <file category="sourceC" name="CMSIS/RTOS2/Source/os_tick_gtim.c"/>
2518       </files>
2519     </component>
2520
2521     <!-- CMSIS-DSP component -->
2522     <component Cclass="CMSIS" Cgroup="DSP" Cversion="1.5.2" condition="CMSIS DSP">
2523       <description>CMSIS-DSP Library for Cortex-M, SC000, and SC300</description>
2524       <files>
2525         <!-- CPU independent -->
2526         <file category="doc" name="CMSIS/Documentation/DSP/html/index.html"/>
2527         <file category="header" name="CMSIS/DSP/Include/arm_math.h"/>
2528
2529         <!-- CPU and Compiler dependent -->
2530         <!-- ARMCC -->
2531         <file category="library" condition="CM0_LE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM0l_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2532         <file category="library" condition="CM0_BE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM0b_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2533         <file category="library" condition="CM3_LE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM3l_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2534         <file category="library" condition="CM3_BE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM3b_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2535         <file category="library" condition="CM4_LE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM4l_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2536         <file category="library" condition="CM4_BE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM4b_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2537         <file category="library" condition="CM4_FP_LE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM4lf_math.lib"     src="CMSIS/DSP/Source/ARM"/>
2538         <file category="library" condition="CM4_FP_BE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM4bf_math.lib"     src="CMSIS/DSP/Source/ARM"/>
2539         <file category="library" condition="CM7_LE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM7l_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2540         <file category="library" condition="CM7_BE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM7b_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2541         <file category="library" condition="CM7_SP_LE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM7lfsp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
2542         <file category="library" condition="CM7_SP_BE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM7bfsp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
2543         <file category="library" condition="CM7_DP_LE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM7lfdp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
2544         <file category="library" condition="CM7_DP_BE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM7bfdp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
2545
2546         <file category="library" condition="CM23_LE_ARMCC"                  name="CMSIS/Lib/ARM/arm_ARMv8MBLl_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2547         <file category="library" condition="CM33_NODSP_NOFPU_LE_ARMCC"      name="CMSIS/Lib/ARM/arm_ARMv8MMLl_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2548         <file category="library" condition="CM33_DSP_NOFPU_LE_ARMCC"        name="CMSIS/Lib/ARM/arm_ARMv8MMLld_math.lib"     src="CMSIS/DSP/Source/ARM"/>
2549         <file category="library" condition="CM33_NODSP_SP_LE_ARMCC"         name="CMSIS/Lib/ARM/arm_ARMv8MMLlfsp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
2550         <file category="library" condition="CM33_DSP_SP_LE_ARMCC"           name="CMSIS/Lib/ARM/arm_ARMv8MMLldfsp_math.lib"  src="CMSIS/DSP/Source/ARM"/>
2551         <file category="library" condition="ARMv8MBL_LE_ARMCC"              name="CMSIS/Lib/ARM/arm_ARMv8MBLl_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2552         <file category="library" condition="ARMv8MML_NODSP_NOFPU_LE_ARMCC"  name="CMSIS/Lib/ARM/arm_ARMv8MMLl_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2553         <file category="library" condition="ARMv8MML_DSP_NOFPU_LE_ARMCC"    name="CMSIS/Lib/ARM/arm_ARMv8MMLld_math.lib"     src="CMSIS/DSP/Source/ARM"/>
2554         <file category="library" condition="ARMv8MML_NODSP_SP_LE_ARMCC"     name="CMSIS/Lib/ARM/arm_ARMv8MMLlfsp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
2555         <file category="library" condition="ARMv8MML_DSP_SP_LE_ARMCC"       name="CMSIS/Lib/ARM/arm_ARMv8MMLldfsp_math.lib"  src="CMSIS/DSP/Source/ARM"/>
2556         <!--file category="library" condition="ARMv8MML_DP_NOFPU_LE_ARMCC"     name="CMSIS/Lib/ARM/arm_ARMv8MMLlfdp_math.lib"   src="CMSIS/DSP/Source/ARM"/-->
2557         <!--file category="library" condition="ARMv8MML_DSP_DP_LE_ARMCC"       name="CMSIS/Lib/ARM/arm_ARMv8MMLldfdp_math.lib"  src="CMSIS/DSP/Source/ARM"/-->
2558
2559         <!-- GCC -->
2560         <file category="library" condition="CM0_LE_GCC"               name="CMSIS/Lib/GCC/libarm_cortexM0l_math.a"     src="CMSIS/DSP/Source/GCC"/>
2561         <file category="library" condition="CM3_LE_GCC"               name="CMSIS/Lib/GCC/libarm_cortexM3l_math.a"     src="CMSIS/DSP/Source/GCC"/>
2562         <file category="library" condition="CM4_LE_GCC"               name="CMSIS/Lib/GCC/libarm_cortexM4l_math.a"     src="CMSIS/DSP/Source/GCC"/>
2563         <file category="library" condition="CM4_FP_LE_GCC"            name="CMSIS/Lib/GCC/libarm_cortexM4lf_math.a"    src="CMSIS/DSP/Source/GCC"/>
2564         <file category="library" condition="CM7_LE_GCC"               name="CMSIS/Lib/GCC/libarm_cortexM7l_math.a"     src="CMSIS/DSP/Source/GCC"/>
2565         <file category="library" condition="CM7_SP_LE_GCC"            name="CMSIS/Lib/GCC/libarm_cortexM7lfsp_math.a"  src="CMSIS/DSP/Source/GCC"/>
2566         <file category="library" condition="CM7_DP_LE_GCC"            name="CMSIS/Lib/GCC/libarm_cortexM7lfdp_math.a"  src="CMSIS/DSP/Source/GCC"/>
2567
2568         <file category="library" condition="CM23_LE_GCC"                    name="CMSIS/Lib/GCC/libarm_ARMv8MBLl_math.a"     src="CMSIS/DSP/Source/GCC"/>
2569         <file category="library" condition="CM33_NODSP_NOFPU_LE_GCC"        name="CMSIS/Lib/GCC/libarm_ARMv8MMLl_math.a"     src="CMSIS/DSP/Source/GCC"/>
2570         <file category="library" condition="CM33_DSP_NOFPU_LE_GCC"          name="CMSIS/Lib/GCC/libarm_ARMv8MMLld_math.a"    src="CMSIS/DSP/Source/GCC"/>
2571         <file category="library" condition="CM33_NODSP_SP_LE_GCC"           name="CMSIS/Lib/GCC/libarm_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP/Source/GCC"/>
2572         <file category="library" condition="CM33_DSP_SP_LE_GCC"             name="CMSIS/Lib/GCC/libarm_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
2573         <file category="library" condition="ARMv8MBL_LE_GCC"                name="CMSIS/Lib/GCC/libarm_ARMv8MBLl_math.a"     src="CMSIS/DSP/Source/GCC"/>
2574         <file category="library" condition="ARMv8MML_NODSP_NOFPU_LE_GCC"    name="CMSIS/Lib/GCC/libarm_ARMv8MMLl_math.a"     src="CMSIS/DSP/Source/GCC"/>
2575         <file category="library" condition="ARMv8MML_DSP_NOFPU_LE_GCC"      name="CMSIS/Lib/GCC/libarm_ARMv8MMLld_math.a"    src="CMSIS/DSP/Source/GCC"/>
2576         <file category="library" condition="ARMv8MML_NODSP_SP_LE_GCC"       name="CMSIS/Lib/GCC/libarm_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP/Source/GCC"/>
2577         <file category="library" condition="ARMv8MML_DSP_SP_LE_GCC"         name="CMSIS/Lib/GCC/libarm_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
2578         <!--file category="library" condition="ARMv8MML_DP_NOFPU_LE_GCC"       name="CMSIS/Lib/GCC/libarm_ARMv8MMLlfdp_math.a"  src="CMSIS/DSP/Source/GCC"/-->
2579         <!--file category="library" condition="ARMv8MML_DSP_DP_LE_GCC"         name="CMSIS/Lib/GCC/libarm_ARMv8MMLldfdp_math.a" src="CMSIS/DSP/Source/GCC"/-->
2580
2581         <!-- IAR -->
2582         <file category="library" condition="CM0_LE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM0l_math.a"     src="CMSIS/DSP/Source/IAR"/>
2583         <file category="library" condition="CM0_BE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM0b_math.a"     src="CMSIS/DSP/Source/IAR"/>
2584         <file category="library" condition="CM3_LE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM3l_math.a"     src="CMSIS/DSP/Source/IAR"/>
2585         <file category="library" condition="CM3_BE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM3b_math.a"     src="CMSIS/DSP/Source/IAR"/>
2586         <file category="library" condition="CM4_LE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM4l_math.a"     src="CMSIS/DSP/Source/IAR"/>
2587         <file category="library" condition="CM4_BE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM4b_math.a"     src="CMSIS/DSP/Source/IAR"/>
2588         <file category="library" condition="CM4_FP_LE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM4lf_math.a"    src="CMSIS/DSP/Source/IAR"/>
2589         <file category="library" condition="CM4_FP_BE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM4bf_math.a"    src="CMSIS/DSP/Source/IAR"/>
2590         <file category="library" condition="CM7_LE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM7l_math.a"     src="CMSIS/DSP/Source/IAR"/>
2591         <file category="library" condition="CM7_BE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM7b_math.a"     src="CMSIS/DSP/Source/IAR"/>
2592         <file category="library" condition="CM7_DP_LE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM7lf_math.a"    src="CMSIS/DSP/Source/IAR"/>
2593         <file category="library" condition="CM7_DP_BE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM7bf_math.a"    src="CMSIS/DSP/Source/IAR"/>
2594         <file category="library" condition="CM7_SP_LE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM7ls_math.a"    src="CMSIS/DSP/Source/IAR"/>
2595         <file category="library" condition="CM7_SP_BE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM7bs_math.a"    src="CMSIS/DSP/Source/IAR"/>
2596
2597         <file category="library" condition="CM23_LE_IAR"              name="CMSIS/Lib/IAR/iar_ARMv8MBLl_math.a"     src="CMSIS/DSP/Source/IAR"/>
2598         <file category="library" condition="CM33_LE_IAR"              name="CMSIS/Lib/IAR/iar_ARMv8MMLl_math.a"     src="CMSIS/DSP/Source/IAR"/>
2599         <file category="library" condition="CM33_DSP_SP_LE_IAR"       name="CMSIS/Lib/IAR/iar_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP/Source/IAR"/>
2600         <file category="library" condition="CM33_FP_LE_IAR"           name="CMSIS/Lib/IAR/iar_ARMv8MMLlfdp_math.a"  src="CMSIS/DSP/Source/IAR"/>
2601         <file category="library" condition="CM33_DSP_NOFPU_LE_IAR"    name="CMSIS/Lib/IAR/iar_ARMv8MMLld_math.a"    src="CMSIS/DSP/Source/IAR"/>
2602         <file category="library" condition="CM33_DSP_SP_LE_IAR"       name="CMSIS/Lib/IAR/iar_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
2603         <!--file category="library" condition="CM33_DSP_DP_LE_IAR"       name="CMSIS/Lib/IAR/iar_ARMv8MMLldfdp_math.a" src="CMSIS/DSP/Source/IAR"/-->
2604         <file category="library" condition="ARMv8MBL_LE_IAR"          name="CMSIS/Lib/IAR/iar_ARMv8MBLl_math.a"     src="CMSIS/DSP/Source/IAR"/>
2605         <file category="library" condition="ARMv8MML_LE_IAR"          name="CMSIS/Lib/IAR/iar_ARMv8MMLl_math.a"     src="CMSIS/DSP/Source/IAR"/>
2606         <file category="library" condition="ARMv8MML_DSP_SP_LE_IAR"   name="CMSIS/Lib/IAR/iar_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP/Source/IAR"/>
2607         <file category="library" condition="ARMv8MML_FP_LE_IAR"       name="CMSIS/Lib/IAR/iar_ARMv8MMLlfdp_math.a"  src="CMSIS/DSP/Source/IAR"/>
2608         <file category="library" condition="ARMv8MML_DSP_NOFPU_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLld_math.a"    src="CMSIS/DSP/Source/IAR"/>
2609         <file category="library" condition="ARMv8MML_DSP_SP_LE_IAR"   name="CMSIS/Lib/IAR/iar_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
2610         <!--file category="library" condition="ARMv8MML_DSP_DP_LE_IAR"   name="CMSIS/Lib/IAR/iar_ARMv8MMLldfdp_math.a" src="CMSIS/DSP/Source/IAR"/-->
2611
2612       </files>
2613     </component>
2614
2615     <!-- CMSIS-NN component -->
2616     <component Cclass="CMSIS" Cgroup="NN Lib" Cversion="1.0.0" condition="CMSIS NN">
2617       <description>CMSIS-NN Neural Network Library</description>
2618       <files>
2619         <file category="doc" name="CMSIS/Documentation/NN/html/index.html"/>
2620         <file category="header" name="CMSIS/NN/Include/arm_nnfunctions.h"/>
2621
2622         <file category="source" name="CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c"/>
2623         <file category="source" name="CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c"/>
2624         <file category="source" name="CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c"/>
2625         <file category="source" name="CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c"/>
2626
2627         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c"/>
2628         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c"/>
2629         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c"/>
2630         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c"/>
2631         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c"/>
2632         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c"/>
2633         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c"/>
2634         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c"/>
2635         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c"/>
2636         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c"/>
2637         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c"/>
2638         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c"/>
2639
2640         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c"/>
2641         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c"/>
2642         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c"/>
2643         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c"/>
2644         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c"/>
2645         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c"/>
2646
2647         <file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c"/>
2648         <file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c"/>
2649         <file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c"/>
2650         <file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.c"/>
2651         <file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.c"/>
2652
2653         <file category="source" name="CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c"/>
2654
2655         <file category="source" name="CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.c"/>
2656         <file category="source" name="CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.c"/>
2657       </files>
2658     </component>
2659
2660     <!-- CMSIS-RTOS Keil RTX component -->
2661     <component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX" Cversion="4.81.1" Capiversion="1.0.0" isDefaultVariant="1" condition="RTOS RTX">
2662       <description>CMSIS-RTOS RTX implementation for Cortex-M, SC000, and SC300</description>
2663       <RTE_Components_h>
2664         <!-- the following content goes into file 'RTE_Components.h' -->
2665         #define RTE_CMSIS_RTOS                  /* CMSIS-RTOS */
2666         #define RTE_CMSIS_RTOS_RTX              /* CMSIS-RTOS Keil RTX */
2667       </RTE_Components_h>
2668       <files>
2669         <!-- CPU independent -->
2670         <file category="doc" name="CMSIS/Documentation/RTOS/html/rtxImplementation.html"/>
2671         <file category="header" name="CMSIS/RTOS/RTX/INC/cmsis_os.h"/>
2672         <file category="source" attr="config"   name="CMSIS/RTOS/RTX/Templates/RTX_Conf_CM.c" version="4.70.1"/>
2673
2674         <!-- RTX templates -->
2675         <file category="header" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/osObjects.h" select="CMSIS-RTOS 'main' function"/>
2676         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/main.c"      select="CMSIS-RTOS 'main' function"/>
2677         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MailQueue.c" select="CMSIS-RTOS Mail Queue"/>
2678         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MemPool.c"   select="CMSIS-RTOS Memory Pool"/>
2679         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MsgQueue.c"  select="CMSIS-RTOS Message Queue"/>
2680         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Mutex.c"     select="CMSIS-RTOS Mutex"/>
2681         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Semaphore.c" select="CMSIS-RTOS Semaphore"/>
2682         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Thread.c"    select="CMSIS-RTOS Thread"/>
2683         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Timer.c"     select="CMSIS-RTOS Timer"/>
2684         <!-- tool-chain specific template file -->
2685         <file category="source" attr="template" condition="ARMCC" name="CMSIS/RTOS/RTX/SRC/ARM/SVC_Table.s" select="CMSIS-RTOS User SVC"/>
2686         <file category="source" attr="template" condition="GCC"   name="CMSIS/RTOS/RTX/SRC/GCC/SVC_Table.S" select="CMSIS-RTOS User SVC"/>
2687         <file category="source" attr="template" condition="IAR"   name="CMSIS/RTOS/RTX/SRC/IAR/SVC_Table.s" select="CMSIS-RTOS User SVC"/>
2688
2689         <!-- CPU and Compiler dependent -->
2690         <!-- ARMCC -->
2691         <file category="library" condition="CM0_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
2692         <file category="library" condition="CM0_BE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
2693         <file category="library" condition="CM3_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
2694         <file category="library" condition="CM3_BE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
2695         <file category="library" condition="CM4_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
2696         <file category="library" condition="CM4_BE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
2697         <file category="library" condition="CM4_FP_LE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
2698         <file category="library" condition="CM4_FP_BE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
2699         <file category="library" condition="CM7_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
2700         <file category="library" condition="CM7_BE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
2701         <file category="library" condition="CM7_FP_LE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
2702         <file category="library" condition="CM7_FP_BE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
2703         <!-- GCC -->
2704         <file category="library" condition="CM0_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
2705         <file category="library" condition="CM0_BE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
2706         <file category="library" condition="CM3_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
2707         <file category="library" condition="CM3_BE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
2708         <file category="library" condition="CM4_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
2709         <file category="library" condition="CM4_BE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
2710         <file category="library" condition="CM4_FP_LE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
2711         <file category="library" condition="CM4_FP_BE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
2712         <file category="library" condition="CM7_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
2713         <file category="library" condition="CM7_BE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
2714         <file category="library" condition="CM7_FP_LE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
2715         <file category="library" condition="CM7_FP_BE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
2716         <!-- IAR -->
2717         <file category="library" condition="CM0_LE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
2718         <file category="library" condition="CM0_BE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
2719         <file category="library" condition="CM3_LE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
2720         <file category="library" condition="CM3_BE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
2721         <file category="library" condition="CM4_LE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
2722         <file category="library" condition="CM4_BE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
2723         <file category="library" condition="CM4_FP_LE_IAR"   name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
2724         <file category="library" condition="CM4_FP_BE_IAR"   name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
2725         <file category="library" condition="CM7_LE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
2726         <file category="library" condition="CM7_BE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
2727         <file category="library" condition="CM7_FP_LE_IAR"   name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
2728         <file category="library" condition="CM7_FP_BE_IAR"   name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
2729       </files>
2730     </component>
2731     <!-- CMSIS-RTOS Keil RTX component (IFX variant) -->
2732     <component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX" Cvariant="IFX" Cversion="4.81.1" Capiversion="1.0.0" condition="RTOS RTX IFX">
2733       <description>CMSIS-RTOS RTX implementation for Infineon XMC4 series affected by PMU_CM.001 errata</description>
2734       <RTE_Components_h>
2735         <!-- the following content goes into file 'RTE_Components.h' -->
2736         #define RTE_CMSIS_RTOS                  /* CMSIS-RTOS */
2737         #define RTE_CMSIS_RTOS_RTX              /* CMSIS-RTOS Keil RTX */
2738       </RTE_Components_h>
2739       <files>
2740         <!-- CPU independent -->
2741         <file category="doc" name="CMSIS/Documentation/RTOS/html/rtxImplementation.html"/>
2742         <file category="header" name="CMSIS/RTOS/RTX/INC/cmsis_os.h"/>
2743         <file category="source" attr="config"   name="CMSIS/RTOS/RTX/Templates/RTX_Conf_CM.c" version="4.70.1"/>
2744
2745         <!-- RTX templates -->
2746         <file category="header" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/osObjects.h" select="CMSIS-RTOS 'main' function"/>
2747         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/main.c"      select="CMSIS-RTOS 'main' function"/>
2748         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MailQueue.c" select="CMSIS-RTOS Mail Queue"/>
2749         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MemPool.c"   select="CMSIS-RTOS Memory Pool"/>
2750         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MsgQueue.c"  select="CMSIS-RTOS Message Queue"/>
2751         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Mutex.c"     select="CMSIS-RTOS Mutex"/>
2752         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Semaphore.c" select="CMSIS-RTOS Semaphore"/>
2753         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Thread.c"    select="CMSIS-RTOS Thread"/>
2754         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Timer.c"     select="CMSIS-RTOS Timer"/>
2755         <!-- tool-chain specific template file -->
2756         <file category="source" attr="template" condition="ARMCC" name="CMSIS/RTOS/RTX/SRC/ARM/SVC_Table.s" select="CMSIS-RTOS User SVC"/>
2757         <file category="source" attr="template" condition="GCC"   name="CMSIS/RTOS/RTX/SRC/GCC/SVC_Table.S" select="CMSIS-RTOS User SVC"/>
2758         <file category="source" attr="template" condition="IAR"   name="CMSIS/RTOS/RTX/SRC/IAR/SVC_Table.s" select="CMSIS-RTOS User SVC"/>
2759
2760         <!-- CPU and Compiler dependent -->
2761         <!-- ARMCC -->
2762         <file category="library" condition="CM4_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_IFX.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
2763         <file category="library" condition="CM4_FP_LE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_IFX.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
2764         <!-- GCC -->
2765         <file category="library" condition="CM4_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_IFX.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
2766         <file category="library" condition="CM4_FP_LE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_IFX.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
2767         <!-- IAR -->
2768       </files>
2769     </component>
2770
2771     <!-- CMSIS-RTOS Keil RTX5 component -->
2772     <component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX5" Cversion="5.4.0" Capiversion="1.0.0" condition="RTOS RTX5">
2773       <description>CMSIS-RTOS RTX5 implementation for Cortex-M, SC000, and SC300</description>
2774       <RTE_Components_h>
2775         <!-- the following content goes into file 'RTE_Components.h' -->
2776         #define RTE_CMSIS_RTOS                  /* CMSIS-RTOS */
2777         #define RTE_CMSIS_RTOS_RTX5             /* CMSIS-RTOS Keil RTX5 */
2778       </RTE_Components_h>
2779       <files>
2780         <!-- RTX header file -->
2781         <file category="header" name="CMSIS/RTOS2/RTX/Include1/cmsis_os.h"/>
2782         <!-- RTX compatibility module for API V1 -->
2783         <file category="source" name="CMSIS/RTOS2/RTX/Library/cmsis_os1.c"/>
2784       </files>
2785     </component>
2786
2787     <!-- CMSIS-RTOS2 Keil RTX5 component -->
2788     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cversion="5.4.0" Capiversion="2.1.3" condition="RTOS2 RTX5 Lib">
2789       <description>CMSIS-RTOS2 RTX5 for Cortex-M, SC000, C300 and Armv8-M (Library)</description>
2790       <RTE_Components_h>
2791         <!-- the following content goes into file 'RTE_Components.h' -->
2792         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
2793         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
2794       </RTE_Components_h>
2795       <files>
2796         <!-- RTX documentation -->
2797         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
2798
2799         <!-- RTX header files -->
2800         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
2801
2802         <!-- RTX configuration -->
2803         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.4.0"/>
2804         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
2805
2806         <!-- RTX templates -->
2807         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.0.0" select="CMSIS-RTOS2 'main' function"/>
2808         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
2809         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
2810         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
2811         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
2812         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
2813         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
2814         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
2815         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
2816         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
2817
2818         <!-- RTX library configuration -->
2819         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
2820
2821         <!-- RTX libraries (CPU and Compiler dependent) -->
2822         <!-- ARMCC -->
2823         <file category="library" condition="CM0_LE_ARMCC"         name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM0.lib"    src="CMSIS/RTOS2/RTX/Source"/>
2824         <file category="library" condition="CM3_LE_ARMCC"         name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM3.lib"    src="CMSIS/RTOS2/RTX/Source"/>
2825         <file category="library" condition="CM4_LE_ARMCC"         name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM3.lib"    src="CMSIS/RTOS2/RTX/Source"/>
2826         <file category="library" condition="CM4_FP_LE_ARMCC"      name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM4F.lib"   src="CMSIS/RTOS2/RTX/Source"/>
2827         <file category="library" condition="CM7_LE_ARMCC"         name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM3.lib"    src="CMSIS/RTOS2/RTX/Source"/>
2828         <file category="library" condition="CM7_FP_LE_ARMCC"      name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM4F.lib"   src="CMSIS/RTOS2/RTX/Source"/>
2829         <file category="library" condition="CM23_LE_ARMCC"        name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MB.lib"   src="CMSIS/RTOS2/RTX/Source"/>
2830         <file category="library" condition="CM33_LE_ARMCC"        name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib"   src="CMSIS/RTOS2/RTX/Source"/>
2831         <file category="library" condition="CM33_FP_LE_ARMCC"     name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib"  src="CMSIS/RTOS2/RTX/Source"/>
2832         <file category="library" condition="ARMv8MBL_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MB.lib"   src="CMSIS/RTOS2/RTX/Source"/>
2833         <file category="library" condition="ARMv8MML_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib"   src="CMSIS/RTOS2/RTX/Source"/>
2834         <file category="library" condition="ARMv8MML_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib"  src="CMSIS/RTOS2/RTX/Source"/>
2835         <!-- GCC -->
2836         <file category="library" condition="CM0_LE_GCC"           name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM0.a"   src="CMSIS/RTOS2/RTX/Source"/>
2837         <file category="library" condition="CM3_LE_GCC"           name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a"   src="CMSIS/RTOS2/RTX/Source"/>
2838         <file category="library" condition="CM4_LE_GCC"           name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a"   src="CMSIS/RTOS2/RTX/Source"/>
2839         <file category="library" condition="CM4_FP_LE_GCC"        name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM4F.a"  src="CMSIS/RTOS2/RTX/Source"/>
2840         <file category="library" condition="CM7_LE_GCC"           name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a"   src="CMSIS/RTOS2/RTX/Source"/>
2841         <file category="library" condition="CM7_FP_LE_GCC"        name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM4F.a"  src="CMSIS/RTOS2/RTX/Source"/>
2842         <file category="library" condition="CM23_LE_GCC"          name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MB.a"  src="CMSIS/RTOS2/RTX/Source"/>
2843         <file category="library" condition="CM33_LE_GCC"          name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a"  src="CMSIS/RTOS2/RTX/Source"/>
2844         <file category="library" condition="CM33_FP_LE_GCC"       name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
2845         <file category="library" condition="ARMv8MBL_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MB.a"  src="CMSIS/RTOS2/RTX/Source"/>
2846         <file category="library" condition="ARMv8MML_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a"  src="CMSIS/RTOS2/RTX/Source"/>
2847         <file category="library" condition="ARMv8MML_FP_LE_GCC"   name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
2848         <!-- IAR -->
2849         <file category="library" condition="CM0_LE_IAR"           name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM0.a"      src="CMSIS/RTOS2/RTX/Source"/>
2850         <file category="library" condition="CM3_LE_IAR"           name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM3.a"      src="CMSIS/RTOS2/RTX/Source"/>
2851         <file category="library" condition="CM4_LE_IAR"           name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM3.a"      src="CMSIS/RTOS2/RTX/Source"/>
2852         <file category="library" condition="CM4_FP_LE_IAR"        name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM4F.a"     src="CMSIS/RTOS2/RTX/Source"/>
2853         <file category="library" condition="CM7_LE_IAR"           name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM3.a"      src="CMSIS/RTOS2/RTX/Source"/>
2854         <file category="library" condition="CM7_FP_LE_IAR"        name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM4F.a"     src="CMSIS/RTOS2/RTX/Source"/>
2855       </files>
2856     </component>
2857     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library_NS" Cversion="5.4.0" Capiversion="2.1.3" condition="RTOS2 RTX5 NS">
2858       <description>CMSIS-RTOS2 RTX5 for Armv8-M Non-Secure Domain (Library)</description>
2859       <RTE_Components_h>
2860         <!-- the following content goes into file 'RTE_Components.h' -->
2861         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
2862         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
2863         #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS  /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */
2864       </RTE_Components_h>
2865       <files>
2866         <!-- RTX documentation -->
2867         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
2868
2869         <!-- RTX header files -->
2870         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
2871
2872         <!-- RTX configuration -->
2873         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.4.0"/>
2874         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
2875
2876         <!-- RTX templates -->
2877         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.0.0" select="CMSIS-RTOS2 'main' function"/>
2878         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
2879         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
2880         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
2881         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
2882         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
2883         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
2884         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
2885         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
2886         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
2887
2888         <!-- RTX library configuration -->
2889         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
2890
2891         <!-- RTX libraries (CPU and Compiler dependent) -->
2892         <!-- ARMCC -->
2893         <file category="library" condition="CM23_LE_ARMCC"        name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MBN.lib"   src="CMSIS/RTOS2/RTX/Source"/>
2894         <file category="library" condition="CM33_LE_ARMCC"        name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib"   src="CMSIS/RTOS2/RTX/Source"/>
2895         <file category="library" condition="CM33_FP_LE_ARMCC"     name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib"  src="CMSIS/RTOS2/RTX/Source"/>
2896         <file category="library" condition="ARMv8MBL_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MBN.lib"   src="CMSIS/RTOS2/RTX/Source"/>
2897         <file category="library" condition="ARMv8MML_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib"   src="CMSIS/RTOS2/RTX/Source"/>
2898         <file category="library" condition="ARMv8MML_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib"  src="CMSIS/RTOS2/RTX/Source"/>
2899         <!-- GCC -->
2900         <file category="library" condition="CM23_LE_GCC"          name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MBN.a"  src="CMSIS/RTOS2/RTX/Source"/>
2901         <file category="library" condition="CM33_LE_GCC"          name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a"  src="CMSIS/RTOS2/RTX/Source"/>
2902         <file category="library" condition="CM33_FP_LE_GCC"       name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
2903         <file category="library" condition="ARMv8MBL_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MBN.a"  src="CMSIS/RTOS2/RTX/Source"/>
2904         <file category="library" condition="ARMv8MML_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a"  src="CMSIS/RTOS2/RTX/Source"/>
2905         <file category="library" condition="ARMv8MML_FP_LE_GCC"   name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
2906       </files>
2907     </component>
2908     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cversion="5.4.0" Capiversion="2.1.3" condition="RTOS2 RTX5">
2909       <description>CMSIS-RTOS2 RTX5 for Cortex-M, SC000, C300 and Armv8-M (Source)</description>
2910       <RTE_Components_h>
2911         <!-- the following content goes into file 'RTE_Components.h' -->
2912         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
2913         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
2914         #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
2915       </RTE_Components_h>
2916       <files>
2917         <!-- RTX documentation -->
2918         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
2919
2920         <!-- RTX header files -->
2921         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
2922
2923         <!-- RTX configuration -->
2924         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.4.0"/>
2925         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
2926
2927         <!-- RTX templates -->
2928         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.0.0" select="CMSIS-RTOS2 'main' function"/>
2929         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
2930         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
2931         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
2932         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
2933         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
2934         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
2935         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
2936         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
2937         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
2938
2939         <!-- RTX sources (core) -->
2940         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_kernel.c"/>
2941         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_thread.c"/>
2942         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_delay.c"/>
2943         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_timer.c"/>
2944         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evflags.c"/>
2945         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mutex.c"/>
2946         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_semaphore.c"/>
2947         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_memory.c"/>
2948         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mempool.c"/>
2949         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c"/>
2950         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_system.c"/>
2951         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evr.c"/>
2952         <!-- RTX sources (library configuration) -->
2953         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
2954         <!-- RTX sources (handlers ARMCC) -->
2955         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm0.s"         condition="CM0_ARMCC"/>
2956         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm3.s"         condition="CM3_ARMCC"/>
2957         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm3.s"         condition="CM4_ARMCC"/>
2958         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm4f.s"        condition="CM4_FP_ARMCC"/>
2959         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm3.s"         condition="CM7_ARMCC"/>
2960         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm4f.s"        condition="CM7_FP_ARMCC"/>
2961         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl.s"    condition="CM23_ARMCC"/>
2962         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="CM33_ARMCC"/>
2963         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="CM33_FP_ARMCC"/>
2964         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl.s"    condition="ARMv8MBL_ARMCC"/>
2965         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="ARMv8MML_ARMCC"/>
2966         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="ARMv8MML_FP_ARMCC"/>
2967         <!-- RTX sources (handlers GCC) -->
2968         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm0.S"         condition="CM0_GCC"/>
2969         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm3.S"         condition="CM3_GCC"/>
2970         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm3.S"         condition="CM4_GCC"/>
2971         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm4f.S"        condition="CM4_FP_GCC"/>
2972         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm3.S"         condition="CM7_GCC"/>
2973         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm4f.S"        condition="CM7_FP_GCC"/>
2974         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S"    condition="CM23_GCC"/>
2975         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S"    condition="CM33_GCC"/>
2976         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp.S" condition="CM33_FP_GCC"/>
2977         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S"    condition="ARMv8MBL_GCC"/>
2978         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S"    condition="ARMv8MML_GCC"/>
2979         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp.S" condition="ARMv8MML_FP_GCC"/>
2980         <!-- RTX sources (handlers IAR) -->
2981         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm0.s"         condition="CM0_IAR"/>
2982         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm3.s"         condition="CM3_IAR"/>
2983         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm3.s"         condition="CM4_IAR"/>
2984         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm4f.s"        condition="CM4_FP_IAR"/>
2985         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm3.s"         condition="CM7_IAR"/>
2986         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm4f.s"        condition="CM7_FP_IAR"/>
2987         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s"    condition="CM23_IAR"/>
2988         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="CM33_IAR"/>
2989         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="CM33_FP_IAR"/>
2990         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s"    condition="ARMv8MBL_IAR"/>
2991         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="ARMv8MML_IAR"/>
2992         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="ARMv8MML_FP_IAR"/>
2993         <!-- OS Tick (SysTick) -->
2994         <file category="source" name="CMSIS/RTOS2/Source/os_systick.c"/>
2995       </files>
2996     </component>
2997     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cversion="5.4.0" Capiversion="2.1.3" condition="RTOS2 RTX5 v7-A">
2998       <description>CMSIS-RTOS2 RTX5 for Armv7-A (Source)</description>
2999       <RTE_Components_h>
3000         <!-- the following content goes into file 'RTE_Components.h' -->
3001         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
3002         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
3003         #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
3004       </RTE_Components_h>
3005       <files>
3006         <!-- RTX documentation -->
3007         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
3008
3009         <!-- RTX header files -->
3010         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
3011
3012         <!-- RTX configuration -->
3013         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.4.0"/>
3014         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
3015
3016         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/handlers.c"    version="5.1.0"/>
3017
3018         <!-- RTX templates -->
3019         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.0.0" select="CMSIS-RTOS2 'main' function"/>
3020         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
3021         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
3022         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
3023         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
3024         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
3025         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
3026         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
3027         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
3028         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
3029
3030         <!-- RTX sources (core) -->
3031         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_kernel.c"/>
3032         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_thread.c"/>
3033         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_delay.c"/>
3034         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_timer.c"/>
3035         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evflags.c"/>
3036         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mutex.c"/>
3037         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_semaphore.c"/>
3038         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_memory.c"/>
3039         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mempool.c"/>
3040         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c"/>
3041         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_system.c"/>
3042         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evr.c"/>
3043         <!-- RTX sources (library configuration) -->
3044         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
3045         <!-- RTX sources (handlers ARMCC) -->
3046         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_ca.s"          condition="CA_ARMCC5"/>
3047         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_ca.S"          condition="CA_ARMCC6"/>
3048         <!-- RTX sources (handlers GCC) -->
3049         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_ca.S"          condition="CA_GCC"/>
3050         <!-- RTX sources (handlers IAR) -->
3051         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_ca.s"          condition="CA_IAR"/>
3052       </files>
3053     </component>
3054     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source_NS" Cversion="5.4.0" Capiversion="2.1.3" condition="RTOS2 RTX5 NS">
3055       <description>CMSIS-RTOS2 RTX5 for Armv8-M Non-Secure Domain (Source)</description>
3056       <RTE_Components_h>
3057         <!-- the following content goes into file 'RTE_Components.h' -->
3058         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
3059         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
3060         #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
3061         #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS  /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */
3062       </RTE_Components_h>
3063       <files>
3064         <!-- RTX documentation -->
3065         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
3066
3067         <!-- RTX header files -->
3068         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
3069
3070         <!-- RTX configuration -->
3071         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.4.0"/>
3072         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
3073
3074         <!-- RTX templates -->
3075         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.0.0" select="CMSIS-RTOS2 'main' function"/>
3076         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
3077         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
3078         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
3079         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
3080         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
3081         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
3082         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
3083         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
3084         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
3085
3086         <!-- RTX sources (core) -->
3087         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_kernel.c"/>
3088         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_thread.c"/>
3089         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_delay.c"/>
3090         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_timer.c"/>
3091         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evflags.c"/>
3092         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mutex.c"/>
3093         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_semaphore.c"/>
3094         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_memory.c"/>
3095         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mempool.c"/>
3096         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c"/>
3097         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_system.c"/>
3098         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evr.c"/>
3099         <!-- RTX sources (library configuration) -->
3100         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
3101         <!-- RTX sources (ARMCC handlers) -->
3102         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl_ns.s"    condition="CM23_ARMCC"/>
3103         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="CM33_ARMCC"/>
3104         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="CM33_FP_ARMCC"/>
3105         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl_ns.s"    condition="ARMv8MBL_ARMCC"/>
3106         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="ARMv8MML_ARMCC"/>
3107         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="ARMv8MML_FP_ARMCC"/>
3108         <!-- RTX sources (GCC handlers) -->
3109         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl_ns.S"    condition="CM23_GCC"/>
3110         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_ns.S"    condition="CM33_GCC"/>
3111         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp_ns.S" condition="CM33_FP_GCC"/>
3112         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl_ns.S"    condition="ARMv8MBL_GCC"/>
3113         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_ns.S"    condition="ARMv8MML_GCC"/>
3114         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp_ns.S" condition="ARMv8MML_FP_GCC"/>
3115         <!-- RTX sources (IAR handlers) -->
3116         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl_ns.s"    condition="CM23_IAR"/>
3117         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="CM33_IAR"/>
3118         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="CM33_FP_IAR"/>
3119         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl_ns.s"    condition="ARMv8MBL_IAR"/>
3120         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="ARMv8MML_IAR"/>
3121         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="ARMv8MML_FP_IAR"/>
3122         <!-- OS Tick (SysTick) -->
3123         <file category="source" name="CMSIS/RTOS2/Source/os_systick.c"/>
3124       </files>
3125     </component>
3126
3127   </components>
3128
3129   <boards>
3130     <board name="uVision Simulator" vendor="Keil">
3131       <description>uVision Simulator</description>
3132       <mountedDevice    deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0"/>
3133       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0P"/>
3134       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0P_MPU"/>
3135       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM3"/>
3136       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM4"/>
3137       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM4_FP"/>
3138       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7"/>
3139       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7_SP"/>
3140       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7_DP"/>
3141       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MBL"/>
3142       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML"/>
3143       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML_SP"/>
3144       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML_DP"/>
3145       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM23"/>
3146       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM23_TZ"/>
3147       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33"/>
3148       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_TZ"/>
3149       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_DSP_FP"/>
3150       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_DSP_FP_TZ"/>
3151     </board>
3152
3153     <board name="Fixed Virtual Platform" vendor="ARM">
3154       <description>Fixed Virtual Platform</description>
3155       <mountedDevice    deviceIndex="0" Dvendor="ARM:82" Dname="ARMCA5"/>
3156       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCA7"/>
3157       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCA9"/>
3158     </board>
3159   </boards>
3160
3161   <examples>
3162     <example name="DSP_Lib Class Marks example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_class_marks_example">
3163       <description>DSP_Lib Class Marks example</description>
3164       <board name="uVision Simulator" vendor="Keil"/>
3165       <project>
3166         <environment name="uv" load="arm_class_marks_example.uvprojx"/>
3167       </project>
3168       <attributes>
3169         <component Cclass="CMSIS" Cgroup="CORE"/>
3170         <component Cclass="CMSIS" Cgroup="DSP"/>
3171         <component Cclass="Device" Cgroup="Startup"/>
3172         <category>Getting Started</category>
3173       </attributes>
3174     </example>
3175
3176     <example name="DSP_Lib Convolution example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_convolution_example">
3177       <description>DSP_Lib Convolution example</description>
3178       <board name="uVision Simulator" vendor="Keil"/>
3179       <project>
3180         <environment name="uv" load="arm_convolution_example.uvprojx"/>
3181       </project>
3182       <attributes>
3183         <component Cclass="CMSIS" Cgroup="CORE"/>
3184         <component Cclass="CMSIS" Cgroup="DSP"/>
3185         <component Cclass="Device" Cgroup="Startup"/>
3186         <category>Getting Started</category>
3187       </attributes>
3188     </example>
3189
3190     <example name="DSP_Lib Dotproduct example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_dotproduct_example">
3191       <description>DSP_Lib Dotproduct example</description>
3192       <board name="uVision Simulator" vendor="Keil"/>
3193       <project>
3194         <environment name="uv" load="arm_dotproduct_example.uvprojx"/>
3195       </project>
3196       <attributes>
3197         <component Cclass="CMSIS" Cgroup="CORE"/>
3198         <component Cclass="CMSIS" Cgroup="DSP"/>
3199         <component Cclass="Device" Cgroup="Startup"/>
3200         <category>Getting Started</category>
3201       </attributes>
3202     </example>
3203
3204     <example name="DSP_Lib FFT Bin example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_fft_bin_example">
3205       <description>DSP_Lib FFT Bin example</description>
3206       <board name="uVision Simulator" vendor="Keil"/>
3207       <project>
3208         <environment name="uv" load="arm_fft_bin_example.uvprojx"/>
3209       </project>
3210       <attributes>
3211         <component Cclass="CMSIS" Cgroup="CORE"/>
3212         <component Cclass="CMSIS" Cgroup="DSP"/>
3213         <component Cclass="Device" Cgroup="Startup"/>
3214         <category>Getting Started</category>
3215       </attributes>
3216     </example>
3217
3218     <example name="DSP_Lib FIR example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_fir_example">
3219       <description>DSP_Lib FIR example</description>
3220       <board name="uVision Simulator" vendor="Keil"/>
3221       <project>
3222         <environment name="uv" load="arm_fir_example.uvprojx"/>
3223       </project>
3224       <attributes>
3225         <component Cclass="CMSIS" Cgroup="CORE"/>
3226         <component Cclass="CMSIS" Cgroup="DSP"/>
3227         <component Cclass="Device" Cgroup="Startup"/>
3228         <category>Getting Started</category>
3229       </attributes>
3230     </example>
3231
3232     <example name="DSP_Lib Graphic Equalizer example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example">
3233       <description>DSP_Lib Graphic Equalizer example</description>
3234       <board name="uVision Simulator" vendor="Keil"/>
3235       <project>
3236         <environment name="uv" load="arm_graphic_equalizer_example.uvprojx"/>
3237       </project>
3238       <attributes>
3239         <component Cclass="CMSIS" Cgroup="CORE"/>
3240         <component Cclass="CMSIS" Cgroup="DSP"/>
3241         <component Cclass="Device" Cgroup="Startup"/>
3242         <category>Getting Started</category>
3243       </attributes>
3244     </example>
3245
3246     <example name="DSP_Lib Linear Interpolation example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_linear_interp_example">
3247       <description>DSP_Lib Linear Interpolation example</description>
3248       <board name="uVision Simulator" vendor="Keil"/>
3249       <project>
3250         <environment name="uv" load="arm_linear_interp_example.uvprojx"/>
3251       </project>
3252       <attributes>
3253         <component Cclass="CMSIS" Cgroup="CORE"/>
3254         <component Cclass="CMSIS" Cgroup="DSP"/>
3255         <component Cclass="Device" Cgroup="Startup"/>
3256         <category>Getting Started</category>
3257       </attributes>
3258     </example>
3259
3260     <example name="DSP_Lib Matrix example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_matrix_example">
3261       <description>DSP_Lib Matrix example</description>
3262       <board name="uVision Simulator" vendor="Keil"/>
3263       <project>
3264         <environment name="uv" load="arm_matrix_example.uvprojx"/>
3265       </project>
3266       <attributes>
3267         <component Cclass="CMSIS" Cgroup="CORE"/>
3268         <component Cclass="CMSIS" Cgroup="DSP"/>
3269         <component Cclass="Device" Cgroup="Startup"/>
3270         <category>Getting Started</category>
3271       </attributes>
3272     </example>
3273
3274     <example name="DSP_Lib Signal Convergence example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_signal_converge_example">
3275       <description>DSP_Lib Signal Convergence example</description>
3276       <board name="uVision Simulator" vendor="Keil"/>
3277       <project>
3278         <environment name="uv" load="arm_signal_converge_example.uvprojx"/>
3279       </project>
3280       <attributes>
3281         <component Cclass="CMSIS" Cgroup="CORE"/>
3282         <component Cclass="CMSIS" Cgroup="DSP"/>
3283         <component Cclass="Device" Cgroup="Startup"/>
3284         <category>Getting Started</category>
3285       </attributes>
3286     </example>
3287
3288     <example name="DSP_Lib Sinus/Cosinus example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_sin_cos_example">
3289       <description>DSP_Lib Sinus/Cosinus example</description>
3290       <board name="uVision Simulator" vendor="Keil"/>
3291       <project>
3292         <environment name="uv" load="arm_sin_cos_example.uvprojx"/>
3293       </project>
3294       <attributes>
3295         <component Cclass="CMSIS" Cgroup="CORE"/>
3296         <component Cclass="CMSIS" Cgroup="DSP"/>
3297         <component Cclass="Device" Cgroup="Startup"/>
3298         <category>Getting Started</category>
3299       </attributes>
3300     </example>
3301
3302     <example name="DSP_Lib Variance example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_variance_example">
3303       <description>DSP_Lib Variance example</description>
3304       <board name="uVision Simulator" vendor="Keil"/>
3305       <project>
3306         <environment name="uv" load="arm_variance_example.uvprojx"/>
3307       </project>
3308       <attributes>
3309         <component Cclass="CMSIS" Cgroup="CORE"/>
3310         <component Cclass="CMSIS" Cgroup="DSP"/>
3311         <component Cclass="Device" Cgroup="Startup"/>
3312         <category>Getting Started</category>
3313       </attributes>
3314     </example>
3315
3316     <example name="NN Library CIFAR10" doc="readme.txt" folder="CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10">
3317       <description>Neural Network CIFAR10 example</description>
3318       <board name="uVision Simulator" vendor="Keil"/>
3319       <project>
3320         <environment name="uv" load="arm_nnexamples_cifar10.uvprojx"/>
3321       </project>
3322       <attributes>
3323         <component Cclass="CMSIS" Cgroup="CORE"/>
3324         <component Cclass="CMSIS" Cgroup="DSP"/>
3325         <component Cclass="CMSIS" Cgroup="NN Lib"/>
3326         <component Cclass="Device" Cgroup="Startup"/>
3327         <category>Getting Started</category>
3328       </attributes>
3329     </example>
3330
3331     <example name="NN Library GRU" doc="readme.txt" folder="CMSIS/NN/Examples/ARM/arm_nn_examples/gru">
3332       <description>Neural Network GRU example</description>
3333       <board name="uVision Simulator" vendor="Keil"/>
3334       <project>
3335         <environment name="uv" load="arm_nnexamples_gru.uvprojx"/>
3336       </project>
3337       <attributes>
3338         <component Cclass="CMSIS" Cgroup="CORE"/>
3339         <component Cclass="CMSIS" Cgroup="DSP"/>
3340         <component Cclass="CMSIS" Cgroup="NN Lib"/>
3341         <component Cclass="Device" Cgroup="Startup"/>
3342         <category>Getting Started</category>
3343       </attributes>
3344     </example>
3345
3346     <example name="CMSIS-RTOS2 Blinky" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/Blinky">
3347       <description>CMSIS-RTOS2 Blinky example</description>
3348       <board name="uVision Simulator" vendor="Keil"/>
3349       <project>
3350         <environment name="uv" load="Blinky.uvprojx"/>
3351       </project>
3352       <attributes>
3353         <component Cclass="CMSIS" Cgroup="CORE"/>
3354         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3355         <component Cclass="Device" Cgroup="Startup"/>
3356         <category>Getting Started</category>
3357       </attributes>
3358     </example>
3359
3360     <example name="CMSIS-RTOS2 RTX5 Migration" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/Migration">
3361       <description>CMSIS-RTOS2 mixed API v1 and v2</description>
3362       <board name="uVision Simulator" vendor="Keil"/>
3363       <project>
3364         <environment name="uv" load="Blinky.uvprojx"/>
3365       </project>
3366       <attributes>
3367         <component Cclass="CMSIS" Cgroup="CORE"/>
3368         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3369         <component Cclass="Device" Cgroup="Startup"/>
3370         <category>Getting Started</category>
3371       </attributes>
3372     </example>
3373
3374     <example name="CMSIS-RTOS2 RTX5 Message Queue" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/MsgQueue">
3375       <description>CMSIS-RTOS2 Message Queue Example</description>
3376       <board name="uVision Simulator" vendor="Keil"/>
3377       <project>
3378         <environment name="uv" load="MsqQueue.uvprojx"/>
3379       </project>
3380       <attributes>
3381         <component Cclass="CMSIS" Cgroup="CORE"/>
3382         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3383         <component Cclass="Compiler" Cgroup="EventRecorder"/>
3384         <component Cclass="Device" Cgroup="Startup"/>
3385         <category>Getting Started</category>
3386       </attributes>
3387     </example>
3388
3389     <example name="CMSIS-RTOS2 RTX5 Memory Pool" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/MemPool">
3390       <description>CMSIS-RTOS2 Memory Pool Example</description>
3391       <board name="Fixed Virtual Platform" vendor="ARM"/>
3392       <project>
3393         <environment name="uv" load="MemPool.uvprojx"/>
3394       </project>
3395       <attributes>
3396         <component Cclass="CMSIS" Cgroup="CORE"/>
3397         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3398         <component Cclass="Compiler" Cgroup="EventRecorder"/>
3399         <component Cclass="Device" Cgroup="Startup"/>
3400         <category>Getting Started</category>
3401       </attributes>
3402     </example>
3403
3404     <example name="TrustZone for ARMv8-M No RTOS" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/NoRTOS">
3405       <description>Bare-metal secure/non-secure example without RTOS</description>
3406       <board name="uVision Simulator" vendor="Keil"/>
3407       <project>
3408         <environment name="uv" load="NoRTOS.uvmpw"/>
3409       </project>
3410       <attributes>
3411         <component Cclass="CMSIS" Cgroup="CORE"/>
3412         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3413         <component Cclass="Device" Cgroup="Startup"/>
3414         <category>Getting Started</category>
3415       </attributes>
3416     </example>
3417
3418     <example name="TrustZone for ARMv8-M RTOS"  doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS">
3419       <description>Secure/non-secure RTOS example with thread context management</description>
3420       <board name="uVision Simulator" vendor="Keil"/>
3421       <project>
3422         <environment name="uv" load="RTOS.uvmpw"/>
3423       </project>
3424       <attributes>
3425         <component Cclass="CMSIS" Cgroup="CORE"/>
3426         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3427         <component Cclass="Device" Cgroup="Startup"/>
3428         <category>Getting Started</category>
3429       </attributes>
3430     </example>
3431
3432     <example name="TrustZone for ARMv8-M RTOS Security Tests"  doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults">
3433       <description>Secure/non-secure RTOS example with security test cases and system recovery</description>
3434       <board name="uVision Simulator" vendor="Keil"/>
3435       <project>
3436         <environment name="uv" load="RTOS_Faults.uvmpw"/>
3437       </project>
3438       <attributes>
3439         <component Cclass="CMSIS" Cgroup="CORE"/>
3440         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3441         <component Cclass="Device" Cgroup="Startup"/>
3442         <category>Getting Started</category>
3443       </attributes>
3444     </example>
3445
3446   </examples>
3447
3448 </package>