begriffs open source - cmsis/blob - main/Core_A/html/group__CMSIS__CPSR__M.html

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  46    <div id="projectname">CMSIS-Core (Cortex-A)
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  55    <div id="projectbrief">CMSIS-Core support for Cortex-A processor-based devices</div>
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 126 <div class="header">
 127   <div class="summary">
 128 <a href="#define-members">Macros</a>  </div>
 129   <div class="headertitle"><div class="title">CPSR M field values<div class="ingroups"><a class="el" href="group__CMSIS__core__register.html">Core Register Access</a> &raquo; <a class="el" href="group__CMSIS__CPSR.html">Current Program Status Register (CPSR)</a></div></div></div>
 130 </div><!--header-->
 131 <div class="contents">
 132
 133 <p>Valid values for CPSR M field.
 134 <a href="#details">More...</a></p>
 135 <table class="memberdecls">
 136 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a>
 137 Macros</h2></td></tr>
 138 <tr class="memitem:gad716a0ee4dc815f0f01e1339d6511a4e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#gad716a0ee4dc815f0f01e1339d6511a4e">CPSR_M_USR</a>&#160;&#160;&#160;0x10U</td></tr>
 139 <tr class="memdesc:gad716a0ee4dc815f0f01e1339d6511a4e"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPSR: M User mode (PL0)  <br /></td></tr>
 140 <tr class="separator:gad716a0ee4dc815f0f01e1339d6511a4e"><td class="memSeparator" colspan="2">&#160;</td></tr>
 141 <tr class="memitem:ga868ef12e003f541f90a613ca7f6ada74"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#ga868ef12e003f541f90a613ca7f6ada74">CPSR_M_FIQ</a>&#160;&#160;&#160;0x11U</td></tr>
 142 <tr class="memdesc:ga868ef12e003f541f90a613ca7f6ada74"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPSR: M Fast Interrupt mode (PL1)  <br /></td></tr>
 143 <tr class="separator:ga868ef12e003f541f90a613ca7f6ada74"><td class="memSeparator" colspan="2">&#160;</td></tr>
 144 <tr class="memitem:gada3f31a773f7fc7bf6567d598cf3a1db"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#gada3f31a773f7fc7bf6567d598cf3a1db">CPSR_M_IRQ</a>&#160;&#160;&#160;0x12U</td></tr>
 145 <tr class="memdesc:gada3f31a773f7fc7bf6567d598cf3a1db"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPSR: M Interrupt mode (PL1)  <br /></td></tr>
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 148 <tr class="memdesc:ga5afcb85bd2968acc2b09cb9d99c531ad"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPSR: M Supervisor mode (PL1)  <br /></td></tr>
 149 <tr class="separator:ga5afcb85bd2968acc2b09cb9d99c531ad"><td class="memSeparator" colspan="2">&#160;</td></tr>
 150 <tr class="memitem:ga69d734db93f67899b4bffcf62f80f098"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#ga69d734db93f67899b4bffcf62f80f098">CPSR_M_MON</a>&#160;&#160;&#160;0x16U</td></tr>
 151 <tr class="memdesc:ga69d734db93f67899b4bffcf62f80f098"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPSR: M Monitor mode (PL1)  <br /></td></tr>
 152 <tr class="separator:ga69d734db93f67899b4bffcf62f80f098"><td class="memSeparator" colspan="2">&#160;</td></tr>
 153 <tr class="memitem:gac8c0a99a21ef256f5d3115595a845bfa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#gac8c0a99a21ef256f5d3115595a845bfa">CPSR_M_ABT</a>&#160;&#160;&#160;0x17U</td></tr>
 154 <tr class="memdesc:gac8c0a99a21ef256f5d3115595a845bfa"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPSR: M Abort mode (PL1)  <br /></td></tr>
 155 <tr class="separator:gac8c0a99a21ef256f5d3115595a845bfa"><td class="memSeparator" colspan="2">&#160;</td></tr>
 156 <tr class="memitem:ga002c78f542ca5c5fdd02d2aeee9f6988"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#ga002c78f542ca5c5fdd02d2aeee9f6988">CPSR_M_HYP</a>&#160;&#160;&#160;0x1AU</td></tr>
 157 <tr class="memdesc:ga002c78f542ca5c5fdd02d2aeee9f6988"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPSR: M Hypervisor mode (PL2)  <br /></td></tr>
 158 <tr class="separator:ga002c78f542ca5c5fdd02d2aeee9f6988"><td class="memSeparator" colspan="2">&#160;</td></tr>
 159 <tr class="memitem:ga07d4f42d6971c2f0cc25872008ddf5ef"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#ga07d4f42d6971c2f0cc25872008ddf5ef">CPSR_M_UND</a>&#160;&#160;&#160;0x1BU</td></tr>
 160 <tr class="memdesc:ga07d4f42d6971c2f0cc25872008ddf5ef"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPSR: M Undefined mode (PL1)  <br /></td></tr>
 161 <tr class="separator:ga07d4f42d6971c2f0cc25872008ddf5ef"><td class="memSeparator" colspan="2">&#160;</td></tr>
 162 <tr class="memitem:gaa0a3996ce096cd205bce34f90b10912c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#gaa0a3996ce096cd205bce34f90b10912c">CPSR_M_SYS</a>&#160;&#160;&#160;0x1FU</td></tr>
 163 <tr class="memdesc:gaa0a3996ce096cd205bce34f90b10912c"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPSR: M System mode (PL1)  <br /></td></tr>
 164 <tr class="separator:gaa0a3996ce096cd205bce34f90b10912c"><td class="memSeparator" colspan="2">&#160;</td></tr>
 165 </table>
 166 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
 167 <p>The M field can contain one of these values which indicates the current processor mode. </p>
 168 <h2 class="groupheader">Macro Definition Documentation</h2>
 169 <a id="gac8c0a99a21ef256f5d3115595a845bfa" name="gac8c0a99a21ef256f5d3115595a845bfa"></a>
 170 <h2 class="memtitle"><span class="permalink"><a href="#gac8c0a99a21ef256f5d3115595a845bfa">&#9670;&#160;</a></span>CPSR_M_ABT</h2>
 171
 172 <div class="memitem">
 173 <div class="memproto">
 174       <table class="memname">
 175         <tr>
 176           <td class="memname">#define CPSR_M_ABT&#160;&#160;&#160;0x17U</td>
 177         </tr>
 178       </table>
 179 </div><div class="memdoc">
 180 <p>Abort mode is the default mode to which a Data Abort exception or Prefetch Abort exception is taken. </p>
 181
 182 </div>
 183 </div>
 184 <a id="ga868ef12e003f541f90a613ca7f6ada74" name="ga868ef12e003f541f90a613ca7f6ada74"></a>
 185 <h2 class="memtitle"><span class="permalink"><a href="#ga868ef12e003f541f90a613ca7f6ada74">&#9670;&#160;</a></span>CPSR_M_FIQ</h2>
 186
 187 <div class="memitem">
 188 <div class="memproto">
 189       <table class="memname">
 190         <tr>
 191           <td class="memname">#define CPSR_M_FIQ&#160;&#160;&#160;0x11U</td>
 192         </tr>
 193       </table>
 194 </div><div class="memdoc">
 195 <p>FIQ mode is the default mode to which an FIQ interrupt is taken. </p>
 196
 197 </div>
 198 </div>
 199 <a id="ga002c78f542ca5c5fdd02d2aeee9f6988" name="ga002c78f542ca5c5fdd02d2aeee9f6988"></a>
 200 <h2 class="memtitle"><span class="permalink"><a href="#ga002c78f542ca5c5fdd02d2aeee9f6988">&#9670;&#160;</a></span>CPSR_M_HYP</h2>
 201
 202 <div class="memitem">
 203 <div class="memproto">
 204       <table class="memname">
 205         <tr>
 206           <td class="memname">#define CPSR_M_HYP&#160;&#160;&#160;0x1AU</td>
 207         </tr>
 208       </table>
 209 </div><div class="memdoc">
 210 <p>Hyp mode is the Non-secure PL2 mode, implemented as part of the Virtualization Extensions. Hyp mode is entered on taking an exception from Non-secure state that must be taken to PL2. </p>
 211
 212 </div>
 213 </div>
 214 <a id="gada3f31a773f7fc7bf6567d598cf3a1db" name="gada3f31a773f7fc7bf6567d598cf3a1db"></a>
 215 <h2 class="memtitle"><span class="permalink"><a href="#gada3f31a773f7fc7bf6567d598cf3a1db">&#9670;&#160;</a></span>CPSR_M_IRQ</h2>
 216
 217 <div class="memitem">
 218 <div class="memproto">
 219       <table class="memname">
 220         <tr>
 221           <td class="memname">#define CPSR_M_IRQ&#160;&#160;&#160;0x12U</td>
 222         </tr>
 223       </table>
 224 </div><div class="memdoc">
 225 <p>IRQ mode is the default mode to which an IRQ interrupt is taken. </p>
 226
 227 </div>
 228 </div>
 229 <a id="ga69d734db93f67899b4bffcf62f80f098" name="ga69d734db93f67899b4bffcf62f80f098"></a>
 230 <h2 class="memtitle"><span class="permalink"><a href="#ga69d734db93f67899b4bffcf62f80f098">&#9670;&#160;</a></span>CPSR_M_MON</h2>
 231
 232 <div class="memitem">
 233 <div class="memproto">
 234       <table class="memname">
 235         <tr>
 236           <td class="memname">#define CPSR_M_MON&#160;&#160;&#160;0x16U</td>
 237         </tr>
 238       </table>
 239 </div><div class="memdoc">
 240 <p>Monitor mode is the mode to which a Secure Monitor Call exception is taken. </p>
 241
 242 </div>
 243 </div>
 244 <a id="ga5afcb85bd2968acc2b09cb9d99c531ad" name="ga5afcb85bd2968acc2b09cb9d99c531ad"></a>
 245 <h2 class="memtitle"><span class="permalink"><a href="#ga5afcb85bd2968acc2b09cb9d99c531ad">&#9670;&#160;</a></span>CPSR_M_SVC</h2>
 246
 247 <div class="memitem">
 248 <div class="memproto">
 249       <table class="memname">
 250         <tr>
 251           <td class="memname">#define CPSR_M_SVC&#160;&#160;&#160;0x13U</td>
 252         </tr>
 253       </table>
 254 </div><div class="memdoc">
 255 <p>Supervisor mode is the default mode to which a Supervisor Call exception is taken. </p>
 256
 257 </div>
 258 </div>
 259 <a id="gaa0a3996ce096cd205bce34f90b10912c" name="gaa0a3996ce096cd205bce34f90b10912c"></a>
 260 <h2 class="memtitle"><span class="permalink"><a href="#gaa0a3996ce096cd205bce34f90b10912c">&#9670;&#160;</a></span>CPSR_M_SYS</h2>
 261
 262 <div class="memitem">
 263 <div class="memproto">
 264       <table class="memname">
 265         <tr>
 266           <td class="memname">#define CPSR_M_SYS&#160;&#160;&#160;0x1FU</td>
 267         </tr>
 268       </table>
 269 </div><div class="memdoc">
 270 <p>Software executing in System mode executes at PL1. System mode has the same registers available as User mode, and is not entered by any exception. </p>
 271
 272 </div>
 273 </div>
 274 <a id="ga07d4f42d6971c2f0cc25872008ddf5ef" name="ga07d4f42d6971c2f0cc25872008ddf5ef"></a>
 275 <h2 class="memtitle"><span class="permalink"><a href="#ga07d4f42d6971c2f0cc25872008ddf5ef">&#9670;&#160;</a></span>CPSR_M_UND</h2>
 276
 277 <div class="memitem">
 278 <div class="memproto">
 279       <table class="memname">
 280         <tr>
 281           <td class="memname">#define CPSR_M_UND&#160;&#160;&#160;0x1BU</td>
 282         </tr>
 283       </table>
 284 </div><div class="memdoc">
 285 <p>Undefined mode is the default mode to which an instruction-related exception, including any attempt to execute an UNDEFINED instruction, is taken. </p>
 286
 287 </div>
 288 </div>
 289 <a id="gad716a0ee4dc815f0f01e1339d6511a4e" name="gad716a0ee4dc815f0f01e1339d6511a4e"></a>
 290 <h2 class="memtitle"><span class="permalink"><a href="#gad716a0ee4dc815f0f01e1339d6511a4e">&#9670;&#160;</a></span>CPSR_M_USR</h2>
 291
 292 <div class="memitem">
 293 <div class="memproto">
 294       <table class="memname">
 295         <tr>
 296           <td class="memname">#define CPSR_M_USR&#160;&#160;&#160;0x10U</td>
 297         </tr>
 298       </table>
 299 </div><div class="memdoc">
 300 <p>An operating system runs applications in User mode to restrict the use of system resources. Software executing in User mode executes at PL0. Execution in User mode is sometimes described as unprivileged execution. </p>
 301
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