begriffs open source - cmsis/blob - main/Core_A/modules.html

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  46    <div id="projectname">CMSIS-Core (Cortex-A)
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  55    <div id="projectbrief">CMSIS-Core support for Cortex-A processor-based devices</div>
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 130   <div class="headertitle"><div class="title">API Reference</div></div>
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 132 <div class="contents">
 133 <div class="textblock">Here is a list of all modules:</div><div class="directory">
 134 <div class="levels">[detail level <span onclick="javascript:toggleLevel(1);">1</span><span onclick="javascript:toggleLevel(2);">2</span><span onclick="javascript:toggleLevel(3);">3</span>]</div><table class="directory">
 135 <tr id="row_0_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><a class="el" href="group__system__init__gr.html" target="_self">System and Clock Configuration</a></td><td class="desc">Functions for system and clock setup available in system_<em>device</em>.c </td></tr>
 136 <tr id="row_1_" class="odd"><td class="entry"><span style="width:0px;display:inline-block;">&#160;</span><span id="arr_1_" class="arrow" onclick="toggleFolder('1_')">&#9658;</span><a class="el" href="group__CMSIS__core__register.html" target="_self">Core Register Access</a></td><td class="desc">Functions to access the Cortex-A core registers </td></tr>
 137 <tr id="row_1_0_" class="even" style="display:none;"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span id="arr_1_0_" class="arrow" onclick="toggleFolder('1_0_')">&#9658;</span><a class="el" href="group__CMSIS__ACTLR.html" target="_self">Auxiliary Control Register (ACTLR)</a></td><td class="desc">The ACTLR provides IMPLEMENTATION DEFINED configuration and control options </td></tr>
 138 <tr id="row_1_0_0_" class="even" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__CMSIS__ACTLR__BITS.html" target="_self">ACTLR Bits</a></td><td class="desc">Bit position and mask macros </td></tr>
 139 <tr id="row_1_1_" class="even" style="display:none;"><td class="entry"><span style="width:32px;display:inline-block;">&#160;</span><a class="el" href="group__CMSIS__CBPM.html" target="_self">Cache and branch predictor maintenance operations</a></td><td class="desc">This section describes the cache and branch predictor maintenance operations </td></tr>
 140 <tr id="row_1_2_" class="even" style="display:none;"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span id="arr_1_2_" class="arrow" onclick="toggleFolder('1_2_')">&#9658;</span><a class="el" href="group__CMSIS__CBAR.html" target="_self">Configuration Base Address Register (CBAR)</a></td><td class="desc">Takes the physical base address value of the memory-mapped SCU peripherals at reset from the external signal PERIPHBASE[31:13] </td></tr>
 141 <tr id="row_1_2_0_" class="even" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__CMSIS__CBAR__BITS.html" target="_self">CBAR Bits</a></td><td class="desc">Bit position and mask macros </td></tr>
 142 <tr id="row_1_3_" class="even" style="display:none;"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span id="arr_1_3_" class="arrow" onclick="toggleFolder('1_3_')">&#9658;</span><a class="el" href="group__CMSIS__CPACR.html" target="_self">Coprocessor Access Control Register (CPACR)</a></td><td class="desc">The CPACR controls access to coprocessors CP0 to CP13 </td></tr>
 143 <tr id="row_1_3_0_" class="even" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__CMSIS__CPACR__BITS.html" target="_self">CPACR Bits</a></td><td class="desc">Bit position and mask macros </td></tr>
 144 <tr id="row_1_3_1_" class="even" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__CMSIS__CPACR__CP.html" target="_self">CPACR CP field values</a></td><td class="desc">Valid values for CPACR CP field </td></tr>
 145 <tr id="row_1_4_" class="even" style="display:none;"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span id="arr_1_4_" class="arrow" onclick="toggleFolder('1_4_')">&#9658;</span><a class="el" href="group__CMSIS__CPSR.html" target="_self">Current Program Status Register (CPSR)</a></td><td class="desc">The Current Program Status Register (CPSR) holds processor status and control information </td></tr>
 146 <tr id="row_1_4_0_" class="even" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__CMSIS__CPSR__BITS.html" target="_self">CPSR Bits</a></td><td class="desc">Bit position and mask macros </td></tr>
 147 <tr id="row_1_4_1_" class="even" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__CMSIS__CPSR__M.html" target="_self">CPSR M field values</a></td><td class="desc">Valid values for CPSR M field </td></tr>
 148 <tr id="row_1_5_" class="even" style="display:none;"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span id="arr_1_5_" class="arrow" onclick="toggleFolder('1_5_')">&#9658;</span><a class="el" href="group__CMSIS__DFSR.html" target="_self">Data Fault Status Register (DFSR)</a></td><td class="desc">The DFSR holds status information about the last data fault </td></tr>
 149 <tr id="row_1_5_0_" class="even" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__CMSIS__DFSR__BITS.html" target="_self">ACTLR Bits</a></td><td class="desc">Bit position and mask macros </td></tr>
 150 <tr id="row_1_6_" class="even" style="display:none;"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span id="arr_1_6_" class="arrow" onclick="toggleFolder('1_6_')">&#9658;</span><a class="el" href="group__CMSIS__DACR.html" target="_self">Domain Access Control Register (DACR)</a></td><td class="desc">DACR defines the access permission for each of the sixteen memory domains </td></tr>
 151 <tr id="row_1_6_0_" class="even" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__CMSIS__DACR__BITS.html" target="_self">DACR Bits</a></td><td class="desc">Bit position and mask macros </td></tr>
 152 <tr id="row_1_6_1_" class="even" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__CMSIS__DACR__Dn.html" target="_self">DACR Dn field values</a></td><td class="desc">Valid values for DACR Dn field </td></tr>
 153 <tr id="row_1_7_" class="even" style="display:none;"><td class="entry"><span style="width:32px;display:inline-block;">&#160;</span><a class="el" href="group__CMSIS__FPEXC.html" target="_self">Floating-Point Exception Control register (FPEXC)</a></td><td class="desc">Provides a global enable for the Advanced SIMD and Floating-point (VFP) Extensions, and indicates how the state of these extensions is recorded </td></tr>
 154 <tr id="row_1_8_" class="even" style="display:none;"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span id="arr_1_8_" class="arrow" onclick="toggleFolder('1_8_')">&#9658;</span><a class="el" href="group__CMSIS__FPSCR.html" target="_self">Floating-point Status and Control Register (FPSCR)</a></td><td class="desc">Provides floating-point system status information and control </td></tr>
 155 <tr id="row_1_8_0_" class="even" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__CMSIS__FPSCR__BITS.html" target="_self">FPSCR Bits</a></td><td class="desc">Bit position and mask macros </td></tr>
 156 <tr id="row_1_9_" class="even" style="display:none;"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span id="arr_1_9_" class="arrow" onclick="toggleFolder('1_9_')">&#9658;</span><a class="el" href="group__CMSIS__IFSR.html" target="_self">Instruction Fault Status Register (IFSR)</a></td><td class="desc">The IFSR holds status information about the last instruction fault </td></tr>
 157 <tr id="row_1_9_0_" class="even" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__CMSIS__IFSR__BITS.html" target="_self">IFSR Bits</a></td><td class="desc">Bit position and mask macros </td></tr>
 158 <tr id="row_1_10_" class="even" style="display:none;"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span id="arr_1_10_" class="arrow" onclick="toggleFolder('1_10_')">&#9658;</span><a class="el" href="group__CMSIS__ISR.html" target="_self">Interrupt Status Register (ISR)</a></td><td class="desc">The ISR shows whether an IRQ, FIQ, or external abort is pending </td></tr>
 159 <tr id="row_1_10_0_" class="even" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__CMSIS__ISR__BITS.html" target="_self">ISR Bits</a></td><td class="desc">Bit position and mask macros </td></tr>
 160 <tr id="row_1_11_" class="even" style="display:none;"><td class="entry"><span style="width:32px;display:inline-block;">&#160;</span><a class="el" href="group__CMSIS__MPIDR.html" target="_self">Multiprocessor Affinity Register (MPIDR)</a></td><td class="desc">In a multiprocessor system, the MPIDR provides an additional processor identification mechanism for scheduling purposes, and indicates whether the implementation includes the Multiprocessing Extensions </td></tr>
 161 <tr id="row_1_12_" class="even" style="display:none;"><td class="entry"><span style="width:32px;display:inline-block;">&#160;</span><a class="el" href="group__CMSIS__CNTFRQ.html" target="_self">Counter Frequency register (CNTFRQ)</a></td><td class="desc">Indicates the clock frequency of the system counter </td></tr>
 162 <tr id="row_1_13_" class="even" style="display:none;"><td class="entry"><span style="width:32px;display:inline-block;">&#160;</span><a class="el" href="group__CMSIS__CNTP__CTL.html" target="_self">PL1 Physical Timer Control register (CNTP_CTL)</a></td><td class="desc">The control register for the physical timer </td></tr>
 163 <tr id="row_1_14_" class="even" style="display:none;"><td class="entry"><span style="width:32px;display:inline-block;">&#160;</span><a class="el" href="group__CMSIS__CNTP__CVAL.html" target="_self">PL1 Physical Timer Compare Value register (CNTP_CVAL)</a></td><td class="desc">Holds the 64-bit compare value for the PL1 physical timer </td></tr>
 164 <tr id="row_1_15_" class="even" style="display:none;"><td class="entry"><span style="width:32px;display:inline-block;">&#160;</span><a class="el" href="group__CMSIS__CNTP__TVAL.html" target="_self">PL1 Physical Timer Value register (CNTP_TVAL)</a></td><td class="desc">Holds the timer value for the PL1 physical timer </td></tr>
 165 <tr id="row_1_16_" class="even" style="display:none;"><td class="entry"><span style="width:32px;display:inline-block;">&#160;</span><a class="el" href="group__CMSIS__CNTPCT.html" target="_self">PL1 Physical Count register (CNTPCT)</a></td><td class="desc">Holds the 64-bit physical count value </td></tr>
 166 <tr id="row_1_17_" class="even" style="display:none;"><td class="entry"><span style="width:32px;display:inline-block;">&#160;</span><a class="el" href="group__CMSIS__SP.html" target="_self">Stack Pointer (SP/R13)</a></td><td class="desc">The processor uses SP as a pointer to the active stack </td></tr>
 167 <tr id="row_1_18_" class="even" style="display:none;"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span id="arr_1_18_" class="arrow" onclick="toggleFolder('1_18_')">&#9658;</span><a class="el" href="group__CMSIS__SCTLR.html" target="_self">System Control Register (SCTLR)</a></td><td class="desc">The SCTLR provides the top level control of the system, including its memory system </td></tr>
 168 <tr id="row_1_18_0_" class="even" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__CMSIS__SCTLR__BITS.html" target="_self">SCTLR Bits</a></td><td class="desc">Bit position and mask macros </td></tr>
 169 <tr id="row_1_19_" class="even" style="display:none;"><td class="entry"><span style="width:32px;display:inline-block;">&#160;</span><a class="el" href="group__CMSIS__TLB.html" target="_self">TLB maintenance operations</a></td><td class="desc">This section describes the TLB operations that are implemented on all Armv7-A implementations </td></tr>
 170 <tr id="row_1_20_" class="even" style="display:none;"><td class="entry"><span style="width:32px;display:inline-block;">&#160;</span><a class="el" href="group__CMSIS__TTBR.html" target="_self">Translation Table Base Registers (TTBR0/TTBR1)</a></td><td class="desc">TTBRn holds the base address of translation table n, and information about the memory it occupies </td></tr>
 171 <tr id="row_1_21_" class="even" style="display:none;"><td class="entry"><span style="width:32px;display:inline-block;">&#160;</span><a class="el" href="group__CMSIS__VBAR.html" target="_self">Vector Base Address Register (VBAR)</a></td><td class="desc">When high exception vectors are not selected, the VBAR holds the exception base address for exceptions that are not taken to Monitor mode or to Hyp mode </td></tr>
 172 <tr id="row_1_22_" class="even" style="display:none;"><td class="entry"><span style="width:32px;display:inline-block;">&#160;</span><a class="el" href="group__CMSIS__MVBAR.html" target="_self">Monitor Vector Base Address Register (MVBAR)</a></td><td class="desc">The MVBAR holds the exception base address for all exceptions that are taken to Monitor mode </td></tr>
 173 <tr id="row_2_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><a class="el" href="group__peripheral__gr.html" target="_self">Peripheral Access</a></td><td class="desc">Naming conventions and optional features for accessing peripherals </td></tr>
 174 <tr id="row_3_" class="odd"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><a class="el" href="group__version__ctrl.html" target="_self">Version Control</a></td><td class="desc">Version symbols for CMSIS release specific C/C++ source code </td></tr>
 175 <tr id="row_4_" class="even"><td class="entry"><span style="width:0px;display:inline-block;">&#160;</span><span id="arr_4_" class="arrow" onclick="toggleFolder('4_')">&#9658;</span><a class="el" href="group__CMSIS__Core__FunctionInterface.html" target="_self">Core Peripherals</a></td><td class="desc"></td></tr>
 176 <tr id="row_4_0_" class="odd" style="display:none;"><td class="entry"><span style="width:32px;display:inline-block;">&#160;</span><a class="el" href="group__GIC__functions.html" target="_self">Generic Interrupt Controller Functions</a></td><td class="desc">The Generic Interrupt Controller Functions grant access to the configuration, control and status registers of the Generic Interrupt Controller (GIC) </td></tr>
 177 <tr id="row_4_1_" class="odd" style="display:none;"><td class="entry"><span style="width:32px;display:inline-block;">&#160;</span><a class="el" href="group__L1__cache__functions.html" target="_self">L1 Cache Functions</a></td><td class="desc">L1 Cache Functions give support to enable, clean and invalidate level 1 instruction and data caches, as well as to enable branch target address cache </td></tr>
 178 <tr id="row_4_2_" class="odd" style="display:none;"><td class="entry"><span style="width:32px;display:inline-block;">&#160;</span><a class="el" href="group__L2__cache__functions.html" target="_self">L2C-310 Cache Controller Functions</a></td><td class="desc">L2C-310 Cache Controller gives access to functions for level 2 cache maintenance.<br  />
 179 Reference: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0246h/index.html">Level 2 Cache Controller L2C-310 Technical Reference Manual</a> </td></tr>
 180 <tr id="row_4_3_" class="odd" style="display:none;"><td class="entry"><span style="width:32px;display:inline-block;">&#160;</span><a class="el" href="group__PL1__timer__functions.html" target="_self">Generic Physical Timer Functions</a></td><td class="desc">Generic Physical Timer Functions allow to control privilege level 1 physical timer registers on Generic Timer for Cortex-A7 class devices.<br  />
 181 Reference: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/index.html">Cortex-A7 MPCore Technical Reference Manual</a> </td></tr>
 182 <tr id="row_4_4_" class="odd" style="display:none;"><td class="entry"><span style="width:32px;display:inline-block;">&#160;</span><a class="el" href="group__PTM__timer__functions.html" target="_self">Private Timer Functions</a></td><td class="desc">Private Timer Functions controls private timer registers present on Cortex-A5 and A9 class devices.<br  />
 183 References: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0434c/index.html">Cortex-A5 MPCore Technical Reference Manual</a>, <a href="http://infocenter.arm.com/help/topic/com.arm.doc.100486_0401_10_en/index.html">Cortex-A9 MPCore Technical Reference Manual</a> </td></tr>
 184 <tr id="row_4_5_" class="odd" style="display:none;"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><span id="arr_4_5_" class="arrow" onclick="toggleFolder('4_5_')">&#9658;</span><a class="el" href="group__MMU__functions.html" target="_self">Memory Management Unit Functions</a></td><td class="desc">MMU Functions provide control of the Memory Management Unit using translation tables and attributes of different regions of the physical memory map.<br  />
 185 Reference: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0406c/index.html">Architecture Reference Manual Reference Manual - Armv7-A and Armv7-R edition</a> </td></tr>
 186 <tr id="row_4_5_0_" class="odd" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__MMU__defs__gr.html" target="_self">MMU Defines and Structs</a></td><td class="desc">Defines and structures that relate to the Memory Management Unit </td></tr>
 187 <tr id="row_4_6_" class="odd" style="display:none;"><td class="entry"><span style="width:32px;display:inline-block;">&#160;</span><a class="el" href="group__FPU__functions.html" target="_self">Floating Point Unit Functions</a></td><td class="desc">FPU Functions enable the use of Floating Point instructions and extensions.<br  />
 188 Reference: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0406c/index.html">Architecture Reference Manual Reference Manual - Armv7-A and Armv7-R edition</a> </td></tr>
 189 <tr id="row_5_" class="odd"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><a class="el" href="group__comp__cntrl__gr.html" target="_self">Compiler Control</a></td><td class="desc">Compiler agnostic #define symbols for generic C/C++ source code </td></tr>
 190 <tr id="row_6_" class="even"><td class="entry"><span style="width:16px;display:inline-block;">&#160;</span><a class="el" href="group__CMSIS__Core__InstructionInterface.html" target="_self">Intrinsic Functions</a></td><td class="desc">Functions that generate specific Cortex-A CPU Instructions </td></tr>
 191 <tr id="row_7_" class="odd"><td class="entry"><span style="width:0px;display:inline-block;">&#160;</span><span id="arr_7_" class="arrow" onclick="toggleFolder('7_')">&#9658;</span><a class="el" href="group__irq__ctrl__gr.html" target="_self">Interrupts and Exceptions</a></td><td class="desc">Generic functions to access the Interrupt Controller </td></tr>
 192 <tr id="row_7_0_" class="even" style="display:none;"><td class="entry"><span style="width:32px;display:inline-block;">&#160;</span><a class="el" href="group__irq__mode__defs.html" target="_self">IRQ Mode Bit-Masks</a></td><td class="desc">Configure interrupt line mode </td></tr>
 193 <tr id="row_7_1_" class="even" style="display:none;"><td class="entry"><span style="width:32px;display:inline-block;">&#160;</span><a class="el" href="group__irq__priority__defs.html" target="_self">IRQ Priority Bit-Masks</a></td><td class="desc">Definitions used by interrupt priority functions </td></tr>
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