2 * Copyright (c) 2009-2024 Arm Limited. All rights reserved.
4 * SPDX-License-Identifier: Apache-2.0
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
10 * www.apache.org/licenses/LICENSE-2.0
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
20 * CMSIS SC300 Core Peripheral Access Layer Header File
23 #if defined ( __ICCARM__ )
24 #pragma system_include /* treat file as system include file for MISRA check */
25 #elif defined (__clang__)
26 #pragma clang system_header /* treat file as system include file */
27 #elif defined ( __GNUC__ )
28 #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
31 #ifndef __CORE_SC300_H_GENERIC
32 #define __CORE_SC300_H_GENERIC
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
55 /*******************************************************************************
57 ******************************************************************************/
63 #include "cmsis_version.h"
65 /* CMSIS SC300 definitions */
67 #define __CORTEX_SC (300U) /*!< Cortex Secure Core */
69 /** __FPU_USED indicates whether an FPU is used or not.
70 This core does not support an FPU at all
74 #if defined ( __CC_ARM )
75 #if defined (__TARGET_FPU_VFP)
76 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
79 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
80 #if defined (__ARM_FP)
81 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
84 #elif defined (__ti__)
85 #if defined (__ARM_FP)
86 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
89 #elif defined ( __GNUC__ )
90 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
91 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
94 #elif defined ( __ICCARM__ )
95 #if defined (__ARMVFP__)
96 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
99 #elif defined ( __TI_ARM__ )
100 #if defined (__TI_VFP_SUPPORT__)
101 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
104 #elif defined ( __TASKING__ )
105 #if defined (__FPU_VFP__)
106 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
109 #elif defined ( __CSMC__ )
110 #if ( __CSMC__ & 0x400U)
111 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
116 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
123 #endif /* __CORE_SC300_H_GENERIC */
125 #ifndef __CMSIS_GENERIC
127 #ifndef __CORE_SC300_H_DEPENDANT
128 #define __CORE_SC300_H_DEPENDANT
134 /* check device defines and use defaults */
135 #if defined __CHECK_DEVICE_DEFINES
137 #define __SC300_REV 0x0000U
138 #warning "__SC300_REV not defined in device header file; using default!"
141 #ifndef __MPU_PRESENT
142 #define __MPU_PRESENT 0U
143 #warning "__MPU_PRESENT not defined in device header file; using default!"
146 #ifndef __VTOR_PRESENT
147 #define __VTOR_PRESENT 1U
148 #warning "__VTOR_PRESENT not defined in device header file; using default!"
151 #ifndef __NVIC_PRIO_BITS
152 #define __NVIC_PRIO_BITS 3U
153 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
156 #ifndef __Vendor_SysTickConfig
157 #define __Vendor_SysTickConfig 0U
158 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
162 /* IO definitions (access restrictions to peripheral registers) */
164 \defgroup CMSIS_glob_defs CMSIS Global Defines
166 <strong>IO Type Qualifiers</strong> are used
167 \li to specify the access to peripheral variables.
168 \li for automatic generation of peripheral register debug information.
171 #define __I volatile /*!< Defines 'read only' permissions */
173 #define __I volatile const /*!< Defines 'read only' permissions */
175 #define __O volatile /*!< Defines 'write only' permissions */
176 #define __IO volatile /*!< Defines 'read / write' permissions */
178 /* following defines should be used for structure members */
179 #define __IM volatile const /*! Defines 'read only' structure member permissions */
180 #define __OM volatile /*! Defines 'write only' structure member permissions */
181 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
183 /*@} end of group SC300 */
187 /*******************************************************************************
188 * Register Abstraction
189 Core Register contain:
193 - Core SysTick Register
194 - Core Debug Register
196 ******************************************************************************/
198 \defgroup CMSIS_core_register Defines and Type Definitions
199 \brief Type definitions and defines for Cortex-M processor based devices.
203 \ingroup CMSIS_core_register
204 \defgroup CMSIS_CORE Status and Control Registers
205 \brief Core Register type definitions.
210 \brief Union type to access the Application Program Status Register (APSR).
216 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
217 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
218 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
219 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
220 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
221 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
222 } b; /*!< Structure used for bit access */
223 uint32_t w; /*!< Type used for word access */
226 /** \brief APSR Register Definitions */
227 #define APSR_N_Pos 31U /*!< APSR: N Position */
228 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
230 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
231 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
233 #define APSR_C_Pos 29U /*!< APSR: C Position */
234 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
236 #define APSR_V_Pos 28U /*!< APSR: V Position */
237 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
239 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
240 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
244 \brief Union type to access the Interrupt Program Status Register (IPSR).
250 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
251 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
252 } b; /*!< Structure used for bit access */
253 uint32_t w; /*!< Type used for word access */
256 /** \brief IPSR Register Definitions */
257 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
258 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
262 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
268 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
269 uint32_t _reserved0:1; /*!< bit: 9 Reserved */
270 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
271 uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
272 uint32_t T:1; /*!< bit: 24 Thumb bit */
273 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
274 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
275 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
276 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
277 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
278 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
279 } b; /*!< Structure used for bit access */
280 uint32_t w; /*!< Type used for word access */
283 /** \brief xPSR Register Definitions */
284 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
285 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
287 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
288 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
290 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
291 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
293 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
294 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
296 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
297 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
299 #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
300 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
302 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
303 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
305 #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
306 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
308 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
309 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
313 \brief Union type to access the Control Registers (CONTROL).
319 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
320 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
321 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
322 } b; /*!< Structure used for bit access */
323 uint32_t w; /*!< Type used for word access */
326 /** \brief CONTROL Register Definitions */
327 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
328 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
330 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
331 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
333 /*@} end of group CMSIS_CORE */
337 \ingroup CMSIS_core_register
338 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
339 \brief Type definitions for the NVIC Registers
344 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
348 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
349 uint32_t RESERVED0[24U];
350 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
351 uint32_t RESERVED1[24U];
352 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
353 uint32_t RESERVED2[24U];
354 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
355 uint32_t RESERVED3[24U];
356 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
357 uint32_t RESERVED4[56U];
358 __IOM uint8_t IPR[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
359 uint32_t RESERVED5[644U];
360 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
363 /** \brief NVIC Software Triggered Interrupt Register Definitions */
364 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
365 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
367 /*@} end of group CMSIS_NVIC */
371 \ingroup CMSIS_core_register
372 \defgroup CMSIS_SCB System Control Block (SCB)
373 \brief Type definitions for the System Control Block Registers
378 \brief Structure type to access the System Control Block (SCB).
382 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
383 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
384 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
385 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
386 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
387 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
388 __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
389 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
390 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
391 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
392 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
393 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
394 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
395 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
396 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
397 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
398 __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
399 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
400 __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
401 uint32_t RESERVED0[5U];
402 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
403 uint32_t RESERVED1[129U];
404 __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
407 /** \brief SCB CPUID Register Definitions */
408 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
409 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
411 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
412 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
414 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
415 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
417 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
418 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
420 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
421 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
423 /** \brief SCB Interrupt Control State Register Definitions */
424 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
425 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
427 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
428 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
430 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
431 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
433 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
434 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
436 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
437 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
439 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
440 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
442 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
443 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
445 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
446 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
448 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
449 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
451 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
452 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
454 /** \brief SCB Vector Table Offset Register Definitions */
455 #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
456 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
458 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
459 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
461 /** \brief SCB Application Interrupt and Reset Control Register Definitions */
462 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
463 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
465 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
466 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
468 #define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */
469 #define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */
471 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
472 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
474 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
475 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
477 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
478 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
480 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
481 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
483 /** \brief SCB System Control Register Definitions */
484 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
485 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
487 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
488 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
490 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
491 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
493 /** \brief SCB Configuration Control Register Definitions */
494 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
495 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
497 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
498 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
500 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
501 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
503 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
504 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
506 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
507 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
509 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
510 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
512 /** \brief SCB System Handler Control and State Register Definitions */
513 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
514 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
516 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
517 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
519 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
520 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
522 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
523 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
525 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
526 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
528 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
529 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
531 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
532 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
534 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
535 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
537 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
538 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
540 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
541 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
543 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
544 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
546 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
547 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
549 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
550 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
552 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
553 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
555 /** \brief SCB Configurable Fault Status Register Definitions */
556 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
557 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
559 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
560 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
562 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
563 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
565 /** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */
566 #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
567 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
569 #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
570 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
572 #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
573 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
575 #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
576 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
578 #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
579 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
581 /** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */
582 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
583 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
585 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
586 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
588 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
589 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
591 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
592 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
594 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
595 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
597 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
598 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
600 /** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */
601 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
602 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
604 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
605 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
607 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
608 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
610 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
611 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
613 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
614 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
616 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
617 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
619 /** \brief SCB Hard Fault Status Register Definitions */
620 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
621 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
623 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
624 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
626 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
627 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
629 /** \brief SCB Debug Fault Status Register Definitions */
630 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
631 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
633 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
634 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
636 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
637 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
639 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
640 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
642 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
643 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
645 /*@} end of group CMSIS_SCB */
649 \ingroup CMSIS_core_register
650 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
651 \brief Type definitions for the System Control and ID Register not in the SCB
656 \brief Structure type to access the System Control and ID Register not in the SCB.
660 uint32_t RESERVED0[1U];
661 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
662 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
665 /** \brief SCnSCB Interrupt Controller Type Register Definitions */
666 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
667 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
669 /** \brief SCnSCB Auxiliary Control Register Definitions */
670 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
671 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
673 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
674 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
676 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
677 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
679 /*@} end of group CMSIS_SCnotSCB */
683 \ingroup CMSIS_core_register
684 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
685 \brief Type definitions for the System Timer Registers.
690 \brief Structure type to access the System Timer (SysTick).
694 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
695 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
696 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
697 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
700 /** \brief SysTick Control / Status Register Definitions */
701 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
702 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
704 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
705 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
707 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
708 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
710 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
711 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
713 /** \brief SysTick Reload Register Definitions */
714 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
715 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
717 /** \brief SysTick Current Register Definitions */
718 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
719 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
721 /** \brief SysTick Calibration Register Definitions */
722 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
723 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
725 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
726 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
728 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
729 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
731 /*@} end of group CMSIS_SysTick */
735 \ingroup CMSIS_core_register
736 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
737 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
742 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
748 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */
749 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */
750 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */
751 } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */
752 uint32_t RESERVED0[864U];
753 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */
754 uint32_t RESERVED1[15U];
755 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */
756 uint32_t RESERVED2[15U];
757 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */
758 uint32_t RESERVED3[32U];
759 uint32_t RESERVED4[43U];
760 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Lock Access Register */
761 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Lock Status Register */
764 /** \brief ITM Trace Privilege Register Definitions */
765 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
766 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
768 /** \brief ITM Trace Control Register Definitions */
769 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
770 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
772 #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
773 #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
775 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
776 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
778 #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPrescale Position */
779 #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPrescale Mask */
781 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
782 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
784 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
785 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
787 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
788 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
790 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
791 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
793 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
794 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
796 /** \brief ITM Lock Status Register Definitions */
797 #define ITM_LSR_BYTEACC_Pos 2U /*!< ITM LSR: ByteAcc Position */
798 #define ITM_LSR_BYTEACC_Msk (1UL << ITM_LSR_BYTEACC_Pos) /*!< ITM LSR: ByteAcc Mask */
800 #define ITM_LSR_ACCESS_Pos 1U /*!< ITM LSR: Access Position */
801 #define ITM_LSR_ACCESS_Msk (1UL << ITM_LSR_ACCESS_Pos) /*!< ITM LSR: Access Mask */
803 #define ITM_LSR_PRESENT_Pos 0U /*!< ITM LSR: Present Position */
804 #define ITM_LSR_PRESENT_Msk (1UL /*<< ITM_LSR_PRESENT_Pos*/) /*!< ITM LSR: Present Mask */
806 /*@}*/ /* end of group CMSIS_ITM */
810 \ingroup CMSIS_core_register
811 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
812 \brief Type definitions for the Data Watchpoint and Trace (DWT)
817 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
821 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
822 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
823 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
824 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
825 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
826 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
827 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
828 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
829 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
830 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
831 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
832 uint32_t RESERVED0[1U];
833 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
834 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
835 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
836 uint32_t RESERVED1[1U];
837 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
838 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
839 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
840 uint32_t RESERVED2[1U];
841 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
842 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
843 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
846 /** \brief DWT Control Register Definitions */
847 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
848 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
850 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
851 #define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
853 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
854 #define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
856 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
857 #define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
859 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
860 #define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
862 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
863 #define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
865 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
866 #define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
868 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
869 #define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
871 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
872 #define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
874 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
875 #define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
877 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
878 #define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
880 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
881 #define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
883 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
884 #define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
886 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
887 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
889 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
890 #define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
892 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
893 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
895 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
896 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
898 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
899 #define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
901 /** \brief DWT CPI Count Register Definitions */
902 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
903 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
905 /** \brief DWT Exception Overhead Count Register Definitions */
906 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
907 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
909 /** \brief DWT Sleep Count Register Definitions */
910 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
911 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
913 /** \brief DWT LSU Count Register Definitions */
914 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
915 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
917 /** \brief DWT Folded-instruction Count Register Definitions */
918 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
919 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
921 /** \brief DWT Comparator Mask Register Definitions */
922 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
923 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
925 /** \brief DWT Comparator Function Register Definitions */
926 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
927 #define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
929 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
930 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
932 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
933 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
935 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
936 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
938 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
939 #define DWT_FUNCTION_LNK1ENA_Msk (1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
941 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
942 #define DWT_FUNCTION_DATAVMATCH_Msk (1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
944 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
945 #define DWT_FUNCTION_CYCMATCH_Msk (1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
947 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
948 #define DWT_FUNCTION_EMITRANGE_Msk (1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
950 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
951 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
953 /*@}*/ /* end of group CMSIS_DWT */
957 \ingroup CMSIS_core_register
958 \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU)
959 \brief Type definitions for the Trace Port Interface Unit (TPIU)
964 \brief Structure type to access the Trace Port Interface Unit Register (TPIU).
968 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
969 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
970 uint32_t RESERVED0[2U];
971 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
972 uint32_t RESERVED1[55U];
973 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
974 uint32_t RESERVED2[131U];
975 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
976 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
977 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
978 uint32_t RESERVED3[759U];
979 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
980 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
981 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
982 uint32_t RESERVED4[1U];
983 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
984 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
985 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
986 uint32_t RESERVED5[39U];
987 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
988 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
989 uint32_t RESERVED7[8U];
990 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
991 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
994 /** \brief TPIU Asynchronous Clock Prescaler Register Definitions */
995 #define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */
996 #define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */
998 /** \brief TPIU Selected Pin Protocol Register Definitions */
999 #define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */
1000 #define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */
1002 /** \brief TPIU Formatter and Flush Status Register Definitions */
1003 #define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */
1004 #define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */
1006 #define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */
1007 #define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */
1009 #define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */
1010 #define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */
1012 #define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */
1013 #define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */
1015 /** \brief TPIU Formatter and Flush Control Register Definitions */
1016 #define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */
1017 #define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */
1019 #define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */
1020 #define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */
1022 /** \brief TPIU TRIGGER Register Definitions */
1023 #define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */
1024 #define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */
1026 /** \brief TPIU Integration ETM Data Register Definitions (FIFO0) */
1027 #define TPIU_FIFO0_ITM_ATVALID_Pos 29U /*!< TPIU FIFO0: ITM_ATVALID Position */
1028 #define TPIU_FIFO0_ITM_ATVALID_Msk (1UL << TPIU_FIFO0_ITM_ATVALID_Pos) /*!< TPIU FIFO0: ITM_ATVALID Mask */
1030 #define TPIU_FIFO0_ITM_bytecount_Pos 27U /*!< TPIU FIFO0: ITM_bytecount Position */
1031 #define TPIU_FIFO0_ITM_bytecount_Msk (0x3UL << TPIU_FIFO0_ITM_bytecount_Pos) /*!< TPIU FIFO0: ITM_bytecount Mask */
1033 #define TPIU_FIFO0_ETM_ATVALID_Pos 26U /*!< TPIU FIFO0: ETM_ATVALID Position */
1034 #define TPIU_FIFO0_ETM_ATVALID_Msk (1UL << TPIU_FIFO0_ETM_ATVALID_Pos) /*!< TPIU FIFO0: ETM_ATVALID Mask */
1036 #define TPIU_FIFO0_ETM_bytecount_Pos 24U /*!< TPIU FIFO0: ETM_bytecount Position */
1037 #define TPIU_FIFO0_ETM_bytecount_Msk (0x3UL << TPIU_FIFO0_ETM_bytecount_Pos) /*!< TPIU FIFO0: ETM_bytecount Mask */
1039 #define TPIU_FIFO0_ETM2_Pos 16U /*!< TPIU FIFO0: ETM2 Position */
1040 #define TPIU_FIFO0_ETM2_Msk (0xFFUL << TPIU_FIFO0_ETM2_Pos) /*!< TPIU FIFO0: ETM2 Mask */
1042 #define TPIU_FIFO0_ETM1_Pos 8U /*!< TPIU FIFO0: ETM1 Position */
1043 #define TPIU_FIFO0_ETM1_Msk (0xFFUL << TPIU_FIFO0_ETM1_Pos) /*!< TPIU FIFO0: ETM1 Mask */
1045 #define TPIU_FIFO0_ETM0_Pos 0U /*!< TPIU FIFO0: ETM0 Position */
1046 #define TPIU_FIFO0_ETM0_Msk (0xFFUL /*<< TPIU_FIFO0_ETM0_Pos*/) /*!< TPIU FIFO0: ETM0 Mask */
1048 /** \brief TPIU ITATBCTR2 Register Definitions */
1049 #define TPIU_ITATBCTR2_ATREADY2_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2 Position */
1050 #define TPIU_ITATBCTR2_ATREADY2_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2 Mask */
1052 #define TPIU_ITATBCTR2_ATREADY1_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1 Position */
1053 #define TPIU_ITATBCTR2_ATREADY1_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1 Mask */
1055 /** \brief TPIU Integration ITM Data Register Definitions (FIFO1) */
1056 #define TPIU_FIFO1_ITM_ATVALID_Pos 29U /*!< TPIU FIFO1: ITM_ATVALID Position */
1057 #define TPIU_FIFO1_ITM_ATVALID_Msk (1UL << TPIU_FIFO1_ITM_ATVALID_Pos) /*!< TPIU FIFO1: ITM_ATVALID Mask */
1059 #define TPIU_FIFO1_ITM_bytecount_Pos 27U /*!< TPIU FIFO1: ITM_bytecount Position */
1060 #define TPIU_FIFO1_ITM_bytecount_Msk (0x3UL << TPIU_FIFO1_ITM_bytecount_Pos) /*!< TPIU FIFO1: ITM_bytecount Mask */
1062 #define TPIU_FIFO1_ETM_ATVALID_Pos 26U /*!< TPIU FIFO1: ETM_ATVALID Position */
1063 #define TPIU_FIFO1_ETM_ATVALID_Msk (1UL << TPIU_FIFO1_ETM_ATVALID_Pos) /*!< TPIU FIFO1: ETM_ATVALID Mask */
1065 #define TPIU_FIFO1_ETM_bytecount_Pos 24U /*!< TPIU FIFO1: ETM_bytecount Position */
1066 #define TPIU_FIFO1_ETM_bytecount_Msk (0x3UL << TPIU_FIFO1_ETM_bytecount_Pos) /*!< TPIU FIFO1: ETM_bytecount Mask */
1068 #define TPIU_FIFO1_ITM2_Pos 16U /*!< TPIU FIFO1: ITM2 Position */
1069 #define TPIU_FIFO1_ITM2_Msk (0xFFUL << TPIU_FIFO1_ITM2_Pos) /*!< TPIU FIFO1: ITM2 Mask */
1071 #define TPIU_FIFO1_ITM1_Pos 8U /*!< TPIU FIFO1: ITM1 Position */
1072 #define TPIU_FIFO1_ITM1_Msk (0xFFUL << TPIU_FIFO1_ITM1_Pos) /*!< TPIU FIFO1: ITM1 Mask */
1074 #define TPIU_FIFO1_ITM0_Pos 0U /*!< TPIU FIFO1: ITM0 Position */
1075 #define TPIU_FIFO1_ITM0_Msk (0xFFUL /*<< TPIU_FIFO1_ITM0_Pos*/) /*!< TPIU FIFO1: ITM0 Mask */
1077 /** \brief TPIU ITATBCTR0 Register Definitions */
1078 #define TPIU_ITATBCTR0_ATREADY2_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2 Position */
1079 #define TPIU_ITATBCTR0_ATREADY2_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2 Mask */
1081 #define TPIU_ITATBCTR0_ATREADY1_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1 Position */
1082 #define TPIU_ITATBCTR0_ATREADY1_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1 Mask */
1084 /** \brief TPIU Integration Mode Control Register Definitions */
1085 #define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */
1086 #define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */
1088 /** \brief TPIU DEVID Register Definitions */
1089 #define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */
1090 #define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */
1092 #define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */
1093 #define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */
1095 #define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */
1096 #define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */
1098 #define TPIU_DEVID_MinBufSz_Pos 6U /*!< TPIU DEVID: MinBufSz Position */
1099 #define TPIU_DEVID_MinBufSz_Msk (0x7UL << TPIU_DEVID_MinBufSz_Pos) /*!< TPIU DEVID: MinBufSz Mask */
1101 #define TPIU_DEVID_AsynClkIn_Pos 5U /*!< TPIU DEVID: AsynClkIn Position */
1102 #define TPIU_DEVID_AsynClkIn_Msk (1UL << TPIU_DEVID_AsynClkIn_Pos) /*!< TPIU DEVID: AsynClkIn Mask */
1104 #define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */
1105 #define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */
1107 /** \brief TPIU DEVTYPE Register Definitions */
1108 #define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */
1109 #define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */
1111 #define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */
1112 #define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */
1114 /*@}*/ /* end of group CMSIS_TPIU */
1117 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1119 \ingroup CMSIS_core_register
1120 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1121 \brief Type definitions for the Memory Protection Unit (MPU)
1126 \brief Structure type to access the Memory Protection Unit (MPU).
1130 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1131 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1132 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
1133 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1134 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
1135 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
1136 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
1137 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
1138 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
1139 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
1140 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
1143 #define MPU_TYPE_RALIASES 4U
1145 /** \brief MPU Type Register Definitions */
1146 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
1147 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1149 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
1150 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1152 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
1153 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
1155 /** \brief MPU Control Register Definitions */
1156 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
1157 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1159 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
1160 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1162 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
1163 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
1165 /** \brief MPU Region Number Register Definitions */
1166 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
1167 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
1169 /** \brief MPU Region Base Address Register Definitions */
1170 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
1171 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
1173 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
1174 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
1176 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
1177 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
1179 /** \brief MPU Region Attribute and Size Register Definitions */
1180 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
1181 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
1183 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
1184 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
1186 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
1187 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
1189 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
1190 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
1192 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
1193 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
1195 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
1196 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
1198 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
1199 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
1201 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
1202 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
1204 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
1205 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
1207 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
1208 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
1210 /*@} end of group CMSIS_MPU */
1215 \ingroup CMSIS_core_register
1216 \defgroup CMSIS_DCB Debug Control Block
1217 \brief Type definitions for the Debug Control Block Registers
1222 \brief Structure type to access the Debug Control Block Registers (DCB).
1226 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1227 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1228 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1229 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1232 /** \brief DCB Debug Halting Control and Status Register Definitions */
1233 #define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
1234 #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
1236 #define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
1237 #define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
1239 #define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
1240 #define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
1242 #define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
1243 #define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
1245 #define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
1246 #define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
1248 #define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
1249 #define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
1251 #define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
1252 #define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
1254 #define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */
1255 #define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */
1257 #define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
1258 #define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
1260 #define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
1261 #define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
1263 #define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
1264 #define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
1266 #define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
1267 #define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
1269 /** \brief DCB Debug Core Register Selector Register Definitions */
1270 #define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
1271 #define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
1273 #define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
1274 #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
1276 /** \brief DCB Debug Core Register Data Register Definitions */
1277 #define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
1278 #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
1280 /** \brief DCB Debug Exception and Monitor Control Register Definitions */
1281 #define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
1282 #define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
1284 #define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */
1285 #define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */
1287 #define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */
1288 #define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */
1290 #define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */
1291 #define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */
1293 #define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */
1294 #define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */
1296 #define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
1297 #define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
1299 #define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */
1300 #define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
1302 #define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */
1303 #define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
1305 #define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */
1306 #define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */
1308 #define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */
1309 #define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */
1311 #define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */
1312 #define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
1314 #define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */
1315 #define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
1317 #define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
1318 #define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
1320 /*@} end of group CMSIS_DCB */
1324 \ingroup CMSIS_core_register
1325 \defgroup CMSIS_core_bitfield Core register bit field macros
1326 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
1331 \brief Mask and shift a bit field value for use in a register bit range.
1332 \param[in] field Name of the register bit field.
1333 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
1334 \return Masked and shifted value.
1336 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1339 \brief Mask and shift a register value to extract a bit filed value.
1340 \param[in] field Name of the register bit field.
1341 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
1342 \return Masked and shifted bit field value.
1344 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1346 /*@} end of group CMSIS_core_bitfield */
1350 \ingroup CMSIS_core_register
1351 \defgroup CMSIS_core_base Core Definitions
1352 \brief Definitions for base addresses, unions, and structures.
1356 /* Memory mapping of Core Hardware */
1357 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1358 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1359 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1360 #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */
1361 #define DCB_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1362 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1363 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1364 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1366 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
1367 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1368 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1369 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1370 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1371 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1372 #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */
1373 #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
1375 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1376 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1377 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1384 \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases
1385 \brief Alias definitions present for backwards compatibility for deprecated symbols.
1389 #ifndef CMSIS_DISABLE_DEPRECATED
1391 #define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos
1392 #define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk
1394 /* deprecated, CMSIS_5 backward compatibility */
1397 __IOM uint32_t DHCSR;
1398 __OM uint32_t DCRSR;
1399 __IOM uint32_t DCRDR;
1400 __IOM uint32_t DEMCR;
1403 /* Debug Halting Control and Status Register Definitions */
1404 #define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos
1405 #define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk
1407 #define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos
1408 #define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk
1410 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos
1411 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk
1413 #define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos
1414 #define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk
1416 #define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos
1417 #define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk
1419 #define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos
1420 #define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk
1422 #define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos
1423 #define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk
1425 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos DCB_DHCSR_C_SNAPSTALL_Pos
1426 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk DCB_DHCSR_C_SNAPSTALL_Msk
1428 #define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos
1429 #define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk
1431 #define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos
1432 #define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk
1434 #define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos
1435 #define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk
1437 #define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos
1438 #define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk
1440 /* Debug Core Register Selector Register Definitions */
1441 #define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos
1442 #define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk
1444 #define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos
1445 #define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk
1447 /* Debug Exception and Monitor Control Register Definitions */
1448 #define CoreDebug_DEMCR_TRCENA_Pos DCB_DEMCR_TRCENA_Pos
1449 #define CoreDebug_DEMCR_TRCENA_Msk DCB_DEMCR_TRCENA_Msk
1451 #define CoreDebug_DEMCR_MON_REQ_Pos DCB_DEMCR_MON_REQ_Pos
1452 #define CoreDebug_DEMCR_MON_REQ_Msk DCB_DEMCR_MON_REQ_Msk
1454 #define CoreDebug_DEMCR_MON_STEP_Pos DCB_DEMCR_MON_STEP_Pos
1455 #define CoreDebug_DEMCR_MON_STEP_Msk DCB_DEMCR_MON_STEP_Msk
1457 #define CoreDebug_DEMCR_MON_PEND_Pos DCB_DEMCR_MON_PEND_Pos
1458 #define CoreDebug_DEMCR_MON_PEND_Msk DCB_DEMCR_MON_PEND_Msk
1460 #define CoreDebug_DEMCR_MON_EN_Pos DCB_DEMCR_MON_EN_Pos
1461 #define CoreDebug_DEMCR_MON_EN_Msk DCB_DEMCR_MON_EN_Msk
1463 #define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos
1464 #define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk
1466 #define CoreDebug_DEMCR_VC_INTERR_Pos DCB_DEMCR_VC_INTERR_Pos
1467 #define CoreDebug_DEMCR_VC_INTERR_Msk DCB_DEMCR_VC_INTERR_Msk
1469 #define CoreDebug_DEMCR_VC_BUSERR_Pos DCB_DEMCR_VC_BUSERR_Pos
1470 #define CoreDebug_DEMCR_VC_BUSERR_Msk DCB_DEMCR_VC_BUSERR_Msk
1472 #define CoreDebug_DEMCR_VC_STATERR_Pos DCB_DEMCR_VC_STATERR_Pos
1473 #define CoreDebug_DEMCR_VC_STATERR_Msk DCB_DEMCR_VC_STATERR_Msk
1475 #define CoreDebug_DEMCR_VC_CHKERR_Pos DCB_DEMCR_VC_CHKERR_Pos
1476 #define CoreDebug_DEMCR_VC_CHKERR_Msk DCB_DEMCR_VC_CHKERR_Msk
1478 #define CoreDebug_DEMCR_VC_NOCPERR_Pos DCB_DEMCR_VC_NOCPERR_Pos
1479 #define CoreDebug_DEMCR_VC_NOCPERR_Msk DCB_DEMCR_VC_NOCPERR_Msk
1481 #define CoreDebug_DEMCR_VC_MMERR_Pos DCB_DEMCR_VC_MMERR_Pos
1482 #define CoreDebug_DEMCR_VC_MMERR_Msk DCB_DEMCR_VC_MMERR_Msk
1484 #define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos
1485 #define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk
1487 #define CoreDebug ((CoreDebug_Type *) DCB_BASE)
1489 #endif // CMSIS_DISABLE_DEPRECATED
1494 /*******************************************************************************
1495 * Hardware Abstraction Layer
1496 Core Function Interface contains:
1497 - Core NVIC Functions
1498 - Core SysTick Functions
1499 - Core Debug Functions
1500 - Core Register Access Functions
1501 ******************************************************************************/
1503 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1508 /* ########################## NVIC functions #################################### */
1510 \ingroup CMSIS_Core_FunctionInterface
1511 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1512 \brief Functions that manage interrupts and exceptions via the NVIC.
1516 #ifdef CMSIS_NVIC_VIRTUAL
1517 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1518 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1520 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1522 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
1523 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
1524 #define NVIC_EnableIRQ __NVIC_EnableIRQ
1525 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1526 #define NVIC_DisableIRQ __NVIC_DisableIRQ
1527 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1528 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1529 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1530 #define NVIC_GetActive __NVIC_GetActive
1531 #define NVIC_SetPriority __NVIC_SetPriority
1532 #define NVIC_GetPriority __NVIC_GetPriority
1533 #define NVIC_SystemReset __NVIC_SystemReset
1534 #endif /* CMSIS_NVIC_VIRTUAL */
1536 #ifdef CMSIS_VECTAB_VIRTUAL
1537 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1538 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1540 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1542 #define NVIC_SetVector __NVIC_SetVector
1543 #define NVIC_GetVector __NVIC_GetVector
1544 #endif /* (CMSIS_VECTAB_VIRTUAL) */
1546 #define NVIC_USER_IRQ_OFFSET 16
1549 /* The following EXC_RETURN values are saved the LR on exception entry */
1550 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
1551 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
1552 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
1556 \brief Set Priority Grouping
1557 \details Sets the priority grouping field using the required unlock sequence.
1558 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1559 Only values from 0..7 are used.
1560 In case of a conflict between priority grouping and available
1561 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1562 \param [in] PriorityGroup Priority grouping field.
1564 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1567 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1569 reg_value = SCB->AIRCR; /* read old register configuration */
1570 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
1571 reg_value = (reg_value |
1572 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1573 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
1574 SCB->AIRCR = reg_value;
1579 \brief Get Priority Grouping
1580 \details Reads the priority grouping field from the NVIC Interrupt Controller.
1581 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1583 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
1585 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1590 \brief Enable Interrupt
1591 \details Enables a device specific interrupt in the NVIC interrupt controller.
1592 \param [in] IRQn Device specific interrupt number.
1593 \note IRQn must not be negative.
1595 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
1597 if ((int32_t)(IRQn) >= 0)
1599 __COMPILER_BARRIER();
1600 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1601 __COMPILER_BARRIER();
1607 \brief Get Interrupt Enable status
1608 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
1609 \param [in] IRQn Device specific interrupt number.
1610 \return 0 Interrupt is not enabled.
1611 \return 1 Interrupt is enabled.
1612 \note IRQn must not be negative.
1614 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
1616 if ((int32_t)(IRQn) >= 0)
1618 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1628 \brief Disable Interrupt
1629 \details Disables a device specific interrupt in the NVIC interrupt controller.
1630 \param [in] IRQn Device specific interrupt number.
1631 \note IRQn must not be negative.
1633 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
1635 if ((int32_t)(IRQn) >= 0)
1637 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1645 \brief Get Pending Interrupt
1646 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
1647 \param [in] IRQn Device specific interrupt number.
1648 \return 0 Interrupt status is not pending.
1649 \return 1 Interrupt status is pending.
1650 \note IRQn must not be negative.
1652 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
1654 if ((int32_t)(IRQn) >= 0)
1656 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1666 \brief Set Pending Interrupt
1667 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
1668 \param [in] IRQn Device specific interrupt number.
1669 \note IRQn must not be negative.
1671 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
1673 if ((int32_t)(IRQn) >= 0)
1675 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1681 \brief Clear Pending Interrupt
1682 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
1683 \param [in] IRQn Device specific interrupt number.
1684 \note IRQn must not be negative.
1686 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1688 if ((int32_t)(IRQn) >= 0)
1690 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1696 \brief Get Active Interrupt
1697 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
1698 \param [in] IRQn Device specific interrupt number.
1699 \return 0 Interrupt status is not active.
1700 \return 1 Interrupt status is active.
1701 \note IRQn must not be negative.
1703 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
1705 if ((int32_t)(IRQn) >= 0)
1707 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1717 \brief Set Interrupt Priority
1718 \details Sets the priority of a device specific interrupt or a processor exception.
1719 The interrupt number can be positive to specify a device specific interrupt,
1720 or negative to specify a processor exception.
1721 \param [in] IRQn Interrupt number.
1722 \param [in] priority Priority to set.
1723 \note The priority cannot be set for every processor exception.
1725 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1727 if ((int32_t)(IRQn) >= 0)
1729 NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1733 SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1739 \brief Get Interrupt Priority
1740 \details Reads the priority of a device specific interrupt or a processor exception.
1741 The interrupt number can be positive to specify a device specific interrupt,
1742 or negative to specify a processor exception.
1743 \param [in] IRQn Interrupt number.
1744 \return Interrupt Priority.
1745 Value is aligned automatically to the implemented priority bits of the microcontroller.
1747 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
1750 if ((int32_t)(IRQn) >= 0)
1752 return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
1756 return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
1762 \brief Encode Priority
1763 \details Encodes the priority for an interrupt with the given priority group,
1764 preemptive priority value, and subpriority value.
1765 In case of a conflict between priority grouping and available
1766 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1767 \param [in] PriorityGroup Used priority group.
1768 \param [in] PreemptPriority Preemptive priority value (starting from 0).
1769 \param [in] SubPriority Subpriority value (starting from 0).
1770 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
1772 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1774 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1775 uint32_t PreemptPriorityBits;
1776 uint32_t SubPriorityBits;
1778 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1779 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1782 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1783 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1789 \brief Decode Priority
1790 \details Decodes an interrupt priority value with a given priority group to
1791 preemptive priority value and subpriority value.
1792 In case of a conflict between priority grouping and available
1793 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
1794 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
1795 \param [in] PriorityGroup Used priority group.
1796 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
1797 \param [out] pSubPriority Subpriority value (starting from 0).
1799 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
1801 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1802 uint32_t PreemptPriorityBits;
1803 uint32_t SubPriorityBits;
1805 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1806 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1808 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1809 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1814 \brief Set Interrupt Vector
1815 \details Sets an interrupt vector in SRAM based interrupt vector table.
1816 The interrupt number can be positive to specify a device specific interrupt,
1817 or negative to specify a processor exception.
1818 VTOR must been relocated to SRAM before.
1819 \param [in] IRQn Interrupt number
1820 \param [in] vector Address of interrupt handler function
1822 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
1824 uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR);
1825 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
1826 /* ARM Application Note 321 states that the M3 does not require the architectural barrier */
1831 \brief Get Interrupt Vector
1832 \details Reads an interrupt vector from interrupt vector table.
1833 The interrupt number can be positive to specify a device specific interrupt,
1834 or negative to specify a processor exception.
1835 \param [in] IRQn Interrupt number.
1836 \return Address of interrupt handler function
1838 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
1840 uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR);
1841 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
1847 \details Initiates a system reset request to reset the MCU.
1849 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
1851 __DSB(); /* Ensure all outstanding memory accesses included
1852 buffered write are completed before reset */
1853 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1854 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1855 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
1856 __DSB(); /* Ensure completion of memory access */
1858 for(;;) /* wait until reset */
1864 /*@} end of CMSIS_Core_NVICFunctions */
1867 /* ########################## MPU functions #################################### */
1869 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1871 #include "m-profile/armv7m_mpu.h"
1876 /* ########################## FPU functions #################################### */
1878 \ingroup CMSIS_Core_FunctionInterface
1879 \defgroup CMSIS_Core_FpuFunctions FPU Functions
1880 \brief Function that provides FPU type.
1886 \details returns the FPU type
1889 - \b 1: Single precision FPU
1890 - \b 2: Double + Single precision FPU
1892 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
1894 return 0U; /* No FPU */
1897 /*@} end of CMSIS_Core_FpuFunctions */
1900 /* ################################## SysTick function ############################################ */
1902 \ingroup CMSIS_Core_FunctionInterface
1903 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
1904 \brief Functions that configure the System.
1908 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
1911 \brief System Tick Configuration
1912 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
1913 Counter is in free running mode to generate periodic interrupts.
1914 \param [in] ticks Number of ticks between two interrupts.
1915 \return 0 Function succeeded.
1916 \return 1 Function failed.
1917 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1918 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
1919 must contain a vendor-specific implementation of this function.
1921 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1923 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
1925 return (1UL); /* Reload value impossible */
1928 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
1929 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
1930 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
1931 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1932 SysTick_CTRL_TICKINT_Msk |
1933 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1934 return (0UL); /* Function successful */
1939 /*@} end of CMSIS_Core_SysTickFunctions */
1943 /* ##################################### Debug In/Output function ########################################### */
1945 \ingroup CMSIS_Core_FunctionInterface
1946 \defgroup CMSIS_core_DebugFunctions ITM Functions
1947 \brief Functions that access the ITM debug interface.
1951 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
1952 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
1956 \brief ITM Send Character
1957 \details Transmits a character via the ITM channel 0, and
1958 \li Just returns when no debugger is connected that has booked the output.
1959 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
1960 \param [in] ch Character to transmit.
1961 \returns Character to transmit.
1963 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
1965 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
1966 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
1968 while (ITM->PORT[0U].u32 == 0UL)
1972 ITM->PORT[0U].u8 = (uint8_t)ch;
1979 \brief ITM Receive Character
1980 \details Inputs a character via the external variable \ref ITM_RxBuffer.
1981 \return Received character.
1982 \return -1 No character pending.
1984 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
1986 int32_t ch = -1; /* no character available */
1988 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
1991 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
1999 \brief ITM Check Character
2000 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
2001 \return 0 No character available.
2002 \return 1 Character available.
2004 __STATIC_INLINE int32_t ITM_CheckChar (void)
2007 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
2009 return (0); /* no character available */
2013 return (1); /* character available */
2017 /*@} end of CMSIS_core_DebugFunctions */
2026 #endif /* __CORE_SC300_H_DEPENDANT */
2028 #endif /* __CMSIS_GENERIC */
begriffs.com / projects / cmsis / blob