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 130   <div class="summary">
 131 <a href="#define-members">Macros</a>  </div>
 132   <div class="headertitle"><div class="title">Define values<div class="ingroups"><a class="el" href="group__mpu__functions.html">MPU Functions for Armv6-M/v7-M</a></div></div></div>
 133 </div><!--header-->
 134 <div class="contents">
 135
 136 <p>Define values for MPU region setup.
 137 <a href="#details">More...</a></p>
 138 <table class="memberdecls">
 139 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a>
 140 Macros</h2></td></tr>
 141 <tr class="memitem:gadb0a92c0928c113120567e85ff1ba05c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__defines.html#gadb0a92c0928c113120567e85ff1ba05c">ARM_MPU_REGION_SIZE_xxx</a></td></tr>
 142 <tr class="memdesc:gadb0a92c0928c113120567e85ff1ba05c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Size values of a MPU region (in RASR field)  <br /></td></tr>
 143 <tr class="separator:gadb0a92c0928c113120567e85ff1ba05c"><td class="memSeparator" colspan="2">&#160;</td></tr>
 144 <tr class="memitem:gabc4788126d7798469cb862a08d3050cc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__defines.html#gabc4788126d7798469cb862a08d3050cc">ARM_MPU_AP_xxx</a></td></tr>
 145 <tr class="memdesc:gabc4788126d7798469cb862a08d3050cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Values for MPU region access permissions (in RASR field)  <br /></td></tr>
 146 <tr class="separator:gabc4788126d7798469cb862a08d3050cc"><td class="memSeparator" colspan="2">&#160;</td></tr>
 147 <tr class="memitem:ga71d41084e984be70a23cb640fd89d1e2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__defines.html#ga71d41084e984be70a23cb640fd89d1e2">ARM_MPU_ACCESS_xxx</a></td></tr>
 148 <tr class="memdesc:ga71d41084e984be70a23cb640fd89d1e2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Values for MPU region access attributes (in RASR field)  <br /></td></tr>
 149 <tr class="separator:ga71d41084e984be70a23cb640fd89d1e2"><td class="memSeparator" colspan="2">&#160;</td></tr>
 150 <tr class="memitem:gab23596306119e7831847bd9683de3934"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__defines.html#gab23596306119e7831847bd9683de3934">ARM_MPU_CACHEP_xxx</a></td></tr>
 151 <tr class="memdesc:gab23596306119e7831847bd9683de3934"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cache policy values for MPU region access attributes (in RASR field)  <br /></td></tr>
 152 <tr class="separator:gab23596306119e7831847bd9683de3934"><td class="memSeparator" colspan="2">&#160;</td></tr>
 153 </table>
 154 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
 155 <p>Define values for MPU region setup. </p>
 156 <p><br  />
 157 </p>
 158 <p>The following define values are used with <a class="el" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a> to setup the <a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">RASR</a> value field in the MPU region.</p>
 159 <dl class="section see"><dt>See also</dt><dd><a class="el" href="structARM__MPU__Region__t.html" title="Setup information of a single MPU Region.">ARM_MPU_Region_t</a>, <a class="el" href="group__mpu__functions.html#ga16931f9ad84d7289e8218e169ae6db5d">ARM_MPU_SetRegion</a>, <a class="el" href="group__mpu__functions.html#ga042ba1a6a1a58795231459ac0410b809">ARM_MPU_SetRegionEx</a>. </dd></dl>
 160 <h2 class="groupheader">Macro Definition Documentation</h2>
 161 <a id="ga71d41084e984be70a23cb640fd89d1e2" name="ga71d41084e984be70a23cb640fd89d1e2"></a>
 162 <h2 class="memtitle"><span class="permalink"><a href="#ga71d41084e984be70a23cb640fd89d1e2">&#9670;&#160;</a></span>ARM_MPU_ACCESS_xxx</h2>
 163
 164 <div class="memitem">
 165 <div class="memproto">
 166       <table class="memname">
 167         <tr>
 168           <td class="memname">#define ARM_MPU_ACCESS_xxx</td>
 169         </tr>
 170       </table>
 171 </div><div class="memdoc">
 172
 173 <p>Values for MPU region access attributes (in RASR field) </p>
 174 <p>The following define values are used to compose the access attributes for an MPU region: </p><table class="markdownTable">
 175 <tr class="markdownTableHead">
 176 <th class="markdownTableHeadLeft">#define   </th><th class="markdownTableHeadLeft">TEX   </th><th class="markdownTableHeadLeft">Shareable   </th><th class="markdownTableHeadLeft">Cacheable   </th><th class="markdownTableHeadLeft">Bufferable   </th><th class="markdownTableHeadLeft">Description    </th></tr>
 177 <tr class="markdownTableRowOdd">
 178 <td class="markdownTableBodyLeft">ARM_MPU_ACCESS_ORDERED   </td><td class="markdownTableBodyLeft">000b   </td><td class="markdownTableBodyLeft">1   </td><td class="markdownTableBodyLeft">0   </td><td class="markdownTableBodyLeft">0   </td><td class="markdownTableBodyLeft">Strongly ordered memory    </td></tr>
 179 <tr class="markdownTableRowEven">
 180 <td class="markdownTableBodyLeft">ARM_MPU_ACCESS_DEVICE(S)   </td><td class="markdownTableBodyLeft">0s0b   </td><td class="markdownTableBodyLeft">S   </td><td class="markdownTableBodyLeft">0   </td><td class="markdownTableBodyLeft">S   </td><td class="markdownTableBodyLeft">Memory mapped peripheral device, shared (S=1) or non-shared (S=0)    </td></tr>
 181 <tr class="markdownTableRowOdd">
 182 <td class="markdownTableBodyLeft">ARM_MPU_ACCESS_NORMAL(O,I,S)   </td><td class="markdownTableBodyLeft">1BBb   </td><td class="markdownTableBodyLeft">S   </td><td class="markdownTableBodyLeft">A   </td><td class="markdownTableBodyLeft">A   </td><td class="markdownTableBodyLeft">Normal memory, with outer/inner cache policy (O/I=<a class="el" href="group__mpu__defines.html#gab23596306119e7831847bd9683de3934">ARM_MPU_CACHEP_xxx</a>, shared (S=1) or non-share (S=0)   </td></tr>
 183 </table>
 184
 185 </div>
 186 </div>
 187 <a id="gabc4788126d7798469cb862a08d3050cc" name="gabc4788126d7798469cb862a08d3050cc"></a>
 188 <h2 class="memtitle"><span class="permalink"><a href="#gabc4788126d7798469cb862a08d3050cc">&#9670;&#160;</a></span>ARM_MPU_AP_xxx</h2>
 189
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 193         <tr>
 194           <td class="memname">#define ARM_MPU_AP_xxx</td>
 195         </tr>
 196       </table>
 197 </div><div class="memdoc">
 198
 199 <p>Values for MPU region access permissions (in RASR field) </p>
 200 <p>The following define values are used to compose the access permission for an MPU region: </p><table class="markdownTable">
 201 <tr class="markdownTableHead">
 202 <th class="markdownTableHeadLeft">#define   </th><th class="markdownTableHeadLeft">Value   </th><th class="markdownTableHeadLeft">Access permissions    </th></tr>
 203 <tr class="markdownTableRowOdd">
 204 <td class="markdownTableBodyLeft">ARM_MPU_AP_NONE   </td><td class="markdownTableBodyLeft">0x0U   </td><td class="markdownTableBodyLeft">None: any access generates a permission fault.    </td></tr>
 205 <tr class="markdownTableRowEven">
 206 <td class="markdownTableBodyLeft">ARM_MPU_AP_PRIV   </td><td class="markdownTableBodyLeft">0x1U   </td><td class="markdownTableBodyLeft">Privileged Read/Write: privileged access only; any unprivileged access generates a permission fault.    </td></tr>
 207 <tr class="markdownTableRowOdd">
 208 <td class="markdownTableBodyLeft">ARM_MPU_AP_URO   </td><td class="markdownTableBodyLeft">0x2U   </td><td class="markdownTableBodyLeft">Privileged Read/Write; Unprivileged Read-only: any unprivileged write generates a permission fault.    </td></tr>
 209 <tr class="markdownTableRowEven">
 210 <td class="markdownTableBodyLeft">ARM_MPU_AP_FULL   </td><td class="markdownTableBodyLeft">0x3U   </td><td class="markdownTableBodyLeft">Privileged Read/Write. Unprivileged Read/Write: full access, permission faults are never generated.    </td></tr>
 211 <tr class="markdownTableRowOdd">
 212 <td class="markdownTableBodyLeft">ARM_MPU_AP_PRO   </td><td class="markdownTableBodyLeft">0x5U   </td><td class="markdownTableBodyLeft">Privileged Read-only: any unprivileged access or privileged write generates a permission fault.    </td></tr>
 213 <tr class="markdownTableRowEven">
 214 <td class="markdownTableBodyLeft">ARM_MPU_AP_RO   </td><td class="markdownTableBodyLeft">0x6U   </td><td class="markdownTableBodyLeft">Privileged and Unprivileged Read-only: any write generates a permission fault.   </td></tr>
 215 </table>
 216
 217 </div>
 218 </div>
 219 <a id="gab23596306119e7831847bd9683de3934" name="gab23596306119e7831847bd9683de3934"></a>
 220 <h2 class="memtitle"><span class="permalink"><a href="#gab23596306119e7831847bd9683de3934">&#9670;&#160;</a></span>ARM_MPU_CACHEP_xxx</h2>
 221
 222 <div class="memitem">
 223 <div class="memproto">
 224       <table class="memname">
 225         <tr>
 226           <td class="memname">#define ARM_MPU_CACHEP_xxx</td>
 227         </tr>
 228       </table>
 229 </div><div class="memdoc">
 230
 231 <p>Cache policy values for MPU region access attributes (in RASR field) </p>
 232 <p>The following define values are used to compose the cacheability flags within the access attributes for an MPU region: </p><table class="markdownTable">
 233 <tr class="markdownTableHead">
 234 <th class="markdownTableHeadLeft">#define   </th><th class="markdownTableHeadLeft">Value   </th><th class="markdownTableHeadLeft">Cacheability policy    </th></tr>
 235 <tr class="markdownTableRowOdd">
 236 <td class="markdownTableBodyLeft">ARM_MPU_CACHEP_NOCACHE   </td><td class="markdownTableBodyLeft">00b   </td><td class="markdownTableBodyLeft">Non-cacheable    </td></tr>
 237 <tr class="markdownTableRowEven">
 238 <td class="markdownTableBodyLeft">ARM_MPU_CACHEP_WB_WRA   </td><td class="markdownTableBodyLeft">01b   </td><td class="markdownTableBodyLeft">Write-back, write and read allocate    </td></tr>
 239 <tr class="markdownTableRowOdd">
 240 <td class="markdownTableBodyLeft">ARM_MPU_CACHEP_WT_NWA   </td><td class="markdownTableBodyLeft">10b   </td><td class="markdownTableBodyLeft">Write-through, no write allocate    </td></tr>
 241 <tr class="markdownTableRowEven">
 242 <td class="markdownTableBodyLeft">ARM_MPU_CACHEP_WB_NWA   </td><td class="markdownTableBodyLeft">11b   </td><td class="markdownTableBodyLeft">Write-back, no write allocate   </td></tr>
 243 </table>
 244
 245 </div>
 246 </div>
 247 <a id="gadb0a92c0928c113120567e85ff1ba05c" name="gadb0a92c0928c113120567e85ff1ba05c"></a>
 248 <h2 class="memtitle"><span class="permalink"><a href="#gadb0a92c0928c113120567e85ff1ba05c">&#9670;&#160;</a></span>ARM_MPU_REGION_SIZE_xxx</h2>
 249
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 251 <div class="memproto">
 252       <table class="memname">
 253         <tr>
 254           <td class="memname">#define ARM_MPU_REGION_SIZE_xxx</td>
 255         </tr>
 256       </table>
 257 </div><div class="memdoc">
 258
 259 <p>Size values of a MPU region (in RASR field) </p>
 260 <p>The following define values are used to compose the size information for an MPU region:</p>
 261 <table class="markdownTable">
 262 <tr class="markdownTableHead">
 263 <th class="markdownTableHeadLeft">#define   </th><th class="markdownTableHeadLeft">Value   </th><th class="markdownTableHeadLeft">Description    </th></tr>
 264 <tr class="markdownTableRowOdd">
 265 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_32B   </td><td class="markdownTableBodyLeft">0x04U   </td><td class="markdownTableBodyLeft">Region size 32 Bytes    </td></tr>
 266 <tr class="markdownTableRowEven">
 267 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_64B   </td><td class="markdownTableBodyLeft">0x05U   </td><td class="markdownTableBodyLeft">Region size 64 Bytes    </td></tr>
 268 <tr class="markdownTableRowOdd">
 269 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_128B   </td><td class="markdownTableBodyLeft">0x06U   </td><td class="markdownTableBodyLeft">Region size 128 Bytes    </td></tr>
 270 <tr class="markdownTableRowEven">
 271 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_256B   </td><td class="markdownTableBodyLeft">0x07U   </td><td class="markdownTableBodyLeft">Region size 256 Bytes    </td></tr>
 272 <tr class="markdownTableRowOdd">
 273 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_512B   </td><td class="markdownTableBodyLeft">0x08U   </td><td class="markdownTableBodyLeft">Region size 512 Bytes    </td></tr>
 274 <tr class="markdownTableRowEven">
 275 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_1KB   </td><td class="markdownTableBodyLeft">0x09U   </td><td class="markdownTableBodyLeft">Region size 1 KByte    </td></tr>
 276 <tr class="markdownTableRowOdd">
 277 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_2KB   </td><td class="markdownTableBodyLeft">0x0AU   </td><td class="markdownTableBodyLeft">Region size 2 KBytes    </td></tr>
 278 <tr class="markdownTableRowEven">
 279 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_4KB   </td><td class="markdownTableBodyLeft">0x0BU   </td><td class="markdownTableBodyLeft">Region size 4 KBytes    </td></tr>
 280 <tr class="markdownTableRowOdd">
 281 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_8KB   </td><td class="markdownTableBodyLeft">0x0CU   </td><td class="markdownTableBodyLeft">Region size 8 KBytes    </td></tr>
 282 <tr class="markdownTableRowEven">
 283 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_16KB   </td><td class="markdownTableBodyLeft">0x0DU   </td><td class="markdownTableBodyLeft">Region size 16 KBytes    </td></tr>
 284 <tr class="markdownTableRowOdd">
 285 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_32KB   </td><td class="markdownTableBodyLeft">0x0EU   </td><td class="markdownTableBodyLeft">Region size 32 KBytes    </td></tr>
 286 <tr class="markdownTableRowEven">
 287 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_64KB   </td><td class="markdownTableBodyLeft">0x0FU   </td><td class="markdownTableBodyLeft">Region size 64 KBytes    </td></tr>
 288 <tr class="markdownTableRowOdd">
 289 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_128KB   </td><td class="markdownTableBodyLeft">0x10U   </td><td class="markdownTableBodyLeft">Region size 128 KBytes    </td></tr>
 290 <tr class="markdownTableRowEven">
 291 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_256KB   </td><td class="markdownTableBodyLeft">0x11U   </td><td class="markdownTableBodyLeft">Region size 256 KBytes    </td></tr>
 292 <tr class="markdownTableRowOdd">
 293 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_512KB   </td><td class="markdownTableBodyLeft">0x12U   </td><td class="markdownTableBodyLeft">Region size 512 KBytes    </td></tr>
 294 <tr class="markdownTableRowEven">
 295 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_1MB   </td><td class="markdownTableBodyLeft">0x13U   </td><td class="markdownTableBodyLeft">Region size 1 MByte    </td></tr>
 296 <tr class="markdownTableRowOdd">
 297 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_2MB   </td><td class="markdownTableBodyLeft">0x14U   </td><td class="markdownTableBodyLeft">Region size 2 MBytes    </td></tr>
 298 <tr class="markdownTableRowEven">
 299 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_4MB   </td><td class="markdownTableBodyLeft">0x15U   </td><td class="markdownTableBodyLeft">Region size 4 MBytes    </td></tr>
 300 <tr class="markdownTableRowOdd">
 301 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_8MB   </td><td class="markdownTableBodyLeft">0x16U   </td><td class="markdownTableBodyLeft">Region size 8 MBytes    </td></tr>
 302 <tr class="markdownTableRowEven">
 303 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_16MB   </td><td class="markdownTableBodyLeft">0x17U   </td><td class="markdownTableBodyLeft">Region size 16 MBytes    </td></tr>
 304 <tr class="markdownTableRowOdd">
 305 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_32MB   </td><td class="markdownTableBodyLeft">0x18U   </td><td class="markdownTableBodyLeft">Region size 32 MBytes    </td></tr>
 306 <tr class="markdownTableRowEven">
 307 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_64MB   </td><td class="markdownTableBodyLeft">0x19U   </td><td class="markdownTableBodyLeft">Region size 64 MBytes    </td></tr>
 308 <tr class="markdownTableRowOdd">
 309 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_128MB   </td><td class="markdownTableBodyLeft">0x1AU   </td><td class="markdownTableBodyLeft">Region size 128 MBytes    </td></tr>
 310 <tr class="markdownTableRowEven">
 311 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_256MB   </td><td class="markdownTableBodyLeft">0x1BU   </td><td class="markdownTableBodyLeft">Region size 256 MBytes    </td></tr>
 312 <tr class="markdownTableRowOdd">
 313 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_512MB   </td><td class="markdownTableBodyLeft">0x1CU   </td><td class="markdownTableBodyLeft">Region size 512 MBytes    </td></tr>
 314 <tr class="markdownTableRowEven">
 315 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_1GB   </td><td class="markdownTableBodyLeft">0x1DU   </td><td class="markdownTableBodyLeft">Region size 1 GByte    </td></tr>
 316 <tr class="markdownTableRowOdd">
 317 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_2GB   </td><td class="markdownTableBodyLeft">0x1EU   </td><td class="markdownTableBodyLeft">Region size 2 GBytes    </td></tr>
 318 <tr class="markdownTableRowEven">
 319 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_4GB   </td><td class="markdownTableBodyLeft">0x1FU   </td><td class="markdownTableBodyLeft">Region size 4 GBytes   </td></tr>
 320 </table>
 321
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