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 129 <div class="header">
 130   <div class="summary">
 131 <a href="#groups">Content</a> &#124;
 132 <a href="#nested-classes">Data Structures</a> &#124;
 133 <a href="#func-members">Functions</a>  </div>
 134   <div class="headertitle"><div class="title">Auxiliary Control Register (ACTLR)<div class="ingroups"><a class="el" href="group__CMSIS__core__register.html">Core Register Access</a></div></div></div>
 135 </div><!--header-->
 136 <div class="contents">
 137
 138 <p>The ACTLR provides IMPLEMENTATION DEFINED configuration and control options.
 139 <a href="#details">More...</a></p>
 140 <table class="memberdecls">
 141 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="groups" name="groups"></a>
 142 Content</h2></td></tr>
 143 <tr class="memitem:group__CMSIS__ACTLR__BITS"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html">ACTLR Bits</a></td></tr>
 144 <tr class="memdesc:group__CMSIS__ACTLR__BITS"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit position and mask macros. <br /></td></tr>
 145 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
 146 </table><table class="memberdecls">
 147 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="nested-classes" name="nested-classes"></a>
 148 Data Structures</h2></td></tr>
 149 <tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionACTLR__Type.html">ACTLR_Type</a></td></tr>
 150 <tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit field declaration for ACTLR layout.  <a href="unionACTLR__Type.html#details">More...</a><br /></td></tr>
 151 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
 152 </table><table class="memberdecls">
 153 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a>
 154 Functions</h2></td></tr>
 155 <tr class="memitem:gabe7491eac1652f740050bd905baea187"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armclang__a_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR.html#gabe7491eac1652f740050bd905baea187">__set_ACTRL</a> (uint32_t actrl)</td></tr>
 156 <tr class="memdesc:gabe7491eac1652f740050bd905baea187"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set ACTRL.  <br /></td></tr>
 157 <tr class="separator:gabe7491eac1652f740050bd905baea187"><td class="memSeparator" colspan="2">&#160;</td></tr>
 158 <tr class="memitem:gae75d412bfd6fe873ade00b021aefcab3"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armclang__a_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR.html#gae75d412bfd6fe873ade00b021aefcab3">__get_ACTLR</a> (void)</td></tr>
 159 <tr class="memdesc:gae75d412bfd6fe873ade00b021aefcab3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get ACTLR.  <br /></td></tr>
 160 <tr class="separator:gae75d412bfd6fe873ade00b021aefcab3"><td class="memSeparator" colspan="2">&#160;</td></tr>
 161 </table>
 162 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
 163 <p>The ACTLR provides IMPLEMENTATION DEFINED configuration and control options. </p>
 164 <p>The ACTLR characteristics are differs between various Armv7-A implementations.</p>
 165 <p><b>Cortex-A5</b></p>
 166 <table class="markdownTable">
 167 <tr class="markdownTableHead">
 168 <th class="markdownTableHeadLeft">Bits   </th><th class="markdownTableHeadLeft">Name   </th><th class="markdownTableHeadLeft">Function    </th></tr>
 169 <tr class="markdownTableRowOdd">
 170 <td class="markdownTableBodyLeft">[31:29]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
 171 <tr class="markdownTableRowEven">
 172 <td class="markdownTableBodyLeft">[28]   </td><td class="markdownTableBodyLeft">DBDI   </td><td class="markdownTableBodyLeft">Disable Branch Dual Issue    </td></tr>
 173 <tr class="markdownTableRowOdd">
 174 <td class="markdownTableBodyLeft">[27:19]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
 175 <tr class="markdownTableRowEven">
 176 <td class="markdownTableBodyLeft">[18]   </td><td class="markdownTableBodyLeft">BTDIS   </td><td class="markdownTableBodyLeft">Disable indirect Branch Target Address Cache (BTAC).    </td></tr>
 177 <tr class="markdownTableRowOdd">
 178 <td class="markdownTableBodyLeft">[17]   </td><td class="markdownTableBodyLeft">RSDIS   </td><td class="markdownTableBodyLeft">Disable return stack operation.    </td></tr>
 179 <tr class="markdownTableRowEven">
 180 <td class="markdownTableBodyLeft">[16:15]   </td><td class="markdownTableBodyLeft">BP   </td><td class="markdownTableBodyLeft">Branch prediction policy.    </td></tr>
 181 <tr class="markdownTableRowOdd">
 182 <td class="markdownTableBodyLeft">[14:13]   </td><td class="markdownTableBodyLeft">L1PCTL   </td><td class="markdownTableBodyLeft">L1 Data prefetch control.    </td></tr>
 183 <tr class="markdownTableRowEven">
 184 <td class="markdownTableBodyLeft">[12]   </td><td class="markdownTableBodyLeft">RADIS   </td><td class="markdownTableBodyLeft">Disable Data Cache read-allocate mode.    </td></tr>
 185 <tr class="markdownTableRowOdd">
 186 <td class="markdownTableBodyLeft">[11]   </td><td class="markdownTableBodyLeft">DWBST   </td><td class="markdownTableBodyLeft">Disable AXI data write bursts to Normal memory.    </td></tr>
 187 <tr class="markdownTableRowEven">
 188 <td class="markdownTableBodyLeft">[10]   </td><td class="markdownTableBodyLeft">DODMBS   </td><td class="markdownTableBodyLeft">Disable optimized data memory barrier behavior.    </td></tr>
 189 <tr class="markdownTableRowOdd">
 190 <td class="markdownTableBodyLeft">[9:8]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
 191 <tr class="markdownTableRowEven">
 192 <td class="markdownTableBodyLeft">[7]   </td><td class="markdownTableBodyLeft">EXCL   </td><td class="markdownTableBodyLeft">Exclusive L1/L2 cache control.    </td></tr>
 193 <tr class="markdownTableRowOdd">
 194 <td class="markdownTableBodyLeft">[6]   </td><td class="markdownTableBodyLeft">SMP   </td><td class="markdownTableBodyLeft">Enables coherent requests to the processor.    </td></tr>
 195 <tr class="markdownTableRowEven">
 196 <td class="markdownTableBodyLeft">[5:1]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
 197 <tr class="markdownTableRowOdd">
 198 <td class="markdownTableBodyLeft">[0]   </td><td class="markdownTableBodyLeft">FW   </td><td class="markdownTableBodyLeft">Cache and TLB maintenance broadcast.   </td></tr>
 199 </table>
 200 <p><b>Cortex-A7</b></p>
 201 <table class="markdownTable">
 202 <tr class="markdownTableHead">
 203 <th class="markdownTableHeadLeft">Bits   </th><th class="markdownTableHeadLeft">Name   </th><th class="markdownTableHeadLeft">Function    </th></tr>
 204 <tr class="markdownTableRowOdd">
 205 <td class="markdownTableBodyLeft">[31:29]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
 206 <tr class="markdownTableRowEven">
 207 <td class="markdownTableBodyLeft">[28]   </td><td class="markdownTableBodyLeft">DDI   </td><td class="markdownTableBodyLeft">Disable Dual Issue    </td></tr>
 208 <tr class="markdownTableRowOdd">
 209 <td class="markdownTableBodyLeft">[27:16]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
 210 <tr class="markdownTableRowEven">
 211 <td class="markdownTableBodyLeft">[15]   </td><td class="markdownTableBodyLeft">DDVM   </td><td class="markdownTableBodyLeft">Disable Distributed Virtual Memory transactions.    </td></tr>
 212 <tr class="markdownTableRowOdd">
 213 <td class="markdownTableBodyLeft">[14:13]   </td><td class="markdownTableBodyLeft">L1PCTL   </td><td class="markdownTableBodyLeft">L1 Data prefetch control.    </td></tr>
 214 <tr class="markdownTableRowEven">
 215 <td class="markdownTableBodyLeft">[12]   </td><td class="markdownTableBodyLeft">L1RADIS   </td><td class="markdownTableBodyLeft">L1 Data Cache read-allocate mode disable.    </td></tr>
 216 <tr class="markdownTableRowOdd">
 217 <td class="markdownTableBodyLeft">[11]   </td><td class="markdownTableBodyLeft">L2RADIS   </td><td class="markdownTableBodyLeft">L2 Data Cache read-allocate mode disable.    </td></tr>
 218 <tr class="markdownTableRowEven">
 219 <td class="markdownTableBodyLeft">[10]   </td><td class="markdownTableBodyLeft">DODMBS   </td><td class="markdownTableBodyLeft">Disable optimized data memory barrier behavior.    </td></tr>
 220 <tr class="markdownTableRowOdd">
 221 <td class="markdownTableBodyLeft">[9:7]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
 222 <tr class="markdownTableRowEven">
 223 <td class="markdownTableBodyLeft">[6]   </td><td class="markdownTableBodyLeft">SMP   </td><td class="markdownTableBodyLeft">Enables coherent requests to the processor.    </td></tr>
 224 <tr class="markdownTableRowOdd">
 225 <td class="markdownTableBodyLeft">[5:0]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.   </td></tr>
 226 </table>
 227 <p><b>Cortex-A9</b></p>
 228 <table class="markdownTable">
 229 <tr class="markdownTableHead">
 230 <th class="markdownTableHeadLeft">Bits   </th><th class="markdownTableHeadLeft">Name   </th><th class="markdownTableHeadLeft">Function    </th></tr>
 231 <tr class="markdownTableRowOdd">
 232 <td class="markdownTableBodyLeft">[31:10]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
 233 <tr class="markdownTableRowEven">
 234 <td class="markdownTableBodyLeft">[9]   </td><td class="markdownTableBodyLeft">PARITY   </td><td class="markdownTableBodyLeft">Support for parity checking, if implemented.    </td></tr>
 235 <tr class="markdownTableRowOdd">
 236 <td class="markdownTableBodyLeft">[8]   </td><td class="markdownTableBodyLeft">AOW   </td><td class="markdownTableBodyLeft">Enable allocation in one cache way only.    </td></tr>
 237 <tr class="markdownTableRowEven">
 238 <td class="markdownTableBodyLeft">[7]   </td><td class="markdownTableBodyLeft">EXCL   </td><td class="markdownTableBodyLeft">Exclusive L1/L2 cache control.    </td></tr>
 239 <tr class="markdownTableRowOdd">
 240 <td class="markdownTableBodyLeft">[6]   </td><td class="markdownTableBodyLeft">SMP   </td><td class="markdownTableBodyLeft">Enables coherent requests to the processor.    </td></tr>
 241 <tr class="markdownTableRowEven">
 242 <td class="markdownTableBodyLeft">[5:4]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
 243 <tr class="markdownTableRowOdd">
 244 <td class="markdownTableBodyLeft">[3]   </td><td class="markdownTableBodyLeft">WFLZM   </td><td class="markdownTableBodyLeft">Enable write full line of zeros modea.    </td></tr>
 245 <tr class="markdownTableRowEven">
 246 <td class="markdownTableBodyLeft">[2]   </td><td class="markdownTableBodyLeft">L1PE   </td><td class="markdownTableBodyLeft">Dside prefetch.    </td></tr>
 247 <tr class="markdownTableRowOdd">
 248 <td class="markdownTableBodyLeft">[1]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
 249 <tr class="markdownTableRowEven">
 250 <td class="markdownTableBodyLeft">[0]   </td><td class="markdownTableBodyLeft">FW   </td><td class="markdownTableBodyLeft">Cache and TLB maintenance broadcast.   </td></tr>
 251 </table>
 252 <p>Consider using <a class="el" href="group__CMSIS__ACTLR.html#gae75d412bfd6fe873ade00b021aefcab3">__get_ACTLR</a> and <a class="el" href="group__CMSIS__ACTLR.html#gabe7491eac1652f740050bd905baea187">__set_ACTRL</a> to access ACTRL register. </p>
 253 <h2 class="groupheader">Function Documentation</h2>
 254 <a id="gae75d412bfd6fe873ade00b021aefcab3" name="gae75d412bfd6fe873ade00b021aefcab3"></a>
 255 <h2 class="memtitle"><span class="permalink"><a href="#gae75d412bfd6fe873ade00b021aefcab3">&#9670;&#160;</a></span>__get_ACTLR()</h2>
 256
 257 <div class="memitem">
 258 <div class="memproto">
 259       <table class="memname">
 260         <tr>
 261           <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t __get_ACTLR </td>
 262           <td>(</td>
 263           <td class="paramtype">void&#160;</td>
 264           <td class="paramname"></td><td>)</td>
 265           <td></td>
 266         </tr>
 267       </table>
 268 </div><div class="memdoc">
 269
 270 <p>Get ACTLR. </p>
 271 <dl class="section return"><dt>Returns</dt><dd>Auxiliary Control register value</dd></dl>
 272 <p>This function returns the value of the <a class="el" href="group__CMSIS__ACTLR.html">Auxiliary Control Register (ACTLR)</a>. </p>
 273
 274 </div>
 275 </div>
 276 <a id="gabe7491eac1652f740050bd905baea187" name="gabe7491eac1652f740050bd905baea187"></a>
 277 <h2 class="memtitle"><span class="permalink"><a href="#gabe7491eac1652f740050bd905baea187">&#9670;&#160;</a></span>__set_ACTRL()</h2>
 278
 279 <div class="memitem">
 280 <div class="memproto">
 281       <table class="memname">
 282         <tr>
 283           <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void __set_ACTRL </td>
 284           <td>(</td>
 285           <td class="paramtype">uint32_t&#160;</td>
 286           <td class="paramname"><em>actrl</em></td><td>)</td>
 287           <td></td>
 288         </tr>
 289       </table>
 290 </div><div class="memdoc">
 291
 292 <p>Set ACTRL. </p>
 293 <dl class="params"><dt>Parameters</dt><dd>
 294   <table class="params">
 295     <tr><td class="paramdir">[in]</td><td class="paramname">actrl</td><td>Auxiliary Control Register value to set</td></tr>
 296   </table>
 297   </dd>
 298 </dl>
 299 <p>This function assigns the given value to the <a class="el" href="group__CMSIS__ACTLR.html">Auxiliary Control Register (ACTLR)</a>. </p>
 300
 301 </div>
 302 </div>
 303 </div><!-- contents -->
 304 </div><!-- doc-content -->
 305 <!-- start footer part -->
 306 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
 307   <ul>
 308     <li class="footer">
 309       <script type="text/javascript">
 310         <!--
 311         writeFooter.call(this);
 312         //-->
 313       </script>
 314     </li>
 315   </ul>
 316 </div>
 317 </body>
 318 </html>