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46    <div id="projectname">CMSIS-Core (Cortex-A)
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130   <div class="headertitle"><div class="title">Startup File startup_&lt;Device&gt;.c </div></div>
131 </div><!--header-->
132 <div class="contents">
133 <div class="textblock"><p>The <a class="el" href="startup_c_pg.html">Startup File startup_&lt;Device&gt;.c</a> contains:</p><ul>
134 <li>Exception vectors of the Cortex-A Processor with weak functions that implement default routines.</li>
135 <li>The reset handler which is executed after CPU reset and typically calls the <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">SystemInit</a> function.</li>
136 <li>The setup values for the various stack pointers, i.e. per exceptional mode and main stack.</li>
137 </ul>
138 <p>The file exists for each supported toolchain and is the only tool-chain specific CMSIS file.</p>
139 <h1><a class="anchor" id="startup_c_sec"></a>
140 startup_Device.c Template File</h1>
141 <p>An Arm Compiler specific startup file for an Armv7-A processor like Cortex-A9 is shown below. The files for other compiler vendors differ slightly in the syntax, but not in the overall structure.</p>
142 <pre class="fragment">/******************************************************************************
143  * @file     startup_&lt;Device&gt;.c
144  * @brief    CMSIS Cortex-A Device Startup
145  * @version  V1.00
146  * @date     10. January 2018
147  ******************************************************************************/
148 /*
149  * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
150  *
151  * SPDX-License-Identifier: Apache-2.0
152  *
153  * Licensed under the Apache License, Version 2.0 (the License); you may
154  * not use this file except in compliance with the License.
155  * You may obtain a copy of the License at
156  *
157  * www.apache.org/licenses/LICENSE-2.0
158  *
159  * Unless required by applicable law or agreed to in writing, software
160  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
161  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
162  * See the License for the specific language governing permissions and
163  * limitations under the License.
164  */
165
166 #include "&lt;Device&gt;.h" /* ToDo: replace '&lt;Device&gt;' with your device name */
167
168 /*----------------------------------------------------------------------------
169   Definitions
170  *----------------------------------------------------------------------------*/
171 #define USR_MODE 0x10            // User mode
172 #define FIQ_MODE 0x11            // Fast Interrupt Request mode
173 #define IRQ_MODE 0x12            // Interrupt Request mode
174 #define SVC_MODE 0x13            // Supervisor mode
175 #define ABT_MODE 0x17            // Abort mode
176 #define UND_MODE 0x1B            // Undefined Instruction mode
177 #define SYS_MODE 0x1F            // System mode
178
179 /*----------------------------------------------------------------------------
180   Internal References
181  *----------------------------------------------------------------------------*/
182 void Vectors       (void) __attribute__ ((section("RESET")));
183 void Reset_Handler (void);
184
185 /*----------------------------------------------------------------------------
186   Exception / Interrupt Handler
187  *----------------------------------------------------------------------------*/
188 void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
189 void SVC_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
190 void PAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
191 void DAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
192 void IRQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
193 void FIQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
194
195 /*----------------------------------------------------------------------------
196   Exception / Interrupt Vector Table
197  *----------------------------------------------------------------------------*/
198 __ASM void Vectors(void) {
199   IMPORT Undef_Handler
200   IMPORT SVC_Handler
201   IMPORT PAbt_Handler
202   IMPORT DAbt_Handler
203   IMPORT IRQ_Handler
204   IMPORT FIQ_Handler
205   LDR    PC, =Reset_Handler
206   LDR    PC, =Undef_Handler
207   LDR    PC, =SVC_Handler
208   LDR    PC, =PAbt_Handler
209   LDR    PC, =DAbt_Handler
210   NOP
211   LDR    PC, =IRQ_Handler
212   LDR    PC, =FIQ_Handler
213 }
214
215 /*----------------------------------------------------------------------------
216   Reset Handler called on controller reset
217  *----------------------------------------------------------------------------*/
218 __ASM void Reset_Handler(void) {
219
220   // Mask interrupts
221   CPSID   if                           
222
223   // Put any cores other than 0 to sleep
224   MRC     p15, 0, R0, c0, c0, 5       // Read MPIDR
225   ANDS    R0, R0, #3
226 goToSleep
227   WFINE
228   BNE     goToSleep
229
230   // Reset SCTLR Settings
231   MRC     p15, 0, R0, c1, c0, 0       // Read CP15 System Control register
232   BIC     R0, R0, #(0x1 &lt;&lt; 12)        // Clear I bit 12 to disable I Cache
233   BIC     R0, R0, #(0x1 &lt;&lt;  2)        // Clear C bit  2 to disable D Cache
234   BIC     R0, R0, #0x1                // Clear M bit  0 to disable MMU
235   BIC     R0, R0, #(0x1 &lt;&lt; 11)        // Clear Z bit 11 to disable branch prediction
236   BIC     R0, R0, #(0x1 &lt;&lt; 13)        // Clear V bit 13 to disable hivecs
237   MCR     p15, 0, R0, c1, c0, 0       // Write value back to CP15 System Control register
238   ISB
239
240   // Configure ACTLR
241   MRC     p15, 0, r0, c1, c0, 1       // Read CP15 Auxiliary Control Register
242   ORR     r0, r0, #(1 &lt;&lt;  1)          // Enable L2 prefetch hint (UNK/WI since r4p1)
243   MCR     p15, 0, r0, c1, c0, 1       // Write CP15 Auxiliary Control Register
244
245   // Set Vector Base Address Register (VBAR) to point to this application's vector table
246   LDR    R0, =Vectors
247   MCR    p15, 0, R0, c12, c0, 0
248
249   // Setup Stack for each exceptional mode
250   IMPORT |Image$$FIQ_STACK$$ZI$$Limit|
251   IMPORT |Image$$IRQ_STACK$$ZI$$Limit|
252   IMPORT |Image$$SVC_STACK$$ZI$$Limit|
253   IMPORT |Image$$ABT_STACK$$ZI$$Limit|
254   IMPORT |Image$$UND_STACK$$ZI$$Limit|
255   IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
256   CPS    #0x11
257   LDR    SP, =|Image$$FIQ_STACK$$ZI$$Limit|
258   CPS    #0x12
259   LDR    SP, =|Image$$IRQ_STACK$$ZI$$Limit|
260   CPS    #0x13
261   LDR    SP, =|Image$$SVC_STACK$$ZI$$Limit|
262   CPS    #0x17
263   LDR    SP, =|Image$$ABT_STACK$$ZI$$Limit|
264   CPS    #0x1B
265   LDR    SP, =|Image$$UND_STACK$$ZI$$Limit|
266   CPS    #0x1F
267   LDR    SP, =|Image$$ARM_LIB_STACK$$ZI$$Limit|
268
269   // Call SystemInit
270   IMPORT SystemInit
271   BL     SystemInit
272
273   // Unmask interrupts
274   CPSIE  if
275
276   // Call __main
277   IMPORT __main
278   BL     __main
279 }
280
281 /*----------------------------------------------------------------------------
282   Default Handler for Exceptions / Interrupts
283  *----------------------------------------------------------------------------*/
284 void Default_Handler(void) {
285   while(1);
286 }
287 </pre> </div></div><!-- contents -->
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