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 131 <a href="#define-members">Macros</a>  </div>
 132   <div class="headertitle"><div class="title">Peripheral Access</div></div>
 133 </div><!--header-->
 134 <div class="contents">
 135
 136 <p>Naming conventions and optional features for accessing peripherals.
 137 <a href="#details">More...</a></p>
 138 <table class="memberdecls">
 139 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a>
 140 Macros</h2></td></tr>
 141 <tr class="memitem:ga286e3b913dbd236c7f48ea70c8821f4e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a>(field,  value)</td></tr>
 142 <tr class="memdesc:ga286e3b913dbd236c7f48ea70c8821f4e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mask and shift a bit field value for assigning the result to a peripheral register.  <br /></td></tr>
 143 <tr class="separator:ga286e3b913dbd236c7f48ea70c8821f4e"><td class="memSeparator" colspan="2">&#160;</td></tr>
 144 <tr class="memitem:ga139b6e261c981f014f386927ca4a8444"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444">_FLD2VAL</a>(field,  value)</td></tr>
 145 <tr class="memdesc:ga139b6e261c981f014f386927ca4a8444"><td class="mdescLeft">&#160;</td><td class="mdescRight">Extract from a peripheral register value the a bit field value.  <br /></td></tr>
 146 <tr class="separator:ga139b6e261c981f014f386927ca4a8444"><td class="memSeparator" colspan="2">&#160;</td></tr>
 147 </table>
 148 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
 149 <p>Naming conventions and optional features for accessing peripherals. </p>
 150 <p>The section below describes the naming conventions, requirements, and optional features for accessing device specific peripherals. Most of the rules also apply to the core peripherals. The <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> contains typically these definition and also includes the core specific header files.</p>
 151 <p>The definitions for <a class="el" href="group__peripheral__gr.html">Peripheral Access</a> can be generated using the <a href="../../SVD/html/index.html"><b>CMSIS-SVD</b></a> System View Description for Peripherals. Refer to <a href="../../SVD/html/svd_SVDConv_pg.html"><b>SVDConv.exe</b></a> for more information.</p>
 152 <p>Each peripheral provides a data type definition with a name that is composed of:</p><ul>
 153 <li>an optional prefix <b>&lt;<em>device abbreviation&gt;</em>_</b></li>
 154 <li><b>&lt;<em>peripheral name</em>&gt;</b></li>
 155 <li>postfix <b>_Type</b> or <b>_TypeDef</b> to identify a type definition.</li>
 156 </ul>
 157 <p>Examples:</p><ul>
 158 <li><b>UART_TypeDef</b> for the peripheral <b>UART</b>.</li>
 159 <li><b>IMX_UART_TypeDef</b> for the device family <b>IMX</b> and the peripheral <b>UART</b>.</li>
 160 </ul>
 161 <p>The data type definition uses standard C data types defined by the ANSI C header file &lt;stdint.h&gt;.</p>
 162 <ul>
 163 <li>IO Type Qualifiers are used to specify the access to peripheral variables. <table class="markdownTable">
 164 <tr class="markdownTableHead">
 165 <th class="markdownTableHeadLeft">IO Type Qualifier   </th><th class="markdownTableHeadLeft">Type   </th><th class="markdownTableHeadLeft">Description    </th></tr>
 166 <tr class="markdownTableRowOdd">
 167 <td class="markdownTableBodyLeft"><b>__IM</b>   </td><td class="markdownTableBodyLeft">Struct member   </td><td class="markdownTableBodyLeft">Defines 'read only' permissions    </td></tr>
 168 <tr class="markdownTableRowEven">
 169 <td class="markdownTableBodyLeft"><b>__OM</b>   </td><td class="markdownTableBodyLeft">Struct member   </td><td class="markdownTableBodyLeft">Defines 'write only' permissions    </td></tr>
 170 <tr class="markdownTableRowOdd">
 171 <td class="markdownTableBodyLeft"><b>__IOM</b>   </td><td class="markdownTableBodyLeft">Struct member   </td><td class="markdownTableBodyLeft">Defines 'read / write' permissions    </td></tr>
 172 <tr class="markdownTableRowEven">
 173 <td class="markdownTableBodyLeft"><b>__I</b>   </td><td class="markdownTableBodyLeft">Scalar variable   </td><td class="markdownTableBodyLeft">Defines 'read only' permissions    </td></tr>
 174 <tr class="markdownTableRowOdd">
 175 <td class="markdownTableBodyLeft"><b>__O</b>   </td><td class="markdownTableBodyLeft">Scalar variable   </td><td class="markdownTableBodyLeft">Defines 'write only' permissions    </td></tr>
 176 <tr class="markdownTableRowEven">
 177 <td class="markdownTableBodyLeft"><b>__IO</b>   </td><td class="markdownTableBodyLeft">Scalar variable   </td><td class="markdownTableBodyLeft">Defines 'read / write' permissions   </td></tr>
 178 </table>
 179 </li>
 180 </ul>
 181 <p>The typedef <b>&lt;<em>device abbreviation</em>&gt;_UART_TypeDef</b> shown below defines the generic register layout for all UART channels in a device.</p>
 182 <div class="fragment"><div class="line"><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
 183 <div class="line">  <a class="code hl_define" href="core__ca_8h.html#a7e25d9380f9ef903923964322e71f2f6">__O</a>  uint32_t UART_CR;            <span class="comment">// Offset: 0x0000 ( /W) Control Register </span></div>
 184 <div class="line">  <a class="code hl_define" href="core__ca_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t UART_MR;            <span class="comment">// Offset: 0x0004 (R/W) Mode Register </span></div>
 185 <div class="line">  <a class="code hl_define" href="core__ca_8h.html#a7e25d9380f9ef903923964322e71f2f6">__O</a>  uint32_t UART_IER;           <span class="comment">// Offset: 0x0008 ( /W) Interrupt Enable Register </span></div>
 186 <div class="line">  <a class="code hl_define" href="core__ca_8h.html#a7e25d9380f9ef903923964322e71f2f6">__O</a>  uint32_t UART_IDR;           <span class="comment">// Offset: 0x000C ( /W) Interrupt Disable Register </span></div>
 187 <div class="line">  <a class="code hl_define" href="core__ca_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a>  uint32_t UART_IMR;           <span class="comment">// Offset: 0x0010 (R/ ) Interrupt Mask Register </span></div>
 188 <div class="line">  <a class="code hl_define" href="core__ca_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a>  uint32_t UART_SR;            <span class="comment">// Offset: 0x0014 (R/ ) Status Register </span></div>
 189 <div class="line">  <a class="code hl_define" href="core__ca_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a>  uint32_t UART_RHR;           <span class="comment">// Offset: 0x0018 (R/ ) Receive Holding Register </span></div>
 190 <div class="line">  <a class="code hl_define" href="core__ca_8h.html#a7e25d9380f9ef903923964322e71f2f6">__O</a>  uint32_t UART_THR;           <span class="comment">// Offset: 0x001C ( /W) Transmit Holding Register </span></div>
 191 <div class="line">  <a class="code hl_define" href="core__ca_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t UART_BRGR;          <span class="comment">// Offset: 0x0020 (R/W) Baud Rate Generator Register </span></div>
 192 <div class="line">  <a class="code hl_define" href="core__ca_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t UART_CMPR;          <span class="comment">// Offset: 0x0024 (R/W) Comparison Register </span></div>
 193 <div class="line">  <a class="code hl_define" href="core__ca_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t UART_RTOR;          <span class="comment">// Offset: 0x0028 (R/W) Receiver Time-out Register </span></div>
 194 <div class="line">  <a class="code hl_define" href="core__ca_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a>  uint32_t <a class="code hl_define" href="core__ca_8h.html#af7f66fda711fd46e157dbb6c1af88e04">RESERVED</a>[46];       <span class="comment">// Offset: 0x002C (R/ ) Reserved                     </span></div>
 195 <div class="line">  <a class="code hl_define" href="core__ca_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t UART_WPMR;          <span class="comment">// Offset: 0x00E4 (R/W) Write Protection Mode Register </span></div>
 196 <div class="line">} IMX_UART_TypeDef;</div>
 197 <div class="ttc" id="acore__ca_8h_html_a7e25d9380f9ef903923964322e71f2f6"><div class="ttname"><a href="core__ca_8h.html#a7e25d9380f9ef903923964322e71f2f6">__O</a></div><div class="ttdeci">#define __O</div><div class="ttdoc">Defines 'write only' permissions.</div><div class="ttdef"><b>Definition:</b> core_ca.h:178</div></div>
 198 <div class="ttc" id="acore__ca_8h_html_aec43007d9998a0a0e01faede4133d6be"><div class="ttname"><a href="core__ca_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a></div><div class="ttdeci">#define __IO</div><div class="ttdoc">Defines 'read / write' permissions.</div><div class="ttdef"><b>Definition:</b> core_ca.h:179</div></div>
 199 <div class="ttc" id="acore__ca_8h_html_af63697ed9952cc71e1225efe205f6cd3"><div class="ttname"><a href="core__ca_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a></div><div class="ttdeci">#define __I</div><div class="ttdoc">Defines 'read only' permissions.</div><div class="ttdef"><b>Definition:</b> core_ca.h:174</div></div>
 200 <div class="ttc" id="acore__ca_8h_html_af7f66fda711fd46e157dbb6c1af88e04"><div class="ttname"><a href="core__ca_8h.html#af7f66fda711fd46e157dbb6c1af88e04">RESERVED</a></div><div class="ttdeci">#define RESERVED(N, T)</div><div class="ttdef"><b>Definition:</b> core_ca.h:185</div></div>
 201 </div><!-- fragment --><p>To access the registers of the UART defined above, pointers to this register structure are defined. If more instances of a peripheral exist, the variables have a postfix (digit or letter) that identifies the peripheral.</p>
 202 <p><b>Example:</b> In this example, <b>IMX_UART2</b> and <b>IMX_UART3</b> are two pointers to UARTs defined with above register structure. <br  />
 203 </p><div class="fragment"><div class="line"><span class="preprocessor">#define IMX_UART2   ((IMX_UART_TypeDef *) IMX_UART2_BASE)</span></div>
 204 <div class="line"><span class="preprocessor">#define IMX_UART3   ((IMX_UART_TypeDef *) IMX_UART3_BASE)</span></div>
 205 </div><!-- fragment --><dl class="section note"><dt>Note</dt><dd><ul>
 206 <li>The prefix <b>IMX</b> is optional.</li>
 207 </ul>
 208 </dd></dl>
 209 <p>The registers in the various UARTs can now be referred in the user code as shown below:<br  />
 210 </p><div class="fragment"><div class="line">val = IMX_UART2-&gt;SR   <span class="comment">// is the Status Register of UART2.</span></div>
 211 </div><!-- fragment --><hr  />
 212 <h1><a class="anchor" id="core_cmsis_pal_min_reqs"></a>
 213 Minimal Requirements</h1>
 214 <p>To access the peripheral registers and related function in a device, the files <b><em>device.h</em></b> and <b><a class="el" href="core__ca_8h.html" title="CMSIS Cortex-A Core Peripheral Access Layer Header File.">core_ca.h</a></b> define as a minimum: <br  />
 215 <br  />
 216 </p><ul>
 217 <li>The <b>Register Layout Typedef</b> for each peripheral that defines all register names. RESERVED is used to introduce space into the structure for adjusting the addresses of the peripheral registers. <br  />
 218 <br  />
 219 <b>Example:</b> <div class="fragment"><div class="line"><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
 220 <div class="line">{</div>
 221 <div class="line">  <a class="code hl_define" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t C_CTLR;              <span class="comment">// Offset: 0x0000 (R/W) CPU Interface Control Register </span></div>
 222 <div class="line">  <a class="code hl_define" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t C_PMR;               <span class="comment">// Offset: 0x0004 (R/W) Interrupt Priority Mask Register </span></div>
 223 <div class="line">  <a class="code hl_define" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t C_BPR;               <span class="comment">// Offset: 0x0008 (R/W) Binary Point Register </span></div>
 224 <div class="line">  <a class="code hl_define" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a>  uint32_t C_IAR;               <span class="comment">// Offset: 0x000C (R/ ) Interrupt Acknowledge Register </span></div>
 225 <div class="line">  <a class="code hl_define" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a>  uint32_t C_EOIR;              <span class="comment">// Offset: 0x0010 ( /W) End Of Interrupt Register </span></div>
 226 <div class="line">  <a class="code hl_define" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a>  uint32_t C_RPR;               <span class="comment">// Offset: 0x0014 (R/ ) Running Priority Register </span></div>
 227 <div class="line">  <a class="code hl_define" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a>  uint32_t C_HPPIR;             <span class="comment">// Offset: 0x0018 (R/ ) Highest Priority Pending Interrupt Register </span></div>
 228 <div class="line">  <a class="code hl_define" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t C_ABPR;              <span class="comment">// Offset: 0x001C (R/W) Aliased Binary Point Register </span></div>
 229 <div class="line">  <a class="code hl_define" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a>  uint32_t C_AIAR;              <span class="comment">// Offset: 0x0020 (R/ ) Aliased Interrupt Acknowledge Register </span></div>
 230 <div class="line">  <a class="code hl_define" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a>  uint32_t C_AEOIR;             <span class="comment">// Offset: 0x0024 ( /W) Aliased End Of Interrupt Register </span></div>
 231 <div class="line">  <a class="code hl_define" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a>  uint32_t C_AHPPIR;            <span class="comment">// Offset: 0x0028 (R/ ) Aliased Highest Priority Pending Interrupt Register </span></div>
 232 <div class="line">  <a class="code hl_define" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t C_STATUSR;           <span class="comment">// Offset: 0x002C (R/W) Error Reporting Status Register, optional </span></div>
 233 <div class="line">  <a class="code hl_define" href="core__ca_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a>   uint32_t RESERVED1[40];       <span class="comment">// Offset: 0x0030 (R/ ) Reserved</span></div>
 234 <div class="line">  <a class="code hl_define" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t C_APR[4];            <span class="comment">// Offset: 0x00D0 (R/W) Active Priority Register </span></div>
 235 <div class="line">  <a class="code hl_define" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t C_NSAPR[4];          <span class="comment">// Offset: 0x00E0 (R/W) Non-secure Active Priority Register </span></div>
 236 <div class="line">  <a class="code hl_define" href="core__ca_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a>   uint32_t RESERVED2[3];        <span class="comment">// Offset: 0x00F6 (R/ ) Reserved</span></div>
 237 <div class="line">  <a class="code hl_define" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a>  uint32_t C_IIDR;              <span class="comment">// Offset: 0x00FC (R/ ) CPU Interface Identification Register </span></div>
 238 <div class="line">  <a class="code hl_define" href="core__ca_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a>   uint32_t RESERVED3[960];      <span class="comment">// Offset: 0x0100 (R/ ) Reserved</span></div>
 239 <div class="line">  <a class="code hl_define" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a>  uint32_t C_DIR;               <span class="comment">// Offset: 0x1000 ( /W) Deactivate Interrupt Register </span></div>
 240 <div class="line">}  <a class="code hl_struct" href="structGICInterface__Type.html">GICInterface_Type</a>;</div>
 241 <div class="ttc" id="acore__ca_8h_html_a0ea2009ed8fd9ef35b48708280fdb758"><div class="ttname"><a href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a></div><div class="ttdeci">#define __OM</div><div class="ttdoc">Defines 'write only' structure member permissions.</div><div class="ttdef"><b>Definition:</b> core_ca.h:183</div></div>
 242 <div class="ttc" id="acore__ca_8h_html_a4cc1649793116d7c2d8afce7a4ffce43"><div class="ttname"><a href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a></div><div class="ttdeci">#define __IM</div><div class="ttdoc">Defines 'read only' structure member permissions.</div><div class="ttdef"><b>Definition:</b> core_ca.h:182</div></div>
 243 <div class="ttc" id="acore__ca_8h_html_ab6caba5853a60a17e8e04499b52bf691"><div class="ttname"><a href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a></div><div class="ttdeci">#define __IOM</div><div class="ttdoc">Defines 'read / write' structure member permissions.</div><div class="ttdef"><b>Definition:</b> core_ca.h:184</div></div>
 244 <div class="ttc" id="astructGICInterface__Type_html"><div class="ttname"><a href="structGICInterface__Type.html">GICInterface_Type</a></div><div class="ttdoc">Structure type to access the Generic Interrupt Controller Interface (GICC)</div><div class="ttdef"><b>Definition:</b> core_ca.h:966</div></div>
 245 </div><!-- fragment --></li>
 246 <li><b>Base Address</b> for each peripheral (in case of multiple peripherals that use the same <b>register layout typedef</b> multiple base addresses are defined). <br  />
 247 <br  />
 248 <b>Example:</b> <div class="fragment"><div class="line"><span class="preprocessor">#define GIC_INTERFACE_BASE (0xe8202000UL)   </span><span class="comment">// GIC Interface Base Address     </span></div>
 249 </div><!-- fragment --></li>
 250 <li><b>Access Definitions</b> for each peripheral. In case of multiple peripherals that are using the same <b>register layout typedef</b>, multiple access definitions exist. <br  />
 251 <br  />
 252 <b>Example:</b> <div class="fragment"><div class="line"><span class="preprocessor">#define GICInterface   ((GICInterface_Type *) GIC_INTERFACE_BASE)   </span><span class="comment">// GIC Interface Access Definition </span></div>
 253 </div><!-- fragment --></li>
 254 </ul>
 255 <p>These definitions allow accessing peripheral registers with simple assignments.</p>
 256 <ul>
 257 <li><b>Example:</b> <br  />
 258 <div class="fragment"><div class="line"><a class="code hl_define" href="group__GIC__functions.html#ga31a083dbdc5cb84178dbf184286180e3">GICInterface</a>-&gt;C_CTLR |= 1;   <span class="comment">// Enable Interface</span></div>
 259 <div class="ttc" id="agroup__GIC__functions_html_ga31a083dbdc5cb84178dbf184286180e3"><div class="ttname"><a href="group__GIC__functions.html#ga31a083dbdc5cb84178dbf184286180e3">GICInterface</a></div><div class="ttdeci">#define GICInterface</div><div class="ttdoc">GIC Interface register set access pointer.</div></div>
 260 </div><!-- fragment --></li>
 261 </ul>
 262 <hr  />
 263 <h1><a class="anchor" id="core_cmsis_pal_opts"></a>
 264 Optional Features</h1>
 265 <p>Optionally, the file <b><em>device</em>.h</b> may define:</p>
 266 <ul>
 267 <li><a class="el" href="group__peripheral__gr.html#core_cmsis_pal_bitfields">Register Bit Fields</a> and #define constants that simplify access to peripheral registers. These constants may define bit-positions or other specific patterns that are required for programming peripheral registers. The identifiers should start with <b>&lt;<em>device abbreviation</em>&gt;_</b> and <b>&lt;<em>peripheral name</em>&gt;_</b>. It is recommended to use CAPITAL letters for #define constants.</li>
 268 <li>More complex functions (i.e. status query before a sending register is accessed). Again, these functions start with <b>&lt;<em>device abbreviation</em>&gt;_</b> and <b>&lt;<em>peripheral name</em>&gt;_</b>.</li>
 269 </ul>
 270 <hr  />
 271 <h1><a class="anchor" id="core_cmsis_pal_bitfields"></a>
 272 Register Bit Fields</h1>
 273 <p>For Core Register, macros define the position and the mask value for a bit field.</p>
 274 <p><b>Example:</b></p>
 275 <p>Bit field definitions for register ACTLR in CP15.</p>
 276 <div class="fragment"><div class="line"><span class="comment">// CP15 Register ACTLR</span></div>
 277 <div class="line"><span class="preprocessor">#define ACTLR_DDI_Pos                  28U                       </span></div>
 278 <div class="line"><span class="preprocessor">#define ACTLR_DDI_Msk                  (1UL &lt;&lt; ACTLR_DDI_Pos)    </span></div>
 279 <div class="line">                                       </div>
 280 <div class="line"><span class="preprocessor">#define ACTLR_DDVM_Pos                 15U                       </span></div>
 281 <div class="line"><span class="preprocessor">#define ACTLR_DDVM_Msk                 (1UL &lt;&lt; ACTLR_DDVM_Pos)   </span></div>
 282 <div class="line">                                       </div>
 283 <div class="line"><span class="preprocessor">#define ACTLR_L1PCTL_Pos               13U                       </span></div>
 284 <div class="line"><span class="preprocessor">#define ACTLR_L1PCTL_Msk               (3UL &lt;&lt; ACTLR_L1PCTL_Pos) </span></div>
 285 <div class="line">                                       </div>
 286 <div class="line"><span class="preprocessor">#define ACTLR_L1RADIS_Pos              12U                       </span></div>
 287 <div class="line"><span class="preprocessor">#define ACTLR_L1RADIS_Msk              (1UL &lt;&lt; ACTLR_L1RADIS_Pos)</span></div>
 288 <div class="line">                                       </div>
 289 <div class="line"><span class="preprocessor">#define ACTLR_L2RADIS_Pos              11U                       </span></div>
 290 <div class="line"><span class="preprocessor">#define ACTLR_L2RADIS_Msk              (1UL &lt;&lt; ACTLR_L2RADIS_Pos)</span></div>
 291 <div class="line">                                       </div>
 292 <div class="line"><span class="preprocessor">#define ACTLR_DODMBS_Pos               10U                       </span></div>
 293 <div class="line"><span class="preprocessor">#define ACTLR_DODMBS_Msk               (1UL &lt;&lt; ACTLR_DODMBS_Pos) </span></div>
 294 <div class="line">                                       </div>
 295 <div class="line"><span class="preprocessor">#define ACTLR_SMP_Pos                  6U                        </span></div>
 296 <div class="line"><span class="preprocessor">#define ACTLR_SMP_Msk                  (1UL &lt;&lt; ACTLR_SMP_Pos)     </span></div>
 297 </div><!-- fragment --><p>The macros <b><a class="el" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e" title="Mask and shift a bit field value for assigning the result to a peripheral register.">_VAL2FLD(field, value)</a></b> and <b><a class="el" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444" title="Extract from a peripheral register value the a bit field value.">_FLD2VAL(field, value)</a></b> enable access to bit fields. </p>
 298 <h2 class="groupheader">Macro Definition Documentation</h2>
 299 <a id="ga139b6e261c981f014f386927ca4a8444" name="ga139b6e261c981f014f386927ca4a8444"></a>
 300 <h2 class="memtitle"><span class="permalink"><a href="#ga139b6e261c981f014f386927ca4a8444">&#9670;&#160;</a></span>_FLD2VAL</h2>
 301
 302 <div class="memitem">
 303 <div class="memproto">
 304       <table class="memname">
 305         <tr>
 306           <td class="memname">#define _FLD2VAL</td>
 307           <td>(</td>
 308           <td class="paramtype">&#160;</td>
 309           <td class="paramname">field, </td>
 310         </tr>
 311         <tr>
 312           <td class="paramkey"></td>
 313           <td></td>
 314           <td class="paramtype">&#160;</td>
 315           <td class="paramname">value&#160;</td>
 316         </tr>
 317         <tr>
 318           <td></td>
 319           <td>)</td>
 320           <td></td><td></td>
 321         </tr>
 322       </table>
 323 </div><div class="memdoc">
 324
 325 <p>Extract from a peripheral register value the a bit field value. </p>
 326 <dl class="params"><dt>Parameters</dt><dd>
 327   <table class="params">
 328     <tr><td class="paramname">field</td><td>name of bit field. </td></tr>
 329     <tr><td class="paramname">value</td><td>value of the register. This parameter is interpreted as an uint32_t type.</td></tr>
 330   </table>
 331   </dd>
 332 </dl>
 333 <p>The macro <a class="el" href="core__ca_8h.html#a139b6e261c981f014f386927ca4a8444">_FLD2VAL</a> uses the #define's <em>_Pos</em> and <em>_Msk</em> of the related bit field to extract the value of a bit field from a register.</p>
 334 <p><b>Example:</b> </p><div class="fragment"><div class="line">i = <a class="code hl_define" href="core__ca_8h.html#a139b6e261c981f014f386927ca4a8444">_FLD2VAL</a>(ACTLR_SMP, ACTLR);</div>
 335 <div class="ttc" id="acore__ca_8h_html_a139b6e261c981f014f386927ca4a8444"><div class="ttname"><a href="core__ca_8h.html#a139b6e261c981f014f386927ca4a8444">_FLD2VAL</a></div><div class="ttdeci">#define _FLD2VAL(field, value)</div><div class="ttdoc">Mask and shift a register value to extract a bit filed value.</div><div class="ttdef"><b>Definition:</b> core_ca.h:678</div></div>
 336 </div><!-- fragment -->
 337 </div>
 338 </div>
 339 <a id="ga286e3b913dbd236c7f48ea70c8821f4e" name="ga286e3b913dbd236c7f48ea70c8821f4e"></a>
 340 <h2 class="memtitle"><span class="permalink"><a href="#ga286e3b913dbd236c7f48ea70c8821f4e">&#9670;&#160;</a></span>_VAL2FLD</h2>
 341
 342 <div class="memitem">
 343 <div class="memproto">
 344       <table class="memname">
 345         <tr>
 346           <td class="memname">#define _VAL2FLD</td>
 347           <td>(</td>
 348           <td class="paramtype">&#160;</td>
 349           <td class="paramname">field, </td>
 350         </tr>
 351         <tr>
 352           <td class="paramkey"></td>
 353           <td></td>
 354           <td class="paramtype">&#160;</td>
 355           <td class="paramname">value&#160;</td>
 356         </tr>
 357         <tr>
 358           <td></td>
 359           <td>)</td>
 360           <td></td><td></td>
 361         </tr>
 362       </table>
 363 </div><div class="memdoc">
 364
 365 <p>Mask and shift a bit field value for assigning the result to a peripheral register. </p>
 366 <dl class="params"><dt>Parameters</dt><dd>
 367   <table class="params">
 368     <tr><td class="paramname">field</td><td>name of bit field. </td></tr>
 369     <tr><td class="paramname">value</td><td>value for the bit field. This parameter is interpreted as an uint32_t type.</td></tr>
 370   </table>
 371   </dd>
 372 </dl>
 373 <p>The macro <a class="el" href="core__ca_8h.html#a286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a> uses the #define's <em>_Pos</em> and <em>_Msk</em> of the related bit field to shift bit-field values for assigning to a register.</p>
 374 <p><b>Example:</b> </p><div class="fragment"><div class="line">ACTLR = <a class="code hl_define" href="core__ca_8h.html#a286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a>(ACTLR_SMP, 0x1)</div>
 375 <div class="ttc" id="acore__ca_8h_html_a286e3b913dbd236c7f48ea70c8821f4e"><div class="ttname"><a href="core__ca_8h.html#a286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a></div><div class="ttdeci">#define _VAL2FLD(field, value)</div><div class="ttdoc">Mask and shift a bit field value for use in a register bit range.</div><div class="ttdef"><b>Definition:</b> core_ca.h:670</div></div>
 376 </div><!-- fragment -->
 377 </div>
 378 </div>
 379 </div><!-- contents -->
 380 </div><!-- doc-content -->
 381 <!-- start footer part -->
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