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52 <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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127 <div class="summary">
128 <a href="#define-members">Macros</a> </div>
129 <div class="headertitle"><div class="title">PMU Events for Armv8.1-M<div class="ingroups"><a class="el" href="group__pmu8__functions.html">PMU Functions for Armv8.1-M</a></div></div></div>
131 <div class="contents">
133 <p>IDs for Armv8.1-M architecture defined events.
134 <a href="#details">More...</a></p>
135 <table class="memberdecls">
136 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a>
137 Macros</h2></td></tr>
138 <tr class="memitem:gaf2e0a38b7c0d63d1194f08478781a3f0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf2e0a38b7c0d63d1194f08478781a3f0">ARM_PMU_BF_CANCEL</a>   0x0109</td></tr>
139 <tr class="memdesc:gaf2e0a38b7c0d63d1194f08478781a3f0"><td class="mdescLeft"> </td><td class="mdescRight">Branch future instruction not taken. <br /></td></tr>
140 <tr class="separator:gaf2e0a38b7c0d63d1194f08478781a3f0"><td class="memSeparator" colspan="2"> </td></tr>
141 <tr class="memitem:gab8570f46393e3e44bb118591d33723f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab8570f46393e3e44bb118591d33723f4">ARM_PMU_BF_RETIRED</a>   0x0104</td></tr>
142 <tr class="memdesc:gab8570f46393e3e44bb118591d33723f4"><td class="mdescLeft"> </td><td class="mdescRight">Branch future instruction architecturally executed and condition code check pass. <br /></td></tr>
143 <tr class="separator:gab8570f46393e3e44bb118591d33723f4"><td class="memSeparator" colspan="2"> </td></tr>
144 <tr class="memitem:ga6b1e4823d8b45678a29a5f54b859d4e3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga6b1e4823d8b45678a29a5f54b859d4e3">ARM_PMU_BF_SPEC</a>   0x0105</td></tr>
145 <tr class="memdesc:ga6b1e4823d8b45678a29a5f54b859d4e3"><td class="mdescLeft"> </td><td class="mdescRight">Branch future instruction speculatively executed and condition code check pass. <br /></td></tr>
146 <tr class="separator:ga6b1e4823d8b45678a29a5f54b859d4e3"><td class="memSeparator" colspan="2"> </td></tr>
147 <tr class="memitem:ga22bfb189fff7c1ea9f81097a543ed756"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga22bfb189fff7c1ea9f81097a543ed756">ARM_PMU_BR_IMMED_RETIRED</a>   0x000D</td></tr>
148 <tr class="memdesc:ga22bfb189fff7c1ea9f81097a543ed756"><td class="mdescLeft"> </td><td class="mdescRight">Immediate branch architecturally executed. <br /></td></tr>
149 <tr class="separator:ga22bfb189fff7c1ea9f81097a543ed756"><td class="memSeparator" colspan="2"> </td></tr>
150 <tr class="memitem:gabfa921c85a61f0a21c9bee289e63c102"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gabfa921c85a61f0a21c9bee289e63c102">ARM_PMU_BR_MIS_PRED</a>   0x0010</td></tr>
151 <tr class="memdesc:gabfa921c85a61f0a21c9bee289e63c102"><td class="mdescLeft"> </td><td class="mdescRight">Mispredicted or not predicted branch speculatively executed. <br /></td></tr>
152 <tr class="separator:gabfa921c85a61f0a21c9bee289e63c102"><td class="memSeparator" colspan="2"> </td></tr>
153 <tr class="memitem:gae12baa616c5f0cdd081231fcf8cdad68"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gae12baa616c5f0cdd081231fcf8cdad68">ARM_PMU_BR_MIS_PRED_RETIRED</a>   0x0022</td></tr>
154 <tr class="memdesc:gae12baa616c5f0cdd081231fcf8cdad68"><td class="mdescLeft"> </td><td class="mdescRight">Mispredicted branch instruction architecturally executed. <br /></td></tr>
155 <tr class="separator:gae12baa616c5f0cdd081231fcf8cdad68"><td class="memSeparator" colspan="2"> </td></tr>
156 <tr class="memitem:ga60ccf42eae576e2fde3b9e17a8defeaa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga60ccf42eae576e2fde3b9e17a8defeaa">ARM_PMU_BR_PRED</a>   0x0012</td></tr>
157 <tr class="memdesc:ga60ccf42eae576e2fde3b9e17a8defeaa"><td class="mdescLeft"> </td><td class="mdescRight">Predictable branch speculatively executed. <br /></td></tr>
158 <tr class="separator:ga60ccf42eae576e2fde3b9e17a8defeaa"><td class="memSeparator" colspan="2"> </td></tr>
159 <tr class="memitem:gab3b505a8bcc2b2885626d2f2cd542b73"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab3b505a8bcc2b2885626d2f2cd542b73">ARM_PMU_BR_RETIRED</a>   0x0021</td></tr>
160 <tr class="memdesc:gab3b505a8bcc2b2885626d2f2cd542b73"><td class="mdescLeft"> </td><td class="mdescRight">Branch instruction architecturally executed. <br /></td></tr>
161 <tr class="separator:gab3b505a8bcc2b2885626d2f2cd542b73"><td class="memSeparator" colspan="2"> </td></tr>
162 <tr class="memitem:gab717347b1c3601cffb9c99b43b2a45c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab717347b1c3601cffb9c99b43b2a45c5">ARM_PMU_BR_RETURN_RETIRED</a>   0x000E</td></tr>
163 <tr class="memdesc:gab717347b1c3601cffb9c99b43b2a45c5"><td class="mdescLeft"> </td><td class="mdescRight">Function return instruction architecturally executed and the condition code check pass. <br /></td></tr>
164 <tr class="separator:gab717347b1c3601cffb9c99b43b2a45c5"><td class="memSeparator" colspan="2"> </td></tr>
165 <tr class="memitem:gaa681d3db56b42775093869b8fdf1abb9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaa681d3db56b42775093869b8fdf1abb9">ARM_PMU_BUS_ACCESS</a>   0x0019</td></tr>
166 <tr class="memdesc:gaa681d3db56b42775093869b8fdf1abb9"><td class="mdescLeft"> </td><td class="mdescRight">Bus access. <br /></td></tr>
167 <tr class="separator:gaa681d3db56b42775093869b8fdf1abb9"><td class="memSeparator" colspan="2"> </td></tr>
168 <tr class="memitem:gae4c955416707f44f066ffd2560b9ae4c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gae4c955416707f44f066ffd2560b9ae4c">ARM_PMU_BUS_CYCLES</a>   0x001D</td></tr>
169 <tr class="memdesc:gae4c955416707f44f066ffd2560b9ae4c"><td class="mdescLeft"> </td><td class="mdescRight">Bus cycles. <br /></td></tr>
170 <tr class="separator:gae4c955416707f44f066ffd2560b9ae4c"><td class="memSeparator" colspan="2"> </td></tr>
171 <tr class="memitem:gaca14907c5a1e1f9915159bc4cf323cf0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaca14907c5a1e1f9915159bc4cf323cf0">ARM_PMU_CHAIN</a>   0x001E</td></tr>
172 <tr class="memdesc:gaca14907c5a1e1f9915159bc4cf323cf0"><td class="mdescLeft"> </td><td class="mdescRight">For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE. <br /></td></tr>
173 <tr class="separator:gaca14907c5a1e1f9915159bc4cf323cf0"><td class="memSeparator" colspan="2"> </td></tr>
174 <tr class="memitem:ga550d524d435a653b2f46acc1380a5ace"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga550d524d435a653b2f46acc1380a5ace">ARM_PMU_CPU_CYCLES</a>   0x0011</td></tr>
175 <tr class="memdesc:ga550d524d435a653b2f46acc1380a5ace"><td class="mdescLeft"> </td><td class="mdescRight">Cycle. <br /></td></tr>
176 <tr class="separator:ga550d524d435a653b2f46acc1380a5ace"><td class="memSeparator" colspan="2"> </td></tr>
177 <tr class="memitem:ga290974d72b8cac214f4e9a152ca64a56"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga290974d72b8cac214f4e9a152ca64a56">ARM_PMU_CTI_TRIGOUT4</a>   0x4018</td></tr>
178 <tr class="memdesc:ga290974d72b8cac214f4e9a152ca64a56"><td class="mdescLeft"> </td><td class="mdescRight">Cross-trigger Interface output trigger 4. <br /></td></tr>
179 <tr class="separator:ga290974d72b8cac214f4e9a152ca64a56"><td class="memSeparator" colspan="2"> </td></tr>
180 <tr class="memitem:ga7a05420b7fae6f5c3d35e12a9846c7e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga7a05420b7fae6f5c3d35e12a9846c7e2">ARM_PMU_CTI_TRIGOUT5</a>   0x4019</td></tr>
181 <tr class="memdesc:ga7a05420b7fae6f5c3d35e12a9846c7e2"><td class="mdescLeft"> </td><td class="mdescRight">Cross-trigger Interface output trigger 5. <br /></td></tr>
182 <tr class="separator:ga7a05420b7fae6f5c3d35e12a9846c7e2"><td class="memSeparator" colspan="2"> </td></tr>
183 <tr class="memitem:gade076a5ee512a14f8882d9aec5d3dc0b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gade076a5ee512a14f8882d9aec5d3dc0b">ARM_PMU_CTI_TRIGOUT6</a>   0x401A</td></tr>
184 <tr class="memdesc:gade076a5ee512a14f8882d9aec5d3dc0b"><td class="mdescLeft"> </td><td class="mdescRight">Cross-trigger Interface output trigger 6. <br /></td></tr>
185 <tr class="separator:gade076a5ee512a14f8882d9aec5d3dc0b"><td class="memSeparator" colspan="2"> </td></tr>
186 <tr class="memitem:ga4388c85b636bd71b4ee1a03b6e96c488"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga4388c85b636bd71b4ee1a03b6e96c488">ARM_PMU_CTI_TRIGOUT7</a>   0x401B</td></tr>
187 <tr class="memdesc:ga4388c85b636bd71b4ee1a03b6e96c488"><td class="mdescLeft"> </td><td class="mdescRight">Cross-trigger Interface output trigger 7. <br /></td></tr>
188 <tr class="separator:ga4388c85b636bd71b4ee1a03b6e96c488"><td class="memSeparator" colspan="2"> </td></tr>
189 <tr class="memitem:ga74aaa0fa0571f74168ee9608d5a02403"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga74aaa0fa0571f74168ee9608d5a02403">ARM_PMU_DTCM_ACCESS</a>   0x4008</td></tr>
190 <tr class="memdesc:ga74aaa0fa0571f74168ee9608d5a02403"><td class="mdescLeft"> </td><td class="mdescRight">Data TCM access. <br /></td></tr>
191 <tr class="separator:ga74aaa0fa0571f74168ee9608d5a02403"><td class="memSeparator" colspan="2"> </td></tr>
192 <tr class="memitem:ga18d640aa04b97c7d287e8745f6f2b23d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga18d640aa04b97c7d287e8745f6f2b23d">ARM_PMU_DWT_CMPMATCH0</a>   0x0118</td></tr>
193 <tr class="memdesc:ga18d640aa04b97c7d287e8745f6f2b23d"><td class="mdescLeft"> </td><td class="mdescRight">DWT comparator 0 match. <br /></td></tr>
194 <tr class="separator:ga18d640aa04b97c7d287e8745f6f2b23d"><td class="memSeparator" colspan="2"> </td></tr>
195 <tr class="memitem:ga5dc6eb2be1ff1afe9cbd59af4f6078ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga5dc6eb2be1ff1afe9cbd59af4f6078ab">ARM_PMU_DWT_CMPMATCH1</a>   0x0119</td></tr>
196 <tr class="memdesc:ga5dc6eb2be1ff1afe9cbd59af4f6078ab"><td class="mdescLeft"> </td><td class="mdescRight">DWT comparator 1 match. <br /></td></tr>
197 <tr class="separator:ga5dc6eb2be1ff1afe9cbd59af4f6078ab"><td class="memSeparator" colspan="2"> </td></tr>
198 <tr class="memitem:ga58a4815dba8886088b9cac7b934a332d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga58a4815dba8886088b9cac7b934a332d">ARM_PMU_DWT_CMPMATCH2</a>   0x011A</td></tr>
199 <tr class="memdesc:ga58a4815dba8886088b9cac7b934a332d"><td class="mdescLeft"> </td><td class="mdescRight">DWT comparator 2 match. <br /></td></tr>
200 <tr class="separator:ga58a4815dba8886088b9cac7b934a332d"><td class="memSeparator" colspan="2"> </td></tr>
201 <tr class="memitem:ga594337c6f3c88d8317203a8cd6f9814a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga594337c6f3c88d8317203a8cd6f9814a">ARM_PMU_DWT_CMPMATCH3</a>   0x011B</td></tr>
202 <tr class="memdesc:ga594337c6f3c88d8317203a8cd6f9814a"><td class="mdescLeft"> </td><td class="mdescRight">DWT comparator 3 match. <br /></td></tr>
203 <tr class="separator:ga594337c6f3c88d8317203a8cd6f9814a"><td class="memSeparator" colspan="2"> </td></tr>
204 <tr class="memitem:gaf9424157e9c5dca3a3689d181005c4f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf9424157e9c5dca3a3689d181005c4f8">ARM_PMU_EXC_RETURN</a>   0x000A</td></tr>
205 <tr class="memdesc:gaf9424157e9c5dca3a3689d181005c4f8"><td class="mdescLeft"> </td><td class="mdescRight">Exception return instruction architecturally executed and the condition code check pass. <br /></td></tr>
206 <tr class="separator:gaf9424157e9c5dca3a3689d181005c4f8"><td class="memSeparator" colspan="2"> </td></tr>
207 <tr class="memitem:gac97858bd621eab4592569444f0a5c37f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gac97858bd621eab4592569444f0a5c37f">ARM_PMU_EXC_TAKEN</a>   0x0009</td></tr>
208 <tr class="memdesc:gac97858bd621eab4592569444f0a5c37f"><td class="mdescLeft"> </td><td class="mdescRight">Exception entry. <br /></td></tr>
209 <tr class="separator:gac97858bd621eab4592569444f0a5c37f"><td class="memSeparator" colspan="2"> </td></tr>
210 <tr class="memitem:ga8a5e60eee460addfc66e275a2c4c4800"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8a5e60eee460addfc66e275a2c4c4800">ARM_PMU_INST_RETIRED</a>   0x0008</td></tr>
211 <tr class="memdesc:ga8a5e60eee460addfc66e275a2c4c4800"><td class="mdescLeft"> </td><td class="mdescRight">Instruction architecturally executed. <br /></td></tr>
212 <tr class="separator:ga8a5e60eee460addfc66e275a2c4c4800"><td class="memSeparator" colspan="2"> </td></tr>
213 <tr class="memitem:gaf7bad54617ace5c2fb48bc2e8aebf9c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf7bad54617ace5c2fb48bc2e8aebf9c7">ARM_PMU_INST_SPEC</a>   0x001B</td></tr>
214 <tr class="memdesc:gaf7bad54617ace5c2fb48bc2e8aebf9c7"><td class="mdescLeft"> </td><td class="mdescRight">Instruction speculatively executed. <br /></td></tr>
215 <tr class="separator:gaf7bad54617ace5c2fb48bc2e8aebf9c7"><td class="memSeparator" colspan="2"> </td></tr>
216 <tr class="memitem:gaf23d758fe1a4cfe6f114cb3e78709237"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf23d758fe1a4cfe6f114cb3e78709237">ARM_PMU_ITCM_ACCESS</a>   0x4007</td></tr>
217 <tr class="memdesc:gaf23d758fe1a4cfe6f114cb3e78709237"><td class="mdescLeft"> </td><td class="mdescRight">Instruction TCM access. <br /></td></tr>
218 <tr class="separator:gaf23d758fe1a4cfe6f114cb3e78709237"><td class="memSeparator" colspan="2"> </td></tr>
219 <tr class="memitem:ga7505ae74c1d905f01b05dd5466c1efc0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga7505ae74c1d905f01b05dd5466c1efc0">ARM_PMU_L1D_CACHE</a>   0x0004</td></tr>
220 <tr class="memdesc:ga7505ae74c1d905f01b05dd5466c1efc0"><td class="mdescLeft"> </td><td class="mdescRight">L1 D-Cache access. <br /></td></tr>
221 <tr class="separator:ga7505ae74c1d905f01b05dd5466c1efc0"><td class="memSeparator" colspan="2"> </td></tr>
222 <tr class="memitem:gab55334c8510cb30c4c750913f6eb6279"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab55334c8510cb30c4c750913f6eb6279">ARM_PMU_L1D_CACHE_ALLOCATE</a>   0x001F</td></tr>
223 <tr class="memdesc:gab55334c8510cb30c4c750913f6eb6279"><td class="mdescLeft"> </td><td class="mdescRight">Level 1 data cache allocation without refill. <br /></td></tr>
224 <tr class="separator:gab55334c8510cb30c4c750913f6eb6279"><td class="memSeparator" colspan="2"> </td></tr>
225 <tr class="memitem:ga4687d5d7efc6f49db2db9acc25b590f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga4687d5d7efc6f49db2db9acc25b590f6">ARM_PMU_L1D_CACHE_MISS_RD</a>   0x0039</td></tr>
226 <tr class="memdesc:ga4687d5d7efc6f49db2db9acc25b590f6"><td class="mdescLeft"> </td><td class="mdescRight">Level 1 data cache read miss. <br /></td></tr>
227 <tr class="separator:ga4687d5d7efc6f49db2db9acc25b590f6"><td class="memSeparator" colspan="2"> </td></tr>
228 <tr class="memitem:gaf4236dfbcb4550d3cc98caee837e8e77"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf4236dfbcb4550d3cc98caee837e8e77">ARM_PMU_L1D_CACHE_RD</a>   0x0040</td></tr>
229 <tr class="memdesc:gaf4236dfbcb4550d3cc98caee837e8e77"><td class="mdescLeft"> </td><td class="mdescRight">Level 1 data cache read. <br /></td></tr>
230 <tr class="separator:gaf4236dfbcb4550d3cc98caee837e8e77"><td class="memSeparator" colspan="2"> </td></tr>
231 <tr class="memitem:ga64a3d7bfb7ec9d7bdeb073a4fe1bbc38"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga64a3d7bfb7ec9d7bdeb073a4fe1bbc38">ARM_PMU_L1D_CACHE_REFILL</a>   0x0003</td></tr>
232 <tr class="memdesc:ga64a3d7bfb7ec9d7bdeb073a4fe1bbc38"><td class="mdescLeft"> </td><td class="mdescRight">L1 D-Cache refill. <br /></td></tr>
233 <tr class="separator:ga64a3d7bfb7ec9d7bdeb073a4fe1bbc38"><td class="memSeparator" colspan="2"> </td></tr>
234 <tr class="memitem:ga27d1b8b2c37ae0ae41781880ed3893d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga27d1b8b2c37ae0ae41781880ed3893d0">ARM_PMU_L1D_CACHE_WB</a>   0x0015</td></tr>
235 <tr class="memdesc:ga27d1b8b2c37ae0ae41781880ed3893d0"><td class="mdescLeft"> </td><td class="mdescRight">Level 1 data cache write-back. <br /></td></tr>
236 <tr class="separator:ga27d1b8b2c37ae0ae41781880ed3893d0"><td class="memSeparator" colspan="2"> </td></tr>
237 <tr class="memitem:gaf8e89b2b098e6bec5916517346925ce2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf8e89b2b098e6bec5916517346925ce2">ARM_PMU_L1I_CACHE</a>   0x0014</td></tr>
238 <tr class="memdesc:gaf8e89b2b098e6bec5916517346925ce2"><td class="mdescLeft"> </td><td class="mdescRight">Level 1 instruction cache access. <br /></td></tr>
239 <tr class="separator:gaf8e89b2b098e6bec5916517346925ce2"><td class="memSeparator" colspan="2"> </td></tr>
240 <tr class="memitem:gac43e0e0f9e385ea66402bdeebf3fea3e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gac43e0e0f9e385ea66402bdeebf3fea3e">ARM_PMU_L1I_CACHE_REFILL</a>   0x0001</td></tr>
241 <tr class="memdesc:gac43e0e0f9e385ea66402bdeebf3fea3e"><td class="mdescLeft"> </td><td class="mdescRight">L1 I-Cache refill. <br /></td></tr>
242 <tr class="separator:gac43e0e0f9e385ea66402bdeebf3fea3e"><td class="memSeparator" colspan="2"> </td></tr>
243 <tr class="memitem:gafb1e1f86d091ccb735858769c700e289"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gafb1e1f86d091ccb735858769c700e289">ARM_PMU_L2D_CACHE</a>   0x0016</td></tr>
244 <tr class="memdesc:gafb1e1f86d091ccb735858769c700e289"><td class="mdescLeft"> </td><td class="mdescRight">Level 2 data cache access. <br /></td></tr>
245 <tr class="separator:gafb1e1f86d091ccb735858769c700e289"><td class="memSeparator" colspan="2"> </td></tr>
246 <tr class="memitem:gaad08dcded491bf257d223e4171af41cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaad08dcded491bf257d223e4171af41cc">ARM_PMU_L2D_CACHE_ALLOCATE</a>   0x0020</td></tr>
247 <tr class="memdesc:gaad08dcded491bf257d223e4171af41cc"><td class="mdescLeft"> </td><td class="mdescRight">Level 2 data cache allocation without refill. <br /></td></tr>
248 <tr class="separator:gaad08dcded491bf257d223e4171af41cc"><td class="memSeparator" colspan="2"> </td></tr>
249 <tr class="memitem:gaeb414c1b0375022abc2502ab503a3284"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaeb414c1b0375022abc2502ab503a3284">ARM_PMU_L2D_CACHE_REFILL</a>   0x0017</td></tr>
250 <tr class="memdesc:gaeb414c1b0375022abc2502ab503a3284"><td class="mdescLeft"> </td><td class="mdescRight">Level 2 data cache refill. <br /></td></tr>
251 <tr class="separator:gaeb414c1b0375022abc2502ab503a3284"><td class="memSeparator" colspan="2"> </td></tr>
252 <tr class="memitem:ga1a0c4a1990eeed88edc3e1e0c4b1aca0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga1a0c4a1990eeed88edc3e1e0c4b1aca0">ARM_PMU_L2D_CACHE_WB</a>   0x0018</td></tr>
253 <tr class="memdesc:ga1a0c4a1990eeed88edc3e1e0c4b1aca0"><td class="mdescLeft"> </td><td class="mdescRight">Level 2 data cache write-back. <br /></td></tr>
254 <tr class="separator:ga1a0c4a1990eeed88edc3e1e0c4b1aca0"><td class="memSeparator" colspan="2"> </td></tr>
255 <tr class="memitem:ga3406498b2c17ca080ebd68cc40d9630e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga3406498b2c17ca080ebd68cc40d9630e">ARM_PMU_L2I_CACHE</a>   0x0027</td></tr>
256 <tr class="memdesc:ga3406498b2c17ca080ebd68cc40d9630e"><td class="mdescLeft"> </td><td class="mdescRight">Level 2 instruction cache access. <br /></td></tr>
257 <tr class="separator:ga3406498b2c17ca080ebd68cc40d9630e"><td class="memSeparator" colspan="2"> </td></tr>
258 <tr class="memitem:gaa18cee03802b46076e9ab66fd0a7c61d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaa18cee03802b46076e9ab66fd0a7c61d">ARM_PMU_L2I_CACHE_REFILL</a>   0x0028</td></tr>
259 <tr class="memdesc:gaa18cee03802b46076e9ab66fd0a7c61d"><td class="mdescLeft"> </td><td class="mdescRight">Level 2 instruction cache refill. <br /></td></tr>
260 <tr class="separator:gaa18cee03802b46076e9ab66fd0a7c61d"><td class="memSeparator" colspan="2"> </td></tr>
261 <tr class="memitem:ga4e96b5a6fb13c657e78da342a02db200"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga4e96b5a6fb13c657e78da342a02db200">ARM_PMU_L3D_CACHE</a>   0x002B</td></tr>
262 <tr class="memdesc:ga4e96b5a6fb13c657e78da342a02db200"><td class="mdescLeft"> </td><td class="mdescRight">Level 3 data cache access. <br /></td></tr>
263 <tr class="separator:ga4e96b5a6fb13c657e78da342a02db200"><td class="memSeparator" colspan="2"> </td></tr>
264 <tr class="memitem:gac11cbc6849dbad7bd8b64ab6e2a3f8d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gac11cbc6849dbad7bd8b64ab6e2a3f8d5">ARM_PMU_L3D_CACHE_ALLOCATE</a>   0x0029</td></tr>
265 <tr class="memdesc:gac11cbc6849dbad7bd8b64ab6e2a3f8d5"><td class="mdescLeft"> </td><td class="mdescRight">Level 3 data cache allocation without refill. <br /></td></tr>
266 <tr class="separator:gac11cbc6849dbad7bd8b64ab6e2a3f8d5"><td class="memSeparator" colspan="2"> </td></tr>
267 <tr class="memitem:gafe99db0693125100272247c147fb3b02"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gafe99db0693125100272247c147fb3b02">ARM_PMU_L3D_CACHE_REFILL</a>   0x002A</td></tr>
268 <tr class="memdesc:gafe99db0693125100272247c147fb3b02"><td class="mdescLeft"> </td><td class="mdescRight">Level 3 data cache refill. <br /></td></tr>
269 <tr class="separator:gafe99db0693125100272247c147fb3b02"><td class="memSeparator" colspan="2"> </td></tr>
270 <tr class="memitem:gab823f95f7ac8196a208d12381b1b2a11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab823f95f7ac8196a208d12381b1b2a11">ARM_PMU_L3D_CACHE_WB</a>   0x002C</td></tr>
271 <tr class="memdesc:gab823f95f7ac8196a208d12381b1b2a11"><td class="mdescLeft"> </td><td class="mdescRight">Level 3 data cache write-back. <br /></td></tr>
272 <tr class="separator:gab823f95f7ac8196a208d12381b1b2a11"><td class="memSeparator" colspan="2"> </td></tr>
273 <tr class="memitem:ga2e8725ee07c2b2c75a1b54261bc26cc8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga2e8725ee07c2b2c75a1b54261bc26cc8">ARM_PMU_LD_RETIRED</a>   0x0006</td></tr>
274 <tr class="memdesc:ga2e8725ee07c2b2c75a1b54261bc26cc8"><td class="mdescLeft"> </td><td class="mdescRight">Memory-reading instruction architecturally executed and condition code check pass. <br /></td></tr>
275 <tr class="separator:ga2e8725ee07c2b2c75a1b54261bc26cc8"><td class="memSeparator" colspan="2"> </td></tr>
276 <tr class="memitem:ga8b5641a3cb0e922a2b4e16ec14052861"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8b5641a3cb0e922a2b4e16ec14052861">ARM_PMU_LE_CANCEL</a>   0x0108</td></tr>
277 <tr class="memdesc:ga8b5641a3cb0e922a2b4e16ec14052861"><td class="mdescLeft"> </td><td class="mdescRight">Loop end instruction not taken. <br /></td></tr>
278 <tr class="separator:ga8b5641a3cb0e922a2b4e16ec14052861"><td class="memSeparator" colspan="2"> </td></tr>
279 <tr class="memitem:ga345461506c990125b1f2cbc62e3be22f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga345461506c990125b1f2cbc62e3be22f">ARM_PMU_LE_RETIRED</a>   0x0100</td></tr>
280 <tr class="memdesc:ga345461506c990125b1f2cbc62e3be22f"><td class="mdescLeft"> </td><td class="mdescRight">Loop end instruction executed. <br /></td></tr>
281 <tr class="separator:ga345461506c990125b1f2cbc62e3be22f"><td class="memSeparator" colspan="2"> </td></tr>
282 <tr class="memitem:ga6a1d9f84bda091e96843665ff3913b50"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga6a1d9f84bda091e96843665ff3913b50">ARM_PMU_LE_SPEC</a>   0x0101</td></tr>
283 <tr class="memdesc:ga6a1d9f84bda091e96843665ff3913b50"><td class="mdescLeft"> </td><td class="mdescRight">Loop end instruction speculatively executed. <br /></td></tr>
284 <tr class="separator:ga6a1d9f84bda091e96843665ff3913b50"><td class="memSeparator" colspan="2"> </td></tr>
285 <tr class="memitem:ga6979efa69af7d0e62cc3e2f88b0155b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga6979efa69af7d0e62cc3e2f88b0155b8">ARM_PMU_LL_CACHE_MISS_RD</a>   0x0037</td></tr>
286 <tr class="memdesc:ga6979efa69af7d0e62cc3e2f88b0155b8"><td class="mdescLeft"> </td><td class="mdescRight">Last level data cache read miss. <br /></td></tr>
287 <tr class="separator:ga6979efa69af7d0e62cc3e2f88b0155b8"><td class="memSeparator" colspan="2"> </td></tr>
288 <tr class="memitem:ga902562d8161fffd45726dc4cc8727545"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga902562d8161fffd45726dc4cc8727545">ARM_PMU_LL_CACHE_RD</a>   0x0036</td></tr>
289 <tr class="memdesc:ga902562d8161fffd45726dc4cc8727545"><td class="mdescLeft"> </td><td class="mdescRight">Last level data cache read. <br /></td></tr>
290 <tr class="separator:ga902562d8161fffd45726dc4cc8727545"><td class="memSeparator" colspan="2"> </td></tr>
291 <tr class="memitem:gab3852c2b3d59af106b9db7ea2c20c367"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab3852c2b3d59af106b9db7ea2c20c367">ARM_PMU_MEM_ACCESS</a>   0x0013</td></tr>
292 <tr class="memdesc:gab3852c2b3d59af106b9db7ea2c20c367"><td class="mdescLeft"> </td><td class="mdescRight">Data memory access. <br /></td></tr>
293 <tr class="separator:gab3852c2b3d59af106b9db7ea2c20c367"><td class="memSeparator" colspan="2"> </td></tr>
294 <tr class="memitem:ga2c8d23cc64e87b2044bb39bf8d0bc1b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga2c8d23cc64e87b2044bb39bf8d0bc1b1">ARM_PMU_MEMORY_ERROR</a>   0x001A</td></tr>
295 <tr class="memdesc:ga2c8d23cc64e87b2044bb39bf8d0bc1b1"><td class="mdescLeft"> </td><td class="mdescRight">Local memory error. <br /></td></tr>
296 <tr class="separator:ga2c8d23cc64e87b2044bb39bf8d0bc1b1"><td class="memSeparator" colspan="2"> </td></tr>
297 <tr class="memitem:gaa4c408a006a04e95ade26922669b6695"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaa4c408a006a04e95ade26922669b6695">ARM_PMU_MVE_FP_HP_RETIRED</a>   0x0208</td></tr>
298 <tr class="memdesc:gaa4c408a006a04e95ade26922669b6695"><td class="mdescLeft"> </td><td class="mdescRight">MVE half-precision floating-point instruction architecturally executed. <br /></td></tr>
299 <tr class="separator:gaa4c408a006a04e95ade26922669b6695"><td class="memSeparator" colspan="2"> </td></tr>
300 <tr class="memitem:gaf01d187b0cbf418d1fac55dd0ddd0827"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf01d187b0cbf418d1fac55dd0ddd0827">ARM_PMU_MVE_FP_HP_SPEC</a>   0x0209</td></tr>
301 <tr class="memdesc:gaf01d187b0cbf418d1fac55dd0ddd0827"><td class="mdescLeft"> </td><td class="mdescRight">MVE half-precision floating-point instruction speculatively executed. <br /></td></tr>
302 <tr class="separator:gaf01d187b0cbf418d1fac55dd0ddd0827"><td class="memSeparator" colspan="2"> </td></tr>
303 <tr class="memitem:gac2dc7d92627b3caa391725a3f080288c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gac2dc7d92627b3caa391725a3f080288c">ARM_PMU_MVE_FP_MAC_RETIRED</a>   0x0214</td></tr>
304 <tr class="memdesc:gac2dc7d92627b3caa391725a3f080288c"><td class="mdescLeft"> </td><td class="mdescRight">MVE floating-point multiply or multiply-accumulate instruction architecturally executed. <br /></td></tr>
305 <tr class="separator:gac2dc7d92627b3caa391725a3f080288c"><td class="memSeparator" colspan="2"> </td></tr>
306 <tr class="memitem:gaf5302b3278a862c9264171955328a59a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf5302b3278a862c9264171955328a59a">ARM_PMU_MVE_FP_MAC_SPEC</a>   0x0215</td></tr>
307 <tr class="memdesc:gaf5302b3278a862c9264171955328a59a"><td class="mdescLeft"> </td><td class="mdescRight">MVE floating-point multiply or multiply-accumulate instruction speculatively executed. <br /></td></tr>
308 <tr class="separator:gaf5302b3278a862c9264171955328a59a"><td class="memSeparator" colspan="2"> </td></tr>
309 <tr class="memitem:ga268b0bcbd30e8a928bd0f331fdf53ccf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga268b0bcbd30e8a928bd0f331fdf53ccf">ARM_PMU_MVE_FP_RETIRED</a>   0x0204</td></tr>
310 <tr class="memdesc:ga268b0bcbd30e8a928bd0f331fdf53ccf"><td class="mdescLeft"> </td><td class="mdescRight">MVE floating-point instruction architecturally executed. <br /></td></tr>
311 <tr class="separator:ga268b0bcbd30e8a928bd0f331fdf53ccf"><td class="memSeparator" colspan="2"> </td></tr>
312 <tr class="memitem:gab21171c50ebd1f304b11260edd015f52"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab21171c50ebd1f304b11260edd015f52">ARM_PMU_MVE_FP_SP_RETIRED</a>   0x020C</td></tr>
313 <tr class="memdesc:gab21171c50ebd1f304b11260edd015f52"><td class="mdescLeft"> </td><td class="mdescRight">MVE single-precision floating-point instruction architecturally executed. <br /></td></tr>
314 <tr class="separator:gab21171c50ebd1f304b11260edd015f52"><td class="memSeparator" colspan="2"> </td></tr>
315 <tr class="memitem:gae69e310892661af852ca2d4ec947d18a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gae69e310892661af852ca2d4ec947d18a">ARM_PMU_MVE_FP_SP_SPEC</a>   0x020D</td></tr>
316 <tr class="memdesc:gae69e310892661af852ca2d4ec947d18a"><td class="mdescLeft"> </td><td class="mdescRight">MVE single-precision floating-point instruction speculatively executed. <br /></td></tr>
317 <tr class="separator:gae69e310892661af852ca2d4ec947d18a"><td class="memSeparator" colspan="2"> </td></tr>
318 <tr class="memitem:gadf9cfd45b59acfc314ebc814a1bcdccd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gadf9cfd45b59acfc314ebc814a1bcdccd">ARM_PMU_MVE_FP_SPEC</a>   0x0205</td></tr>
319 <tr class="memdesc:gadf9cfd45b59acfc314ebc814a1bcdccd"><td class="mdescLeft"> </td><td class="mdescRight">MVE floating-point instruction speculatively executed. <br /></td></tr>
320 <tr class="separator:gadf9cfd45b59acfc314ebc814a1bcdccd"><td class="memSeparator" colspan="2"> </td></tr>
321 <tr class="memitem:ga3c1006bed2fb82b0749386261b397727"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga3c1006bed2fb82b0749386261b397727">ARM_PMU_MVE_INST_RETIRED</a>   0x0200</td></tr>
322 <tr class="memdesc:ga3c1006bed2fb82b0749386261b397727"><td class="mdescLeft"> </td><td class="mdescRight">MVE instruction architecturally executed. <br /></td></tr>
323 <tr class="separator:ga3c1006bed2fb82b0749386261b397727"><td class="memSeparator" colspan="2"> </td></tr>
324 <tr class="memitem:ga1e276b6872345eb3b043626a11f235c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga1e276b6872345eb3b043626a11f235c6">ARM_PMU_MVE_INST_SPEC</a>   0x0201</td></tr>
325 <tr class="memdesc:ga1e276b6872345eb3b043626a11f235c6"><td class="mdescLeft"> </td><td class="mdescRight">MVE instruction speculatively executed. <br /></td></tr>
326 <tr class="separator:ga1e276b6872345eb3b043626a11f235c6"><td class="memSeparator" colspan="2"> </td></tr>
327 <tr class="memitem:ga9248c93a3f19fddc93d3804a06f7238a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga9248c93a3f19fddc93d3804a06f7238a">ARM_PMU_MVE_INT_MAC_RETIRED</a>   0x0228</td></tr>
328 <tr class="memdesc:ga9248c93a3f19fddc93d3804a06f7238a"><td class="mdescLeft"> </td><td class="mdescRight">MVE multiply or multiply-accumulate instruction architecturally executed. <br /></td></tr>
329 <tr class="separator:ga9248c93a3f19fddc93d3804a06f7238a"><td class="memSeparator" colspan="2"> </td></tr>
330 <tr class="memitem:ga7036f00faa9183ae450a3e4d9d6f2bbf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga7036f00faa9183ae450a3e4d9d6f2bbf">ARM_PMU_MVE_INT_MAC_SPEC</a>   0x0229</td></tr>
331 <tr class="memdesc:ga7036f00faa9183ae450a3e4d9d6f2bbf"><td class="mdescLeft"> </td><td class="mdescRight">MVE multiply or multiply-accumulate instruction speculatively executed. <br /></td></tr>
332 <tr class="separator:ga7036f00faa9183ae450a3e4d9d6f2bbf"><td class="memSeparator" colspan="2"> </td></tr>
333 <tr class="memitem:ga5e3afafa91ebaeac0469a19ebb54719c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga5e3afafa91ebaeac0469a19ebb54719c">ARM_PMU_MVE_INT_RETIRED</a>   0x0224</td></tr>
334 <tr class="memdesc:ga5e3afafa91ebaeac0469a19ebb54719c"><td class="mdescLeft"> </td><td class="mdescRight">MVE integer instruction architecturally executed. <br /></td></tr>
335 <tr class="separator:ga5e3afafa91ebaeac0469a19ebb54719c"><td class="memSeparator" colspan="2"> </td></tr>
336 <tr class="memitem:ga16ed0bb1bb4718da93c41238da652d33"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga16ed0bb1bb4718da93c41238da652d33">ARM_PMU_MVE_INT_SPEC</a>   0x0225</td></tr>
337 <tr class="memdesc:ga16ed0bb1bb4718da93c41238da652d33"><td class="mdescLeft"> </td><td class="mdescRight">MVE integer instruction speculatively executed. <br /></td></tr>
338 <tr class="separator:ga16ed0bb1bb4718da93c41238da652d33"><td class="memSeparator" colspan="2"> </td></tr>
339 <tr class="memitem:ga8732a737f2b7adc43e3d1da7b3da92e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8732a737f2b7adc43e3d1da7b3da92e6">ARM_PMU_MVE_LD_CONTIG_RETIRED</a>   0x0248</td></tr>
340 <tr class="memdesc:ga8732a737f2b7adc43e3d1da7b3da92e6"><td class="mdescLeft"> </td><td class="mdescRight">MVE contiguous load instruction architecturally executed. <br /></td></tr>
341 <tr class="separator:ga8732a737f2b7adc43e3d1da7b3da92e6"><td class="memSeparator" colspan="2"> </td></tr>
342 <tr class="memitem:ga8e58fe07254256fa3bf3d42fa2062141"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8e58fe07254256fa3bf3d42fa2062141">ARM_PMU_MVE_LD_CONTIG_SPEC</a>   0x0249</td></tr>
343 <tr class="memdesc:ga8e58fe07254256fa3bf3d42fa2062141"><td class="mdescLeft"> </td><td class="mdescRight">MVE contiguous load instruction speculatively executed. <br /></td></tr>
344 <tr class="separator:ga8e58fe07254256fa3bf3d42fa2062141"><td class="memSeparator" colspan="2"> </td></tr>
345 <tr class="memitem:ga50fb13c874b3f5e2b9ed9c320a36452c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga50fb13c874b3f5e2b9ed9c320a36452c">ARM_PMU_MVE_LD_MULTI_RETIRED</a>   0x0260</td></tr>
346 <tr class="memdesc:ga50fb13c874b3f5e2b9ed9c320a36452c"><td class="mdescLeft"> </td><td class="mdescRight">MVE memory load instruction targeting multiple registers architecturally executed. <br /></td></tr>
347 <tr class="separator:ga50fb13c874b3f5e2b9ed9c320a36452c"><td class="memSeparator" colspan="2"> </td></tr>
348 <tr class="memitem:gaf2d4e3d1f06d97899de7fa791477d62b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf2d4e3d1f06d97899de7fa791477d62b">ARM_PMU_MVE_LD_MULTI_SPEC</a>   0x0261</td></tr>
349 <tr class="memdesc:gaf2d4e3d1f06d97899de7fa791477d62b"><td class="mdescLeft"> </td><td class="mdescRight">MVE memory load instruction targeting multiple registers speculatively executed. <br /></td></tr>
350 <tr class="separator:gaf2d4e3d1f06d97899de7fa791477d62b"><td class="memSeparator" colspan="2"> </td></tr>
351 <tr class="memitem:gaaf2ce8c0ea4c03c934aac6afc31fc5ff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaaf2ce8c0ea4c03c934aac6afc31fc5ff">ARM_PMU_MVE_LD_NONCONTIG_RETIRED</a>   0x0254</td></tr>
352 <tr class="memdesc:gaaf2ce8c0ea4c03c934aac6afc31fc5ff"><td class="mdescLeft"> </td><td class="mdescRight">MVE non-contiguous load instruction architecturally executed. <br /></td></tr>
353 <tr class="separator:gaaf2ce8c0ea4c03c934aac6afc31fc5ff"><td class="memSeparator" colspan="2"> </td></tr>
354 <tr class="memitem:gadbcb82b7924b7bbee5c0d42a3de38572"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gadbcb82b7924b7bbee5c0d42a3de38572">ARM_PMU_MVE_LD_NONCONTIG_SPEC</a>   0x0255</td></tr>
355 <tr class="memdesc:gadbcb82b7924b7bbee5c0d42a3de38572"><td class="mdescLeft"> </td><td class="mdescRight">MVE non-contiguous load instruction speculatively executed. <br /></td></tr>
356 <tr class="separator:gadbcb82b7924b7bbee5c0d42a3de38572"><td class="memSeparator" colspan="2"> </td></tr>
357 <tr class="memitem:gaa3379a51350a2fda8d8ab6d7795baa7a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaa3379a51350a2fda8d8ab6d7795baa7a">ARM_PMU_MVE_LD_RETIRED</a>   0x023C</td></tr>
358 <tr class="memdesc:gaa3379a51350a2fda8d8ab6d7795baa7a"><td class="mdescLeft"> </td><td class="mdescRight">MVE load instruction architecturally executed. <br /></td></tr>
359 <tr class="separator:gaa3379a51350a2fda8d8ab6d7795baa7a"><td class="memSeparator" colspan="2"> </td></tr>
360 <tr class="memitem:ga78a6f89ab30ed01f7d8388eda697b4f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga78a6f89ab30ed01f7d8388eda697b4f8">ARM_PMU_MVE_LD_SPEC</a>   0x023D</td></tr>
361 <tr class="memdesc:ga78a6f89ab30ed01f7d8388eda697b4f8"><td class="mdescLeft"> </td><td class="mdescRight">MVE load instruction speculatively executed. <br /></td></tr>
362 <tr class="separator:ga78a6f89ab30ed01f7d8388eda697b4f8"><td class="memSeparator" colspan="2"> </td></tr>
363 <tr class="memitem:ga26ed05deaa7b993904300069f0ecfac4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga26ed05deaa7b993904300069f0ecfac4">ARM_PMU_MVE_LD_UNALIGNED_RETIRED</a>   0x0290</td></tr>
364 <tr class="memdesc:ga26ed05deaa7b993904300069f0ecfac4"><td class="mdescLeft"> </td><td class="mdescRight">MVE unaligned load instruction architecturally executed. <br /></td></tr>
365 <tr class="separator:ga26ed05deaa7b993904300069f0ecfac4"><td class="memSeparator" colspan="2"> </td></tr>
366 <tr class="memitem:gadc3bd0f32e0a08bba2d533479a59bd6e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gadc3bd0f32e0a08bba2d533479a59bd6e">ARM_PMU_MVE_LD_UNALIGNED_SPEC</a>   0x0291</td></tr>
367 <tr class="memdesc:gadc3bd0f32e0a08bba2d533479a59bd6e"><td class="mdescLeft"> </td><td class="mdescRight">MVE unaligned load instruction speculatively executed. <br /></td></tr>
368 <tr class="separator:gadc3bd0f32e0a08bba2d533479a59bd6e"><td class="memSeparator" colspan="2"> </td></tr>
369 <tr class="memitem:ga8acf6a66c63798b76608caf52c96658d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8acf6a66c63798b76608caf52c96658d">ARM_PMU_MVE_LDST_CONTIG_RETIRED</a>   0x0244</td></tr>
370 <tr class="memdesc:ga8acf6a66c63798b76608caf52c96658d"><td class="mdescLeft"> </td><td class="mdescRight">MVE contiguous load or store instruction architecturally executed. <br /></td></tr>
371 <tr class="separator:ga8acf6a66c63798b76608caf52c96658d"><td class="memSeparator" colspan="2"> </td></tr>
372 <tr class="memitem:ga5a83ef6a52739e1d223be503bbdaaab6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga5a83ef6a52739e1d223be503bbdaaab6">ARM_PMU_MVE_LDST_CONTIG_SPEC</a>   0x0245</td></tr>
373 <tr class="memdesc:ga5a83ef6a52739e1d223be503bbdaaab6"><td class="mdescLeft"> </td><td class="mdescRight">MVE contiguous load or store instruction speculatively executed. <br /></td></tr>
374 <tr class="separator:ga5a83ef6a52739e1d223be503bbdaaab6"><td class="memSeparator" colspan="2"> </td></tr>
375 <tr class="memitem:ga7d669378441408fc21aa551e483866cb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga7d669378441408fc21aa551e483866cb">ARM_PMU_MVE_LDST_MULTI_RETIRED</a>   0x025C</td></tr>
376 <tr class="memdesc:ga7d669378441408fc21aa551e483866cb"><td class="mdescLeft"> </td><td class="mdescRight">MVE memory instruction targeting multiple registers architecturally executed. <br /></td></tr>
377 <tr class="separator:ga7d669378441408fc21aa551e483866cb"><td class="memSeparator" colspan="2"> </td></tr>
378 <tr class="memitem:ga7ea46cde08cb0cc4a46ef23835fb5aac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga7ea46cde08cb0cc4a46ef23835fb5aac">ARM_PMU_MVE_LDST_MULTI_SPEC</a>   0x025D</td></tr>
379 <tr class="memdesc:ga7ea46cde08cb0cc4a46ef23835fb5aac"><td class="mdescLeft"> </td><td class="mdescRight">MVE memory instruction targeting multiple registers speculatively executed. <br /></td></tr>
380 <tr class="separator:ga7ea46cde08cb0cc4a46ef23835fb5aac"><td class="memSeparator" colspan="2"> </td></tr>
381 <tr class="memitem:ga7065b7f0aea461858b72912d22c329f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga7065b7f0aea461858b72912d22c329f2">ARM_PMU_MVE_LDST_NONCONTIG_RETIRED</a>   0x0250</td></tr>
382 <tr class="memdesc:ga7065b7f0aea461858b72912d22c329f2"><td class="mdescLeft"> </td><td class="mdescRight">MVE non-contiguous load or store instruction architecturally executed. <br /></td></tr>
383 <tr class="separator:ga7065b7f0aea461858b72912d22c329f2"><td class="memSeparator" colspan="2"> </td></tr>
384 <tr class="memitem:ga193605eb52709741d91a64e3ad1a5894"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga193605eb52709741d91a64e3ad1a5894">ARM_PMU_MVE_LDST_NONCONTIG_SPEC</a>   0x0251</td></tr>
385 <tr class="memdesc:ga193605eb52709741d91a64e3ad1a5894"><td class="mdescLeft"> </td><td class="mdescRight">MVE non-contiguous load or store instruction speculatively executed. <br /></td></tr>
386 <tr class="separator:ga193605eb52709741d91a64e3ad1a5894"><td class="memSeparator" colspan="2"> </td></tr>
387 <tr class="memitem:ga7d7d465a6c64400c49f93b6c8152296f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga7d7d465a6c64400c49f93b6c8152296f">ARM_PMU_MVE_LDST_RETIRED</a>   0x0238</td></tr>
388 <tr class="memdesc:ga7d7d465a6c64400c49f93b6c8152296f"><td class="mdescLeft"> </td><td class="mdescRight">MVE load or store instruction architecturally executed. <br /></td></tr>
389 <tr class="separator:ga7d7d465a6c64400c49f93b6c8152296f"><td class="memSeparator" colspan="2"> </td></tr>
390 <tr class="memitem:gaa98a18c06bd13daf2df6f89219ec68d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaa98a18c06bd13daf2df6f89219ec68d5">ARM_PMU_MVE_LDST_SPEC</a>   0x0239</td></tr>
391 <tr class="memdesc:gaa98a18c06bd13daf2df6f89219ec68d5"><td class="mdescLeft"> </td><td class="mdescRight">MVE load or store instruction speculatively executed. <br /></td></tr>
392 <tr class="separator:gaa98a18c06bd13daf2df6f89219ec68d5"><td class="memSeparator" colspan="2"> </td></tr>
393 <tr class="memitem:ga627920bebd935709655687d844848934"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga627920bebd935709655687d844848934">ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED</a>   0x0298</td></tr>
394 <tr class="memdesc:ga627920bebd935709655687d844848934"><td class="mdescLeft"> </td><td class="mdescRight">MVE unaligned noncontiguous load or store instruction architecturally executed. <br /></td></tr>
395 <tr class="separator:ga627920bebd935709655687d844848934"><td class="memSeparator" colspan="2"> </td></tr>
396 <tr class="memitem:gaf9ebeb1f49dba56d8f90f9bd5d3da58e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf9ebeb1f49dba56d8f90f9bd5d3da58e">ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC</a>   0x0299</td></tr>
397 <tr class="memdesc:gaf9ebeb1f49dba56d8f90f9bd5d3da58e"><td class="mdescLeft"> </td><td class="mdescRight">MVE unaligned noncontiguous load or store instruction speculatively executed. <br /></td></tr>
398 <tr class="separator:gaf9ebeb1f49dba56d8f90f9bd5d3da58e"><td class="memSeparator" colspan="2"> </td></tr>
399 <tr class="memitem:gaf358a9ed5c83a10cb695d9b19b1b3bc1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf358a9ed5c83a10cb695d9b19b1b3bc1">ARM_PMU_MVE_LDST_UNALIGNED_RETIRED</a>   0x028C</td></tr>
400 <tr class="memdesc:gaf358a9ed5c83a10cb695d9b19b1b3bc1"><td class="mdescLeft"> </td><td class="mdescRight">MVE unaligned memory load or store instruction architecturally executed. <br /></td></tr>
401 <tr class="separator:gaf358a9ed5c83a10cb695d9b19b1b3bc1"><td class="memSeparator" colspan="2"> </td></tr>
402 <tr class="memitem:gab2264786bed578c89109859b55909c76"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab2264786bed578c89109859b55909c76">ARM_PMU_MVE_LDST_UNALIGNED_SPEC</a>   0x028D</td></tr>
403 <tr class="memdesc:gab2264786bed578c89109859b55909c76"><td class="mdescLeft"> </td><td class="mdescRight">MVE unaligned memory load or store instruction speculatively executed. <br /></td></tr>
404 <tr class="separator:gab2264786bed578c89109859b55909c76"><td class="memSeparator" colspan="2"> </td></tr>
405 <tr class="memitem:ga01b4792990494b8f084ee00933a1adb0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga01b4792990494b8f084ee00933a1adb0">ARM_PMU_MVE_PRED</a>   0x02B8</td></tr>
406 <tr class="memdesc:ga01b4792990494b8f084ee00933a1adb0"><td class="mdescLeft"> </td><td class="mdescRight">Cycles where one or more predicated beats architecturally executed. <br /></td></tr>
407 <tr class="separator:ga01b4792990494b8f084ee00933a1adb0"><td class="memSeparator" colspan="2"> </td></tr>
408 <tr class="memitem:gacb3c0b922eae9aac321df97ec889e0ed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gacb3c0b922eae9aac321df97ec889e0ed">ARM_PMU_MVE_ST_CONTIG_RETIRED</a>   0x024C</td></tr>
409 <tr class="memdesc:gacb3c0b922eae9aac321df97ec889e0ed"><td class="mdescLeft"> </td><td class="mdescRight">MVE contiguous store instruction architecturally executed. <br /></td></tr>
410 <tr class="separator:gacb3c0b922eae9aac321df97ec889e0ed"><td class="memSeparator" colspan="2"> </td></tr>
411 <tr class="memitem:ga02cd64b9444e4babc7b69e8571d39bdd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga02cd64b9444e4babc7b69e8571d39bdd">ARM_PMU_MVE_ST_CONTIG_SPEC</a>   0x024D</td></tr>
412 <tr class="memdesc:ga02cd64b9444e4babc7b69e8571d39bdd"><td class="mdescLeft"> </td><td class="mdescRight">MVE contiguous store instruction speculatively executed. <br /></td></tr>
413 <tr class="separator:ga02cd64b9444e4babc7b69e8571d39bdd"><td class="memSeparator" colspan="2"> </td></tr>
414 <tr class="memitem:ga76057cbda353b4ad6fbc3b6a63c193a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga76057cbda353b4ad6fbc3b6a63c193a5">ARM_PMU_MVE_ST_MULTI_RETIRED</a>   0x0261</td></tr>
415 <tr class="memdesc:ga76057cbda353b4ad6fbc3b6a63c193a5"><td class="mdescLeft"> </td><td class="mdescRight">MVE memory store instruction targeting multiple registers architecturally executed. <br /></td></tr>
416 <tr class="separator:ga76057cbda353b4ad6fbc3b6a63c193a5"><td class="memSeparator" colspan="2"> </td></tr>
417 <tr class="memitem:gaf6a14402c79dba8fa765e8663dd0734d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf6a14402c79dba8fa765e8663dd0734d">ARM_PMU_MVE_ST_MULTI_SPEC</a>   0x0265</td></tr>
418 <tr class="memdesc:gaf6a14402c79dba8fa765e8663dd0734d"><td class="mdescLeft"> </td><td class="mdescRight">MVE memory store instruction targeting multiple registers speculatively executed. <br /></td></tr>
419 <tr class="separator:gaf6a14402c79dba8fa765e8663dd0734d"><td class="memSeparator" colspan="2"> </td></tr>
420 <tr class="memitem:ga8271f415ecc7573b57e82a24aec86ef1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8271f415ecc7573b57e82a24aec86ef1">ARM_PMU_MVE_ST_NONCONTIG_RETIRED</a>   0x0258</td></tr>
421 <tr class="memdesc:ga8271f415ecc7573b57e82a24aec86ef1"><td class="mdescLeft"> </td><td class="mdescRight">MVE non-contiguous store instruction architecturally executed. <br /></td></tr>
422 <tr class="separator:ga8271f415ecc7573b57e82a24aec86ef1"><td class="memSeparator" colspan="2"> </td></tr>
423 <tr class="memitem:ga059327c80f396918a9f8192bcd0fa4a8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga059327c80f396918a9f8192bcd0fa4a8">ARM_PMU_MVE_ST_NONCONTIG_SPEC</a>   0x0259</td></tr>
424 <tr class="memdesc:ga059327c80f396918a9f8192bcd0fa4a8"><td class="mdescLeft"> </td><td class="mdescRight">MVE non-contiguous store instruction speculatively executed. <br /></td></tr>
425 <tr class="separator:ga059327c80f396918a9f8192bcd0fa4a8"><td class="memSeparator" colspan="2"> </td></tr>
426 <tr class="memitem:gad8d0079977fa97de4ee263703f1b2908"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gad8d0079977fa97de4ee263703f1b2908">ARM_PMU_MVE_ST_RETIRED</a>   0x0240</td></tr>
427 <tr class="memdesc:gad8d0079977fa97de4ee263703f1b2908"><td class="mdescLeft"> </td><td class="mdescRight">MVE store instruction architecturally executed. <br /></td></tr>
428 <tr class="separator:gad8d0079977fa97de4ee263703f1b2908"><td class="memSeparator" colspan="2"> </td></tr>
429 <tr class="memitem:gabd3984d299b5416aac8d630722680c55"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gabd3984d299b5416aac8d630722680c55">ARM_PMU_MVE_ST_SPEC</a>   0x0241</td></tr>
430 <tr class="memdesc:gabd3984d299b5416aac8d630722680c55"><td class="mdescLeft"> </td><td class="mdescRight">MVE store instruction speculatively executed. <br /></td></tr>
431 <tr class="separator:gabd3984d299b5416aac8d630722680c55"><td class="memSeparator" colspan="2"> </td></tr>
432 <tr class="memitem:ga391afd8cb92cc65161b13ee3a3256d40"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga391afd8cb92cc65161b13ee3a3256d40">ARM_PMU_MVE_ST_UNALIGNED_RETIRED</a>   0x0294</td></tr>
433 <tr class="memdesc:ga391afd8cb92cc65161b13ee3a3256d40"><td class="mdescLeft"> </td><td class="mdescRight">MVE unaligned store instruction architecturally executed. <br /></td></tr>
434 <tr class="separator:ga391afd8cb92cc65161b13ee3a3256d40"><td class="memSeparator" colspan="2"> </td></tr>
435 <tr class="memitem:ga21bf105499df85196b4137cb075a6fbe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga21bf105499df85196b4137cb075a6fbe">ARM_PMU_MVE_ST_UNALIGNED_SPEC</a>   0x0295</td></tr>
436 <tr class="memdesc:ga21bf105499df85196b4137cb075a6fbe"><td class="mdescLeft"> </td><td class="mdescRight">MVE unaligned store instruction speculatively executed. <br /></td></tr>
437 <tr class="separator:ga21bf105499df85196b4137cb075a6fbe"><td class="memSeparator" colspan="2"> </td></tr>
438 <tr class="memitem:ga2a45ec75b2011bd8375d89b7562b2de6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga2a45ec75b2011bd8375d89b7562b2de6">ARM_PMU_MVE_STALL</a>   0x02CC</td></tr>
439 <tr class="memdesc:ga2a45ec75b2011bd8375d89b7562b2de6"><td class="mdescLeft"> </td><td class="mdescRight">Stall cycles caused by an MVE instruction. <br /></td></tr>
440 <tr class="separator:ga2a45ec75b2011bd8375d89b7562b2de6"><td class="memSeparator" colspan="2"> </td></tr>
441 <tr class="memitem:ga9a1cfef96ec7cd70acf134e368d8826a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga9a1cfef96ec7cd70acf134e368d8826a">ARM_PMU_MVE_STALL_BREAK</a>   0x02D3</td></tr>
442 <tr class="memdesc:ga9a1cfef96ec7cd70acf134e368d8826a"><td class="mdescLeft"> </td><td class="mdescRight">Stall cycles caused by an MVE chain break. <br /></td></tr>
443 <tr class="separator:ga9a1cfef96ec7cd70acf134e368d8826a"><td class="memSeparator" colspan="2"> </td></tr>
444 <tr class="memitem:ga29bc4c2e820914e94e2eb68a6a3352b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga29bc4c2e820914e94e2eb68a6a3352b9">ARM_PMU_MVE_STALL_DEPENDENCY</a>   0x02D4</td></tr>
445 <tr class="memdesc:ga29bc4c2e820914e94e2eb68a6a3352b9"><td class="mdescLeft"> </td><td class="mdescRight">Stall cycles caused by MVE register dependency. <br /></td></tr>
446 <tr class="separator:ga29bc4c2e820914e94e2eb68a6a3352b9"><td class="memSeparator" colspan="2"> </td></tr>
447 <tr class="memitem:ga8f4949084efce03d09bf5ba74cc91edd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8f4949084efce03d09bf5ba74cc91edd">ARM_PMU_MVE_STALL_RESOURCE</a>   0x02CD</td></tr>
448 <tr class="memdesc:ga8f4949084efce03d09bf5ba74cc91edd"><td class="mdescLeft"> </td><td class="mdescRight">Stall cycles caused by an MVE instruction because of resource conflicts. <br /></td></tr>
449 <tr class="separator:ga8f4949084efce03d09bf5ba74cc91edd"><td class="memSeparator" colspan="2"> </td></tr>
450 <tr class="memitem:ga7e76060791618f9b4d49ad493cfb6ba9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga7e76060791618f9b4d49ad493cfb6ba9">ARM_PMU_MVE_STALL_RESOURCE_FP</a>   0x02CF</td></tr>
451 <tr class="memdesc:ga7e76060791618f9b4d49ad493cfb6ba9"><td class="mdescLeft"> </td><td class="mdescRight">Stall cycles caused by an MVE instruction because of floating-point resource conflicts. <br /></td></tr>
452 <tr class="separator:ga7e76060791618f9b4d49ad493cfb6ba9"><td class="memSeparator" colspan="2"> </td></tr>
453 <tr class="memitem:gaef33b3ff7f12d31238ff4dded5e67a11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaef33b3ff7f12d31238ff4dded5e67a11">ARM_PMU_MVE_STALL_RESOURCE_INT</a>   0x02D0</td></tr>
454 <tr class="memdesc:gaef33b3ff7f12d31238ff4dded5e67a11"><td class="mdescLeft"> </td><td class="mdescRight">Stall cycles caused by an MVE instruction because of integer resource conflicts. <br /></td></tr>
455 <tr class="separator:gaef33b3ff7f12d31238ff4dded5e67a11"><td class="memSeparator" colspan="2"> </td></tr>
456 <tr class="memitem:gab486f5753edd9f10b0f100ff78944dd3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab486f5753edd9f10b0f100ff78944dd3">ARM_PMU_MVE_STALL_RESOURCE_MEM</a>   0x02CE</td></tr>
457 <tr class="memdesc:gab486f5753edd9f10b0f100ff78944dd3"><td class="mdescLeft"> </td><td class="mdescRight">Stall cycles caused by an MVE instruction because of memory resource conflicts. <br /></td></tr>
458 <tr class="separator:gab486f5753edd9f10b0f100ff78944dd3"><td class="memSeparator" colspan="2"> </td></tr>
459 <tr class="memitem:ga77fad5ad424271ed63fec98af071bb79"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga77fad5ad424271ed63fec98af071bb79">ARM_PMU_MVE_VREDUCE_FP_RETIRED</a>   0x02A4</td></tr>
460 <tr class="memdesc:ga77fad5ad424271ed63fec98af071bb79"><td class="mdescLeft"> </td><td class="mdescRight">MVE floating-point vector reduction instruction architecturally executed. <br /></td></tr>
461 <tr class="separator:ga77fad5ad424271ed63fec98af071bb79"><td class="memSeparator" colspan="2"> </td></tr>
462 <tr class="memitem:gaa07c698f58c622d234a0007249717265"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaa07c698f58c622d234a0007249717265">ARM_PMU_MVE_VREDUCE_FP_SPEC</a>   0x02A5</td></tr>
463 <tr class="memdesc:gaa07c698f58c622d234a0007249717265"><td class="mdescLeft"> </td><td class="mdescRight">MVE floating-point vector reduction instruction speculatively executed. <br /></td></tr>
464 <tr class="separator:gaa07c698f58c622d234a0007249717265"><td class="memSeparator" colspan="2"> </td></tr>
465 <tr class="memitem:ga649e7e81f0fd04ca6611f6a6c4035c57"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga649e7e81f0fd04ca6611f6a6c4035c57">ARM_PMU_MVE_VREDUCE_INT_RETIRED</a>   0x02A8</td></tr>
466 <tr class="memdesc:ga649e7e81f0fd04ca6611f6a6c4035c57"><td class="mdescLeft"> </td><td class="mdescRight">MVE integer vector reduction instruction architecturally executed. <br /></td></tr>
467 <tr class="separator:ga649e7e81f0fd04ca6611f6a6c4035c57"><td class="memSeparator" colspan="2"> </td></tr>
468 <tr class="memitem:ga5b6f0bcfd63207c7bab03ea20167dd4b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga5b6f0bcfd63207c7bab03ea20167dd4b">ARM_PMU_MVE_VREDUCE_INT_SPEC</a>   0x02A9</td></tr>
469 <tr class="memdesc:ga5b6f0bcfd63207c7bab03ea20167dd4b"><td class="mdescLeft"> </td><td class="mdescRight">MVE integer vector reduction instruction speculatively executed. <br /></td></tr>
470 <tr class="separator:ga5b6f0bcfd63207c7bab03ea20167dd4b"><td class="memSeparator" colspan="2"> </td></tr>
471 <tr class="memitem:ga9546b924daa3c62e5f117026de58ad94"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga9546b924daa3c62e5f117026de58ad94">ARM_PMU_MVE_VREDUCE_RETIRED</a>   0x02A0</td></tr>
472 <tr class="memdesc:ga9546b924daa3c62e5f117026de58ad94"><td class="mdescLeft"> </td><td class="mdescRight">MVE vector reduction instruction architecturally executed. <br /></td></tr>
473 <tr class="separator:ga9546b924daa3c62e5f117026de58ad94"><td class="memSeparator" colspan="2"> </td></tr>
474 <tr class="memitem:gac714f988ae45871b2865f82c11383b36"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gac714f988ae45871b2865f82c11383b36">ARM_PMU_MVE_VREDUCE_SPEC</a>   0x02A1</td></tr>
475 <tr class="memdesc:gac714f988ae45871b2865f82c11383b36"><td class="mdescLeft"> </td><td class="mdescRight">MVE vector reduction instruction speculatively executed. <br /></td></tr>
476 <tr class="separator:gac714f988ae45871b2865f82c11383b36"><td class="memSeparator" colspan="2"> </td></tr>
477 <tr class="memitem:ga2fe9d3ea67ce833bd6323e4ce1a4e894"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga2fe9d3ea67ce833bd6323e4ce1a4e894">ARM_PMU_OP_COMPLETE</a>   0x003A</td></tr>
478 <tr class="memdesc:ga2fe9d3ea67ce833bd6323e4ce1a4e894"><td class="mdescLeft"> </td><td class="mdescRight">Operation retired. <br /></td></tr>
479 <tr class="separator:ga2fe9d3ea67ce833bd6323e4ce1a4e894"><td class="memSeparator" colspan="2"> </td></tr>
480 <tr class="memitem:ga6c59149e9b1754987b44b62092bc9f09"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga6c59149e9b1754987b44b62092bc9f09">ARM_PMU_OP_SPEC</a>   0x003B</td></tr>
481 <tr class="memdesc:ga6c59149e9b1754987b44b62092bc9f09"><td class="mdescLeft"> </td><td class="mdescRight">Operation speculatively executed. <br /></td></tr>
482 <tr class="separator:ga6c59149e9b1754987b44b62092bc9f09"><td class="memSeparator" colspan="2"> </td></tr>
483 <tr class="memitem:ga54fd2c392399221077c67866a395e587"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga54fd2c392399221077c67866a395e587">ARM_PMU_PC_WRITE_RETIRED</a>   0x000C</td></tr>
484 <tr class="memdesc:ga54fd2c392399221077c67866a395e587"><td class="mdescLeft"> </td><td class="mdescRight">Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass. <br /></td></tr>
485 <tr class="separator:ga54fd2c392399221077c67866a395e587"><td class="memSeparator" colspan="2"> </td></tr>
486 <tr class="memitem:gaaae2c32a8ecd36b59ac98cf8e23b3cab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaaae2c32a8ecd36b59ac98cf8e23b3cab">ARM_PMU_SE_CALL_NS</a>   0x0115</td></tr>
487 <tr class="memdesc:gaaae2c32a8ecd36b59ac98cf8e23b3cab"><td class="mdescLeft"> </td><td class="mdescRight">Call to non-secure function, resulting in Security state change. <br /></td></tr>
488 <tr class="separator:gaaae2c32a8ecd36b59ac98cf8e23b3cab"><td class="memSeparator" colspan="2"> </td></tr>
489 <tr class="memitem:gad3ba2effbe303ca3fafdbc022fe206c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gad3ba2effbe303ca3fafdbc022fe206c1">ARM_PMU_SE_CALL_S</a>   0x0114</td></tr>
490 <tr class="memdesc:gad3ba2effbe303ca3fafdbc022fe206c1"><td class="mdescLeft"> </td><td class="mdescRight">Call to secure function, resulting in Security state change. <br /></td></tr>
491 <tr class="separator:gad3ba2effbe303ca3fafdbc022fe206c1"><td class="memSeparator" colspan="2"> </td></tr>
492 <tr class="memitem:ga8179d1144f8ec993bd1343e276d7b49b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8179d1144f8ec993bd1343e276d7b49b">ARM_PMU_ST_RETIRED</a>   0x0007</td></tr>
493 <tr class="memdesc:ga8179d1144f8ec993bd1343e276d7b49b"><td class="mdescLeft"> </td><td class="mdescRight">Memory-writing instruction architecturally executed and condition code check pass. <br /></td></tr>
494 <tr class="separator:ga8179d1144f8ec993bd1343e276d7b49b"><td class="memSeparator" colspan="2"> </td></tr>
495 <tr class="memitem:ga8bf75efa06a125ee2dfa9a130e7ba9a8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8bf75efa06a125ee2dfa9a130e7ba9a8">ARM_PMU_STALL</a>   0x003C</td></tr>
496 <tr class="memdesc:ga8bf75efa06a125ee2dfa9a130e7ba9a8"><td class="mdescLeft"> </td><td class="mdescRight">Stall cycle for instruction or operation not sent for execution. <br /></td></tr>
497 <tr class="separator:ga8bf75efa06a125ee2dfa9a130e7ba9a8"><td class="memSeparator" colspan="2"> </td></tr>
498 <tr class="memitem:ga8737bee352820bd7d1bc8e5e4260143c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8737bee352820bd7d1bc8e5e4260143c">ARM_PMU_STALL_BACKEND</a>   0x0024</td></tr>
499 <tr class="memdesc:ga8737bee352820bd7d1bc8e5e4260143c"><td class="mdescLeft"> </td><td class="mdescRight">No operation issued because of the backend. <br /></td></tr>
500 <tr class="separator:ga8737bee352820bd7d1bc8e5e4260143c"><td class="memSeparator" colspan="2"> </td></tr>
501 <tr class="memitem:ga5b068593baa831348664dfa7d44f5483"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga5b068593baa831348664dfa7d44f5483">ARM_PMU_STALL_FRONTEND</a>   0x0023</td></tr>
502 <tr class="memdesc:ga5b068593baa831348664dfa7d44f5483"><td class="mdescLeft"> </td><td class="mdescRight">No operation issued because of the frontend. <br /></td></tr>
503 <tr class="separator:ga5b068593baa831348664dfa7d44f5483"><td class="memSeparator" colspan="2"> </td></tr>
504 <tr class="memitem:ga197b491f691110fb52aef4291782b6ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga197b491f691110fb52aef4291782b6ab">ARM_PMU_STALL_OP</a>   0x003F</td></tr>
505 <tr class="memdesc:ga197b491f691110fb52aef4291782b6ab"><td class="mdescLeft"> </td><td class="mdescRight">Instruction or operation slots not occupied each cycle. <br /></td></tr>
506 <tr class="separator:ga197b491f691110fb52aef4291782b6ab"><td class="memSeparator" colspan="2"> </td></tr>
507 <tr class="memitem:ga9700ec74727a9fe3cd4cd40736628a23"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga9700ec74727a9fe3cd4cd40736628a23">ARM_PMU_STALL_OP_BACKEND</a>   0x003D</td></tr>
508 <tr class="memdesc:ga9700ec74727a9fe3cd4cd40736628a23"><td class="mdescLeft"> </td><td class="mdescRight">Stall cycle for instruction or operation not sent for execution due to pipeline backend. <br /></td></tr>
509 <tr class="separator:ga9700ec74727a9fe3cd4cd40736628a23"><td class="memSeparator" colspan="2"> </td></tr>
510 <tr class="memitem:ga69cfd3558cf6c6f3bb621ee75430427c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga69cfd3558cf6c6f3bb621ee75430427c">ARM_PMU_STALL_OP_FRONTEND</a>   0x003E</td></tr>
511 <tr class="memdesc:ga69cfd3558cf6c6f3bb621ee75430427c"><td class="mdescLeft"> </td><td class="mdescRight">Stall cycle for instruction or operation not sent for execution due to pipeline frontend. <br /></td></tr>
512 <tr class="separator:ga69cfd3558cf6c6f3bb621ee75430427c"><td class="memSeparator" colspan="2"> </td></tr>
513 <tr class="memitem:ga6e02b08550d7e9b273ff7913f1b57bea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga6e02b08550d7e9b273ff7913f1b57bea">ARM_PMU_SW_INCR</a>   0x0000</td></tr>
514 <tr class="memdesc:ga6e02b08550d7e9b273ff7913f1b57bea"><td class="mdescLeft"> </td><td class="mdescRight">Software update to the PMU_SWINC register, architecturally executed and condition code check pass. <br /></td></tr>
515 <tr class="separator:ga6e02b08550d7e9b273ff7913f1b57bea"><td class="memSeparator" colspan="2"> </td></tr>
516 <tr class="memitem:gadaa75dc2ccfbf7a2263da9a9011f1603"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gadaa75dc2ccfbf7a2263da9a9011f1603">ARM_PMU_TRCEXTOUT0</a>   0x4010</td></tr>
517 <tr class="memdesc:gadaa75dc2ccfbf7a2263da9a9011f1603"><td class="mdescLeft"> </td><td class="mdescRight">ETM external output 0. <br /></td></tr>
518 <tr class="separator:gadaa75dc2ccfbf7a2263da9a9011f1603"><td class="memSeparator" colspan="2"> </td></tr>
519 <tr class="memitem:ga47fe03fe6fe9bfebd98283cb57d94560"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga47fe03fe6fe9bfebd98283cb57d94560">ARM_PMU_TRCEXTOUT1</a>   0x4011</td></tr>
520 <tr class="memdesc:ga47fe03fe6fe9bfebd98283cb57d94560"><td class="mdescLeft"> </td><td class="mdescRight">ETM external output 1. <br /></td></tr>
521 <tr class="separator:ga47fe03fe6fe9bfebd98283cb57d94560"><td class="memSeparator" colspan="2"> </td></tr>
522 <tr class="memitem:gab80e47ffebc3ae6ed2952756b020dbb9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab80e47ffebc3ae6ed2952756b020dbb9">ARM_PMU_TRCEXTOUT2</a>   0x4012</td></tr>
523 <tr class="memdesc:gab80e47ffebc3ae6ed2952756b020dbb9"><td class="mdescLeft"> </td><td class="mdescRight">ETM external output 2. <br /></td></tr>
524 <tr class="separator:gab80e47ffebc3ae6ed2952756b020dbb9"><td class="memSeparator" colspan="2"> </td></tr>
525 <tr class="memitem:gad70a3b074efd967485ffbfd3e387051d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gad70a3b074efd967485ffbfd3e387051d">ARM_PMU_TRCEXTOUT3</a>   0x4013</td></tr>
526 <tr class="memdesc:gad70a3b074efd967485ffbfd3e387051d"><td class="mdescLeft"> </td><td class="mdescRight">ETM external output 3. <br /></td></tr>
527 <tr class="separator:gad70a3b074efd967485ffbfd3e387051d"><td class="memSeparator" colspan="2"> </td></tr>
528 <tr class="memitem:ga45d5ea86fdc015f4fc100462150c92da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga45d5ea86fdc015f4fc100462150c92da">ARM_PMU_UNALIGNED_LDST_RETIRED</a>   0x000F</td></tr>
529 <tr class="memdesc:ga45d5ea86fdc015f4fc100462150c92da"><td class="mdescLeft"> </td><td class="mdescRight">Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass. <br /></td></tr>
530 <tr class="separator:ga45d5ea86fdc015f4fc100462150c92da"><td class="memSeparator" colspan="2"> </td></tr>
532 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
533 <p>IDs for Armv8.1-M architecture defined events. </p>
534 <p>These events are available on all Armv8.1-M devices including a PMU. </p>
535 <h2 class="groupheader">Macro Definition Documentation</h2>
536 <a id="gaf2e0a38b7c0d63d1194f08478781a3f0" name="gaf2e0a38b7c0d63d1194f08478781a3f0"></a>
537 <h2 class="memtitle"><span class="permalink"><a href="#gaf2e0a38b7c0d63d1194f08478781a3f0">◆ </a></span>ARM_PMU_BF_CANCEL</h2>
539 <div class="memitem">
540 <div class="memproto">
541 <table class="memname">
543 <td class="memname">#define ARM_PMU_BF_CANCEL   0x0109</td>
546 </div><div class="memdoc">
548 <p>Branch future instruction not taken. </p>
552 <a id="gab8570f46393e3e44bb118591d33723f4" name="gab8570f46393e3e44bb118591d33723f4"></a>
553 <h2 class="memtitle"><span class="permalink"><a href="#gab8570f46393e3e44bb118591d33723f4">◆ </a></span>ARM_PMU_BF_RETIRED</h2>
555 <div class="memitem">
556 <div class="memproto">
557 <table class="memname">
559 <td class="memname">#define ARM_PMU_BF_RETIRED   0x0104</td>
562 </div><div class="memdoc">
564 <p>Branch future instruction architecturally executed and condition code check pass. </p>
568 <a id="ga6b1e4823d8b45678a29a5f54b859d4e3" name="ga6b1e4823d8b45678a29a5f54b859d4e3"></a>
569 <h2 class="memtitle"><span class="permalink"><a href="#ga6b1e4823d8b45678a29a5f54b859d4e3">◆ </a></span>ARM_PMU_BF_SPEC</h2>
571 <div class="memitem">
572 <div class="memproto">
573 <table class="memname">
575 <td class="memname">#define ARM_PMU_BF_SPEC   0x0105</td>
578 </div><div class="memdoc">
580 <p>Branch future instruction speculatively executed and condition code check pass. </p>
584 <a id="ga22bfb189fff7c1ea9f81097a543ed756" name="ga22bfb189fff7c1ea9f81097a543ed756"></a>
585 <h2 class="memtitle"><span class="permalink"><a href="#ga22bfb189fff7c1ea9f81097a543ed756">◆ </a></span>ARM_PMU_BR_IMMED_RETIRED</h2>
587 <div class="memitem">
588 <div class="memproto">
589 <table class="memname">
591 <td class="memname">#define ARM_PMU_BR_IMMED_RETIRED   0x000D</td>
594 </div><div class="memdoc">
596 <p>Immediate branch architecturally executed. </p>
600 <a id="gabfa921c85a61f0a21c9bee289e63c102" name="gabfa921c85a61f0a21c9bee289e63c102"></a>
601 <h2 class="memtitle"><span class="permalink"><a href="#gabfa921c85a61f0a21c9bee289e63c102">◆ </a></span>ARM_PMU_BR_MIS_PRED</h2>
603 <div class="memitem">
604 <div class="memproto">
605 <table class="memname">
607 <td class="memname">#define ARM_PMU_BR_MIS_PRED   0x0010</td>
610 </div><div class="memdoc">
612 <p>Mispredicted or not predicted branch speculatively executed. </p>
616 <a id="gae12baa616c5f0cdd081231fcf8cdad68" name="gae12baa616c5f0cdd081231fcf8cdad68"></a>
617 <h2 class="memtitle"><span class="permalink"><a href="#gae12baa616c5f0cdd081231fcf8cdad68">◆ </a></span>ARM_PMU_BR_MIS_PRED_RETIRED</h2>
619 <div class="memitem">
620 <div class="memproto">
621 <table class="memname">
623 <td class="memname">#define ARM_PMU_BR_MIS_PRED_RETIRED   0x0022</td>
626 </div><div class="memdoc">
628 <p>Mispredicted branch instruction architecturally executed. </p>
632 <a id="ga60ccf42eae576e2fde3b9e17a8defeaa" name="ga60ccf42eae576e2fde3b9e17a8defeaa"></a>
633 <h2 class="memtitle"><span class="permalink"><a href="#ga60ccf42eae576e2fde3b9e17a8defeaa">◆ </a></span>ARM_PMU_BR_PRED</h2>
635 <div class="memitem">
636 <div class="memproto">
637 <table class="memname">
639 <td class="memname">#define ARM_PMU_BR_PRED   0x0012</td>
642 </div><div class="memdoc">
644 <p>Predictable branch speculatively executed. </p>
648 <a id="gab3b505a8bcc2b2885626d2f2cd542b73" name="gab3b505a8bcc2b2885626d2f2cd542b73"></a>
649 <h2 class="memtitle"><span class="permalink"><a href="#gab3b505a8bcc2b2885626d2f2cd542b73">◆ </a></span>ARM_PMU_BR_RETIRED</h2>
651 <div class="memitem">
652 <div class="memproto">
653 <table class="memname">
655 <td class="memname">#define ARM_PMU_BR_RETIRED   0x0021</td>
658 </div><div class="memdoc">
660 <p>Branch instruction architecturally executed. </p>
664 <a id="gab717347b1c3601cffb9c99b43b2a45c5" name="gab717347b1c3601cffb9c99b43b2a45c5"></a>
665 <h2 class="memtitle"><span class="permalink"><a href="#gab717347b1c3601cffb9c99b43b2a45c5">◆ </a></span>ARM_PMU_BR_RETURN_RETIRED</h2>
667 <div class="memitem">
668 <div class="memproto">
669 <table class="memname">
671 <td class="memname">#define ARM_PMU_BR_RETURN_RETIRED   0x000E</td>
674 </div><div class="memdoc">
676 <p>Function return instruction architecturally executed and the condition code check pass. </p>
680 <a id="gaa681d3db56b42775093869b8fdf1abb9" name="gaa681d3db56b42775093869b8fdf1abb9"></a>
681 <h2 class="memtitle"><span class="permalink"><a href="#gaa681d3db56b42775093869b8fdf1abb9">◆ </a></span>ARM_PMU_BUS_ACCESS</h2>
683 <div class="memitem">
684 <div class="memproto">
685 <table class="memname">
687 <td class="memname">#define ARM_PMU_BUS_ACCESS   0x0019</td>
690 </div><div class="memdoc">
696 <a id="gae4c955416707f44f066ffd2560b9ae4c" name="gae4c955416707f44f066ffd2560b9ae4c"></a>
697 <h2 class="memtitle"><span class="permalink"><a href="#gae4c955416707f44f066ffd2560b9ae4c">◆ </a></span>ARM_PMU_BUS_CYCLES</h2>
699 <div class="memitem">
700 <div class="memproto">
701 <table class="memname">
703 <td class="memname">#define ARM_PMU_BUS_CYCLES   0x001D</td>
706 </div><div class="memdoc">
712 <a id="gaca14907c5a1e1f9915159bc4cf323cf0" name="gaca14907c5a1e1f9915159bc4cf323cf0"></a>
713 <h2 class="memtitle"><span class="permalink"><a href="#gaca14907c5a1e1f9915159bc4cf323cf0">◆ </a></span>ARM_PMU_CHAIN</h2>
715 <div class="memitem">
716 <div class="memproto">
717 <table class="memname">
719 <td class="memname">#define ARM_PMU_CHAIN   0x001E</td>
722 </div><div class="memdoc">
724 <p>For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE. </p>
728 <a id="ga550d524d435a653b2f46acc1380a5ace" name="ga550d524d435a653b2f46acc1380a5ace"></a>
729 <h2 class="memtitle"><span class="permalink"><a href="#ga550d524d435a653b2f46acc1380a5ace">◆ </a></span>ARM_PMU_CPU_CYCLES</h2>
731 <div class="memitem">
732 <div class="memproto">
733 <table class="memname">
735 <td class="memname">#define ARM_PMU_CPU_CYCLES   0x0011</td>
738 </div><div class="memdoc">
744 <a id="ga290974d72b8cac214f4e9a152ca64a56" name="ga290974d72b8cac214f4e9a152ca64a56"></a>
745 <h2 class="memtitle"><span class="permalink"><a href="#ga290974d72b8cac214f4e9a152ca64a56">◆ </a></span>ARM_PMU_CTI_TRIGOUT4</h2>
747 <div class="memitem">
748 <div class="memproto">
749 <table class="memname">
751 <td class="memname">#define ARM_PMU_CTI_TRIGOUT4   0x4018</td>
754 </div><div class="memdoc">
756 <p>Cross-trigger Interface output trigger 4. </p>
760 <a id="ga7a05420b7fae6f5c3d35e12a9846c7e2" name="ga7a05420b7fae6f5c3d35e12a9846c7e2"></a>
761 <h2 class="memtitle"><span class="permalink"><a href="#ga7a05420b7fae6f5c3d35e12a9846c7e2">◆ </a></span>ARM_PMU_CTI_TRIGOUT5</h2>
763 <div class="memitem">
764 <div class="memproto">
765 <table class="memname">
767 <td class="memname">#define ARM_PMU_CTI_TRIGOUT5   0x4019</td>
770 </div><div class="memdoc">
772 <p>Cross-trigger Interface output trigger 5. </p>
776 <a id="gade076a5ee512a14f8882d9aec5d3dc0b" name="gade076a5ee512a14f8882d9aec5d3dc0b"></a>
777 <h2 class="memtitle"><span class="permalink"><a href="#gade076a5ee512a14f8882d9aec5d3dc0b">◆ </a></span>ARM_PMU_CTI_TRIGOUT6</h2>
779 <div class="memitem">
780 <div class="memproto">
781 <table class="memname">
783 <td class="memname">#define ARM_PMU_CTI_TRIGOUT6   0x401A</td>
786 </div><div class="memdoc">
788 <p>Cross-trigger Interface output trigger 6. </p>
792 <a id="ga4388c85b636bd71b4ee1a03b6e96c488" name="ga4388c85b636bd71b4ee1a03b6e96c488"></a>
793 <h2 class="memtitle"><span class="permalink"><a href="#ga4388c85b636bd71b4ee1a03b6e96c488">◆ </a></span>ARM_PMU_CTI_TRIGOUT7</h2>
795 <div class="memitem">
796 <div class="memproto">
797 <table class="memname">
799 <td class="memname">#define ARM_PMU_CTI_TRIGOUT7   0x401B</td>
802 </div><div class="memdoc">
804 <p>Cross-trigger Interface output trigger 7. </p>
808 <a id="ga74aaa0fa0571f74168ee9608d5a02403" name="ga74aaa0fa0571f74168ee9608d5a02403"></a>
809 <h2 class="memtitle"><span class="permalink"><a href="#ga74aaa0fa0571f74168ee9608d5a02403">◆ </a></span>ARM_PMU_DTCM_ACCESS</h2>
811 <div class="memitem">
812 <div class="memproto">
813 <table class="memname">
815 <td class="memname">#define ARM_PMU_DTCM_ACCESS   0x4008</td>
818 </div><div class="memdoc">
820 <p>Data TCM access. </p>
824 <a id="ga18d640aa04b97c7d287e8745f6f2b23d" name="ga18d640aa04b97c7d287e8745f6f2b23d"></a>
825 <h2 class="memtitle"><span class="permalink"><a href="#ga18d640aa04b97c7d287e8745f6f2b23d">◆ </a></span>ARM_PMU_DWT_CMPMATCH0</h2>
827 <div class="memitem">
828 <div class="memproto">
829 <table class="memname">
831 <td class="memname">#define ARM_PMU_DWT_CMPMATCH0   0x0118</td>
834 </div><div class="memdoc">
836 <p>DWT comparator 0 match. </p>
840 <a id="ga5dc6eb2be1ff1afe9cbd59af4f6078ab" name="ga5dc6eb2be1ff1afe9cbd59af4f6078ab"></a>
841 <h2 class="memtitle"><span class="permalink"><a href="#ga5dc6eb2be1ff1afe9cbd59af4f6078ab">◆ </a></span>ARM_PMU_DWT_CMPMATCH1</h2>
843 <div class="memitem">
844 <div class="memproto">
845 <table class="memname">
847 <td class="memname">#define ARM_PMU_DWT_CMPMATCH1   0x0119</td>
850 </div><div class="memdoc">
852 <p>DWT comparator 1 match. </p>
856 <a id="ga58a4815dba8886088b9cac7b934a332d" name="ga58a4815dba8886088b9cac7b934a332d"></a>
857 <h2 class="memtitle"><span class="permalink"><a href="#ga58a4815dba8886088b9cac7b934a332d">◆ </a></span>ARM_PMU_DWT_CMPMATCH2</h2>
859 <div class="memitem">
860 <div class="memproto">
861 <table class="memname">
863 <td class="memname">#define ARM_PMU_DWT_CMPMATCH2   0x011A</td>
866 </div><div class="memdoc">
868 <p>DWT comparator 2 match. </p>
872 <a id="ga594337c6f3c88d8317203a8cd6f9814a" name="ga594337c6f3c88d8317203a8cd6f9814a"></a>
873 <h2 class="memtitle"><span class="permalink"><a href="#ga594337c6f3c88d8317203a8cd6f9814a">◆ </a></span>ARM_PMU_DWT_CMPMATCH3</h2>
875 <div class="memitem">
876 <div class="memproto">
877 <table class="memname">
879 <td class="memname">#define ARM_PMU_DWT_CMPMATCH3   0x011B</td>
882 </div><div class="memdoc">
884 <p>DWT comparator 3 match. </p>
888 <a id="gaf9424157e9c5dca3a3689d181005c4f8" name="gaf9424157e9c5dca3a3689d181005c4f8"></a>
889 <h2 class="memtitle"><span class="permalink"><a href="#gaf9424157e9c5dca3a3689d181005c4f8">◆ </a></span>ARM_PMU_EXC_RETURN</h2>
891 <div class="memitem">
892 <div class="memproto">
893 <table class="memname">
895 <td class="memname">#define ARM_PMU_EXC_RETURN   0x000A</td>
898 </div><div class="memdoc">
900 <p>Exception return instruction architecturally executed and the condition code check pass. </p>
904 <a id="gac97858bd621eab4592569444f0a5c37f" name="gac97858bd621eab4592569444f0a5c37f"></a>
905 <h2 class="memtitle"><span class="permalink"><a href="#gac97858bd621eab4592569444f0a5c37f">◆ </a></span>ARM_PMU_EXC_TAKEN</h2>
907 <div class="memitem">
908 <div class="memproto">
909 <table class="memname">
911 <td class="memname">#define ARM_PMU_EXC_TAKEN   0x0009</td>
914 </div><div class="memdoc">
916 <p>Exception entry. </p>
920 <a id="ga8a5e60eee460addfc66e275a2c4c4800" name="ga8a5e60eee460addfc66e275a2c4c4800"></a>
921 <h2 class="memtitle"><span class="permalink"><a href="#ga8a5e60eee460addfc66e275a2c4c4800">◆ </a></span>ARM_PMU_INST_RETIRED</h2>
923 <div class="memitem">
924 <div class="memproto">
925 <table class="memname">
927 <td class="memname">#define ARM_PMU_INST_RETIRED   0x0008</td>
930 </div><div class="memdoc">
932 <p>Instruction architecturally executed. </p>
936 <a id="gaf7bad54617ace5c2fb48bc2e8aebf9c7" name="gaf7bad54617ace5c2fb48bc2e8aebf9c7"></a>
937 <h2 class="memtitle"><span class="permalink"><a href="#gaf7bad54617ace5c2fb48bc2e8aebf9c7">◆ </a></span>ARM_PMU_INST_SPEC</h2>
939 <div class="memitem">
940 <div class="memproto">
941 <table class="memname">
943 <td class="memname">#define ARM_PMU_INST_SPEC   0x001B</td>
946 </div><div class="memdoc">
948 <p>Instruction speculatively executed. </p>
952 <a id="gaf23d758fe1a4cfe6f114cb3e78709237" name="gaf23d758fe1a4cfe6f114cb3e78709237"></a>
953 <h2 class="memtitle"><span class="permalink"><a href="#gaf23d758fe1a4cfe6f114cb3e78709237">◆ </a></span>ARM_PMU_ITCM_ACCESS</h2>
955 <div class="memitem">
956 <div class="memproto">
957 <table class="memname">
959 <td class="memname">#define ARM_PMU_ITCM_ACCESS   0x4007</td>
962 </div><div class="memdoc">
964 <p>Instruction TCM access. </p>
968 <a id="ga7505ae74c1d905f01b05dd5466c1efc0" name="ga7505ae74c1d905f01b05dd5466c1efc0"></a>
969 <h2 class="memtitle"><span class="permalink"><a href="#ga7505ae74c1d905f01b05dd5466c1efc0">◆ </a></span>ARM_PMU_L1D_CACHE</h2>
971 <div class="memitem">
972 <div class="memproto">
973 <table class="memname">
975 <td class="memname">#define ARM_PMU_L1D_CACHE   0x0004</td>
978 </div><div class="memdoc">
980 <p>L1 D-Cache access. </p>
984 <a id="gab55334c8510cb30c4c750913f6eb6279" name="gab55334c8510cb30c4c750913f6eb6279"></a>
985 <h2 class="memtitle"><span class="permalink"><a href="#gab55334c8510cb30c4c750913f6eb6279">◆ </a></span>ARM_PMU_L1D_CACHE_ALLOCATE</h2>
987 <div class="memitem">
988 <div class="memproto">
989 <table class="memname">
991 <td class="memname">#define ARM_PMU_L1D_CACHE_ALLOCATE   0x001F</td>
994 </div><div class="memdoc">
996 <p>Level 1 data cache allocation without refill. </p>
1000 <a id="ga4687d5d7efc6f49db2db9acc25b590f6" name="ga4687d5d7efc6f49db2db9acc25b590f6"></a>
1001 <h2 class="memtitle"><span class="permalink"><a href="#ga4687d5d7efc6f49db2db9acc25b590f6">◆ </a></span>ARM_PMU_L1D_CACHE_MISS_RD</h2>
1003 <div class="memitem">
1004 <div class="memproto">
1005 <table class="memname">
1007 <td class="memname">#define ARM_PMU_L1D_CACHE_MISS_RD   0x0039</td>
1010 </div><div class="memdoc">
1012 <p>Level 1 data cache read miss. </p>
1016 <a id="gaf4236dfbcb4550d3cc98caee837e8e77" name="gaf4236dfbcb4550d3cc98caee837e8e77"></a>
1017 <h2 class="memtitle"><span class="permalink"><a href="#gaf4236dfbcb4550d3cc98caee837e8e77">◆ </a></span>ARM_PMU_L1D_CACHE_RD</h2>
1019 <div class="memitem">
1020 <div class="memproto">
1021 <table class="memname">
1023 <td class="memname">#define ARM_PMU_L1D_CACHE_RD   0x0040</td>
1026 </div><div class="memdoc">
1028 <p>Level 1 data cache read. </p>
1032 <a id="ga64a3d7bfb7ec9d7bdeb073a4fe1bbc38" name="ga64a3d7bfb7ec9d7bdeb073a4fe1bbc38"></a>
1033 <h2 class="memtitle"><span class="permalink"><a href="#ga64a3d7bfb7ec9d7bdeb073a4fe1bbc38">◆ </a></span>ARM_PMU_L1D_CACHE_REFILL</h2>
1035 <div class="memitem">
1036 <div class="memproto">
1037 <table class="memname">
1039 <td class="memname">#define ARM_PMU_L1D_CACHE_REFILL   0x0003</td>
1042 </div><div class="memdoc">
1044 <p>L1 D-Cache refill. </p>
1048 <a id="ga27d1b8b2c37ae0ae41781880ed3893d0" name="ga27d1b8b2c37ae0ae41781880ed3893d0"></a>
1049 <h2 class="memtitle"><span class="permalink"><a href="#ga27d1b8b2c37ae0ae41781880ed3893d0">◆ </a></span>ARM_PMU_L1D_CACHE_WB</h2>
1051 <div class="memitem">
1052 <div class="memproto">
1053 <table class="memname">
1055 <td class="memname">#define ARM_PMU_L1D_CACHE_WB   0x0015</td>
1058 </div><div class="memdoc">
1060 <p>Level 1 data cache write-back. </p>
1064 <a id="gaf8e89b2b098e6bec5916517346925ce2" name="gaf8e89b2b098e6bec5916517346925ce2"></a>
1065 <h2 class="memtitle"><span class="permalink"><a href="#gaf8e89b2b098e6bec5916517346925ce2">◆ </a></span>ARM_PMU_L1I_CACHE</h2>
1067 <div class="memitem">
1068 <div class="memproto">
1069 <table class="memname">
1071 <td class="memname">#define ARM_PMU_L1I_CACHE   0x0014</td>
1074 </div><div class="memdoc">
1076 <p>Level 1 instruction cache access. </p>
1080 <a id="gac43e0e0f9e385ea66402bdeebf3fea3e" name="gac43e0e0f9e385ea66402bdeebf3fea3e"></a>
1081 <h2 class="memtitle"><span class="permalink"><a href="#gac43e0e0f9e385ea66402bdeebf3fea3e">◆ </a></span>ARM_PMU_L1I_CACHE_REFILL</h2>
1083 <div class="memitem">
1084 <div class="memproto">
1085 <table class="memname">
1087 <td class="memname">#define ARM_PMU_L1I_CACHE_REFILL   0x0001</td>
1090 </div><div class="memdoc">
1092 <p>L1 I-Cache refill. </p>
1096 <a id="gafb1e1f86d091ccb735858769c700e289" name="gafb1e1f86d091ccb735858769c700e289"></a>
1097 <h2 class="memtitle"><span class="permalink"><a href="#gafb1e1f86d091ccb735858769c700e289">◆ </a></span>ARM_PMU_L2D_CACHE</h2>
1099 <div class="memitem">
1100 <div class="memproto">
1101 <table class="memname">
1103 <td class="memname">#define ARM_PMU_L2D_CACHE   0x0016</td>
1106 </div><div class="memdoc">
1108 <p>Level 2 data cache access. </p>
1112 <a id="gaad08dcded491bf257d223e4171af41cc" name="gaad08dcded491bf257d223e4171af41cc"></a>
1113 <h2 class="memtitle"><span class="permalink"><a href="#gaad08dcded491bf257d223e4171af41cc">◆ </a></span>ARM_PMU_L2D_CACHE_ALLOCATE</h2>
1115 <div class="memitem">
1116 <div class="memproto">
1117 <table class="memname">
1119 <td class="memname">#define ARM_PMU_L2D_CACHE_ALLOCATE   0x0020</td>
1122 </div><div class="memdoc">
1124 <p>Level 2 data cache allocation without refill. </p>
1128 <a id="gaeb414c1b0375022abc2502ab503a3284" name="gaeb414c1b0375022abc2502ab503a3284"></a>
1129 <h2 class="memtitle"><span class="permalink"><a href="#gaeb414c1b0375022abc2502ab503a3284">◆ </a></span>ARM_PMU_L2D_CACHE_REFILL</h2>
1131 <div class="memitem">
1132 <div class="memproto">
1133 <table class="memname">
1135 <td class="memname">#define ARM_PMU_L2D_CACHE_REFILL   0x0017</td>
1138 </div><div class="memdoc">
1140 <p>Level 2 data cache refill. </p>
1144 <a id="ga1a0c4a1990eeed88edc3e1e0c4b1aca0" name="ga1a0c4a1990eeed88edc3e1e0c4b1aca0"></a>
1145 <h2 class="memtitle"><span class="permalink"><a href="#ga1a0c4a1990eeed88edc3e1e0c4b1aca0">◆ </a></span>ARM_PMU_L2D_CACHE_WB</h2>
1147 <div class="memitem">
1148 <div class="memproto">
1149 <table class="memname">
1151 <td class="memname">#define ARM_PMU_L2D_CACHE_WB   0x0018</td>
1154 </div><div class="memdoc">
1156 <p>Level 2 data cache write-back. </p>
1160 <a id="ga3406498b2c17ca080ebd68cc40d9630e" name="ga3406498b2c17ca080ebd68cc40d9630e"></a>
1161 <h2 class="memtitle"><span class="permalink"><a href="#ga3406498b2c17ca080ebd68cc40d9630e">◆ </a></span>ARM_PMU_L2I_CACHE</h2>
1163 <div class="memitem">
1164 <div class="memproto">
1165 <table class="memname">
1167 <td class="memname">#define ARM_PMU_L2I_CACHE   0x0027</td>
1170 </div><div class="memdoc">
1172 <p>Level 2 instruction cache access. </p>
1176 <a id="gaa18cee03802b46076e9ab66fd0a7c61d" name="gaa18cee03802b46076e9ab66fd0a7c61d"></a>
1177 <h2 class="memtitle"><span class="permalink"><a href="#gaa18cee03802b46076e9ab66fd0a7c61d">◆ </a></span>ARM_PMU_L2I_CACHE_REFILL</h2>
1179 <div class="memitem">
1180 <div class="memproto">
1181 <table class="memname">
1183 <td class="memname">#define ARM_PMU_L2I_CACHE_REFILL   0x0028</td>
1186 </div><div class="memdoc">
1188 <p>Level 2 instruction cache refill. </p>
1192 <a id="ga4e96b5a6fb13c657e78da342a02db200" name="ga4e96b5a6fb13c657e78da342a02db200"></a>
1193 <h2 class="memtitle"><span class="permalink"><a href="#ga4e96b5a6fb13c657e78da342a02db200">◆ </a></span>ARM_PMU_L3D_CACHE</h2>
1195 <div class="memitem">
1196 <div class="memproto">
1197 <table class="memname">
1199 <td class="memname">#define ARM_PMU_L3D_CACHE   0x002B</td>
1202 </div><div class="memdoc">
1204 <p>Level 3 data cache access. </p>
1208 <a id="gac11cbc6849dbad7bd8b64ab6e2a3f8d5" name="gac11cbc6849dbad7bd8b64ab6e2a3f8d5"></a>
1209 <h2 class="memtitle"><span class="permalink"><a href="#gac11cbc6849dbad7bd8b64ab6e2a3f8d5">◆ </a></span>ARM_PMU_L3D_CACHE_ALLOCATE</h2>
1211 <div class="memitem">
1212 <div class="memproto">
1213 <table class="memname">
1215 <td class="memname">#define ARM_PMU_L3D_CACHE_ALLOCATE   0x0029</td>
1218 </div><div class="memdoc">
1220 <p>Level 3 data cache allocation without refill. </p>
1224 <a id="gafe99db0693125100272247c147fb3b02" name="gafe99db0693125100272247c147fb3b02"></a>
1225 <h2 class="memtitle"><span class="permalink"><a href="#gafe99db0693125100272247c147fb3b02">◆ </a></span>ARM_PMU_L3D_CACHE_REFILL</h2>
1227 <div class="memitem">
1228 <div class="memproto">
1229 <table class="memname">
1231 <td class="memname">#define ARM_PMU_L3D_CACHE_REFILL   0x002A</td>
1234 </div><div class="memdoc">
1236 <p>Level 3 data cache refill. </p>
1240 <a id="gab823f95f7ac8196a208d12381b1b2a11" name="gab823f95f7ac8196a208d12381b1b2a11"></a>
1241 <h2 class="memtitle"><span class="permalink"><a href="#gab823f95f7ac8196a208d12381b1b2a11">◆ </a></span>ARM_PMU_L3D_CACHE_WB</h2>
1243 <div class="memitem">
1244 <div class="memproto">
1245 <table class="memname">
1247 <td class="memname">#define ARM_PMU_L3D_CACHE_WB   0x002C</td>
1250 </div><div class="memdoc">
1252 <p>Level 3 data cache write-back. </p>
1256 <a id="ga2e8725ee07c2b2c75a1b54261bc26cc8" name="ga2e8725ee07c2b2c75a1b54261bc26cc8"></a>
1257 <h2 class="memtitle"><span class="permalink"><a href="#ga2e8725ee07c2b2c75a1b54261bc26cc8">◆ </a></span>ARM_PMU_LD_RETIRED</h2>
1259 <div class="memitem">
1260 <div class="memproto">
1261 <table class="memname">
1263 <td class="memname">#define ARM_PMU_LD_RETIRED   0x0006</td>
1266 </div><div class="memdoc">
1268 <p>Memory-reading instruction architecturally executed and condition code check pass. </p>
1272 <a id="ga8b5641a3cb0e922a2b4e16ec14052861" name="ga8b5641a3cb0e922a2b4e16ec14052861"></a>
1273 <h2 class="memtitle"><span class="permalink"><a href="#ga8b5641a3cb0e922a2b4e16ec14052861">◆ </a></span>ARM_PMU_LE_CANCEL</h2>
1275 <div class="memitem">
1276 <div class="memproto">
1277 <table class="memname">
1279 <td class="memname">#define ARM_PMU_LE_CANCEL   0x0108</td>
1282 </div><div class="memdoc">
1284 <p>Loop end instruction not taken. </p>
1288 <a id="ga345461506c990125b1f2cbc62e3be22f" name="ga345461506c990125b1f2cbc62e3be22f"></a>
1289 <h2 class="memtitle"><span class="permalink"><a href="#ga345461506c990125b1f2cbc62e3be22f">◆ </a></span>ARM_PMU_LE_RETIRED</h2>
1291 <div class="memitem">
1292 <div class="memproto">
1293 <table class="memname">
1295 <td class="memname">#define ARM_PMU_LE_RETIRED   0x0100</td>
1298 </div><div class="memdoc">
1300 <p>Loop end instruction executed. </p>
1304 <a id="ga6a1d9f84bda091e96843665ff3913b50" name="ga6a1d9f84bda091e96843665ff3913b50"></a>
1305 <h2 class="memtitle"><span class="permalink"><a href="#ga6a1d9f84bda091e96843665ff3913b50">◆ </a></span>ARM_PMU_LE_SPEC</h2>
1307 <div class="memitem">
1308 <div class="memproto">
1309 <table class="memname">
1311 <td class="memname">#define ARM_PMU_LE_SPEC   0x0101</td>
1314 </div><div class="memdoc">
1316 <p>Loop end instruction speculatively executed. </p>
1320 <a id="ga6979efa69af7d0e62cc3e2f88b0155b8" name="ga6979efa69af7d0e62cc3e2f88b0155b8"></a>
1321 <h2 class="memtitle"><span class="permalink"><a href="#ga6979efa69af7d0e62cc3e2f88b0155b8">◆ </a></span>ARM_PMU_LL_CACHE_MISS_RD</h2>
1323 <div class="memitem">
1324 <div class="memproto">
1325 <table class="memname">
1327 <td class="memname">#define ARM_PMU_LL_CACHE_MISS_RD   0x0037</td>
1330 </div><div class="memdoc">
1332 <p>Last level data cache read miss. </p>
1336 <a id="ga902562d8161fffd45726dc4cc8727545" name="ga902562d8161fffd45726dc4cc8727545"></a>
1337 <h2 class="memtitle"><span class="permalink"><a href="#ga902562d8161fffd45726dc4cc8727545">◆ </a></span>ARM_PMU_LL_CACHE_RD</h2>
1339 <div class="memitem">
1340 <div class="memproto">
1341 <table class="memname">
1343 <td class="memname">#define ARM_PMU_LL_CACHE_RD   0x0036</td>
1346 </div><div class="memdoc">
1348 <p>Last level data cache read. </p>
1352 <a id="gab3852c2b3d59af106b9db7ea2c20c367" name="gab3852c2b3d59af106b9db7ea2c20c367"></a>
1353 <h2 class="memtitle"><span class="permalink"><a href="#gab3852c2b3d59af106b9db7ea2c20c367">◆ </a></span>ARM_PMU_MEM_ACCESS</h2>
1355 <div class="memitem">
1356 <div class="memproto">
1357 <table class="memname">
1359 <td class="memname">#define ARM_PMU_MEM_ACCESS   0x0013</td>
1362 </div><div class="memdoc">
1364 <p>Data memory access. </p>
1368 <a id="ga2c8d23cc64e87b2044bb39bf8d0bc1b1" name="ga2c8d23cc64e87b2044bb39bf8d0bc1b1"></a>
1369 <h2 class="memtitle"><span class="permalink"><a href="#ga2c8d23cc64e87b2044bb39bf8d0bc1b1">◆ </a></span>ARM_PMU_MEMORY_ERROR</h2>
1371 <div class="memitem">
1372 <div class="memproto">
1373 <table class="memname">
1375 <td class="memname">#define ARM_PMU_MEMORY_ERROR   0x001A</td>
1378 </div><div class="memdoc">
1380 <p>Local memory error. </p>
1384 <a id="gaa4c408a006a04e95ade26922669b6695" name="gaa4c408a006a04e95ade26922669b6695"></a>
1385 <h2 class="memtitle"><span class="permalink"><a href="#gaa4c408a006a04e95ade26922669b6695">◆ </a></span>ARM_PMU_MVE_FP_HP_RETIRED</h2>
1387 <div class="memitem">
1388 <div class="memproto">
1389 <table class="memname">
1391 <td class="memname">#define ARM_PMU_MVE_FP_HP_RETIRED   0x0208</td>
1394 </div><div class="memdoc">
1396 <p>MVE half-precision floating-point instruction architecturally executed. </p>
1400 <a id="gaf01d187b0cbf418d1fac55dd0ddd0827" name="gaf01d187b0cbf418d1fac55dd0ddd0827"></a>
1401 <h2 class="memtitle"><span class="permalink"><a href="#gaf01d187b0cbf418d1fac55dd0ddd0827">◆ </a></span>ARM_PMU_MVE_FP_HP_SPEC</h2>
1403 <div class="memitem">
1404 <div class="memproto">
1405 <table class="memname">
1407 <td class="memname">#define ARM_PMU_MVE_FP_HP_SPEC   0x0209</td>
1410 </div><div class="memdoc">
1412 <p>MVE half-precision floating-point instruction speculatively executed. </p>
1416 <a id="gac2dc7d92627b3caa391725a3f080288c" name="gac2dc7d92627b3caa391725a3f080288c"></a>
1417 <h2 class="memtitle"><span class="permalink"><a href="#gac2dc7d92627b3caa391725a3f080288c">◆ </a></span>ARM_PMU_MVE_FP_MAC_RETIRED</h2>
1419 <div class="memitem">
1420 <div class="memproto">
1421 <table class="memname">
1423 <td class="memname">#define ARM_PMU_MVE_FP_MAC_RETIRED   0x0214</td>
1426 </div><div class="memdoc">
1428 <p>MVE floating-point multiply or multiply-accumulate instruction architecturally executed. </p>
1432 <a id="gaf5302b3278a862c9264171955328a59a" name="gaf5302b3278a862c9264171955328a59a"></a>
1433 <h2 class="memtitle"><span class="permalink"><a href="#gaf5302b3278a862c9264171955328a59a">◆ </a></span>ARM_PMU_MVE_FP_MAC_SPEC</h2>
1435 <div class="memitem">
1436 <div class="memproto">
1437 <table class="memname">
1439 <td class="memname">#define ARM_PMU_MVE_FP_MAC_SPEC   0x0215</td>
1442 </div><div class="memdoc">
1444 <p>MVE floating-point multiply or multiply-accumulate instruction speculatively executed. </p>
1448 <a id="ga268b0bcbd30e8a928bd0f331fdf53ccf" name="ga268b0bcbd30e8a928bd0f331fdf53ccf"></a>
1449 <h2 class="memtitle"><span class="permalink"><a href="#ga268b0bcbd30e8a928bd0f331fdf53ccf">◆ </a></span>ARM_PMU_MVE_FP_RETIRED</h2>
1451 <div class="memitem">
1452 <div class="memproto">
1453 <table class="memname">
1455 <td class="memname">#define ARM_PMU_MVE_FP_RETIRED   0x0204</td>
1458 </div><div class="memdoc">
1460 <p>MVE floating-point instruction architecturally executed. </p>
1464 <a id="gab21171c50ebd1f304b11260edd015f52" name="gab21171c50ebd1f304b11260edd015f52"></a>
1465 <h2 class="memtitle"><span class="permalink"><a href="#gab21171c50ebd1f304b11260edd015f52">◆ </a></span>ARM_PMU_MVE_FP_SP_RETIRED</h2>
1467 <div class="memitem">
1468 <div class="memproto">
1469 <table class="memname">
1471 <td class="memname">#define ARM_PMU_MVE_FP_SP_RETIRED   0x020C</td>
1474 </div><div class="memdoc">
1476 <p>MVE single-precision floating-point instruction architecturally executed. </p>
1480 <a id="gae69e310892661af852ca2d4ec947d18a" name="gae69e310892661af852ca2d4ec947d18a"></a>
1481 <h2 class="memtitle"><span class="permalink"><a href="#gae69e310892661af852ca2d4ec947d18a">◆ </a></span>ARM_PMU_MVE_FP_SP_SPEC</h2>
1483 <div class="memitem">
1484 <div class="memproto">
1485 <table class="memname">
1487 <td class="memname">#define ARM_PMU_MVE_FP_SP_SPEC   0x020D</td>
1490 </div><div class="memdoc">
1492 <p>MVE single-precision floating-point instruction speculatively executed. </p>
1496 <a id="gadf9cfd45b59acfc314ebc814a1bcdccd" name="gadf9cfd45b59acfc314ebc814a1bcdccd"></a>
1497 <h2 class="memtitle"><span class="permalink"><a href="#gadf9cfd45b59acfc314ebc814a1bcdccd">◆ </a></span>ARM_PMU_MVE_FP_SPEC</h2>
1499 <div class="memitem">
1500 <div class="memproto">
1501 <table class="memname">
1503 <td class="memname">#define ARM_PMU_MVE_FP_SPEC   0x0205</td>
1506 </div><div class="memdoc">
1508 <p>MVE floating-point instruction speculatively executed. </p>
1512 <a id="ga3c1006bed2fb82b0749386261b397727" name="ga3c1006bed2fb82b0749386261b397727"></a>
1513 <h2 class="memtitle"><span class="permalink"><a href="#ga3c1006bed2fb82b0749386261b397727">◆ </a></span>ARM_PMU_MVE_INST_RETIRED</h2>
1515 <div class="memitem">
1516 <div class="memproto">
1517 <table class="memname">
1519 <td class="memname">#define ARM_PMU_MVE_INST_RETIRED   0x0200</td>
1522 </div><div class="memdoc">
1524 <p>MVE instruction architecturally executed. </p>
1528 <a id="ga1e276b6872345eb3b043626a11f235c6" name="ga1e276b6872345eb3b043626a11f235c6"></a>
1529 <h2 class="memtitle"><span class="permalink"><a href="#ga1e276b6872345eb3b043626a11f235c6">◆ </a></span>ARM_PMU_MVE_INST_SPEC</h2>
1531 <div class="memitem">
1532 <div class="memproto">
1533 <table class="memname">
1535 <td class="memname">#define ARM_PMU_MVE_INST_SPEC   0x0201</td>
1538 </div><div class="memdoc">
1540 <p>MVE instruction speculatively executed. </p>
1544 <a id="ga9248c93a3f19fddc93d3804a06f7238a" name="ga9248c93a3f19fddc93d3804a06f7238a"></a>
1545 <h2 class="memtitle"><span class="permalink"><a href="#ga9248c93a3f19fddc93d3804a06f7238a">◆ </a></span>ARM_PMU_MVE_INT_MAC_RETIRED</h2>
1547 <div class="memitem">
1548 <div class="memproto">
1549 <table class="memname">
1551 <td class="memname">#define ARM_PMU_MVE_INT_MAC_RETIRED   0x0228</td>
1554 </div><div class="memdoc">
1556 <p>MVE multiply or multiply-accumulate instruction architecturally executed. </p>
1560 <a id="ga7036f00faa9183ae450a3e4d9d6f2bbf" name="ga7036f00faa9183ae450a3e4d9d6f2bbf"></a>
1561 <h2 class="memtitle"><span class="permalink"><a href="#ga7036f00faa9183ae450a3e4d9d6f2bbf">◆ </a></span>ARM_PMU_MVE_INT_MAC_SPEC</h2>
1563 <div class="memitem">
1564 <div class="memproto">
1565 <table class="memname">
1567 <td class="memname">#define ARM_PMU_MVE_INT_MAC_SPEC   0x0229</td>
1570 </div><div class="memdoc">
1572 <p>MVE multiply or multiply-accumulate instruction speculatively executed. </p>
1576 <a id="ga5e3afafa91ebaeac0469a19ebb54719c" name="ga5e3afafa91ebaeac0469a19ebb54719c"></a>
1577 <h2 class="memtitle"><span class="permalink"><a href="#ga5e3afafa91ebaeac0469a19ebb54719c">◆ </a></span>ARM_PMU_MVE_INT_RETIRED</h2>
1579 <div class="memitem">
1580 <div class="memproto">
1581 <table class="memname">
1583 <td class="memname">#define ARM_PMU_MVE_INT_RETIRED   0x0224</td>
1586 </div><div class="memdoc">
1588 <p>MVE integer instruction architecturally executed. </p>
1592 <a id="ga16ed0bb1bb4718da93c41238da652d33" name="ga16ed0bb1bb4718da93c41238da652d33"></a>
1593 <h2 class="memtitle"><span class="permalink"><a href="#ga16ed0bb1bb4718da93c41238da652d33">◆ </a></span>ARM_PMU_MVE_INT_SPEC</h2>
1595 <div class="memitem">
1596 <div class="memproto">
1597 <table class="memname">
1599 <td class="memname">#define ARM_PMU_MVE_INT_SPEC   0x0225</td>
1602 </div><div class="memdoc">
1604 <p>MVE integer instruction speculatively executed. </p>
1608 <a id="ga8732a737f2b7adc43e3d1da7b3da92e6" name="ga8732a737f2b7adc43e3d1da7b3da92e6"></a>
1609 <h2 class="memtitle"><span class="permalink"><a href="#ga8732a737f2b7adc43e3d1da7b3da92e6">◆ </a></span>ARM_PMU_MVE_LD_CONTIG_RETIRED</h2>
1611 <div class="memitem">
1612 <div class="memproto">
1613 <table class="memname">
1615 <td class="memname">#define ARM_PMU_MVE_LD_CONTIG_RETIRED   0x0248</td>
1618 </div><div class="memdoc">
1620 <p>MVE contiguous load instruction architecturally executed. </p>
1624 <a id="ga8e58fe07254256fa3bf3d42fa2062141" name="ga8e58fe07254256fa3bf3d42fa2062141"></a>
1625 <h2 class="memtitle"><span class="permalink"><a href="#ga8e58fe07254256fa3bf3d42fa2062141">◆ </a></span>ARM_PMU_MVE_LD_CONTIG_SPEC</h2>
1627 <div class="memitem">
1628 <div class="memproto">
1629 <table class="memname">
1631 <td class="memname">#define ARM_PMU_MVE_LD_CONTIG_SPEC   0x0249</td>
1634 </div><div class="memdoc">
1636 <p>MVE contiguous load instruction speculatively executed. </p>
1640 <a id="ga50fb13c874b3f5e2b9ed9c320a36452c" name="ga50fb13c874b3f5e2b9ed9c320a36452c"></a>
1641 <h2 class="memtitle"><span class="permalink"><a href="#ga50fb13c874b3f5e2b9ed9c320a36452c">◆ </a></span>ARM_PMU_MVE_LD_MULTI_RETIRED</h2>
1643 <div class="memitem">
1644 <div class="memproto">
1645 <table class="memname">
1647 <td class="memname">#define ARM_PMU_MVE_LD_MULTI_RETIRED   0x0260</td>
1650 </div><div class="memdoc">
1652 <p>MVE memory load instruction targeting multiple registers architecturally executed. </p>
1656 <a id="gaf2d4e3d1f06d97899de7fa791477d62b" name="gaf2d4e3d1f06d97899de7fa791477d62b"></a>
1657 <h2 class="memtitle"><span class="permalink"><a href="#gaf2d4e3d1f06d97899de7fa791477d62b">◆ </a></span>ARM_PMU_MVE_LD_MULTI_SPEC</h2>
1659 <div class="memitem">
1660 <div class="memproto">
1661 <table class="memname">
1663 <td class="memname">#define ARM_PMU_MVE_LD_MULTI_SPEC   0x0261</td>
1666 </div><div class="memdoc">
1668 <p>MVE memory load instruction targeting multiple registers speculatively executed. </p>
1672 <a id="gaaf2ce8c0ea4c03c934aac6afc31fc5ff" name="gaaf2ce8c0ea4c03c934aac6afc31fc5ff"></a>
1673 <h2 class="memtitle"><span class="permalink"><a href="#gaaf2ce8c0ea4c03c934aac6afc31fc5ff">◆ </a></span>ARM_PMU_MVE_LD_NONCONTIG_RETIRED</h2>
1675 <div class="memitem">
1676 <div class="memproto">
1677 <table class="memname">
1679 <td class="memname">#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED   0x0254</td>
1682 </div><div class="memdoc">
1684 <p>MVE non-contiguous load instruction architecturally executed. </p>
1688 <a id="gadbcb82b7924b7bbee5c0d42a3de38572" name="gadbcb82b7924b7bbee5c0d42a3de38572"></a>
1689 <h2 class="memtitle"><span class="permalink"><a href="#gadbcb82b7924b7bbee5c0d42a3de38572">◆ </a></span>ARM_PMU_MVE_LD_NONCONTIG_SPEC</h2>
1691 <div class="memitem">
1692 <div class="memproto">
1693 <table class="memname">
1695 <td class="memname">#define ARM_PMU_MVE_LD_NONCONTIG_SPEC   0x0255</td>
1698 </div><div class="memdoc">
1700 <p>MVE non-contiguous load instruction speculatively executed. </p>
1704 <a id="gaa3379a51350a2fda8d8ab6d7795baa7a" name="gaa3379a51350a2fda8d8ab6d7795baa7a"></a>
1705 <h2 class="memtitle"><span class="permalink"><a href="#gaa3379a51350a2fda8d8ab6d7795baa7a">◆ </a></span>ARM_PMU_MVE_LD_RETIRED</h2>
1707 <div class="memitem">
1708 <div class="memproto">
1709 <table class="memname">
1711 <td class="memname">#define ARM_PMU_MVE_LD_RETIRED   0x023C</td>
1714 </div><div class="memdoc">
1716 <p>MVE load instruction architecturally executed. </p>
1720 <a id="ga78a6f89ab30ed01f7d8388eda697b4f8" name="ga78a6f89ab30ed01f7d8388eda697b4f8"></a>
1721 <h2 class="memtitle"><span class="permalink"><a href="#ga78a6f89ab30ed01f7d8388eda697b4f8">◆ </a></span>ARM_PMU_MVE_LD_SPEC</h2>
1723 <div class="memitem">
1724 <div class="memproto">
1725 <table class="memname">
1727 <td class="memname">#define ARM_PMU_MVE_LD_SPEC   0x023D</td>
1730 </div><div class="memdoc">
1732 <p>MVE load instruction speculatively executed. </p>
1736 <a id="ga26ed05deaa7b993904300069f0ecfac4" name="ga26ed05deaa7b993904300069f0ecfac4"></a>
1737 <h2 class="memtitle"><span class="permalink"><a href="#ga26ed05deaa7b993904300069f0ecfac4">◆ </a></span>ARM_PMU_MVE_LD_UNALIGNED_RETIRED</h2>
1739 <div class="memitem">
1740 <div class="memproto">
1741 <table class="memname">
1743 <td class="memname">#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED   0x0290</td>
1746 </div><div class="memdoc">
1748 <p>MVE unaligned load instruction architecturally executed. </p>
1752 <a id="gadc3bd0f32e0a08bba2d533479a59bd6e" name="gadc3bd0f32e0a08bba2d533479a59bd6e"></a>
1753 <h2 class="memtitle"><span class="permalink"><a href="#gadc3bd0f32e0a08bba2d533479a59bd6e">◆ </a></span>ARM_PMU_MVE_LD_UNALIGNED_SPEC</h2>
1755 <div class="memitem">
1756 <div class="memproto">
1757 <table class="memname">
1759 <td class="memname">#define ARM_PMU_MVE_LD_UNALIGNED_SPEC   0x0291</td>
1762 </div><div class="memdoc">
1764 <p>MVE unaligned load instruction speculatively executed. </p>
1768 <a id="ga8acf6a66c63798b76608caf52c96658d" name="ga8acf6a66c63798b76608caf52c96658d"></a>
1769 <h2 class="memtitle"><span class="permalink"><a href="#ga8acf6a66c63798b76608caf52c96658d">◆ </a></span>ARM_PMU_MVE_LDST_CONTIG_RETIRED</h2>
1771 <div class="memitem">
1772 <div class="memproto">
1773 <table class="memname">
1775 <td class="memname">#define ARM_PMU_MVE_LDST_CONTIG_RETIRED   0x0244</td>
1778 </div><div class="memdoc">
1780 <p>MVE contiguous load or store instruction architecturally executed. </p>
1784 <a id="ga5a83ef6a52739e1d223be503bbdaaab6" name="ga5a83ef6a52739e1d223be503bbdaaab6"></a>
1785 <h2 class="memtitle"><span class="permalink"><a href="#ga5a83ef6a52739e1d223be503bbdaaab6">◆ </a></span>ARM_PMU_MVE_LDST_CONTIG_SPEC</h2>
1787 <div class="memitem">
1788 <div class="memproto">
1789 <table class="memname">
1791 <td class="memname">#define ARM_PMU_MVE_LDST_CONTIG_SPEC   0x0245</td>
1794 </div><div class="memdoc">
1796 <p>MVE contiguous load or store instruction speculatively executed. </p>
1800 <a id="ga7d669378441408fc21aa551e483866cb" name="ga7d669378441408fc21aa551e483866cb"></a>
1801 <h2 class="memtitle"><span class="permalink"><a href="#ga7d669378441408fc21aa551e483866cb">◆ </a></span>ARM_PMU_MVE_LDST_MULTI_RETIRED</h2>
1803 <div class="memitem">
1804 <div class="memproto">
1805 <table class="memname">
1807 <td class="memname">#define ARM_PMU_MVE_LDST_MULTI_RETIRED   0x025C</td>
1810 </div><div class="memdoc">
1812 <p>MVE memory instruction targeting multiple registers architecturally executed. </p>
1816 <a id="ga7ea46cde08cb0cc4a46ef23835fb5aac" name="ga7ea46cde08cb0cc4a46ef23835fb5aac"></a>
1817 <h2 class="memtitle"><span class="permalink"><a href="#ga7ea46cde08cb0cc4a46ef23835fb5aac">◆ </a></span>ARM_PMU_MVE_LDST_MULTI_SPEC</h2>
1819 <div class="memitem">
1820 <div class="memproto">
1821 <table class="memname">
1823 <td class="memname">#define ARM_PMU_MVE_LDST_MULTI_SPEC   0x025D</td>
1826 </div><div class="memdoc">
1828 <p>MVE memory instruction targeting multiple registers speculatively executed. </p>
1832 <a id="ga7065b7f0aea461858b72912d22c329f2" name="ga7065b7f0aea461858b72912d22c329f2"></a>
1833 <h2 class="memtitle"><span class="permalink"><a href="#ga7065b7f0aea461858b72912d22c329f2">◆ </a></span>ARM_PMU_MVE_LDST_NONCONTIG_RETIRED</h2>
1835 <div class="memitem">
1836 <div class="memproto">
1837 <table class="memname">
1839 <td class="memname">#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED   0x0250</td>
1842 </div><div class="memdoc">
1844 <p>MVE non-contiguous load or store instruction architecturally executed. </p>
1848 <a id="ga193605eb52709741d91a64e3ad1a5894" name="ga193605eb52709741d91a64e3ad1a5894"></a>
1849 <h2 class="memtitle"><span class="permalink"><a href="#ga193605eb52709741d91a64e3ad1a5894">◆ </a></span>ARM_PMU_MVE_LDST_NONCONTIG_SPEC</h2>
1851 <div class="memitem">
1852 <div class="memproto">
1853 <table class="memname">
1855 <td class="memname">#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC   0x0251</td>
1858 </div><div class="memdoc">
1860 <p>MVE non-contiguous load or store instruction speculatively executed. </p>
1864 <a id="ga7d7d465a6c64400c49f93b6c8152296f" name="ga7d7d465a6c64400c49f93b6c8152296f"></a>
1865 <h2 class="memtitle"><span class="permalink"><a href="#ga7d7d465a6c64400c49f93b6c8152296f">◆ </a></span>ARM_PMU_MVE_LDST_RETIRED</h2>
1867 <div class="memitem">
1868 <div class="memproto">
1869 <table class="memname">
1871 <td class="memname">#define ARM_PMU_MVE_LDST_RETIRED   0x0238</td>
1874 </div><div class="memdoc">
1876 <p>MVE load or store instruction architecturally executed. </p>
1880 <a id="gaa98a18c06bd13daf2df6f89219ec68d5" name="gaa98a18c06bd13daf2df6f89219ec68d5"></a>
1881 <h2 class="memtitle"><span class="permalink"><a href="#gaa98a18c06bd13daf2df6f89219ec68d5">◆ </a></span>ARM_PMU_MVE_LDST_SPEC</h2>
1883 <div class="memitem">
1884 <div class="memproto">
1885 <table class="memname">
1887 <td class="memname">#define ARM_PMU_MVE_LDST_SPEC   0x0239</td>
1890 </div><div class="memdoc">
1892 <p>MVE load or store instruction speculatively executed. </p>
1896 <a id="ga627920bebd935709655687d844848934" name="ga627920bebd935709655687d844848934"></a>
1897 <h2 class="memtitle"><span class="permalink"><a href="#ga627920bebd935709655687d844848934">◆ </a></span>ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED</h2>
1899 <div class="memitem">
1900 <div class="memproto">
1901 <table class="memname">
1903 <td class="memname">#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED   0x0298</td>
1906 </div><div class="memdoc">
1908 <p>MVE unaligned noncontiguous load or store instruction architecturally executed. </p>
1912 <a id="gaf9ebeb1f49dba56d8f90f9bd5d3da58e" name="gaf9ebeb1f49dba56d8f90f9bd5d3da58e"></a>
1913 <h2 class="memtitle"><span class="permalink"><a href="#gaf9ebeb1f49dba56d8f90f9bd5d3da58e">◆ </a></span>ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC</h2>
1915 <div class="memitem">
1916 <div class="memproto">
1917 <table class="memname">
1919 <td class="memname">#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC   0x0299</td>
1922 </div><div class="memdoc">
1924 <p>MVE unaligned noncontiguous load or store instruction speculatively executed. </p>
1928 <a id="gaf358a9ed5c83a10cb695d9b19b1b3bc1" name="gaf358a9ed5c83a10cb695d9b19b1b3bc1"></a>
1929 <h2 class="memtitle"><span class="permalink"><a href="#gaf358a9ed5c83a10cb695d9b19b1b3bc1">◆ </a></span>ARM_PMU_MVE_LDST_UNALIGNED_RETIRED</h2>
1931 <div class="memitem">
1932 <div class="memproto">
1933 <table class="memname">
1935 <td class="memname">#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED   0x028C</td>
1938 </div><div class="memdoc">
1940 <p>MVE unaligned memory load or store instruction architecturally executed. </p>
1944 <a id="gab2264786bed578c89109859b55909c76" name="gab2264786bed578c89109859b55909c76"></a>
1945 <h2 class="memtitle"><span class="permalink"><a href="#gab2264786bed578c89109859b55909c76">◆ </a></span>ARM_PMU_MVE_LDST_UNALIGNED_SPEC</h2>
1947 <div class="memitem">
1948 <div class="memproto">
1949 <table class="memname">
1951 <td class="memname">#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC   0x028D</td>
1954 </div><div class="memdoc">
1956 <p>MVE unaligned memory load or store instruction speculatively executed. </p>
1960 <a id="ga01b4792990494b8f084ee00933a1adb0" name="ga01b4792990494b8f084ee00933a1adb0"></a>
1961 <h2 class="memtitle"><span class="permalink"><a href="#ga01b4792990494b8f084ee00933a1adb0">◆ </a></span>ARM_PMU_MVE_PRED</h2>
1963 <div class="memitem">
1964 <div class="memproto">
1965 <table class="memname">
1967 <td class="memname">#define ARM_PMU_MVE_PRED   0x02B8</td>
1970 </div><div class="memdoc">
1972 <p>Cycles where one or more predicated beats architecturally executed. </p>
1976 <a id="gacb3c0b922eae9aac321df97ec889e0ed" name="gacb3c0b922eae9aac321df97ec889e0ed"></a>
1977 <h2 class="memtitle"><span class="permalink"><a href="#gacb3c0b922eae9aac321df97ec889e0ed">◆ </a></span>ARM_PMU_MVE_ST_CONTIG_RETIRED</h2>
1979 <div class="memitem">
1980 <div class="memproto">
1981 <table class="memname">
1983 <td class="memname">#define ARM_PMU_MVE_ST_CONTIG_RETIRED   0x024C</td>
1986 </div><div class="memdoc">
1988 <p>MVE contiguous store instruction architecturally executed. </p>
1992 <a id="ga02cd64b9444e4babc7b69e8571d39bdd" name="ga02cd64b9444e4babc7b69e8571d39bdd"></a>
1993 <h2 class="memtitle"><span class="permalink"><a href="#ga02cd64b9444e4babc7b69e8571d39bdd">◆ </a></span>ARM_PMU_MVE_ST_CONTIG_SPEC</h2>
1995 <div class="memitem">
1996 <div class="memproto">
1997 <table class="memname">
1999 <td class="memname">#define ARM_PMU_MVE_ST_CONTIG_SPEC   0x024D</td>
2002 </div><div class="memdoc">
2004 <p>MVE contiguous store instruction speculatively executed. </p>
2008 <a id="ga76057cbda353b4ad6fbc3b6a63c193a5" name="ga76057cbda353b4ad6fbc3b6a63c193a5"></a>
2009 <h2 class="memtitle"><span class="permalink"><a href="#ga76057cbda353b4ad6fbc3b6a63c193a5">◆ </a></span>ARM_PMU_MVE_ST_MULTI_RETIRED</h2>
2011 <div class="memitem">
2012 <div class="memproto">
2013 <table class="memname">
2015 <td class="memname">#define ARM_PMU_MVE_ST_MULTI_RETIRED   0x0261</td>
2018 </div><div class="memdoc">
2020 <p>MVE memory store instruction targeting multiple registers architecturally executed. </p>
2024 <a id="gaf6a14402c79dba8fa765e8663dd0734d" name="gaf6a14402c79dba8fa765e8663dd0734d"></a>
2025 <h2 class="memtitle"><span class="permalink"><a href="#gaf6a14402c79dba8fa765e8663dd0734d">◆ </a></span>ARM_PMU_MVE_ST_MULTI_SPEC</h2>
2027 <div class="memitem">
2028 <div class="memproto">
2029 <table class="memname">
2031 <td class="memname">#define ARM_PMU_MVE_ST_MULTI_SPEC   0x0265</td>
2034 </div><div class="memdoc">
2036 <p>MVE memory store instruction targeting multiple registers speculatively executed. </p>
2040 <a id="ga8271f415ecc7573b57e82a24aec86ef1" name="ga8271f415ecc7573b57e82a24aec86ef1"></a>
2041 <h2 class="memtitle"><span class="permalink"><a href="#ga8271f415ecc7573b57e82a24aec86ef1">◆ </a></span>ARM_PMU_MVE_ST_NONCONTIG_RETIRED</h2>
2043 <div class="memitem">
2044 <div class="memproto">
2045 <table class="memname">
2047 <td class="memname">#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED   0x0258</td>
2050 </div><div class="memdoc">
2052 <p>MVE non-contiguous store instruction architecturally executed. </p>
2056 <a id="ga059327c80f396918a9f8192bcd0fa4a8" name="ga059327c80f396918a9f8192bcd0fa4a8"></a>
2057 <h2 class="memtitle"><span class="permalink"><a href="#ga059327c80f396918a9f8192bcd0fa4a8">◆ </a></span>ARM_PMU_MVE_ST_NONCONTIG_SPEC</h2>
2059 <div class="memitem">
2060 <div class="memproto">
2061 <table class="memname">
2063 <td class="memname">#define ARM_PMU_MVE_ST_NONCONTIG_SPEC   0x0259</td>
2066 </div><div class="memdoc">
2068 <p>MVE non-contiguous store instruction speculatively executed. </p>
2072 <a id="gad8d0079977fa97de4ee263703f1b2908" name="gad8d0079977fa97de4ee263703f1b2908"></a>
2073 <h2 class="memtitle"><span class="permalink"><a href="#gad8d0079977fa97de4ee263703f1b2908">◆ </a></span>ARM_PMU_MVE_ST_RETIRED</h2>
2075 <div class="memitem">
2076 <div class="memproto">
2077 <table class="memname">
2079 <td class="memname">#define ARM_PMU_MVE_ST_RETIRED   0x0240</td>
2082 </div><div class="memdoc">
2084 <p>MVE store instruction architecturally executed. </p>
2088 <a id="gabd3984d299b5416aac8d630722680c55" name="gabd3984d299b5416aac8d630722680c55"></a>
2089 <h2 class="memtitle"><span class="permalink"><a href="#gabd3984d299b5416aac8d630722680c55">◆ </a></span>ARM_PMU_MVE_ST_SPEC</h2>
2091 <div class="memitem">
2092 <div class="memproto">
2093 <table class="memname">
2095 <td class="memname">#define ARM_PMU_MVE_ST_SPEC   0x0241</td>
2098 </div><div class="memdoc">
2100 <p>MVE store instruction speculatively executed. </p>
2104 <a id="ga391afd8cb92cc65161b13ee3a3256d40" name="ga391afd8cb92cc65161b13ee3a3256d40"></a>
2105 <h2 class="memtitle"><span class="permalink"><a href="#ga391afd8cb92cc65161b13ee3a3256d40">◆ </a></span>ARM_PMU_MVE_ST_UNALIGNED_RETIRED</h2>
2107 <div class="memitem">
2108 <div class="memproto">
2109 <table class="memname">
2111 <td class="memname">#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED   0x0294</td>
2114 </div><div class="memdoc">
2116 <p>MVE unaligned store instruction architecturally executed. </p>
2120 <a id="ga21bf105499df85196b4137cb075a6fbe" name="ga21bf105499df85196b4137cb075a6fbe"></a>
2121 <h2 class="memtitle"><span class="permalink"><a href="#ga21bf105499df85196b4137cb075a6fbe">◆ </a></span>ARM_PMU_MVE_ST_UNALIGNED_SPEC</h2>
2123 <div class="memitem">
2124 <div class="memproto">
2125 <table class="memname">
2127 <td class="memname">#define ARM_PMU_MVE_ST_UNALIGNED_SPEC   0x0295</td>
2130 </div><div class="memdoc">
2132 <p>MVE unaligned store instruction speculatively executed. </p>
2136 <a id="ga2a45ec75b2011bd8375d89b7562b2de6" name="ga2a45ec75b2011bd8375d89b7562b2de6"></a>
2137 <h2 class="memtitle"><span class="permalink"><a href="#ga2a45ec75b2011bd8375d89b7562b2de6">◆ </a></span>ARM_PMU_MVE_STALL</h2>
2139 <div class="memitem">
2140 <div class="memproto">
2141 <table class="memname">
2143 <td class="memname">#define ARM_PMU_MVE_STALL   0x02CC</td>
2146 </div><div class="memdoc">
2148 <p>Stall cycles caused by an MVE instruction. </p>
2152 <a id="ga9a1cfef96ec7cd70acf134e368d8826a" name="ga9a1cfef96ec7cd70acf134e368d8826a"></a>
2153 <h2 class="memtitle"><span class="permalink"><a href="#ga9a1cfef96ec7cd70acf134e368d8826a">◆ </a></span>ARM_PMU_MVE_STALL_BREAK</h2>
2155 <div class="memitem">
2156 <div class="memproto">
2157 <table class="memname">
2159 <td class="memname">#define ARM_PMU_MVE_STALL_BREAK   0x02D3</td>
2162 </div><div class="memdoc">
2164 <p>Stall cycles caused by an MVE chain break. </p>
2168 <a id="ga29bc4c2e820914e94e2eb68a6a3352b9" name="ga29bc4c2e820914e94e2eb68a6a3352b9"></a>
2169 <h2 class="memtitle"><span class="permalink"><a href="#ga29bc4c2e820914e94e2eb68a6a3352b9">◆ </a></span>ARM_PMU_MVE_STALL_DEPENDENCY</h2>
2171 <div class="memitem">
2172 <div class="memproto">
2173 <table class="memname">
2175 <td class="memname">#define ARM_PMU_MVE_STALL_DEPENDENCY   0x02D4</td>
2178 </div><div class="memdoc">
2180 <p>Stall cycles caused by MVE register dependency. </p>
2184 <a id="ga8f4949084efce03d09bf5ba74cc91edd" name="ga8f4949084efce03d09bf5ba74cc91edd"></a>
2185 <h2 class="memtitle"><span class="permalink"><a href="#ga8f4949084efce03d09bf5ba74cc91edd">◆ </a></span>ARM_PMU_MVE_STALL_RESOURCE</h2>
2187 <div class="memitem">
2188 <div class="memproto">
2189 <table class="memname">
2191 <td class="memname">#define ARM_PMU_MVE_STALL_RESOURCE   0x02CD</td>
2194 </div><div class="memdoc">
2196 <p>Stall cycles caused by an MVE instruction because of resource conflicts. </p>
2200 <a id="ga7e76060791618f9b4d49ad493cfb6ba9" name="ga7e76060791618f9b4d49ad493cfb6ba9"></a>
2201 <h2 class="memtitle"><span class="permalink"><a href="#ga7e76060791618f9b4d49ad493cfb6ba9">◆ </a></span>ARM_PMU_MVE_STALL_RESOURCE_FP</h2>
2203 <div class="memitem">
2204 <div class="memproto">
2205 <table class="memname">
2207 <td class="memname">#define ARM_PMU_MVE_STALL_RESOURCE_FP   0x02CF</td>
2210 </div><div class="memdoc">
2212 <p>Stall cycles caused by an MVE instruction because of floating-point resource conflicts. </p>
2216 <a id="gaef33b3ff7f12d31238ff4dded5e67a11" name="gaef33b3ff7f12d31238ff4dded5e67a11"></a>
2217 <h2 class="memtitle"><span class="permalink"><a href="#gaef33b3ff7f12d31238ff4dded5e67a11">◆ </a></span>ARM_PMU_MVE_STALL_RESOURCE_INT</h2>
2219 <div class="memitem">
2220 <div class="memproto">
2221 <table class="memname">
2223 <td class="memname">#define ARM_PMU_MVE_STALL_RESOURCE_INT   0x02D0</td>
2226 </div><div class="memdoc">
2228 <p>Stall cycles caused by an MVE instruction because of integer resource conflicts. </p>
2232 <a id="gab486f5753edd9f10b0f100ff78944dd3" name="gab486f5753edd9f10b0f100ff78944dd3"></a>
2233 <h2 class="memtitle"><span class="permalink"><a href="#gab486f5753edd9f10b0f100ff78944dd3">◆ </a></span>ARM_PMU_MVE_STALL_RESOURCE_MEM</h2>
2235 <div class="memitem">
2236 <div class="memproto">
2237 <table class="memname">
2239 <td class="memname">#define ARM_PMU_MVE_STALL_RESOURCE_MEM   0x02CE</td>
2242 </div><div class="memdoc">
2244 <p>Stall cycles caused by an MVE instruction because of memory resource conflicts. </p>
2248 <a id="ga77fad5ad424271ed63fec98af071bb79" name="ga77fad5ad424271ed63fec98af071bb79"></a>
2249 <h2 class="memtitle"><span class="permalink"><a href="#ga77fad5ad424271ed63fec98af071bb79">◆ </a></span>ARM_PMU_MVE_VREDUCE_FP_RETIRED</h2>
2251 <div class="memitem">
2252 <div class="memproto">
2253 <table class="memname">
2255 <td class="memname">#define ARM_PMU_MVE_VREDUCE_FP_RETIRED   0x02A4</td>
2258 </div><div class="memdoc">
2260 <p>MVE floating-point vector reduction instruction architecturally executed. </p>
2264 <a id="gaa07c698f58c622d234a0007249717265" name="gaa07c698f58c622d234a0007249717265"></a>
2265 <h2 class="memtitle"><span class="permalink"><a href="#gaa07c698f58c622d234a0007249717265">◆ </a></span>ARM_PMU_MVE_VREDUCE_FP_SPEC</h2>
2267 <div class="memitem">
2268 <div class="memproto">
2269 <table class="memname">
2271 <td class="memname">#define ARM_PMU_MVE_VREDUCE_FP_SPEC   0x02A5</td>
2274 </div><div class="memdoc">
2276 <p>MVE floating-point vector reduction instruction speculatively executed. </p>
2280 <a id="ga649e7e81f0fd04ca6611f6a6c4035c57" name="ga649e7e81f0fd04ca6611f6a6c4035c57"></a>
2281 <h2 class="memtitle"><span class="permalink"><a href="#ga649e7e81f0fd04ca6611f6a6c4035c57">◆ </a></span>ARM_PMU_MVE_VREDUCE_INT_RETIRED</h2>
2283 <div class="memitem">
2284 <div class="memproto">
2285 <table class="memname">
2287 <td class="memname">#define ARM_PMU_MVE_VREDUCE_INT_RETIRED   0x02A8</td>
2290 </div><div class="memdoc">
2292 <p>MVE integer vector reduction instruction architecturally executed. </p>
2296 <a id="ga5b6f0bcfd63207c7bab03ea20167dd4b" name="ga5b6f0bcfd63207c7bab03ea20167dd4b"></a>
2297 <h2 class="memtitle"><span class="permalink"><a href="#ga5b6f0bcfd63207c7bab03ea20167dd4b">◆ </a></span>ARM_PMU_MVE_VREDUCE_INT_SPEC</h2>
2299 <div class="memitem">
2300 <div class="memproto">
2301 <table class="memname">
2303 <td class="memname">#define ARM_PMU_MVE_VREDUCE_INT_SPEC   0x02A9</td>
2306 </div><div class="memdoc">
2308 <p>MVE integer vector reduction instruction speculatively executed. </p>
2312 <a id="ga9546b924daa3c62e5f117026de58ad94" name="ga9546b924daa3c62e5f117026de58ad94"></a>
2313 <h2 class="memtitle"><span class="permalink"><a href="#ga9546b924daa3c62e5f117026de58ad94">◆ </a></span>ARM_PMU_MVE_VREDUCE_RETIRED</h2>
2315 <div class="memitem">
2316 <div class="memproto">
2317 <table class="memname">
2319 <td class="memname">#define ARM_PMU_MVE_VREDUCE_RETIRED   0x02A0</td>
2322 </div><div class="memdoc">
2324 <p>MVE vector reduction instruction architecturally executed. </p>
2328 <a id="gac714f988ae45871b2865f82c11383b36" name="gac714f988ae45871b2865f82c11383b36"></a>
2329 <h2 class="memtitle"><span class="permalink"><a href="#gac714f988ae45871b2865f82c11383b36">◆ </a></span>ARM_PMU_MVE_VREDUCE_SPEC</h2>
2331 <div class="memitem">
2332 <div class="memproto">
2333 <table class="memname">
2335 <td class="memname">#define ARM_PMU_MVE_VREDUCE_SPEC   0x02A1</td>
2338 </div><div class="memdoc">
2340 <p>MVE vector reduction instruction speculatively executed. </p>
2344 <a id="ga2fe9d3ea67ce833bd6323e4ce1a4e894" name="ga2fe9d3ea67ce833bd6323e4ce1a4e894"></a>
2345 <h2 class="memtitle"><span class="permalink"><a href="#ga2fe9d3ea67ce833bd6323e4ce1a4e894">◆ </a></span>ARM_PMU_OP_COMPLETE</h2>
2347 <div class="memitem">
2348 <div class="memproto">
2349 <table class="memname">
2351 <td class="memname">#define ARM_PMU_OP_COMPLETE   0x003A</td>
2354 </div><div class="memdoc">
2356 <p>Operation retired. </p>
2360 <a id="ga6c59149e9b1754987b44b62092bc9f09" name="ga6c59149e9b1754987b44b62092bc9f09"></a>
2361 <h2 class="memtitle"><span class="permalink"><a href="#ga6c59149e9b1754987b44b62092bc9f09">◆ </a></span>ARM_PMU_OP_SPEC</h2>
2363 <div class="memitem">
2364 <div class="memproto">
2365 <table class="memname">
2367 <td class="memname">#define ARM_PMU_OP_SPEC   0x003B</td>
2370 </div><div class="memdoc">
2372 <p>Operation speculatively executed. </p>
2376 <a id="ga54fd2c392399221077c67866a395e587" name="ga54fd2c392399221077c67866a395e587"></a>
2377 <h2 class="memtitle"><span class="permalink"><a href="#ga54fd2c392399221077c67866a395e587">◆ </a></span>ARM_PMU_PC_WRITE_RETIRED</h2>
2379 <div class="memitem">
2380 <div class="memproto">
2381 <table class="memname">
2383 <td class="memname">#define ARM_PMU_PC_WRITE_RETIRED   0x000C</td>
2386 </div><div class="memdoc">
2388 <p>Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass. </p>
2392 <a id="gaaae2c32a8ecd36b59ac98cf8e23b3cab" name="gaaae2c32a8ecd36b59ac98cf8e23b3cab"></a>
2393 <h2 class="memtitle"><span class="permalink"><a href="#gaaae2c32a8ecd36b59ac98cf8e23b3cab">◆ </a></span>ARM_PMU_SE_CALL_NS</h2>
2395 <div class="memitem">
2396 <div class="memproto">
2397 <table class="memname">
2399 <td class="memname">#define ARM_PMU_SE_CALL_NS   0x0115</td>
2402 </div><div class="memdoc">
2404 <p>Call to non-secure function, resulting in Security state change. </p>
2408 <a id="gad3ba2effbe303ca3fafdbc022fe206c1" name="gad3ba2effbe303ca3fafdbc022fe206c1"></a>
2409 <h2 class="memtitle"><span class="permalink"><a href="#gad3ba2effbe303ca3fafdbc022fe206c1">◆ </a></span>ARM_PMU_SE_CALL_S</h2>
2411 <div class="memitem">
2412 <div class="memproto">
2413 <table class="memname">
2415 <td class="memname">#define ARM_PMU_SE_CALL_S   0x0114</td>
2418 </div><div class="memdoc">
2420 <p>Call to secure function, resulting in Security state change. </p>
2424 <a id="ga8179d1144f8ec993bd1343e276d7b49b" name="ga8179d1144f8ec993bd1343e276d7b49b"></a>
2425 <h2 class="memtitle"><span class="permalink"><a href="#ga8179d1144f8ec993bd1343e276d7b49b">◆ </a></span>ARM_PMU_ST_RETIRED</h2>
2427 <div class="memitem">
2428 <div class="memproto">
2429 <table class="memname">
2431 <td class="memname">#define ARM_PMU_ST_RETIRED   0x0007</td>
2434 </div><div class="memdoc">
2436 <p>Memory-writing instruction architecturally executed and condition code check pass. </p>
2440 <a id="ga8bf75efa06a125ee2dfa9a130e7ba9a8" name="ga8bf75efa06a125ee2dfa9a130e7ba9a8"></a>
2441 <h2 class="memtitle"><span class="permalink"><a href="#ga8bf75efa06a125ee2dfa9a130e7ba9a8">◆ </a></span>ARM_PMU_STALL</h2>
2443 <div class="memitem">
2444 <div class="memproto">
2445 <table class="memname">
2447 <td class="memname">#define ARM_PMU_STALL   0x003C</td>
2450 </div><div class="memdoc">
2452 <p>Stall cycle for instruction or operation not sent for execution. </p>
2456 <a id="ga8737bee352820bd7d1bc8e5e4260143c" name="ga8737bee352820bd7d1bc8e5e4260143c"></a>
2457 <h2 class="memtitle"><span class="permalink"><a href="#ga8737bee352820bd7d1bc8e5e4260143c">◆ </a></span>ARM_PMU_STALL_BACKEND</h2>
2459 <div class="memitem">
2460 <div class="memproto">
2461 <table class="memname">
2463 <td class="memname">#define ARM_PMU_STALL_BACKEND   0x0024</td>
2466 </div><div class="memdoc">
2468 <p>No operation issued because of the backend. </p>
2472 <a id="ga5b068593baa831348664dfa7d44f5483" name="ga5b068593baa831348664dfa7d44f5483"></a>
2473 <h2 class="memtitle"><span class="permalink"><a href="#ga5b068593baa831348664dfa7d44f5483">◆ </a></span>ARM_PMU_STALL_FRONTEND</h2>
2475 <div class="memitem">
2476 <div class="memproto">
2477 <table class="memname">
2479 <td class="memname">#define ARM_PMU_STALL_FRONTEND   0x0023</td>
2482 </div><div class="memdoc">
2484 <p>No operation issued because of the frontend. </p>
2488 <a id="ga197b491f691110fb52aef4291782b6ab" name="ga197b491f691110fb52aef4291782b6ab"></a>
2489 <h2 class="memtitle"><span class="permalink"><a href="#ga197b491f691110fb52aef4291782b6ab">◆ </a></span>ARM_PMU_STALL_OP</h2>
2491 <div class="memitem">
2492 <div class="memproto">
2493 <table class="memname">
2495 <td class="memname">#define ARM_PMU_STALL_OP   0x003F</td>
2498 </div><div class="memdoc">
2500 <p>Instruction or operation slots not occupied each cycle. </p>
2504 <a id="ga9700ec74727a9fe3cd4cd40736628a23" name="ga9700ec74727a9fe3cd4cd40736628a23"></a>
2505 <h2 class="memtitle"><span class="permalink"><a href="#ga9700ec74727a9fe3cd4cd40736628a23">◆ </a></span>ARM_PMU_STALL_OP_BACKEND</h2>
2507 <div class="memitem">
2508 <div class="memproto">
2509 <table class="memname">
2511 <td class="memname">#define ARM_PMU_STALL_OP_BACKEND   0x003D</td>
2514 </div><div class="memdoc">
2516 <p>Stall cycle for instruction or operation not sent for execution due to pipeline backend. </p>
2520 <a id="ga69cfd3558cf6c6f3bb621ee75430427c" name="ga69cfd3558cf6c6f3bb621ee75430427c"></a>
2521 <h2 class="memtitle"><span class="permalink"><a href="#ga69cfd3558cf6c6f3bb621ee75430427c">◆ </a></span>ARM_PMU_STALL_OP_FRONTEND</h2>
2523 <div class="memitem">
2524 <div class="memproto">
2525 <table class="memname">
2527 <td class="memname">#define ARM_PMU_STALL_OP_FRONTEND   0x003E</td>
2530 </div><div class="memdoc">
2532 <p>Stall cycle for instruction or operation not sent for execution due to pipeline frontend. </p>
2536 <a id="ga6e02b08550d7e9b273ff7913f1b57bea" name="ga6e02b08550d7e9b273ff7913f1b57bea"></a>
2537 <h2 class="memtitle"><span class="permalink"><a href="#ga6e02b08550d7e9b273ff7913f1b57bea">◆ </a></span>ARM_PMU_SW_INCR</h2>
2539 <div class="memitem">
2540 <div class="memproto">
2541 <table class="memname">
2543 <td class="memname">#define ARM_PMU_SW_INCR   0x0000</td>
2546 </div><div class="memdoc">
2548 <p>Software update to the PMU_SWINC register, architecturally executed and condition code check pass. </p>
2552 <a id="gadaa75dc2ccfbf7a2263da9a9011f1603" name="gadaa75dc2ccfbf7a2263da9a9011f1603"></a>
2553 <h2 class="memtitle"><span class="permalink"><a href="#gadaa75dc2ccfbf7a2263da9a9011f1603">◆ </a></span>ARM_PMU_TRCEXTOUT0</h2>
2555 <div class="memitem">
2556 <div class="memproto">
2557 <table class="memname">
2559 <td class="memname">#define ARM_PMU_TRCEXTOUT0   0x4010</td>
2562 </div><div class="memdoc">
2564 <p>ETM external output 0. </p>
2568 <a id="ga47fe03fe6fe9bfebd98283cb57d94560" name="ga47fe03fe6fe9bfebd98283cb57d94560"></a>
2569 <h2 class="memtitle"><span class="permalink"><a href="#ga47fe03fe6fe9bfebd98283cb57d94560">◆ </a></span>ARM_PMU_TRCEXTOUT1</h2>
2571 <div class="memitem">
2572 <div class="memproto">
2573 <table class="memname">
2575 <td class="memname">#define ARM_PMU_TRCEXTOUT1   0x4011</td>
2578 </div><div class="memdoc">
2580 <p>ETM external output 1. </p>
2584 <a id="gab80e47ffebc3ae6ed2952756b020dbb9" name="gab80e47ffebc3ae6ed2952756b020dbb9"></a>
2585 <h2 class="memtitle"><span class="permalink"><a href="#gab80e47ffebc3ae6ed2952756b020dbb9">◆ </a></span>ARM_PMU_TRCEXTOUT2</h2>
2587 <div class="memitem">
2588 <div class="memproto">
2589 <table class="memname">
2591 <td class="memname">#define ARM_PMU_TRCEXTOUT2   0x4012</td>
2594 </div><div class="memdoc">
2596 <p>ETM external output 2. </p>
2600 <a id="gad70a3b074efd967485ffbfd3e387051d" name="gad70a3b074efd967485ffbfd3e387051d"></a>
2601 <h2 class="memtitle"><span class="permalink"><a href="#gad70a3b074efd967485ffbfd3e387051d">◆ </a></span>ARM_PMU_TRCEXTOUT3</h2>
2603 <div class="memitem">
2604 <div class="memproto">
2605 <table class="memname">
2607 <td class="memname">#define ARM_PMU_TRCEXTOUT3   0x4013</td>
2610 </div><div class="memdoc">
2612 <p>ETM external output 3. </p>
2616 <a id="ga45d5ea86fdc015f4fc100462150c92da" name="ga45d5ea86fdc015f4fc100462150c92da"></a>
2617 <h2 class="memtitle"><span class="permalink"><a href="#ga45d5ea86fdc015f4fc100462150c92da">◆ </a></span>ARM_PMU_UNALIGNED_LDST_RETIRED</h2>
2619 <div class="memitem">
2620 <div class="memproto">
2621 <table class="memname">
2623 <td class="memname">#define ARM_PMU_UNALIGNED_LDST_RETIRED   0x000F</td>
2626 </div><div class="memdoc">
2628 <p>Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass. </p>
2632 </div><!-- contents -->
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