begriffs open source - cmsis/blob - main/Core_A/group__CMSIS__Core__FunctionInterface.html

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 137 Content</h2></td></tr>
 138 <tr class="memitem:group__GIC__functions"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html">Generic Interrupt Controller Functions</a></td></tr>
 139 <tr class="memdesc:group__GIC__functions"><td class="mdescLeft">&#160;</td><td class="mdescRight">The Generic Interrupt Controller Functions grant access to the configuration, control and status registers of the Generic Interrupt Controller (GIC). <br /></td></tr>
 140 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
 141 <tr class="memitem:group__L1__cache__functions"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html">L1 Cache Functions</a></td></tr>
 142 <tr class="memdesc:group__L1__cache__functions"><td class="mdescLeft">&#160;</td><td class="mdescRight">L1 Cache Functions give support to enable, clean and invalidate level 1 instruction and data caches, as well as to enable branch target address cache. <br /></td></tr>
 143 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
 144 <tr class="memitem:group__L2__cache__functions"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__L2__cache__functions.html">L2C-310 Cache Controller Functions</a></td></tr>
 145 <tr class="memdesc:group__L2__cache__functions"><td class="mdescLeft">&#160;</td><td class="mdescRight">L2C-310 Cache Controller gives access to functions for level 2 cache maintenance.<br  />
 146 Reference: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0246h/index.html">Level 2 Cache Controller L2C-310 Technical Reference Manual</a>. <br /></td></tr>
 147 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
 148 <tr class="memitem:group__PL1__timer__functions"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__PL1__timer__functions.html">Generic Physical Timer Functions</a></td></tr>
 149 <tr class="memdesc:group__PL1__timer__functions"><td class="mdescLeft">&#160;</td><td class="mdescRight">Generic Physical Timer Functions allow to control privilege level 1 physical timer registers on Generic Timer for Cortex-A7 class devices.<br  />
 150 Reference: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/index.html">Cortex-A7 MPCore Technical Reference Manual</a>. <br /></td></tr>
 151 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
 152 <tr class="memitem:group__PTM__timer__functions"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__PTM__timer__functions.html">Private Timer Functions</a></td></tr>
 153 <tr class="memdesc:group__PTM__timer__functions"><td class="mdescLeft">&#160;</td><td class="mdescRight">Private Timer Functions controls private timer registers present on Cortex-A5 and A9 class devices.<br  />
 154 References: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0434c/index.html">Cortex-A5 MPCore Technical Reference Manual</a>, <a href="http://infocenter.arm.com/help/topic/com.arm.doc.100486_0401_10_en/index.html">Cortex-A9 MPCore Technical Reference Manual</a>. <br /></td></tr>
 155 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
 156 <tr class="memitem:group__MMU__functions"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html">Memory Management Unit Functions</a></td></tr>
 157 <tr class="memdesc:group__MMU__functions"><td class="mdescLeft">&#160;</td><td class="mdescRight">MMU Functions provide control of the Memory Management Unit using translation tables and attributes of different regions of the physical memory map.<br  />
 158 Reference: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0406c/index.html">Architecture Reference Manual Reference Manual - Armv7-A and Armv7-R edition</a>. <br /></td></tr>
 159 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
 160 <tr class="memitem:group__FPU__functions"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__FPU__functions.html">Floating Point Unit Functions</a></td></tr>
 161 <tr class="memdesc:group__FPU__functions"><td class="mdescLeft">&#160;</td><td class="mdescRight">FPU Functions enable the use of Floating Point instructions and extensions.<br  />
 162 Reference: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0406c/index.html">Architecture Reference Manual Reference Manual - Armv7-A and Armv7-R edition</a>. <br /></td></tr>
 163 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
 164 </table>
 165 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
 166 <p>Hardware Abstraction Layer. The Core-A function interface contains:</p><ul>
 167 <li><a class="el" href="group__FPU__functions.html">Floating Point Unit Functions</a></li>
 168 <li><a class="el" href="group__GIC__functions.html">Generic Interrupt Controller Functions</a></li>
 169 <li><a class="el" href="group__L1__cache__functions.html">L1 Cache Functions</a></li>
 170 <li><a class="el" href="group__L2__cache__functions.html">L2C-310 Cache Controller Functions</a></li>
 171 <li><a class="el" href="group__MMU__functions.html">Memory Management Unit Functions</a></li>
 172 <li><a class="el" href="group__PL1__timer__functions.html">Generic Physical Timer Functions</a></li>
 173 <li><a class="el" href="group__PTM__timer__functions.html">Private Timer Functions</a> </li>
 174 </ul>
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