begriffs open source - cmsis/blob - ARM.CMSIS.pdsc

   1 <?xml version="1.0" encoding="UTF-8"?>
   2
   3 <package schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="PACK.xsd">
   4   <name>CMSIS</name>
   5   <description>CMSIS (Cortex Microcontroller Software Interface Standard)</description>
   6   <vendor>ARM</vendor>
   7   <!-- <license>license.txt</license> -->
   8   <url>http://www.keil.com/pack/</url>
   9
  10   <releases>
  11     <release version="5.5.0-dev4">
  12       Active development ...
  13       CMSIS-Core(M):
  14        - Added generic Armv8.1-M Mainline device support.
  15     </release>
  16     <release version="5.5.0-dev3">
  17       CMSIS-Driver:
  18         - Added WiFi Driver API 1.0.0-beta
  19     </release>
  20     <release version="5.5.0-dev2">
  21       CMSIS-Core(M):
  22         - Reworked Stack/Heap configuration for ARM startup files.
  23         - Added Cortex-M35P device support.
  24       CMSIS-RTOS2:
  25         - RTX 5.5.0 (see revision history for details)
  26       DSP_Lib:
  27         - updated arm_math.h
  28         - reduced ARM_MATH_CMx macros
  29         - added GitHub pull requests
  30     </release>
  31     <release version="5.4.0" date="2018-08-01">
  32       Aligned pack structure with repository.
  33       The following folders are deprecated:
  34         - CMSIS/Include/
  35         - CMSIS/DSP_Lib/
  36
  37       CMSIS-Core(M): 5.1.2 (see revision history for details)
  38         - Added Cortex-M1 support (beta).
  39       CMSIS-Core(A): 1.1.2 (see revision history for details)
  40       CMSIS-NN: 1.1.0
  41         - Added new math functions.
  42       CMSIS-RTOS2:
  43         - API 2.1.3 (see revision history for details)
  44         - RTX 5.4.0 (see revision history for details)
  45           * Updated exception handling on Cortex-A
  46       CMSIS-Driver:
  47         - Flash Driver API V2.2.0
  48       Utilities:
  49         - SVDConv 3.3.21
  50         - PackChk 1.3.71
  51     </release>
  52     <release version="5.3.0" date="2018-02-22">
  53       Updated Arm company brand.
  54       CMSIS-Core(M): 5.1.1 (see revision history for details)
  55       CMSIS-Core(A): 1.1.1 (see revision history for details)
  56       CMSIS-DAP: 2.0.0 (see revision history for details)
  57       CMSIS-NN: 1.0.0
  58         - Initial contribution of the bare metal Neural Network Library.
  59       CMSIS-RTOS2:
  60         - RTX 5.3.0 (see revision history for details)
  61         - OS Tick API 1.0.1
  62     </release>
  63     <release version="5.2.0" date="2017-11-16">
  64       CMSIS-Core(M): 5.1.0 (see revision history for details)
  65         - Added MPU Functions for ARMv8-M for Cortex-M23/M33.
  66         - Added compiler_iccarm.h to replace compiler_iar.h shipped with the compiler.
  67       CMSIS-Core(A): 1.1.0 (see revision history for details)
  68         - Added compiler_iccarm.h.
  69         - Added additional access functions for physical timer.
  70       CMSIS-DAP: 1.2.0 (see revision history for details)
  71       CMSIS-DSP: 1.5.2 (see revision history for details)
  72       CMSIS-Driver: 2.6.0 (see revision history for details)
  73         - CAN Driver API V1.2.0
  74         - NAND Driver API V2.3.0
  75       CMSIS-RTOS:
  76         - RTX: added variant for Infineon XMC4 series affected by PMU_CM.001 errata.
  77       CMSIS-RTOS2:
  78         - API 2.1.2 (see revision history for details)
  79         - RTX 5.2.3 (see revision history for details)
  80       Devices:
  81         - Added GCC startup and linker script for Cortex-A9.
  82         - Added device ARMCM0plus_MPU for Cortex-M0+ with MPU.
  83         - Added IAR startup code for Cortex-A9
  84     </release>
  85     <release version="5.1.1" date="2017-09-19">
  86       CMSIS-RTOS2:
  87       - RTX 5.2.1 (see revision history for details)
  88     </release>
  89     <release version="5.1.0" date="2017-08-04">
  90       CMSIS-Core(M): 5.0.2 (see revision history for details)
  91       - Changed Version Control macros to be core agnostic.
  92       - Added MPU Functions for ARMv7-M for Cortex-M0+/M3/M4/M7.
  93       CMSIS-Core(A): 1.0.0 (see revision history for details)
  94       - Initial release
  95       - IRQ Controller API 1.0.0
  96       CMSIS-Driver: 2.05 (see revision history for details)
  97       - All typedefs related to status have been made volatile.
  98       CMSIS-RTOS2:
  99       - API 2.1.1 (see revision history for details)
 100       - RTX 5.2.0 (see revision history for details)
 101       - OS Tick API 1.0.0
 102       CMSIS-DSP: 1.5.2 (see revision history for details)
 103       - Fixed GNU Compiler specific diagnostics.
 104       CMSIS-Pack: 1.5.0 (see revision history for details)
 105       - added System Description File (*.SDF) Format
 106       CMSIS-Zone: 0.0.1 (Preview)
 107       - Initial specification draft
 108     </release>
 109     <release version="5.0.1" date="2017-02-03">
 110       Package Description:
 111       - added taxonomy for Cclass RTOS
 112       CMSIS-RTOS2:
 113       - API 2.1   (see revision history for details)
 114       - RTX 5.1.0 (see revision history for details)
 115       CMSIS-Core: 5.0.1 (see revision history for details)
 116       - Added __PACKED_STRUCT macro
 117       - Added uVisior support
 118       - Updated cmsis_armcc.h: corrected macro __ARM_ARCH_6M__
 119       - Updated template for secure main function (main_s.c)
 120       - Updated template for Context Management for ARMv8-M TrustZone (tz_context.c)
 121       CMSIS-DSP: 1.5.1 (see revision history for details)
 122       - added ARMv8M DSP libraries.
 123       CMSIS-Pack:1.4.9 (see revision history for details)
 124       - added Pack Index File specification and schema file
 125     </release>
 126     <release version="5.0.0" date="2016-11-11">
 127       Changed open source license to Apache 2.0
 128       CMSIS_Core:
 129        - Added support for Cortex-M23 and Cortex-M33.
 130        - Added ARMv8-M device configurations for mainline and baseline.
 131        - Added CMSE support and thread context management for TrustZone for ARMv8-M
 132        - Added cmsis_compiler.h to unify compiler behaviour.
 133        - Updated function SCB_EnableICache (for Cortex-M7).
 134        - Added functions: NVIC_GetEnableIRQ, SCB_GetFPUType
 135       CMSIS-RTOS:
 136         - bug fix in RTX 4.82 (see revision history for details)
 137       CMSIS-RTOS2:
 138         - new API including compatibility layer to CMSIS-RTOS
 139         - reference implementation based on RTX5
 140         - supports all Cortex-M variants including TrustZone for ARMv8-M
 141       CMSIS-SVD:
 142        - reworked SVD format documentation
 143        - removed SVD file database documentation as SVD files are distributed in packs
 144        - updated SVDConv for Win32 and Linux
 145       CMSIS-DSP:
 146        - Moved DSP libraries from CMSIS/DSP/Lib to CMSIS/Lib.
 147        - Added DSP libraries build projects to CMSIS pack.
 148     </release>
 149     <release version="4.5.0" date="2015-10-28">
 150       - CMSIS-Core     4.30.0  (see revision history for details)
 151       - CMSIS-DAP      1.1.0   (unchanged)
 152       - CMSIS-Driver   2.04.0  (see revision history for details)
 153       - CMSIS-DSP      1.4.7   (no source code change [still labeled 1.4.5], see revision history for details)
 154       - CMSIS-Pack     1.4.1   (see revision history for details)
 155       - CMSIS-RTOS     4.80.0  Restored time delay parameter 'millisec' old behavior (prior V4.79) for software compatibility. (see revision history for details)
 156       - CMSIS-SVD      1.3.1   (see revision history for details)
 157     </release>
 158     <release version="4.4.0" date="2015-09-11">
 159       - CMSIS-Core     4.20   (see revision history for details)
 160       - CMSIS-DSP      1.4.6  (no source code change [still labeled 1.4.5], see revision history for details)
 161       - CMSIS-Pack     1.4.0  (adding memory attributes, algorithm style)
 162       - CMSIS-Driver   2.03.0 (adding CAN [Controller Area Network] API)
 163       - CMSIS-RTOS
 164         -- API         1.02   (unchanged)
 165         -- RTX         4.79   (see revision history for details)
 166       - CMSIS-SVD      1.3.0  (see revision history for details)
 167       - CMSIS-DAP      1.1.0  (extended with SWO support)
 168     </release>
 169     <release version="4.3.0" date="2015-03-20">
 170       - CMSIS-Core     4.10   (Cortex-M7 extended Cache Maintenance functions)
 171       - CMSIS-DSP      1.4.5  (see revision history for details)
 172       - CMSIS-Driver   2.02   (adding SAI (Serial Audio Interface) API)
 173       - CMSIS-Pack     1.3.3  (Semantic Versioning, Generator extensions)
 174       - CMSIS-RTOS
 175         -- API         1.02   (unchanged)
 176         -- RTX         4.78   (see revision history for details)
 177       - CMSIS-SVD      1.2    (unchanged)
 178     </release>
 179     <release version="4.2.0" date="2014-09-24">
 180       Adding Cortex-M7 support
 181       - CMSIS-Core     4.00  (Cortex-M7 support, corrected C++ include guards in core header files)
 182       - CMSIS-DSP      1.4.4 (Cortex-M7 support and corrected out of bound issues)
 183       - CMSIS-Pack     1.3.1 (Cortex-M7 updates, clarification, corrected batch files in Tutorial)
 184       - CMSIS-SVD      1.2   (Cortex-M7 extensions)
 185       - CMSIS-RTOS RTX 4.75  (see revision history for details)
 186     </release>
 187     <release version="4.1.1" date="2014-06-30">
 188       - fixed conditions preventing the inclusion of the DSP library in projects for Infineon XMC4000 series devices
 189     </release>
 190     <release version="4.1.0" date="2014-06-12">
 191       - CMSIS-Driver   2.02  (incompatible update)
 192       - CMSIS-Pack     1.3   (see revision history for details)
 193       - CMSIS-DSP      1.4.2 (unchanged)
 194       - CMSIS-Core     3.30  (unchanged)
 195       - CMSIS-RTOS RTX 4.74  (unchanged)
 196       - CMSIS-RTOS API 1.02  (unchanged)
 197       - CMSIS-SVD      1.10  (unchanged)
 198       PACK:
 199       - removed G++ specific files from PACK
 200       - added Component Startup variant "C Startup"
 201       - added Pack Checking Utility
 202       - updated conditions to reflect tool-chain dependency
 203       - added Taxonomy for Graphics
 204       - updated Taxonomy for unified drivers from "Drivers" to "CMSIS Drivers"
 205     </release>
 206     <release version="4.0.0">
 207       - CMSIS-Driver   2.00  Preliminary (incompatible update)
 208       - CMSIS-Pack     1.1   Preliminary
 209       - CMSIS-DSP      1.4.2 (see revision history for details)
 210       - CMSIS-Core     3.30  (see revision history for details)
 211       - CMSIS-RTOS RTX 4.74  (see revision history for details)
 212       - CMSIS-RTOS API 1.02  (unchanged)
 213       - CMSIS-SVD      1.10  (unchanged)
 214     </release>
 215     <release version="3.20.4">
 216       - CMSIS-RTOS 4.74 (see revision history for details)
 217       - PACK Extensions (Boards, Device Features, Flash Programming, Generators, Configuration Wizard). Schema version 1.1.
 218     </release>
 219     <release version="3.20.3">
 220       - CMSIS-Driver API Version 1.10 ARM prefix added (incompatible change)
 221       - CMSIS-RTOS 4.73 (see revision history for details)
 222     </release>
 223     <release version="3.20.2">
 224       - CMSIS-Pack documentation has been added
 225       - CMSIS-Drivers header and documentation have been added to PACK
 226       - CMSIS-CORE, CMSIS-DSP, CMSIS-RTOS API and CMSIS-SVD remain unchanged
 227     </release>
 228     <release version="3.20.1">
 229       - CMSIS-RTOS Keil RTX V4.72 has been added to PACK
 230       - CMSIS-CORE, CMSIS-DSP, CMSIS-RTOS API and CMSIS-SVD remain unchanged
 231     </release>
 232     <release version="3.20.0">
 233       The software portions that are deployed in the application program are now under a BSD license which allows usage
 234       of CMSIS components in any commercial or open source projects.  The Pack Description file Arm.CMSIS.pdsc describes the use cases
 235       The individual components have been update as listed below:
 236       - CMSIS-CORE adds functions for setting breakpoints, supports the latest GCC Compiler, and contains several corrections.
 237       - CMSIS-DSP library is optimized for more performance and contains several bug fixes.
 238       - CMSIS-RTOS API is extended with capabilities for short timeouts, Kernel initialization, and prepared for a C++ interface.
 239       - CMSIS-SVD is unchanged.
 240     </release>
 241   </releases>
 242
 243   <taxonomy>
 244     <description Cclass="Board Support">Generic Interfaces for Evaluation and Development Boards</description>
 245     <description Cclass="CMSIS" doc="CMSIS/Documentation/General/html/index.html">Cortex Microcontroller Software Interface Components</description>
 246     <description Cclass="Device" doc="CMSIS/Documentation/Core/html/index.html">Startup, System Setup</description>
 247     <description Cclass="CMSIS Driver" doc="CMSIS/Documentation/Driver/html/index.html">Unified Device Drivers compliant to CMSIS-Driver Specifications</description>
 248     <description Cclass="File System">File Drive Support and File System</description>
 249     <description Cclass="Graphics">Graphical User Interface</description>
 250     <description Cclass="Network">Network Stack using Internet Protocols</description>
 251     <description Cclass="USB">Universal Serial Bus Stack</description>
 252     <description Cclass="Compiler">Compiler Software Extensions</description>
 253     <description Cclass="RTOS">Real-time Operating System</description>
 254   </taxonomy>
 255
 256   <devices>
 257     <!-- ******************************  Cortex-M0  ****************************** -->
 258     <family Dfamily="ARM Cortex M0" Dvendor="ARM:82">
 259       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/index.html" title="Cortex-M0 Device Generic Users Guide"/>
 260       <description>
 261 The Cortex-M0 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 262 - simple, easy-to-use programmers model
 263 - highly efficient ultra-low power operation
 264 - excellent code density
 265 - deterministic, high-performance interrupt handling
 266 - upward compatibility with the rest of the Cortex-M processor family.
 267       </description>
 268       <!-- debug svd="Device/ARM/SVD/ARMCM0.svd"/ SVD files do not contain any peripheral -->
 269       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 270       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 271       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 272
 273       <device Dname="ARMCM0">
 274         <processor Dcore="Cortex-M0" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
 275         <compile header="Device/ARM/ARMCM0/Include/ARMCM0.h" define="ARMCM0"/>
 276       </device>
 277     </family>
 278
 279     <!-- ******************************  Cortex-M0P  ****************************** -->
 280     <family Dfamily="ARM Cortex M0 plus" Dvendor="ARM:82">
 281       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0662b/index.html" title="Cortex-M0+ Device Generic Users Guide"/>
 282       <description>
 283 The Cortex-M0+ processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 284 - simple, easy-to-use programmers model
 285 - highly efficient ultra-low power operation
 286 - excellent code density
 287 - deterministic, high-performance interrupt handling
 288 - upward compatibility with the rest of the Cortex-M processor family.
 289       </description>
 290       <!-- debug svd="Device/ARM/SVD/ARMCM0P.svd"/ SVD files do not contain any peripheral -->
 291       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 292       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 293       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 294
 295       <device Dname="ARMCM0P">
 296         <processor Dcore="Cortex-M0+" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
 297         <compile header="Device/ARM/ARMCM0plus/Include/ARMCM0plus.h" define="ARMCM0P"/>
 298       </device>
 299
 300       <device Dname="ARMCM0P_MPU">
 301         <processor Dcore="Cortex-M0+" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 302         <compile header="Device/ARM/ARMCM0plus/Include/ARMCM0plus_MPU.h" define="ARMCM0P_MPU"/>
 303       </device>
 304     </family>
 305
 306     <!-- ******************************  Cortex-M1  ****************************** -->
 307     <family Dfamily="ARM Cortex M1" Dvendor="ARM:82">
 308       <!--book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/index.html" title="Cortex-M1 Device Generic Users Guide"/-->
 309       <description>
 310 The ARM Cortex-M1 FPGA processor is intended for deeply embedded applications that require a small processor integrated into an FPGA.
 311 The ARM Cortex-M1 processor implements the ARMv6-M architecture profile.
 312       </description>
 313       <!-- debug svd="Device/ARM/SVD/ARMCM0.svd"/ SVD files do not contain any peripheral -->
 314       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 315       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 316       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 317
 318       <device Dname="ARMCM1">
 319         <processor Dcore="Cortex-M1" DcoreVersion="r1p0" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
 320         <compile header="Device/ARM/ARMCM1/Include/ARMCM1.h" define="ARMCM1"/>
 321       </device>
 322     </family>
 323
 324     <!-- ******************************  Cortex-M3  ****************************** -->
 325     <family Dfamily="ARM Cortex M3" Dvendor="ARM:82">
 326       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/index.html" title="Cortex-M3 Device Generic Users Guide"/>
 327       <description>
 328 The Cortex-M3 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 329 - simple, easy-to-use programmers model
 330 - highly efficient ultra-low power operation
 331 - excellent code density
 332 - deterministic, high-performance interrupt handling
 333 - upward compatibility with the rest of the Cortex-M processor family.
 334       </description>
 335       <!-- debug svd="Device/ARM/SVD/ARMCM3.svd"/ SVD files do not contain any peripheral -->
 336       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 337       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 338       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 339
 340       <device Dname="ARMCM3">
 341         <processor Dcore="Cortex-M3" DcoreVersion="r2p1" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 342         <compile header="Device/ARM/ARMCM3/Include/ARMCM3.h" define="ARMCM3"/>
 343       </device>
 344     </family>
 345
 346     <!-- ******************************  Cortex-M4  ****************************** -->
 347     <family Dfamily="ARM Cortex M4" Dvendor="ARM:82">
 348       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/index.html" title="Cortex-M4 Device Generic Users Guide"/>
 349       <description>
 350 The Cortex-M4 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 351 - simple, easy-to-use programmers model
 352 - highly efficient ultra-low power operation
 353 - excellent code density
 354 - deterministic, high-performance interrupt handling
 355 - upward compatibility with the rest of the Cortex-M processor family.
 356       </description>
 357       <!-- debug svd="Device/ARM/SVD/ARMCM4.svd"/ SVD files do not contain any peripheral -->
 358       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 359       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 360       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 361
 362       <device Dname="ARMCM4">
 363         <processor Dcore="Cortex-M4" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 364         <compile header="Device/ARM/ARMCM4/Include/ARMCM4.h"    define="ARMCM4"/>
 365       </device>
 366
 367       <device Dname="ARMCM4_FP">
 368         <processor Dcore="Cortex-M4" DcoreVersion="r0p1" Dfpu="SP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 369         <compile header="Device/ARM/ARMCM4/Include/ARMCM4_FP.h" define="ARMCM4_FP"/>
 370       </device>
 371     </family>
 372
 373     <!-- ******************************  Cortex-M7  ****************************** -->
 374     <family Dfamily="ARM Cortex M7" Dvendor="ARM:82">
 375       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0646b/index.html" title="Cortex-M7 Device Generic Users Guide"/>
 376       <description>
 377 The Cortex-M7 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 378 - simple, easy-to-use programmers model
 379 - highly efficient ultra-low power operation
 380 - excellent code density
 381 - deterministic, high-performance interrupt handling
 382 - upward compatibility with the rest of the Cortex-M processor family.
 383       </description>
 384       <!-- debug svd="Device/ARM/SVD/ARMCM7.svd"/ SVD files do not contain any peripheral -->
 385       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 386       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 387       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 388
 389       <device Dname="ARMCM7">
 390         <processor Dcore="Cortex-M7" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 391         <compile header="Device/ARM/ARMCM7/Include/ARMCM7.h" define="ARMCM7"/>
 392       </device>
 393
 394       <device Dname="ARMCM7_SP">
 395         <processor Dcore="Cortex-M7" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 396         <compile header="Device/ARM/ARMCM7/Include/ARMCM7_SP.h" define="ARMCM7_SP"/>
 397       </device>
 398
 399       <device Dname="ARMCM7_DP">
 400         <processor Dcore="Cortex-M7" DcoreVersion="r0p0" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 401         <compile header="Device/ARM/ARMCM7/Include/ARMCM7_DP.h" define="ARMCM7_DP"/>
 402       </device>
 403     </family>
 404
 405     <!-- ******************************  Cortex-M23  ********************** -->
 406     <family Dfamily="ARM Cortex M23" Dvendor="ARM:82">
 407       <!--book name="Device/ARM/Documents/??_dgug.pdf"       title="?? Device Generic Users Guide"/-->
 408       <description>
 409 The Arm Cortex-M23 is based on the Armv8-M baseline architecture.
 410 It is the smallest and most energy efficient Arm processor with Arm TrustZone technology.
 411 Cortex-M23 is the ideal processor for constrained embedded applications requiring efficient security.
 412       </description>
 413       <!-- debug svd="Device/ARM/SVD/ARMCM23.svd"/ SVD files do not contain any peripheral -->
 414       <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
 415       <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
 416       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 417       <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
 418       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 419
 420       <device Dname="ARMCM23">
 421         <processor Dcore="Cortex-M23" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
 422         <compile header="Device/ARM/ARMCM23/Include/ARMCM23.h" define="ARMCM23"/>
 423       </device>
 424
 425       <device Dname="ARMCM23_TZ">
 426         <processor Dcore="Cortex-M23" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 427         <compile header="Device/ARM/ARMCM23/Include/ARMCM23_TZ.h" define="ARMCM23_TZ"/>
 428       </device>
 429     </family>
 430
 431     <!-- ******************************  Cortex-M33  ****************************** -->
 432     <family Dfamily="ARM Cortex M33" Dvendor="ARM:82">
 433       <!--book name="Device/ARM/Documents/??_dgug.pdf"       title="?? Device Generic Users Guide"/-->
 434       <description>
 435 The Arm Cortex-M33 is the most configurable of all Cortex-M processors. It is a full featured microcontroller
 436 class processor based on the Armv8-M mainline architecture with Arm TrustZone security.
 437       </description>
 438       <!-- debug svd="Device/ARM/SVD/ARMCM33.svd"/ SVD files do not contain any peripheral -->
 439       <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
 440       <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
 441       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 442       <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
 443       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"          default="1"/-->
 444
 445       <device Dname="ARMCM33">
 446         <processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
 447         <description>
 448           no DSP Instructions, no Floating Point Unit, no TrustZone
 449         </description>
 450         <compile header="Device/ARM/ARMCM33/Include/ARMCM33.h" define="ARMCM33"/>
 451       </device>
 452
 453       <device Dname="ARMCM33_TZ">
 454         <processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 455         <description>
 456           no DSP Instructions, no Floating Point Unit, TrustZone
 457         </description>
 458         <compile header="Device/ARM/ARMCM33/Include/ARMCM33_TZ.h" define="ARMCM33_TZ"/>
 459       </device>
 460
 461       <device Dname="ARMCM33_DSP_FP">
 462         <processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
 463         <description>
 464           DSP Instructions, Single Precision Floating Point Unit, no TrustZone
 465         </description>
 466         <compile header="Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP.h" define="ARMCM33_DSP_FP"/>
 467       </device>
 468
 469       <device Dname="ARMCM33_DSP_FP_TZ">
 470         <processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 471         <description>
 472           DSP Instructions, Single Precision Floating Point Unit, TrustZone
 473         </description>
 474         <compile header="Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h" define="ARMCM33_DSP_FP_TZ"/>
 475       </device>
 476     </family>
 477
 478     <!-- ******************************  Cortex-M35P  ****************************** -->
 479     <family Dfamily="ARM Cortex M35P" Dvendor="ARM:82">
 480       <!--book name="Device/ARM/Documents/??_dgug.pdf"       title="?? Device Generic Users Guide"/-->
 481       <description>
 482 The Arm Cortex-M35P is the most configurable of all Cortex-M processors. It is a full featured microcontroller
 483 class processor based on the Armv8-M mainline architecture with Arm TrustZone security designed for a broad range of secure embedded applications.
 484       </description>
 485
 486       <!-- debug svd="Device/ARM/SVD/ARMCM35P.svd"/ SVD files do not contain any peripheral -->
 487       <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
 488       <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
 489       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 490       <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
 491       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"          default="1"/-->
 492
 493       <device Dname="ARMCM35P">
 494         <processor Dcore="Cortex-M35P" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
 495         <description>
 496           no DSP Instructions, no Floating Point Unit, no TrustZone
 497         </description>
 498         <compile header="Device/ARM/ARMCM35P/Include/ARMCM35P.h" define="ARMCM35P"/>
 499       </device>
 500
 501       <device Dname="ARMCM35P_TZ">
 502         <processor Dcore="Cortex-M35P" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 503         <description>
 504           no DSP Instructions, no Floating Point Unit, TrustZone
 505         </description>
 506         <compile header="Device/ARM/ARMCM35P/Include/ARMCM35P_TZ.h" define="ARMCM35P_TZ"/>
 507       </device>
 508
 509       <device Dname="ARMCM35P_DSP_FP">
 510         <processor Dcore="Cortex-M35P" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
 511         <description>
 512           DSP Instructions, Single Precision Floating Point Unit, no TrustZone
 513         </description>
 514         <compile header="Device/ARM/ARMCM35P/Include/ARMCM35P_DSP_FP.h" define="ARMCM35P_DSP_FP"/>
 515       </device>
 516
 517       <device Dname="ARMCM35P_DSP_FP_TZ">
 518         <processor Dcore="Cortex-M35P" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 519         <description>
 520           DSP Instructions, Single Precision Floating Point Unit, TrustZone
 521         </description>
 522         <compile header="Device/ARM/ARMCM35P/Include/ARMCM35P_DSP_FP_TZ.h" define="ARMCM35P_DSP_FP_TZ"/>
 523       </device>
 524     </family>
 525
 526     <!-- ******************************  ARMSC000  ****************************** -->
 527     <family Dfamily="ARM SC000" Dvendor="ARM:82">
 528       <description>
 529 The Arm SC000 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including:
 530 - simple, easy-to-use programmers model
 531 - highly efficient ultra-low power operation
 532 - excellent code density
 533 - deterministic, high-performance interrupt handling
 534       </description>
 535       <!-- debug svd="Device/ARM/SVD/ARMSC000.svd"/ SVD files do not contain any peripheral -->
 536       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 537       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 538       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 539
 540       <device Dname="ARMSC000">
 541         <processor Dcore="SC000" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
 542         <compile header="Device/ARM/ARMSC000/Include/ARMSC000.h" define="ARMSC000"/>
 543       </device>
 544     </family>
 545
 546     <!-- ******************************  ARMSC300  ****************************** -->
 547     <family Dfamily="ARM SC300" Dvendor="ARM:82">
 548       <description>
 549 The ARM SC300 processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including:
 550 - simple, easy-to-use programmers model
 551 - highly efficient ultra-low power operation
 552 - excellent code density
 553 - deterministic, high-performance interrupt handling
 554       </description>
 555       <!-- debug svd="Device/ARM/SVD/ARMSC300.svd"/ SVD files do not contain any peripheral -->
 556       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 557       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 558       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 559
 560       <device Dname="ARMSC300">
 561         <processor Dcore="SC300" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
 562         <compile header="Device/ARM/ARMSC300/Include/ARMSC300.h" define="ARMSC300"/>
 563       </device>
 564     </family>
 565
 566     <!-- ******************************  ARMv8-M Baseline  ********************** -->
 567     <family Dfamily="ARMv8-M Baseline" Dvendor="ARM:82">
 568       <!--book name="Device/ARM/Documents/ARMv8MBL_dgug.pdf"       title="ARMv8MBL Device Generic Users Guide"/-->
 569       <description>
 570 Armv8-M Baseline based device with TrustZone
 571       </description>
 572       <!-- debug svd="Device/ARM/SVD/ARMv8MBL.svd"/ SVD files do not contain any peripheral -->
 573       <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
 574       <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
 575       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 576       <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
 577       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 578
 579       <device Dname="ARMv8MBL">
 580         <processor Dcore="ARMV8MBL" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 581         <compile header="Device/ARM/ARMv8MBL/Include/ARMv8MBL.h" define="ARMv8MBL"/>
 582       </device>
 583     </family>
 584
 585     <!-- ******************************  ARMv8-M Mainline  ****************************** -->
 586     <family Dfamily="ARMv8-M Mainline" Dvendor="ARM:82">
 587       <!--book name="Device/ARM/Documents/ARMv8MML_dgug.pdf"       title="ARMv8MML Device Generic Users Guide"/-->
 588       <description>
 589 Armv8-M Mainline based device with TrustZone
 590       </description>
 591       <!-- debug svd="Device/ARM/SVD/ARMv8MML.svd"/ SVD files do not contain any peripheral -->
 592       <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
 593       <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
 594       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 595       <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
 596       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 597
 598       <device Dname="ARMv8MML">
 599         <processor Dcore="ARMV8MML" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 600         <description>
 601           no DSP Instructions, no Floating Point Unit, TrustZone
 602         </description>
 603         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML.h" define="ARMv8MML"/>
 604       </device>
 605
 606       <device Dname="ARMv8MML_DSP">
 607         <processor Dcore="ARMV8MML" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 608         <description>
 609           DSP Instructions, no Floating Point Unit, TrustZone
 610         </description>
 611         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DSP.h" define="ARMv8MML_DSP"/>
 612       </device>
 613
 614       <device Dname="ARMv8MML_SP">
 615         <processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 616         <description>
 617           no DSP Instructions, Single Precision Floating Point Unit, TrustZone
 618         </description>
 619         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_SP.h" define="ARMv8MML_SP"/>
 620       </device>
 621
 622       <device Dname="ARMv8MML_DSP_SP">
 623         <processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 624         <description>
 625           DSP Instructions, Single Precision Floating Point Unit, TrustZone
 626         </description>
 627         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_SP.h" define="ARMv8MML_DSP_SP"/>
 628       </device>
 629
 630       <device Dname="ARMv8MML_DP">
 631         <processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="DP_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 632         <description>
 633           no DSP Instructions, Double Precision Floating Point Unit, TrustZone
 634         </description>
 635         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DP.h" define="ARMv8MML_DP"/>
 636       </device>
 637
 638       <device Dname="ARMv8MML_DSP_DP">
 639         <processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="DP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 640         <description>
 641           DSP Instructions, Double Precision Floating Point Unit, TrustZone
 642         </description>
 643         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h" define="ARMv8MML_DSP_DP"/>
 644       </device>
 645     </family>
 646
 647     <!-- ******************************  ARMv8.1-M Mainline  ****************************** -->
 648     <family Dfamily="ARMv8.1-M Mainline" Dvendor="ARM:82">
 649       <!--book name="Device/ARM/Documents/ARMv8MML_dgug.pdf"       title="ARMv8MML Device Generic Users Guide"/-->
 650       <description>
 651 Armv8.1-M Mainline based device with TrustZone and MVE
 652       </description>
 653       <!-- <debug svd="Device/ARM/SVD/ARMv8MML.svd"/> -->
 654       <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
 655       <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
 656       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 657       <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
 658       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 659
 660
 661       <device Dname="ARMv81MML_DSP_DP_MVE_FP">
 662         <processor Dcore="ARMV81MML" DcoreVersion="r0p0" Dfpu="DP_FPU" Dmpu="MPU" Dmve="FP_MVE" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 663         <description>
 664           Double Precision Vector Extensions, DSP Instructions, Double Precision Floating Point Unit, TrustZone
 665         </description>
 666         <compile header="Device/ARM/ARMv81MML/Include/ARMv81MML_DSP_DP_MVE_FP.h" define="ARMv81MML_DSP_DP_MVE_FP"/>
 667       </device>
 668     </family>
 669
 670     <!-- ******************************  Cortex-A5  ****************************** -->
 671     <family Dfamily="ARM Cortex A5" Dvendor="ARM:82">
 672       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0433c/index.html" title="Cortex-A5 Technical Reference Manual"/>
 673       <description>
 674 The Arm Cortex-A5 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full
 675 virtual memory capabilities. The Cortex-A5 processor implements the Armv7-A architecture profile and can execute 32-bit
 676 Arm instructions and 16-bit and 32-bit Thumb instructions. The Cortex-A5 is the smallest member of the Cortex-A processor family.
 677       </description>
 678
 679       <memory id="IROM1"                                start="0x80000000" size="0x00200000" startup="1" default="1"/>
 680       <memory id="IRAM1"                                start="0x80200000" size="0x00200000" init   ="0" default="1"/>
 681
 682       <device Dname="ARMCA5">
 683         <processor Dcore="Cortex-A5" DcoreVersion="r0p1" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable"/>
 684         <compile header="Device/ARM/ARMCA5/Include/ARMCA5.h" define="ARMCA5"/>
 685       </device>
 686     </family>
 687
 688     <!-- ******************************  Cortex-A7  ****************************** -->
 689     <family Dfamily="ARM Cortex A7" Dvendor="ARM:82">
 690       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/index.html" title="Cortex-A7 MPCore Technical Reference Manual"/>
 691       <description>
 692 The Cortex-A7 MPCore processor is a high-performance, low-power processor that implements the Armv7-A architecture.
 693 The Cortex-A7 MPCore processor has one to four processors in a single multiprocessor device with a L1 cache subsystem,
 694 an optional integrated GIC, and an optional L2 cache controller.
 695       </description>
 696
 697       <memory id="IROM1"                                start="0x80000000" size="0x00200000" startup="1" default="1"/>
 698       <memory id="IRAM1"                                start="0x80200000" size="0x00200000" init   ="0" default="1"/>
 699
 700       <device Dname="ARMCA7">
 701         <processor Dcore="Cortex-A7" DcoreVersion="r0p5" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable"/>
 702         <compile header="Device/ARM/ARMCA7/Include/ARMCA7.h" define="ARMCA7"/>
 703       </device>
 704     </family>
 705
 706     <!-- ******************************  Cortex-A9  ****************************** -->
 707     <family Dfamily="ARM Cortex A9" Dvendor="ARM:82">
 708       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.100511_0401_10_en/index.html" title="Cortex-A9 Technical Reference Manual"/>
 709       <description>
 710 The Cortex-A9 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full virtual memory capabilities.
 711 The Cortex-A9 processor implements the Armv7-A architecture and runs 32-bit Arm instructions, 16-bit and 32-bit Thumb instructions,
 712 and 8-bit Java bytecodes in Jazelle state.
 713       </description>
 714
 715       <memory id="IROM1"                                start="0x80000000" size="0x00200000" startup="1" default="1"/>
 716       <memory id="IRAM1"                                start="0x80200000" size="0x00200000" init   ="0" default="1"/>
 717
 718       <device Dname="ARMCA9">
 719         <processor Dcore="Cortex-A9" DcoreVersion="r4p1" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable"/>
 720         <compile header="Device/ARM/ARMCA9/Include/ARMCA9.h" define="ARMCA9"/>
 721       </device>
 722     </family>
 723   </devices>
 724
 725
 726   <apis>
 727     <!-- CMSIS Device API -->
 728     <api Cclass="Device" Cgroup="IRQ Controller" Capiversion="1.0.0" exclusive="1">
 729       <description>Device interrupt controller interface</description>
 730       <files>
 731         <file category="header" name="CMSIS/Core_A/Include/irq_ctrl.h"/>
 732       </files>
 733     </api>
 734     <api Cclass="Device" Cgroup="OS Tick" Capiversion="1.0.1" exclusive="1">
 735       <description>RTOS Kernel system tick timer interface</description>
 736       <files>
 737         <file category="header" name="CMSIS/RTOS2/Include/os_tick.h"/>
 738       </files>
 739     </api>
 740     <!-- CMSIS-RTOS API -->
 741     <api Cclass="CMSIS" Cgroup="RTOS" Capiversion="1.0.0" exclusive="1">
 742       <description>CMSIS-RTOS API for Cortex-M, SC000, and SC300</description>
 743       <files>
 744         <file category="doc" name="CMSIS/Documentation/RTOS/html/index.html"/>
 745       </files>
 746     </api>
 747     <api Cclass="CMSIS" Cgroup="RTOS2" Capiversion="2.1.3" exclusive="1">
 748       <description>CMSIS-RTOS API for Cortex-M, SC000, and SC300</description>
 749       <files>
 750         <file category="doc" name="CMSIS/Documentation/RTOS2/html/index.html"/>
 751         <file category="header" name="CMSIS/RTOS2/Include/cmsis_os2.h"/>
 752       </files>
 753     </api>
 754     <!-- CMSIS Driver API -->
 755     <api Cclass="CMSIS Driver" Cgroup="USART" Capiversion="2.3.0" exclusive="0">
 756       <description>USART Driver API for Cortex-M</description>
 757       <files>
 758         <file category="doc" name="CMSIS/Documentation/Driver/html/group__usart__interface__gr.html" />
 759         <file category="header" name="CMSIS/Driver/Include/Driver_USART.h" />
 760       </files>
 761     </api>
 762     <api Cclass="CMSIS Driver" Cgroup="SPI" Capiversion="2.2.0" exclusive="0">
 763       <description>SPI Driver API for Cortex-M</description>
 764       <files>
 765         <file category="doc" name="CMSIS/Documentation/Driver/html/group__spi__interface__gr.html" />
 766         <file category="header" name="CMSIS/Driver/Include/Driver_SPI.h" />
 767       </files>
 768     </api>
 769     <api Cclass="CMSIS Driver" Cgroup="SAI" Capiversion="1.1.0" exclusive="0">
 770       <description>SAI Driver API for Cortex-M</description>
 771       <files>
 772         <file category="doc" name="CMSIS/Documentation/Driver/html/group__sai__interface__gr.html"/>
 773         <file category="header" name="CMSIS/Driver/Include/Driver_SAI.h" />
 774       </files>
 775     </api>
 776     <api Cclass="CMSIS Driver" Cgroup="I2C" Capiversion="2.3.0" exclusive="0">
 777       <description>I2C Driver API for Cortex-M</description>
 778       <files>
 779         <file category="doc" name="CMSIS/Documentation/Driver/html/group__i2c__interface__gr.html"/>
 780         <file category="header" name="CMSIS/Driver/Include/Driver_I2C.h" />
 781       </files>
 782     </api>
 783     <api Cclass="CMSIS Driver" Cgroup="CAN" Capiversion="1.2.0" exclusive="0">
 784       <description>CAN Driver API for Cortex-M</description>
 785       <files>
 786         <file category="doc" name="CMSIS/Documentation/Driver/html/group__can__interface__gr.html"/>
 787         <file category="header" name="CMSIS/Driver/Include/Driver_CAN.h" />
 788       </files>
 789     </api>
 790     <api Cclass="CMSIS Driver" Cgroup="Flash" Capiversion="2.2.0" exclusive="0">
 791       <description>Flash Driver API for Cortex-M</description>
 792       <files>
 793         <file category="doc" name="CMSIS/Documentation/Driver/html/group__flash__interface__gr.html" />
 794         <file category="header" name="CMSIS/Driver/Include/Driver_Flash.h" />
 795       </files>
 796     </api>
 797     <api Cclass="CMSIS Driver" Cgroup="MCI" Capiversion="2.3.0" exclusive="0">
 798       <description>MCI Driver API for Cortex-M</description>
 799       <files>
 800         <file category="doc" name="CMSIS/Documentation/Driver/html/group__mci__interface__gr.html" />
 801         <file category="header" name="CMSIS/Driver/Include/Driver_MCI.h" />
 802       </files>
 803     </api>
 804     <api Cclass="CMSIS Driver" Cgroup="NAND" Capiversion="2.3.0" exclusive="0">
 805       <description>NAND Flash Driver API for Cortex-M</description>
 806       <files>
 807         <file category="doc" name="CMSIS/Documentation/Driver/html/group__nand__interface__gr.html" />
 808         <file category="header" name="CMSIS/Driver/Include/Driver_NAND.h" />
 809       </files>
 810     </api>
 811     <api Cclass="CMSIS Driver" Cgroup="Ethernet" Capiversion="2.1.0" exclusive="0">
 812       <description>Ethernet MAC and PHY Driver API for Cortex-M</description>
 813       <files>
 814         <file category="doc" name="CMSIS/Documentation/Driver/html/group__eth__interface__gr.html" />
 815         <file category="header" name="CMSIS/Driver/Include/Driver_ETH_MAC.h" />
 816         <file category="header" name="CMSIS/Driver/Include/Driver_ETH_PHY.h" />
 817       </files>
 818     </api>
 819     <api Cclass="CMSIS Driver" Cgroup="Ethernet MAC" Capiversion="2.1.0" exclusive="0">
 820       <description>Ethernet MAC Driver API for Cortex-M</description>
 821       <files>
 822         <file category="doc" name="CMSIS/Documentation/Driver/html/group__eth__mac__interface__gr.html" />
 823         <file category="header" name="CMSIS/Driver/Include/Driver_ETH_MAC.h" />
 824       </files>
 825     </api>
 826     <api Cclass="CMSIS Driver" Cgroup="Ethernet PHY" Capiversion="2.1.0" exclusive="0">
 827       <description>Ethernet PHY Driver API for Cortex-M</description>
 828       <files>
 829         <file category="doc" name="CMSIS/Documentation/Driver/html/group__eth__phy__interface__gr.html" />
 830         <file category="header" name="CMSIS/Driver/Include/Driver_ETH_PHY.h" />
 831       </files>
 832     </api>
 833     <api Cclass="CMSIS Driver" Cgroup="USB Device" Capiversion="2.2.0" exclusive="0">
 834       <description>USB Device Driver API for Cortex-M</description>
 835       <files>
 836         <file category="doc" name="CMSIS/Documentation/Driver/html/group__usbd__interface__gr.html" />
 837         <file category="header" name="CMSIS/Driver/Include/Driver_USBD.h" />
 838       </files>
 839     </api>
 840     <api Cclass="CMSIS Driver" Cgroup="USB Host" Capiversion="2.2.0" exclusive="0">
 841       <description>USB Host Driver API for Cortex-M</description>
 842       <files>
 843         <file category="doc" name="CMSIS/Documentation/Driver/html/group__usbh__interface__gr.html" />
 844         <file category="header" name="CMSIS/Driver/Include/Driver_USBH.h" />
 845       </files>
 846     </api>
 847     <api Cclass="CMSIS Driver" Cgroup="WiFi" Capiversion="1.0.0-beta" exclusive="0">
 848       <description>WiFi driver</description>
 849       <files>
 850         <file category="header" name="CMSIS/Driver/Include/Driver_WiFi.h"/>
 851       </files>
 852     </api>
 853   </apis>
 854
 855   <!-- conditions are dependency rules that can apply to a component or an individual file -->
 856   <conditions>
 857     <!-- compiler -->
 858     <condition id="ARMCC6">
 859       <accept Tcompiler="ARMCC" Toptions="AC6"/>
 860       <accept Tcompiler="ARMCC" Toptions="AC6LTO"/>
 861     </condition>
 862     <condition id="ARMCC5">
 863       <require Tcompiler="ARMCC" Toptions="AC5"/>
 864     </condition>
 865     <condition id="ARMCC">
 866       <require Tcompiler="ARMCC"/>
 867     </condition>
 868     <condition id="GCC">
 869       <require Tcompiler="GCC"/>
 870     </condition>
 871     <condition id="IAR">
 872       <require Tcompiler="IAR"/>
 873     </condition>
 874     <condition id="ARMCC GCC">
 875       <accept Tcompiler="ARMCC"/>
 876       <accept Tcompiler="GCC"/>
 877     </condition>
 878     <condition id="ARMCC GCC IAR">
 879       <accept Tcompiler="ARMCC"/>
 880       <accept Tcompiler="GCC"/>
 881       <accept Tcompiler="IAR"/>
 882     </condition>
 883
 884     <!-- Arm architecture -->
 885     <condition id="ARMv6-M Device">
 886       <description>Armv6-M architecture based device</description>
 887       <accept Dcore="Cortex-M0"/>
 888       <accept Dcore="Cortex-M1"/>
 889       <accept Dcore="Cortex-M0+"/>
 890       <accept Dcore="SC000"/>
 891     </condition>
 892     <condition id="ARMv7-M Device">
 893       <description>Armv7-M architecture based device</description>
 894       <accept Dcore="Cortex-M3"/>
 895       <accept Dcore="Cortex-M4"/>
 896       <accept Dcore="Cortex-M7"/>
 897       <accept Dcore="SC300"/>
 898     </condition>
 899     <condition id="ARMv8-M Device">
 900       <description>Armv8-M architecture based device</description>
 901       <accept Dcore="ARMV8MBL"/>
 902       <accept Dcore="ARMV8MML"/>
 903       <accept Dcore="ARMV81MML"/>
 904       <accept Dcore="Cortex-M23"/>
 905       <accept Dcore="Cortex-M33"/>
 906       <accept Dcore="Cortex-M35P"/>
 907     </condition>
 908     <condition id="ARMv8-M TZ Device">
 909       <description>Armv8-M architecture based device with TrustZone</description>
 910       <require condition="ARMv8-M Device"/>
 911       <require Dtz="TZ"/>
 912     </condition>
 913     <condition id="ARMv6_7-M Device">
 914       <description>Armv6_7-M architecture based device</description>
 915       <accept condition="ARMv6-M Device"/>
 916       <accept condition="ARMv7-M Device"/>
 917     </condition>
 918     <condition id="ARMv6_7_8-M Device">
 919       <description>Armv6_7_8-M architecture based device</description>
 920       <accept condition="ARMv6-M Device"/>
 921       <accept condition="ARMv7-M Device"/>
 922       <accept condition="ARMv8-M Device"/>
 923     </condition>
 924     <condition id="ARMv7-A Device">
 925       <description>Armv7-A architecture based device</description>
 926       <accept Dcore="Cortex-A5"/>
 927       <accept Dcore="Cortex-A7"/>
 928       <accept Dcore="Cortex-A9"/>
 929     </condition>
 930
 931     <!-- ARM core -->
 932     <condition id="CM0">
 933       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device</description>
 934       <accept Dcore="Cortex-M0"/>
 935       <accept Dcore="Cortex-M0+"/>
 936       <accept Dcore="SC000"/>
 937     </condition>
 938     <condition id="CM1">
 939       <description>Cortex-M1</description>
 940       <require Dcore="Cortex-M1"/>
 941     </condition>
 942     <condition id="CM3">
 943       <description>Cortex-M3 or SC300 processor based device</description>
 944       <accept Dcore="Cortex-M3"/>
 945       <accept Dcore="SC300"/>
 946     </condition>
 947     <condition id="CM4">
 948       <description>Cortex-M4 processor based device</description>
 949       <require Dcore="Cortex-M4" Dfpu="NO_FPU"/>
 950     </condition>
 951     <condition id="CM4_FP">
 952       <description>Cortex-M4 processor based device using Floating Point Unit</description>
 953       <accept Dcore="Cortex-M4" Dfpu="FPU"/>
 954       <accept Dcore="Cortex-M4" Dfpu="SP_FPU"/>
 955       <accept Dcore="Cortex-M4" Dfpu="DP_FPU"/>
 956     </condition>
 957     <condition id="CM7">
 958       <description>Cortex-M7 processor based device</description>
 959       <require Dcore="Cortex-M7" Dfpu="NO_FPU"/>
 960     </condition>
 961     <condition id="CM7_FP">
 962       <description>Cortex-M7 processor based device using Floating Point Unit</description>
 963       <accept Dcore="Cortex-M7" Dfpu="SP_FPU"/>
 964       <accept Dcore="Cortex-M7" Dfpu="DP_FPU"/>
 965     </condition>
 966     <condition id="CM7_SP">
 967       <description>Cortex-M7 processor based device using Floating Point Unit (SP)</description>
 968       <require Dcore="Cortex-M7" Dfpu="SP_FPU"/>
 969     </condition>
 970     <condition id="CM7_DP">
 971       <description>Cortex-M7 processor based device using Floating Point Unit (DP)</description>
 972       <require Dcore="Cortex-M7" Dfpu="DP_FPU"/>
 973     </condition>
 974     <condition id="CM23">
 975       <description>Cortex-M23 processor based device</description>
 976       <require Dcore="Cortex-M23"/>
 977     </condition>
 978     <condition id="CM33">
 979       <description>Cortex-M33 processor based device</description>
 980       <require Dcore="Cortex-M33" Dfpu="NO_FPU"/>
 981     </condition>
 982     <condition id="CM33_FP">
 983       <description>Cortex-M33 processor based device using Floating Point Unit</description>
 984       <require Dcore="Cortex-M33" Dfpu="SP_FPU"/>
 985     </condition>
 986     <condition id="CM35P">
 987       <description>Cortex-M35P processor based device</description>
 988       <require Dcore="Cortex-M35P" Dfpu="NO_FPU"/>
 989     </condition>
 990     <condition id="CM35P_FP">
 991       <description>Cortex-M35P processor based device using Floating Point Unit</description>
 992       <require Dcore="Cortex-M35P" Dfpu="SP_FPU"/>
 993     </condition>
 994     <condition id="ARMv8MBL">
 995       <description>Armv8-M Baseline processor based device</description>
 996       <require Dcore="ARMV8MBL"/>
 997     </condition>
 998     <condition id="ARMv8MML">
 999       <description>Armv8-M Mainline processor based device</description>
1000       <require Dcore="ARMV8MML" Dfpu="NO_FPU"/>
1001     </condition>
1002     <condition id="ARMv8MML_FP">
1003       <description>Armv8-M Mainline processor based device using Floating Point Unit</description>
1004       <accept Dcore="ARMV8MML" Dfpu="SP_FPU"/>
1005       <accept Dcore="ARMV8MML" Dfpu="DP_FPU"/>
1006     </condition>
1007
1008     <condition id="CM33_NODSP_NOFPU">
1009       <description>CM33, no DSP, no FPU</description>
1010       <require Dcore="Cortex-M33" Ddsp="NO_DSP" Dfpu="NO_FPU"/>
1011     </condition>
1012     <condition id="CM33_DSP_NOFPU">
1013       <description>CM33, DSP, no FPU</description>
1014       <require Dcore="Cortex-M33" Ddsp="DSP" Dfpu="NO_FPU"/>
1015     </condition>
1016     <condition id="CM33_NODSP_SP">
1017       <description>CM33, no DSP, SP FPU</description>
1018       <require Dcore="Cortex-M33" Ddsp="NO_DSP" Dfpu="SP_FPU"/>
1019     </condition>
1020     <condition id="CM33_DSP_SP">
1021       <description>CM33, DSP, SP FPU</description>
1022       <require Dcore="Cortex-M33" Ddsp="DSP" Dfpu="SP_FPU"/>
1023     </condition>
1024
1025     <condition id="CM35P_NODSP_NOFPU">
1026       <description>CM35P, no DSP, no FPU</description>
1027       <require Dcore="Cortex-M35P" Ddsp="NO_DSP" Dfpu="NO_FPU"/>
1028     </condition>
1029     <condition id="CM35P_DSP_NOFPU">
1030       <description>CM35P, DSP, no FPU</description>
1031       <require Dcore="Cortex-M35P" Ddsp="DSP" Dfpu="NO_FPU"/>
1032     </condition>
1033     <condition id="CM35P_NODSP_SP">
1034       <description>CM35P, no DSP, SP FPU</description>
1035       <require Dcore="Cortex-M35P" Ddsp="NO_DSP" Dfpu="SP_FPU"/>
1036     </condition>
1037     <condition id="CM35P_DSP_SP">
1038       <description>CM35P, DSP, SP FPU</description>
1039       <require Dcore="Cortex-M35P" Ddsp="DSP" Dfpu="SP_FPU"/>
1040     </condition>
1041
1042     <condition id="ARMv8MML_NODSP_NOFPU">
1043       <description>Armv8-M Mainline, no DSP, no FPU</description>
1044       <require Dcore="ARMV8MML" Ddsp="NO_DSP" Dfpu="NO_FPU"/>
1045     </condition>
1046     <condition id="ARMv8MML_DSP_NOFPU">
1047       <description>Armv8-M Mainline, DSP, no FPU</description>
1048       <require Dcore="ARMV8MML" Ddsp="DSP" Dfpu="NO_FPU"/>
1049     </condition>
1050     <condition id="ARMv8MML_NODSP_SP">
1051       <description>Armv8-M Mainline, no DSP, SP FPU</description>
1052       <require Dcore="ARMV8MML" Ddsp="NO_DSP" Dfpu="SP_FPU"/>
1053     </condition>
1054     <condition id="ARMv8MML_DSP_SP">
1055       <description>Armv8-M Mainline, DSP, SP FPU</description>
1056       <require Dcore="ARMV8MML" Ddsp="DSP" Dfpu="SP_FPU"/>
1057     </condition>
1058
1059     <condition id="ARMv81MML">
1060       <description>Armv8.1-M Mainline</description>
1061       <require Dvendor="ARM:82" Dname="ARMv81MML*"/>
1062     </condition>
1063
1064     <condition id="CA5_CA9">
1065       <description>Cortex-A5 or Cortex-A9 processor based device</description>
1066       <accept Dcore="Cortex-A5"/>
1067       <accept Dcore="Cortex-A9"/>
1068     </condition>
1069
1070     <condition id="CA7">
1071       <description>Cortex-A7 processor based device</description>
1072       <accept Dcore="Cortex-A7"/>
1073     </condition>
1074
1075     <!-- ARMCC compiler -->
1076     <condition id="CA_ARMCC5">
1077       <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the Arm Compiler 5</description>
1078       <require condition="ARMv7-A Device"/>
1079       <require condition="ARMCC5"/>
1080     </condition>
1081     <condition id="CA_ARMCC6">
1082       <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the Arm Compiler 6</description>
1083       <require condition="ARMv7-A Device"/>
1084       <require condition="ARMCC6"/>
1085     </condition>
1086
1087     <condition id="CM0_ARMCC">
1088       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device for the Arm Compiler</description>
1089       <require condition="CM0"/>
1090       <require Tcompiler="ARMCC"/>
1091     </condition>
1092     <condition id="CM0_LE_ARMCC">
1093       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the Arm Compiler</description>
1094       <require condition="CM0_ARMCC"/>
1095       <require Dendian="Little-endian"/>
1096     </condition>
1097     <condition id="CM0_BE_ARMCC">
1098       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the Arm Compiler</description>
1099       <require condition="CM0_ARMCC"/>
1100       <require Dendian="Big-endian"/>
1101     </condition>
1102
1103     <condition id="CM1_ARMCC">
1104       <description>Cortex-M1 based device for the Arm Compiler</description>
1105       <require condition="CM1"/>
1106       <require Tcompiler="ARMCC"/>
1107     </condition>
1108     <condition id="CM1_LE_ARMCC">
1109       <description>Cortex-M1 based device in little endian mode for the Arm Compiler</description>
1110       <require condition="CM1_ARMCC"/>
1111       <require Dendian="Little-endian"/>
1112     </condition>
1113     <condition id="CM1_BE_ARMCC">
1114       <description>Cortex-M1 based device in big endian mode for the Arm Compiler</description>
1115       <require condition="CM1_ARMCC"/>
1116       <require Dendian="Big-endian"/>
1117     </condition>
1118
1119     <condition id="CM3_ARMCC">
1120       <description>Cortex-M3 or SC300 processor based device for the Arm Compiler</description>
1121       <require condition="CM3"/>
1122       <require Tcompiler="ARMCC"/>
1123     </condition>
1124     <condition id="CM3_LE_ARMCC">
1125       <description>Cortex-M3 or SC300 processor based device in little endian mode for the Arm Compiler</description>
1126       <require condition="CM3_ARMCC"/>
1127       <require Dendian="Little-endian"/>
1128     </condition>
1129     <condition id="CM3_BE_ARMCC">
1130       <description>Cortex-M3 or SC300 processor based device in big endian mode for the Arm Compiler</description>
1131       <require condition="CM3_ARMCC"/>
1132       <require Dendian="Big-endian"/>
1133     </condition>
1134
1135     <condition id="CM4_ARMCC">
1136       <description>Cortex-M4 processor based device for the Arm Compiler</description>
1137       <require condition="CM4"/>
1138       <require Tcompiler="ARMCC"/>
1139     </condition>
1140     <condition id="CM4_LE_ARMCC">
1141       <description>Cortex-M4 processor based device in little endian mode for the Arm Compiler</description>
1142       <require condition="CM4_ARMCC"/>
1143       <require Dendian="Little-endian"/>
1144     </condition>
1145     <condition id="CM4_BE_ARMCC">
1146       <description>Cortex-M4 processor based device in big endian mode for the Arm Compiler</description>
1147       <require condition="CM4_ARMCC"/>
1148       <require Dendian="Big-endian"/>
1149     </condition>
1150
1151     <condition id="CM4_FP_ARMCC">
1152       <description>Cortex-M4 processor based device using Floating Point Unit for the Arm Compiler</description>
1153       <require condition="CM4_FP"/>
1154       <require Tcompiler="ARMCC"/>
1155     </condition>
1156     <condition id="CM4_FP_LE_ARMCC">
1157       <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
1158       <require condition="CM4_FP_ARMCC"/>
1159       <require Dendian="Little-endian"/>
1160     </condition>
1161     <condition id="CM4_FP_BE_ARMCC">
1162       <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
1163       <require condition="CM4_FP_ARMCC"/>
1164       <require Dendian="Big-endian"/>
1165     </condition>
1166
1167     <condition id="CM7_ARMCC">
1168       <description>Cortex-M7 processor based device for the Arm Compiler</description>
1169       <require condition="CM7"/>
1170       <require Tcompiler="ARMCC"/>
1171     </condition>
1172     <condition id="CM7_LE_ARMCC">
1173       <description>Cortex-M7 processor based device in little endian mode for the Arm Compiler</description>
1174       <require condition="CM7_ARMCC"/>
1175       <require Dendian="Little-endian"/>
1176     </condition>
1177     <condition id="CM7_BE_ARMCC">
1178       <description>Cortex-M7 processor based device in big endian mode for the Arm Compiler</description>
1179       <require condition="CM7_ARMCC"/>
1180       <require Dendian="Big-endian"/>
1181     </condition>
1182
1183     <condition id="CM7_FP_ARMCC">
1184       <description>Cortex-M7 processor based device using Floating Point Unit for the Arm Compiler</description>
1185       <require condition="CM7_FP"/>
1186       <require Tcompiler="ARMCC"/>
1187     </condition>
1188     <condition id="CM7_FP_LE_ARMCC">
1189       <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
1190       <require condition="CM7_FP_ARMCC"/>
1191       <require Dendian="Little-endian"/>
1192     </condition>
1193     <condition id="CM7_FP_BE_ARMCC">
1194       <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
1195       <require condition="CM7_FP_ARMCC"/>
1196       <require Dendian="Big-endian"/>
1197     </condition>
1198
1199     <condition id="CM7_SP_ARMCC">
1200       <description>Cortex-M7 processor based device using Floating Point Unit (SP) for the Arm Compiler</description>
1201       <require condition="CM7_SP"/>
1202       <require Tcompiler="ARMCC"/>
1203     </condition>
1204     <condition id="CM7_SP_LE_ARMCC">
1205       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the Arm Compiler</description>
1206       <require condition="CM7_SP_ARMCC"/>
1207       <require Dendian="Little-endian"/>
1208     </condition>
1209     <condition id="CM7_SP_BE_ARMCC">
1210       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the Arm Compiler</description>
1211       <require condition="CM7_SP_ARMCC"/>
1212       <require Dendian="Big-endian"/>
1213     </condition>
1214
1215     <condition id="CM7_DP_ARMCC">
1216       <description>Cortex-M7 processor based device using Floating Point Unit (DP) for the Arm Compiler</description>
1217       <require condition="CM7_DP"/>
1218       <require Tcompiler="ARMCC"/>
1219     </condition>
1220     <condition id="CM7_DP_LE_ARMCC">
1221       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the Arm Compiler</description>
1222       <require condition="CM7_DP_ARMCC"/>
1223       <require Dendian="Little-endian"/>
1224     </condition>
1225     <condition id="CM7_DP_BE_ARMCC">
1226       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the Arm Compiler</description>
1227       <require condition="CM7_DP_ARMCC"/>
1228       <require Dendian="Big-endian"/>
1229     </condition>
1230
1231     <condition id="CM23_ARMCC">
1232       <description>Cortex-M23 processor based device for the Arm Compiler</description>
1233       <require condition="CM23"/>
1234       <require Tcompiler="ARMCC"/>
1235     </condition>
1236     <condition id="CM23_LE_ARMCC">
1237       <description>Cortex-M23 processor based device in little endian mode for the Arm Compiler</description>
1238       <require condition="CM23_ARMCC"/>
1239       <require Dendian="Little-endian"/>
1240     </condition>
1241     <condition id="CM23_BE_ARMCC">
1242       <description>Cortex-M23 processor based device in big endian mode for the Arm Compiler</description>
1243       <require condition="CM23_ARMCC"/>
1244       <require Dendian="Big-endian"/>
1245     </condition>
1246
1247     <condition id="CM33_ARMCC">
1248       <description>Cortex-M33 processor based device for the Arm Compiler</description>
1249       <require condition="CM33"/>
1250       <require Tcompiler="ARMCC"/>
1251     </condition>
1252     <condition id="CM33_LE_ARMCC">
1253       <description>Cortex-M33 processor based device in little endian mode for the Arm Compiler</description>
1254       <require condition="CM33_ARMCC"/>
1255       <require Dendian="Little-endian"/>
1256     </condition>
1257     <condition id="CM33_BE_ARMCC">
1258       <description>Cortex-M33 processor based device in big endian mode for the Arm Compiler</description>
1259       <require condition="CM33_ARMCC"/>
1260       <require Dendian="Big-endian"/>
1261     </condition>
1262
1263     <condition id="CM33_FP_ARMCC">
1264       <description>Cortex-M33 processor based device using Floating Point Unit for the Arm Compiler</description>
1265       <require condition="CM33_FP"/>
1266       <require Tcompiler="ARMCC"/>
1267     </condition>
1268     <condition id="CM33_FP_LE_ARMCC">
1269       <description>Cortex-M33 processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
1270       <require condition="CM33_FP_ARMCC"/>
1271       <require Dendian="Little-endian"/>
1272     </condition>
1273     <condition id="CM33_FP_BE_ARMCC">
1274       <description>Cortex-M33 processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
1275       <require condition="CM33_FP_ARMCC"/>
1276       <require Dendian="Big-endian"/>
1277     </condition>
1278
1279     <condition id="CM33_NODSP_NOFPU_ARMCC">
1280       <description>Cortex-M33 processor, no DSP, no FPU, Arm Compiler</description>
1281       <require condition="CM33_NODSP_NOFPU"/>
1282       <require Tcompiler="ARMCC"/>
1283     </condition>
1284     <condition id="CM33_DSP_NOFPU_ARMCC">
1285       <description>Cortex-M33 processor, DSP, no FPU, Arm Compiler</description>
1286       <require condition="CM33_DSP_NOFPU"/>
1287       <require Tcompiler="ARMCC"/>
1288     </condition>
1289     <condition id="CM33_NODSP_SP_ARMCC">
1290       <description>Cortex-M33 processor, no DSP, SP FPU, Arm Compiler</description>
1291       <require condition="CM33_NODSP_SP"/>
1292       <require Tcompiler="ARMCC"/>
1293     </condition>
1294     <condition id="CM33_DSP_SP_ARMCC">
1295       <description>Cortex-M33 processor, DSP, SP FPU, Arm Compiler</description>
1296       <require condition="CM33_DSP_SP"/>
1297       <require Tcompiler="ARMCC"/>
1298     </condition>
1299     <condition id="CM33_NODSP_NOFPU_LE_ARMCC">
1300       <description>Cortex-M33 processor, little endian, no DSP, no FPU, Arm Compiler</description>
1301       <require condition="CM33_NODSP_NOFPU_ARMCC"/>
1302       <require Dendian="Little-endian"/>
1303     </condition>
1304     <condition id="CM33_DSP_NOFPU_LE_ARMCC">
1305       <description>Cortex-M33 processor, little endian, DSP, no FPU, Arm Compiler</description>
1306       <require condition="CM33_DSP_NOFPU_ARMCC"/>
1307       <require Dendian="Little-endian"/>
1308     </condition>
1309     <condition id="CM33_NODSP_SP_LE_ARMCC">
1310       <description>Cortex-M33 processor, little endian, no DSP, SP FPU, Arm Compiler</description>
1311       <require condition="CM33_NODSP_SP_ARMCC"/>
1312       <require Dendian="Little-endian"/>
1313     </condition>
1314     <condition id="CM33_DSP_SP_LE_ARMCC">
1315       <description>Cortex-M33 processor, little endian, DSP, SP FPU, Arm Compiler</description>
1316       <require condition="CM33_DSP_SP_ARMCC"/>
1317       <require Dendian="Little-endian"/>
1318     </condition>
1319
1320     <condition id="CM35P_ARMCC">
1321       <description>Cortex-M35P processor based device for the Arm Compiler</description>
1322       <require condition="CM35P"/>
1323       <require Tcompiler="ARMCC"/>
1324     </condition>
1325     <condition id="CM35P_LE_ARMCC">
1326       <description>Cortex-M35P processor based device in little endian mode for the Arm Compiler</description>
1327       <require condition="CM35P_ARMCC"/>
1328       <require Dendian="Little-endian"/>
1329     </condition>
1330     <condition id="CM35P_BE_ARMCC">
1331       <description>Cortex-M35P processor based device in big endian mode for the Arm Compiler</description>
1332       <require condition="CM35P_ARMCC"/>
1333       <require Dendian="Big-endian"/>
1334     </condition>
1335
1336     <condition id="CM35P_FP_ARMCC">
1337       <description>Cortex-M35P processor based device using Floating Point Unit for the Arm Compiler</description>
1338       <require condition="CM35P_FP"/>
1339       <require Tcompiler="ARMCC"/>
1340     </condition>
1341     <condition id="CM35P_FP_LE_ARMCC">
1342       <description>Cortex-M35P processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
1343       <require condition="CM35P_FP_ARMCC"/>
1344       <require Dendian="Little-endian"/>
1345     </condition>
1346     <condition id="CM35P_FP_BE_ARMCC">
1347       <description>Cortex-M35P processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
1348       <require condition="CM35P_FP_ARMCC"/>
1349       <require Dendian="Big-endian"/>
1350     </condition>
1351
1352     <condition id="CM35P_NODSP_NOFPU_ARMCC">
1353       <description>Cortex-M35P processor, no DSP, no FPU, Arm Compiler</description>
1354       <require condition="CM35P_NODSP_NOFPU"/>
1355       <require Tcompiler="ARMCC"/>
1356     </condition>
1357     <condition id="CM35P_DSP_NOFPU_ARMCC">
1358       <description>Cortex-M35P processor, DSP, no FPU, Arm Compiler</description>
1359       <require condition="CM35P_DSP_NOFPU"/>
1360       <require Tcompiler="ARMCC"/>
1361     </condition>
1362     <condition id="CM35P_NODSP_SP_ARMCC">
1363       <description>Cortex-M35P processor, no DSP, SP FPU, Arm Compiler</description>
1364       <require condition="CM35P_NODSP_SP"/>
1365       <require Tcompiler="ARMCC"/>
1366     </condition>
1367     <condition id="CM35P_DSP_SP_ARMCC">
1368       <description>Cortex-M35P processor, DSP, SP FPU, Arm Compiler</description>
1369       <require condition="CM35P_DSP_SP"/>
1370       <require Tcompiler="ARMCC"/>
1371     </condition>
1372     <condition id="CM35P_NODSP_NOFPU_LE_ARMCC">
1373       <description>Cortex-M35P processor, little endian, no DSP, no FPU, Arm Compiler</description>
1374       <require condition="CM35P_NODSP_NOFPU_ARMCC"/>
1375       <require Dendian="Little-endian"/>
1376     </condition>
1377     <condition id="CM35P_DSP_NOFPU_LE_ARMCC">
1378       <description>Cortex-M35P processor, little endian, DSP, no FPU, Arm Compiler</description>
1379       <require condition="CM35P_DSP_NOFPU_ARMCC"/>
1380       <require Dendian="Little-endian"/>
1381     </condition>
1382     <condition id="CM35P_NODSP_SP_LE_ARMCC">
1383       <description>Cortex-M35P processor, little endian, no DSP, SP FPU, Arm Compiler</description>
1384       <require condition="CM35P_NODSP_SP_ARMCC"/>
1385       <require Dendian="Little-endian"/>
1386     </condition>
1387     <condition id="CM35P_DSP_SP_LE_ARMCC">
1388       <description>Cortex-M35P processor, little endian, DSP, SP FPU, Arm Compiler</description>
1389       <require condition="CM35P_DSP_SP_ARMCC"/>
1390       <require Dendian="Little-endian"/>
1391     </condition>
1392
1393     <condition id="ARMv8MBL_ARMCC">
1394       <description>Armv8-M Baseline processor based device for the Arm Compiler</description>
1395       <require condition="ARMv8MBL"/>
1396       <require Tcompiler="ARMCC"/>
1397     </condition>
1398     <condition id="ARMv8MBL_LE_ARMCC">
1399       <description>Armv8-M Baseline processor based device in little endian mode for the Arm Compiler</description>
1400       <require condition="ARMv8MBL_ARMCC"/>
1401       <require Dendian="Little-endian"/>
1402     </condition>
1403     <condition id="ARMv8MBL_BE_ARMCC">
1404       <description>Armv8-M Baseline processor based device in big endian mode for the Arm Compiler</description>
1405       <require condition="ARMv8MBL_ARMCC"/>
1406       <require Dendian="Big-endian"/>
1407     </condition>
1408
1409     <condition id="ARMv8MML_ARMCC">
1410       <description>Armv8-M Mainline processor based device for the Arm Compiler</description>
1411       <require condition="ARMv8MML"/>
1412       <require Tcompiler="ARMCC"/>
1413     </condition>
1414     <condition id="ARMv8MML_LE_ARMCC">
1415       <description>Armv8-M Mainline processor based device in little endian mode for the Arm Compiler</description>
1416       <require condition="ARMv8MML_ARMCC"/>
1417       <require Dendian="Little-endian"/>
1418     </condition>
1419     <condition id="ARMv8MML_BE_ARMCC">
1420       <description>Armv8-M Mainline processor based device in big endian mode for the Arm Compiler</description>
1421       <require condition="ARMv8MML_ARMCC"/>
1422       <require Dendian="Big-endian"/>
1423     </condition>
1424
1425     <condition id="ARMv8MML_FP_ARMCC">
1426       <description>Armv8-M Mainline processor based device using Floating Point Unit for the Arm Compiler</description>
1427       <require condition="ARMv8MML_FP"/>
1428       <require Tcompiler="ARMCC"/>
1429     </condition>
1430     <condition id="ARMv8MML_FP_LE_ARMCC">
1431       <description>Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
1432       <require condition="ARMv8MML_FP_ARMCC"/>
1433       <require Dendian="Little-endian"/>
1434     </condition>
1435     <condition id="ARMv8MML_FP_BE_ARMCC">
1436       <description>Armv8-M Mainline processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
1437       <require condition="ARMv8MML_FP_ARMCC"/>
1438       <require Dendian="Big-endian"/>
1439     </condition>
1440
1441     <condition id="ARMv8MML_NODSP_NOFPU_ARMCC">
1442       <description>Armv8-M Mainline, no DSP, no FPU, Arm Compiler</description>
1443       <require condition="ARMv8MML_NODSP_NOFPU"/>
1444       <require Tcompiler="ARMCC"/>
1445     </condition>
1446     <condition id="ARMv8MML_DSP_NOFPU_ARMCC">
1447       <description>Armv8-M Mainline, DSP, no FPU, Arm Compiler</description>
1448       <require condition="ARMv8MML_DSP_NOFPU"/>
1449       <require Tcompiler="ARMCC"/>
1450     </condition>
1451     <condition id="ARMv8MML_NODSP_SP_ARMCC">
1452       <description>Armv8-M Mainline, no DSP, SP FPU, Arm Compiler</description>
1453       <require condition="ARMv8MML_NODSP_SP"/>
1454       <require Tcompiler="ARMCC"/>
1455     </condition>
1456     <condition id="ARMv8MML_DSP_SP_ARMCC">
1457       <description>Armv8-M Mainline, DSP, SP FPU, Arm Compiler</description>
1458       <require condition="ARMv8MML_DSP_SP"/>
1459       <require Tcompiler="ARMCC"/>
1460     </condition>
1461     <condition id="ARMv8MML_NODSP_NOFPU_LE_ARMCC">
1462       <description>Armv8-M Mainline, little endian, no DSP, no FPU, Arm Compiler</description>
1463       <require condition="ARMv8MML_NODSP_NOFPU_ARMCC"/>
1464       <require Dendian="Little-endian"/>
1465     </condition>
1466     <condition id="ARMv8MML_DSP_NOFPU_LE_ARMCC">
1467       <description>Armv8-M Mainline, little endian, DSP, no FPU, Arm Compiler</description>
1468       <require condition="ARMv8MML_DSP_NOFPU_ARMCC"/>
1469       <require Dendian="Little-endian"/>
1470     </condition>
1471     <condition id="ARMv8MML_NODSP_SP_LE_ARMCC">
1472       <description>Armv8-M Mainline, little endian, no DSP, SP FPU, Arm Compiler</description>
1473       <require condition="ARMv8MML_NODSP_SP_ARMCC"/>
1474       <require Dendian="Little-endian"/>
1475     </condition>
1476     <condition id="ARMv8MML_DSP_SP_LE_ARMCC">
1477       <description>Armv8-M Mainline, little endian, DSP, SP FPU, Arm Compiler</description>
1478       <require condition="ARMv8MML_DSP_SP_ARMCC"/>
1479       <require Dendian="Little-endian"/>
1480     </condition>
1481
1482     <!-- GCC compiler -->
1483     <condition id="CA_GCC">
1484       <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the GCC Compiler</description>
1485       <require condition="ARMv7-A Device"/>
1486       <require Tcompiler="GCC"/>
1487     </condition>
1488
1489     <condition id="CM0_GCC">
1490       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device for the GCC Compiler</description>
1491       <require condition="CM0"/>
1492       <require Tcompiler="GCC"/>
1493     </condition>
1494     <condition id="CM0_LE_GCC">
1495       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the GCC Compiler</description>
1496       <require condition="CM0_GCC"/>
1497       <require Dendian="Little-endian"/>
1498     </condition>
1499     <condition id="CM0_BE_GCC">
1500       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the GCC Compiler</description>
1501       <require condition="CM0_GCC"/>
1502       <require Dendian="Big-endian"/>
1503     </condition>
1504
1505     <condition id="CM1_GCC">
1506       <description>Cortex-M1 based device for the GCC Compiler</description>
1507       <require condition="CM1"/>
1508       <require Tcompiler="GCC"/>
1509     </condition>
1510     <condition id="CM1_LE_GCC">
1511       <description>Cortex-M1 based device in little endian mode for the GCC Compiler</description>
1512       <require condition="CM1_GCC"/>
1513       <require Dendian="Little-endian"/>
1514     </condition>
1515     <condition id="CM1_BE_GCC">
1516       <description>Cortex-M1 based device in big endian mode for the GCC Compiler</description>
1517       <require condition="CM1_GCC"/>
1518       <require Dendian="Big-endian"/>
1519     </condition>
1520
1521     <condition id="CM3_GCC">
1522       <description>Cortex-M3 or SC300 processor based device for the GCC Compiler</description>
1523       <require condition="CM3"/>
1524       <require Tcompiler="GCC"/>
1525     </condition>
1526     <condition id="CM3_LE_GCC">
1527       <description>Cortex-M3 or SC300 processor based device in little endian mode for the GCC Compiler</description>
1528       <require condition="CM3_GCC"/>
1529       <require Dendian="Little-endian"/>
1530     </condition>
1531     <condition id="CM3_BE_GCC">
1532       <description>Cortex-M3 or SC300 processor based device in big endian mode for the GCC Compiler</description>
1533       <require condition="CM3_GCC"/>
1534       <require Dendian="Big-endian"/>
1535     </condition>
1536
1537     <condition id="CM4_GCC">
1538       <description>Cortex-M4 processor based device for the GCC Compiler</description>
1539       <require condition="CM4"/>
1540       <require Tcompiler="GCC"/>
1541     </condition>
1542     <condition id="CM4_LE_GCC">
1543       <description>Cortex-M4 processor based device in little endian mode for the GCC Compiler</description>
1544       <require condition="CM4_GCC"/>
1545       <require Dendian="Little-endian"/>
1546     </condition>
1547     <condition id="CM4_BE_GCC">
1548       <description>Cortex-M4 processor based device in big endian mode for the GCC Compiler</description>
1549       <require condition="CM4_GCC"/>
1550       <require Dendian="Big-endian"/>
1551     </condition>
1552
1553     <condition id="CM4_FP_GCC">
1554       <description>Cortex-M4 processor based device using Floating Point Unit for the GCC Compiler</description>
1555       <require condition="CM4_FP"/>
1556       <require Tcompiler="GCC"/>
1557     </condition>
1558     <condition id="CM4_FP_LE_GCC">
1559       <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
1560       <require condition="CM4_FP_GCC"/>
1561       <require Dendian="Little-endian"/>
1562     </condition>
1563     <condition id="CM4_FP_BE_GCC">
1564       <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
1565       <require condition="CM4_FP_GCC"/>
1566       <require Dendian="Big-endian"/>
1567     </condition>
1568
1569     <condition id="CM7_GCC">
1570       <description>Cortex-M7 processor based device for the GCC Compiler</description>
1571       <require condition="CM7"/>
1572       <require Tcompiler="GCC"/>
1573     </condition>
1574     <condition id="CM7_LE_GCC">
1575       <description>Cortex-M7 processor based device in little endian mode for the GCC Compiler</description>
1576       <require condition="CM7_GCC"/>
1577       <require Dendian="Little-endian"/>
1578     </condition>
1579     <condition id="CM7_BE_GCC">
1580       <description>Cortex-M7 processor based device in big endian mode for the GCC Compiler</description>
1581       <require condition="CM7_GCC"/>
1582       <require Dendian="Big-endian"/>
1583     </condition>
1584
1585     <condition id="CM7_FP_GCC">
1586       <description>Cortex-M7 processor based device using Floating Point Unit for the GCC Compiler</description>
1587       <require condition="CM7_FP"/>
1588       <require Tcompiler="GCC"/>
1589     </condition>
1590     <condition id="CM7_FP_LE_GCC">
1591       <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
1592       <require condition="CM7_FP_GCC"/>
1593       <require Dendian="Little-endian"/>
1594     </condition>
1595     <condition id="CM7_FP_BE_GCC">
1596       <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
1597       <require condition="CM7_FP_GCC"/>
1598       <require Dendian="Big-endian"/>
1599     </condition>
1600
1601     <condition id="CM7_SP_GCC">
1602       <description>Cortex-M7 processor based device using Floating Point Unit (SP) for the GCC Compiler</description>
1603       <require condition="CM7_SP"/>
1604       <require Tcompiler="GCC"/>
1605     </condition>
1606     <condition id="CM7_SP_LE_GCC">
1607       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the GCC Compiler</description>
1608       <require condition="CM7_SP_GCC"/>
1609       <require Dendian="Little-endian"/>
1610     </condition>
1611     <condition id="CM7_SP_BE_GCC">
1612       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the GCC Compiler</description>
1613       <require condition="CM7_SP_GCC"/>
1614       <require Dendian="Big-endian"/>
1615     </condition>
1616
1617     <condition id="CM7_DP_GCC">
1618       <description>Cortex-M7 processor based device using Floating Point Unit (DP) for the GCC Compiler</description>
1619       <require condition="CM7_DP"/>
1620       <require Tcompiler="GCC"/>
1621     </condition>
1622     <condition id="CM7_DP_LE_GCC">
1623       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the GCC Compiler</description>
1624       <require condition="CM7_DP_GCC"/>
1625       <require Dendian="Little-endian"/>
1626     </condition>
1627     <condition id="CM7_DP_BE_GCC">
1628       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the GCC Compiler</description>
1629       <require condition="CM7_DP_GCC"/>
1630       <require Dendian="Big-endian"/>
1631     </condition>
1632
1633     <condition id="CM23_GCC">
1634       <description>Cortex-M23 processor based device for the GCC Compiler</description>
1635       <require condition="CM23"/>
1636       <require Tcompiler="GCC"/>
1637     </condition>
1638     <condition id="CM23_LE_GCC">
1639       <description>Cortex-M23 processor based device in little endian mode for the GCC Compiler</description>
1640       <require condition="CM23_GCC"/>
1641       <require Dendian="Little-endian"/>
1642     </condition>
1643     <condition id="CM23_BE_GCC">
1644       <description>Cortex-M23 processor based device in big endian mode for the GCC Compiler</description>
1645       <require condition="CM23_GCC"/>
1646       <require Dendian="Big-endian"/>
1647     </condition>
1648
1649     <condition id="CM33_GCC">
1650       <description>Cortex-M33 processor based device for the GCC Compiler</description>
1651       <require condition="CM33"/>
1652       <require Tcompiler="GCC"/>
1653     </condition>
1654     <condition id="CM33_LE_GCC">
1655       <description>Cortex-M33 processor based device in little endian mode for the GCC Compiler</description>
1656       <require condition="CM33_GCC"/>
1657       <require Dendian="Little-endian"/>
1658     </condition>
1659     <condition id="CM33_BE_GCC">
1660       <description>Cortex-M33 processor based device in big endian mode for the GCC Compiler</description>
1661       <require condition="CM33_GCC"/>
1662       <require Dendian="Big-endian"/>
1663     </condition>
1664
1665     <condition id="CM33_FP_GCC">
1666       <description>Cortex-M33 processor based device using Floating Point Unit for the GCC Compiler</description>
1667       <require condition="CM33_FP"/>
1668       <require Tcompiler="GCC"/>
1669     </condition>
1670     <condition id="CM33_FP_LE_GCC">
1671       <description>Cortex-M33 processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
1672       <require condition="CM33_FP_GCC"/>
1673       <require Dendian="Little-endian"/>
1674     </condition>
1675     <condition id="CM33_FP_BE_GCC">
1676       <description>Cortex-M33 processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
1677       <require condition="CM33_FP_GCC"/>
1678       <require Dendian="Big-endian"/>
1679     </condition>
1680
1681     <condition id="CM33_NODSP_NOFPU_GCC">
1682       <description>CM33, no DSP, no FPU, GCC Compiler</description>
1683       <require condition="CM33_NODSP_NOFPU"/>
1684       <require Tcompiler="GCC"/>
1685     </condition>
1686     <condition id="CM33_DSP_NOFPU_GCC">
1687       <description>CM33, DSP, no FPU, GCC Compiler</description>
1688       <require condition="CM33_DSP_NOFPU"/>
1689       <require Tcompiler="GCC"/>
1690     </condition>
1691     <condition id="CM33_NODSP_SP_GCC">
1692       <description>CM33, no DSP, SP FPU, GCC Compiler</description>
1693       <require condition="CM33_NODSP_SP"/>
1694       <require Tcompiler="GCC"/>
1695     </condition>
1696     <condition id="CM33_DSP_SP_GCC">
1697       <description>CM33, DSP, SP FPU, GCC Compiler</description>
1698       <require condition="CM33_DSP_SP"/>
1699       <require Tcompiler="GCC"/>
1700     </condition>
1701     <condition id="CM33_NODSP_NOFPU_LE_GCC">
1702       <description>CM33, little endian, no DSP, no FPU, GCC Compiler</description>
1703       <require condition="CM33_NODSP_NOFPU_GCC"/>
1704       <require Dendian="Little-endian"/>
1705     </condition>
1706     <condition id="CM33_DSP_NOFPU_LE_GCC">
1707       <description>CM33, little endian, DSP, no FPU, GCC Compiler</description>
1708       <require condition="CM33_DSP_NOFPU_GCC"/>
1709       <require Dendian="Little-endian"/>
1710     </condition>
1711     <condition id="CM33_NODSP_SP_LE_GCC">
1712       <description>CM33, little endian, no DSP, SP FPU, GCC Compiler</description>
1713       <require condition="CM33_NODSP_SP_GCC"/>
1714       <require Dendian="Little-endian"/>
1715     </condition>
1716     <condition id="CM33_DSP_SP_LE_GCC">
1717       <description>CM33, little endian, DSP, SP FPU, GCC Compiler</description>
1718       <require condition="CM33_DSP_SP_GCC"/>
1719       <require Dendian="Little-endian"/>
1720     </condition>
1721
1722     <condition id="CM35P_GCC">
1723       <description>Cortex-M35P processor based device for the GCC Compiler</description>
1724       <require condition="CM35P"/>
1725       <require Tcompiler="GCC"/>
1726     </condition>
1727     <condition id="CM35P_LE_GCC">
1728       <description>Cortex-M35P processor based device in little endian mode for the GCC Compiler</description>
1729       <require condition="CM35P_GCC"/>
1730       <require Dendian="Little-endian"/>
1731     </condition>
1732     <condition id="CM35P_BE_GCC">
1733       <description>Cortex-M35P processor based device in big endian mode for the GCC Compiler</description>
1734       <require condition="CM35P_GCC"/>
1735       <require Dendian="Big-endian"/>
1736     </condition>
1737
1738     <condition id="CM35P_FP_GCC">
1739       <description>Cortex-M35P processor based device using Floating Point Unit for the GCC Compiler</description>
1740       <require condition="CM35P_FP"/>
1741       <require Tcompiler="GCC"/>
1742     </condition>
1743     <condition id="CM35P_FP_LE_GCC">
1744       <description>Cortex-M35P processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
1745       <require condition="CM35P_FP_GCC"/>
1746       <require Dendian="Little-endian"/>
1747     </condition>
1748     <condition id="CM35P_FP_BE_GCC">
1749       <description>Cortex-M35P processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
1750       <require condition="CM35P_FP_GCC"/>
1751       <require Dendian="Big-endian"/>
1752     </condition>
1753
1754     <condition id="CM35P_NODSP_NOFPU_GCC">
1755       <description>CM35P, no DSP, no FPU, GCC Compiler</description>
1756       <require condition="CM35P_NODSP_NOFPU"/>
1757       <require Tcompiler="GCC"/>
1758     </condition>
1759     <condition id="CM35P_DSP_NOFPU_GCC">
1760       <description>CM35P, DSP, no FPU, GCC Compiler</description>
1761       <require condition="CM35P_DSP_NOFPU"/>
1762       <require Tcompiler="GCC"/>
1763     </condition>
1764     <condition id="CM35P_NODSP_SP_GCC">
1765       <description>CM35P, no DSP, SP FPU, GCC Compiler</description>
1766       <require condition="CM35P_NODSP_SP"/>
1767       <require Tcompiler="GCC"/>
1768     </condition>
1769     <condition id="CM35P_DSP_SP_GCC">
1770       <description>CM35P, DSP, SP FPU, GCC Compiler</description>
1771       <require condition="CM35P_DSP_SP"/>
1772       <require Tcompiler="GCC"/>
1773     </condition>
1774     <condition id="CM35P_NODSP_NOFPU_LE_GCC">
1775       <description>CM35P, little endian, no DSP, no FPU, GCC Compiler</description>
1776       <require condition="CM35P_NODSP_NOFPU_GCC"/>
1777       <require Dendian="Little-endian"/>
1778     </condition>
1779     <condition id="CM35P_DSP_NOFPU_LE_GCC">
1780       <description>CM35P, little endian, DSP, no FPU, GCC Compiler</description>
1781       <require condition="CM35P_DSP_NOFPU_GCC"/>
1782       <require Dendian="Little-endian"/>
1783     </condition>
1784     <condition id="CM35P_NODSP_SP_LE_GCC">
1785       <description>CM35P, little endian, no DSP, SP FPU, GCC Compiler</description>
1786       <require condition="CM35P_NODSP_SP_GCC"/>
1787       <require Dendian="Little-endian"/>
1788     </condition>
1789     <condition id="CM35P_DSP_SP_LE_GCC">
1790       <description>CM35P, little endian, DSP, SP FPU, GCC Compiler</description>
1791       <require condition="CM35P_DSP_SP_GCC"/>
1792       <require Dendian="Little-endian"/>
1793     </condition>
1794
1795     <condition id="ARMv8MBL_GCC">
1796       <description>Armv8-M Baseline processor based device for the GCC Compiler</description>
1797       <require condition="ARMv8MBL"/>
1798       <require Tcompiler="GCC"/>
1799     </condition>
1800     <condition id="ARMv8MBL_LE_GCC">
1801       <description>Armv8-M Baseline processor based device in little endian mode for the GCC Compiler</description>
1802       <require condition="ARMv8MBL_GCC"/>
1803       <require Dendian="Little-endian"/>
1804     </condition>
1805     <condition id="ARMv8MBL_BE_GCC">
1806       <description>Armv8-M Baseline processor based device in big endian mode for the GCC Compiler</description>
1807       <require condition="ARMv8MBL_GCC"/>
1808       <require Dendian="Big-endian"/>
1809     </condition>
1810
1811     <condition id="ARMv8MML_GCC">
1812       <description>Armv8-M Mainline processor based device for the GCC Compiler</description>
1813       <require condition="ARMv8MML"/>
1814       <require Tcompiler="GCC"/>
1815     </condition>
1816     <condition id="ARMv8MML_LE_GCC">
1817       <description>Armv8-M Mainline processor based device in little endian mode for the GCC Compiler</description>
1818       <require condition="ARMv8MML_GCC"/>
1819       <require Dendian="Little-endian"/>
1820     </condition>
1821     <condition id="ARMv8MML_BE_GCC">
1822       <description>Armv8-M Mainline processor based device in big endian mode for the GCC Compiler</description>
1823       <require condition="ARMv8MML_GCC"/>
1824       <require Dendian="Big-endian"/>
1825     </condition>
1826
1827     <condition id="ARMv8MML_FP_GCC">
1828       <description>Armv8-M Mainline processor based device using Floating Point Unit for the GCC Compiler</description>
1829       <require condition="ARMv8MML_FP"/>
1830       <require Tcompiler="GCC"/>
1831     </condition>
1832     <condition id="ARMv8MML_FP_LE_GCC">
1833       <description>Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
1834       <require condition="ARMv8MML_FP_GCC"/>
1835       <require Dendian="Little-endian"/>
1836     </condition>
1837     <condition id="ARMv8MML_FP_BE_GCC">
1838       <description>Armv8-M Mainline processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
1839       <require condition="ARMv8MML_FP_GCC"/>
1840       <require Dendian="Big-endian"/>
1841     </condition>
1842
1843     <condition id="ARMv8MML_NODSP_NOFPU_GCC">
1844       <description>Armv8-M Mainline, no DSP, no FPU, GCC Compiler</description>
1845       <require condition="ARMv8MML_NODSP_NOFPU"/>
1846       <require Tcompiler="GCC"/>
1847     </condition>
1848     <condition id="ARMv8MML_DSP_NOFPU_GCC">
1849       <description>Armv8-M Mainline, DSP, no FPU, GCC Compiler</description>
1850       <require condition="ARMv8MML_DSP_NOFPU"/>
1851       <require Tcompiler="GCC"/>
1852     </condition>
1853     <condition id="ARMv8MML_NODSP_SP_GCC">
1854       <description>Armv8-M Mainline, no DSP, SP FPU, GCC Compiler</description>
1855       <require condition="ARMv8MML_NODSP_SP"/>
1856       <require Tcompiler="GCC"/>
1857     </condition>
1858     <condition id="ARMv8MML_DSP_SP_GCC">
1859       <description>Armv8-M Mainline, DSP, SP FPU, GCC Compiler</description>
1860       <require condition="ARMv8MML_DSP_SP"/>
1861       <require Tcompiler="GCC"/>
1862     </condition>
1863     <condition id="ARMv8MML_NODSP_NOFPU_LE_GCC">
1864       <description>Armv8-M Mainline, little endian, no DSP, no FPU, GCC Compiler</description>
1865       <require condition="ARMv8MML_NODSP_NOFPU_GCC"/>
1866       <require Dendian="Little-endian"/>
1867     </condition>
1868     <condition id="ARMv8MML_DSP_NOFPU_LE_GCC">
1869       <description>Armv8-M Mainline, little endian, DSP, no FPU, GCC Compiler</description>
1870       <require condition="ARMv8MML_DSP_NOFPU_GCC"/>
1871       <require Dendian="Little-endian"/>
1872     </condition>
1873     <condition id="ARMv8MML_NODSP_SP_LE_GCC">
1874       <description>Armv8-M Mainline, little endian, no DSP, SP FPU, GCC Compiler</description>
1875       <require condition="ARMv8MML_NODSP_SP_GCC"/>
1876       <require Dendian="Little-endian"/>
1877     </condition>
1878     <condition id="ARMv8MML_DSP_SP_LE_GCC">
1879       <description>Armv8-M Mainline, little endian, DSP, SP FPU, GCC Compiler</description>
1880       <require condition="ARMv8MML_DSP_SP_GCC"/>
1881       <require Dendian="Little-endian"/>
1882     </condition>
1883
1884     <!-- IAR compiler -->
1885     <condition id="CA_IAR">
1886       <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the IAR Compiler</description>
1887       <require condition="ARMv7-A Device"/>
1888       <require Tcompiler="IAR"/>
1889     </condition>
1890
1891     <condition id="CM0_IAR">
1892       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device for the IAR Compiler</description>
1893       <require condition="CM0"/>
1894       <require Tcompiler="IAR"/>
1895     </condition>
1896     <condition id="CM0_LE_IAR">
1897       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the IAR Compiler</description>
1898       <require condition="CM0_IAR"/>
1899       <require Dendian="Little-endian"/>
1900     </condition>
1901     <condition id="CM0_BE_IAR">
1902       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the IAR Compiler</description>
1903       <require condition="CM0_IAR"/>
1904       <require Dendian="Big-endian"/>
1905     </condition>
1906
1907     <condition id="CM1_IAR">
1908       <description>Cortex-M1 based device for the IAR Compiler</description>
1909       <require condition="CM1"/>
1910       <require Tcompiler="IAR"/>
1911     </condition>
1912     <condition id="CM1_LE_IAR">
1913       <description>Cortex-M1 based device in little endian mode for the IAR Compiler</description>
1914       <require condition="CM1_IAR"/>
1915       <require Dendian="Little-endian"/>
1916     </condition>
1917     <condition id="CM1_BE_IAR">
1918       <description>Cortex-M1 based device in big endian mode for the IAR Compiler</description>
1919       <require condition="CM1_IAR"/>
1920       <require Dendian="Big-endian"/>
1921     </condition>
1922
1923     <condition id="CM3_IAR">
1924       <description>Cortex-M3 or SC300 processor based device for the IAR Compiler</description>
1925       <require condition="CM3"/>
1926       <require Tcompiler="IAR"/>
1927     </condition>
1928     <condition id="CM3_LE_IAR">
1929       <description>Cortex-M3 or SC300 processor based device in little endian mode for the IAR Compiler</description>
1930       <require condition="CM3_IAR"/>
1931       <require Dendian="Little-endian"/>
1932     </condition>
1933     <condition id="CM3_BE_IAR">
1934       <description>Cortex-M3 or SC300 processor based device in big endian mode for the IAR Compiler</description>
1935       <require condition="CM3_IAR"/>
1936       <require Dendian="Big-endian"/>
1937     </condition>
1938
1939     <condition id="CM4_IAR">
1940       <description>Cortex-M4 processor based device for the IAR Compiler</description>
1941       <require condition="CM4"/>
1942       <require Tcompiler="IAR"/>
1943     </condition>
1944     <condition id="CM4_LE_IAR">
1945       <description>Cortex-M4 processor based device in little endian mode for the IAR Compiler</description>
1946       <require condition="CM4_IAR"/>
1947       <require Dendian="Little-endian"/>
1948     </condition>
1949     <condition id="CM4_BE_IAR">
1950       <description>Cortex-M4 processor based device in big endian mode for the IAR Compiler</description>
1951       <require condition="CM4_IAR"/>
1952       <require Dendian="Big-endian"/>
1953     </condition>
1954
1955     <condition id="CM4_FP_IAR">
1956       <description>Cortex-M4 processor based device using Floating Point Unit for the IAR Compiler</description>
1957       <require condition="CM4_FP"/>
1958       <require Tcompiler="IAR"/>
1959     </condition>
1960     <condition id="CM4_FP_LE_IAR">
1961       <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
1962       <require condition="CM4_FP_IAR"/>
1963       <require Dendian="Little-endian"/>
1964     </condition>
1965     <condition id="CM4_FP_BE_IAR">
1966       <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
1967       <require condition="CM4_FP_IAR"/>
1968       <require Dendian="Big-endian"/>
1969     </condition>
1970
1971     <condition id="CM7_IAR">
1972       <description>Cortex-M7 processor based device for the IAR Compiler</description>
1973       <require condition="CM7"/>
1974       <require Tcompiler="IAR"/>
1975     </condition>
1976     <condition id="CM7_LE_IAR">
1977       <description>Cortex-M7 processor based device in little endian mode for the IAR Compiler</description>
1978       <require condition="CM7_IAR"/>
1979       <require Dendian="Little-endian"/>
1980     </condition>
1981     <condition id="CM7_BE_IAR">
1982       <description>Cortex-M7 processor based device in big endian mode for the IAR Compiler</description>
1983       <require condition="CM7_IAR"/>
1984       <require Dendian="Big-endian"/>
1985     </condition>
1986
1987     <condition id="CM7_FP_IAR">
1988       <description>Cortex-M7 processor based device using Floating Point Unit for the IAR Compiler</description>
1989       <require condition="CM7_FP"/>
1990       <require Tcompiler="IAR"/>
1991     </condition>
1992     <condition id="CM7_FP_LE_IAR">
1993       <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
1994       <require condition="CM7_FP_IAR"/>
1995       <require Dendian="Little-endian"/>
1996     </condition>
1997     <condition id="CM7_FP_BE_IAR">
1998       <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
1999       <require condition="CM7_FP_IAR"/>
2000       <require Dendian="Big-endian"/>
2001     </condition>
2002
2003     <condition id="CM7_SP_IAR">
2004       <description>Cortex-M7 processor based device using Floating Point Unit (SP) for the IAR Compiler</description>
2005       <require condition="CM7_SP"/>
2006       <require Tcompiler="IAR"/>
2007     </condition>
2008     <condition id="CM7_SP_LE_IAR">
2009       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the IAR Compiler</description>
2010       <require condition="CM7_SP_IAR"/>
2011       <require Dendian="Little-endian"/>
2012     </condition>
2013     <condition id="CM7_SP_BE_IAR">
2014       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the IAR Compiler</description>
2015       <require condition="CM7_SP_IAR"/>
2016       <require Dendian="Big-endian"/>
2017     </condition>
2018
2019     <condition id="CM7_DP_IAR">
2020       <description>Cortex-M7 processor based device using Floating Point Unit (DP) for the IAR Compiler</description>
2021       <require condition="CM7_DP"/>
2022       <require Tcompiler="IAR"/>
2023     </condition>
2024     <condition id="CM7_DP_LE_IAR">
2025       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the IAR Compiler</description>
2026       <require condition="CM7_DP_IAR"/>
2027       <require Dendian="Little-endian"/>
2028     </condition>
2029     <condition id="CM7_DP_BE_IAR">
2030       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the IAR Compiler</description>
2031       <require condition="CM7_DP_IAR"/>
2032       <require Dendian="Big-endian"/>
2033     </condition>
2034
2035     <condition id="CM23_IAR">
2036       <description>Cortex-M23 processor based device for the IAR Compiler</description>
2037       <require condition="CM23"/>
2038       <require Tcompiler="IAR"/>
2039     </condition>
2040     <condition id="CM23_LE_IAR">
2041       <description>Cortex-M23 processor based device in little endian mode for the IAR Compiler</description>
2042       <require condition="CM23_IAR"/>
2043       <require Dendian="Little-endian"/>
2044     </condition>
2045     <condition id="CM23_BE_IAR">
2046       <description>Cortex-M23 processor based device in big endian mode for the IAR Compiler</description>
2047       <require condition="CM23_IAR"/>
2048       <require Dendian="Big-endian"/>
2049     </condition>
2050
2051     <condition id="CM33_IAR">
2052       <description>Cortex-M33 processor based device for the IAR Compiler</description>
2053       <require condition="CM33"/>
2054       <require Tcompiler="IAR"/>
2055     </condition>
2056     <condition id="CM33_LE_IAR">
2057       <description>Cortex-M33 processor based device in little endian mode for the IAR Compiler</description>
2058       <require condition="CM33_IAR"/>
2059       <require Dendian="Little-endian"/>
2060     </condition>
2061     <condition id="CM33_BE_IAR">
2062       <description>Cortex-M33 processor based device in big endian mode for the IAR Compiler</description>
2063       <require condition="CM33_IAR"/>
2064       <require Dendian="Big-endian"/>
2065     </condition>
2066
2067     <condition id="CM33_FP_IAR">
2068       <description>Cortex-M33 processor based device using Floating Point Unit for the IAR Compiler</description>
2069       <require condition="CM33_FP"/>
2070       <require Tcompiler="IAR"/>
2071     </condition>
2072     <condition id="CM33_FP_LE_IAR">
2073       <description>Cortex-M33 processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
2074       <require condition="CM33_FP_IAR"/>
2075       <require Dendian="Little-endian"/>
2076     </condition>
2077     <condition id="CM33_FP_BE_IAR">
2078       <description>Cortex-M33 processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
2079       <require condition="CM33_FP_IAR"/>
2080       <require Dendian="Big-endian"/>
2081     </condition>
2082
2083     <condition id="CM33_NODSP_NOFPU_IAR">
2084       <description>CM33, no DSP, no FPU, IAR Compiler</description>
2085       <require condition="CM33_NODSP_NOFPU"/>
2086       <require Tcompiler="IAR"/>
2087     </condition>
2088     <condition id="CM33_DSP_NOFPU_IAR">
2089       <description>CM33, DSP, no FPU, IAR Compiler</description>
2090       <require condition="CM33_DSP_NOFPU"/>
2091       <require Tcompiler="IAR"/>
2092     </condition>
2093     <condition id="CM33_NODSP_SP_IAR">
2094       <description>CM33, no DSP, SP FPU, IAR Compiler</description>
2095       <require condition="CM33_NODSP_SP"/>
2096       <require Tcompiler="IAR"/>
2097     </condition>
2098     <condition id="CM33_DSP_SP_IAR">
2099       <description>CM33, DSP, SP FPU, IAR Compiler</description>
2100       <require condition="CM33_DSP_SP"/>
2101       <require Tcompiler="IAR"/>
2102     </condition>
2103     <condition id="CM33_NODSP_NOFPU_LE_IAR">
2104       <description>CM33, little endian, no DSP, no FPU, IAR Compiler</description>
2105       <require condition="CM33_NODSP_NOFPU_IAR"/>
2106       <require Dendian="Little-endian"/>
2107     </condition>
2108     <condition id="CM33_DSP_NOFPU_LE_IAR">
2109       <description>CM33, little endian, DSP, no FPU, IAR Compiler</description>
2110       <require condition="CM33_DSP_NOFPU_IAR"/>
2111       <require Dendian="Little-endian"/>
2112     </condition>
2113     <condition id="CM33_NODSP_SP_LE_IAR">
2114       <description>CM33, little endian, no DSP, SP FPU, IAR Compiler</description>
2115       <require condition="CM33_NODSP_SP_IAR"/>
2116       <require Dendian="Little-endian"/>
2117     </condition>
2118     <condition id="CM33_DSP_SP_LE_IAR">
2119       <description>CM33, little endian, DSP, SP FPU, IAR Compiler</description>
2120       <require condition="CM33_DSP_SP_IAR"/>
2121       <require Dendian="Little-endian"/>
2122     </condition>
2123
2124     <condition id="CM35P_IAR">
2125       <description>Cortex-M35P processor based device for the IAR Compiler</description>
2126       <require condition="CM35P"/>
2127       <require Tcompiler="IAR"/>
2128     </condition>
2129     <condition id="CM35P_LE_IAR">
2130       <description>Cortex-M35P processor based device in little endian mode for the IAR Compiler</description>
2131       <require condition="CM35P_IAR"/>
2132       <require Dendian="Little-endian"/>
2133     </condition>
2134     <condition id="CM35P_BE_IAR">
2135       <description>Cortex-M35P processor based device in big endian mode for the IAR Compiler</description>
2136       <require condition="CM35P_IAR"/>
2137       <require Dendian="Big-endian"/>
2138     </condition>
2139
2140     <condition id="CM35P_FP_IAR">
2141       <description>Cortex-M35P processor based device using Floating Point Unit for the IAR Compiler</description>
2142       <require condition="CM35P_FP"/>
2143       <require Tcompiler="IAR"/>
2144     </condition>
2145     <condition id="CM35P_FP_LE_IAR">
2146       <description>Cortex-M35P processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
2147       <require condition="CM35P_FP_IAR"/>
2148       <require Dendian="Little-endian"/>
2149     </condition>
2150     <condition id="CM35P_FP_BE_IAR">
2151       <description>Cortex-M35P processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
2152       <require condition="CM35P_FP_IAR"/>
2153       <require Dendian="Big-endian"/>
2154     </condition>
2155
2156     <condition id="CM35P_NODSP_NOFPU_IAR">
2157       <description>CM35P, no DSP, no FPU, IAR Compiler</description>
2158       <require condition="CM35P_NODSP_NOFPU"/>
2159       <require Tcompiler="IAR"/>
2160     </condition>
2161     <condition id="CM35P_DSP_NOFPU_IAR">
2162       <description>CM35P, DSP, no FPU, IAR Compiler</description>
2163       <require condition="CM35P_DSP_NOFPU"/>
2164       <require Tcompiler="IAR"/>
2165     </condition>
2166     <condition id="CM35P_NODSP_SP_IAR">
2167       <description>CM35P, no DSP, SP FPU, IAR Compiler</description>
2168       <require condition="CM35P_NODSP_SP"/>
2169       <require Tcompiler="IAR"/>
2170     </condition>
2171     <condition id="CM35P_DSP_SP_IAR">
2172       <description>CM35P, DSP, SP FPU, IAR Compiler</description>
2173       <require condition="CM35P_DSP_SP"/>
2174       <require Tcompiler="IAR"/>
2175     </condition>
2176     <condition id="CM35P_NODSP_NOFPU_LE_IAR">
2177       <description>CM35P, little endian, no DSP, no FPU, IAR Compiler</description>
2178       <require condition="CM35P_NODSP_NOFPU_IAR"/>
2179       <require Dendian="Little-endian"/>
2180     </condition>
2181     <condition id="CM35P_DSP_NOFPU_LE_IAR">
2182       <description>CM35P, little endian, DSP, no FPU, IAR Compiler</description>
2183       <require condition="CM35P_DSP_NOFPU_IAR"/>
2184       <require Dendian="Little-endian"/>
2185     </condition>
2186     <condition id="CM35P_NODSP_SP_LE_IAR">
2187       <description>CM35P, little endian, no DSP, SP FPU, IAR Compiler</description>
2188       <require condition="CM35P_NODSP_SP_IAR"/>
2189       <require Dendian="Little-endian"/>
2190     </condition>
2191     <condition id="CM35P_DSP_SP_LE_IAR">
2192       <description>CM35P, little endian, DSP, SP FPU, IAR Compiler</description>
2193       <require condition="CM35P_DSP_SP_IAR"/>
2194       <require Dendian="Little-endian"/>
2195     </condition>
2196
2197     <condition id="ARMv8MBL_IAR">
2198       <description>Armv8-M Baseline processor based device for the IAR Compiler</description>
2199       <require condition="ARMv8MBL"/>
2200       <require Tcompiler="IAR"/>
2201     </condition>
2202     <condition id="ARMv8MBL_LE_IAR">
2203       <description>Armv8-M Baseline processor based device in little endian mode for the IAR Compiler</description>
2204       <require condition="ARMv8MBL_IAR"/>
2205       <require Dendian="Little-endian"/>
2206     </condition>
2207     <condition id="ARMv8MBL_BE_IAR">
2208       <description>Armv8-M Baseline processor based device in big endian mode for the IAR Compiler</description>
2209       <require condition="ARMv8MBL_IAR"/>
2210       <require Dendian="Big-endian"/>
2211     </condition>
2212
2213     <condition id="ARMv8MML_IAR">
2214       <description>Armv8-M Mainline processor based device for the IAR Compiler</description>
2215       <require condition="ARMv8MML"/>
2216       <require Tcompiler="IAR"/>
2217     </condition>
2218     <condition id="ARMv8MML_LE_IAR">
2219       <description>Armv8-M Mainline processor based device in little endian mode for the IAR Compiler</description>
2220       <require condition="ARMv8MML_IAR"/>
2221       <require Dendian="Little-endian"/>
2222     </condition>
2223     <condition id="ARMv8MML_BE_IAR">
2224       <description>Armv8-M Mainline processor based device in big endian mode for the IAR Compiler</description>
2225       <require condition="ARMv8MML_IAR"/>
2226       <require Dendian="Big-endian"/>
2227     </condition>
2228
2229     <condition id="ARMv8MML_FP_IAR">
2230       <description>Armv8-M Mainline processor based device using Floating Point Unit for the IAR Compiler</description>
2231       <require condition="ARMv8MML_FP"/>
2232       <require Tcompiler="IAR"/>
2233     </condition>
2234     <condition id="ARMv8MML_FP_LE_IAR">
2235       <description>Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
2236       <require condition="ARMv8MML_FP_IAR"/>
2237       <require Dendian="Little-endian"/>
2238     </condition>
2239     <condition id="ARMv8MML_FP_BE_IAR">
2240       <description>Armv8-M Mainline processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
2241       <require condition="ARMv8MML_FP_IAR"/>
2242       <require Dendian="Big-endian"/>
2243     </condition>
2244
2245     <condition id="ARMv8MML_NODSP_NOFPU_IAR">
2246       <description>Armv8-M Mainline, no DSP, no FPU, IAR Compiler</description>
2247       <require condition="ARMv8MML_NODSP_NOFPU"/>
2248       <require Tcompiler="IAR"/>
2249     </condition>
2250     <condition id="ARMv8MML_DSP_NOFPU_IAR">
2251       <description>Armv8-M Mainline, DSP, no FPU, IAR Compiler</description>
2252       <require condition="ARMv8MML_DSP_NOFPU"/>
2253       <require Tcompiler="IAR"/>
2254     </condition>
2255     <condition id="ARMv8MML_NODSP_SP_IAR">
2256       <description>Armv8-M Mainline, no DSP, SP FPU, IAR Compiler</description>
2257       <require condition="ARMv8MML_NODSP_SP"/>
2258       <require Tcompiler="IAR"/>
2259     </condition>
2260     <condition id="ARMv8MML_DSP_SP_IAR">
2261       <description>Armv8-M Mainline, DSP, SP FPU, IAR Compiler</description>
2262       <require condition="ARMv8MML_DSP_SP"/>
2263       <require Tcompiler="IAR"/>
2264     </condition>
2265     <condition id="ARMv8MML_NODSP_NOFPU_LE_IAR">
2266       <description>Armv8-M Mainline, little endian, no DSP, no FPU, IAR Compiler</description>
2267       <require condition="ARMv8MML_NODSP_NOFPU_IAR"/>
2268       <require Dendian="Little-endian"/>
2269     </condition>
2270     <condition id="ARMv8MML_DSP_NOFPU_LE_IAR">
2271       <description>Armv8-M Mainline, little endian, DSP, no FPU, IAR Compiler</description>
2272       <require condition="ARMv8MML_DSP_NOFPU_IAR"/>
2273       <require Dendian="Little-endian"/>
2274     </condition>
2275     <condition id="ARMv8MML_NODSP_SP_LE_IAR">
2276       <description>Armv8-M Mainline, little endian, no DSP, SP FPU, IAR Compiler</description>
2277       <require condition="ARMv8MML_NODSP_SP_IAR"/>
2278       <require Dendian="Little-endian"/>
2279     </condition>
2280     <condition id="ARMv8MML_DSP_SP_LE_IAR">
2281       <description>Armv8-M Mainline, little endian, DSP, SP FPU, IAR Compiler</description>
2282       <require condition="ARMv8MML_DSP_SP_IAR"/>
2283       <require Dendian="Little-endian"/>
2284     </condition>
2285
2286     <!-- conditions selecting single devices and CMSIS Core -->
2287     <!-- used for component startup, GCC version is used for C-Startup -->
2288     <condition id="ARMCM0 CMSIS">
2289       <description>Generic Arm Cortex-M0 device startup and depends on CMSIS Core</description>
2290       <require Dvendor="ARM:82" Dname="ARMCM0"/>
2291       <require Cclass="CMSIS" Cgroup="CORE"/>
2292     </condition>
2293     <condition id="ARMCM0 CMSIS GCC">
2294       <description>Generic ARM Cortex-M0 device startup and depends on CMSIS Core requiring GCC</description>
2295       <require condition="ARMCM0 CMSIS"/>
2296       <require condition="GCC"/>
2297     </condition>
2298
2299     <condition id="ARMCM0+ CMSIS">
2300       <description>Generic Arm Cortex-M0+ device startup and depends on CMSIS Core</description>
2301       <require Dvendor="ARM:82" Dname="ARMCM0P*"/>
2302       <require Cclass="CMSIS" Cgroup="CORE"/>
2303     </condition>
2304     <condition id="ARMCM0+ CMSIS GCC">
2305       <description>Generic Arm Cortex-M0+ device startup and depends CMSIS Core requiring GCC</description>
2306       <require condition="ARMCM0+ CMSIS"/>
2307       <require condition="GCC"/>
2308     </condition>
2309
2310     <condition id="ARMCM1 CMSIS">
2311       <description>Generic Arm Cortex-M1 device startup and depends on CMSIS Core</description>
2312       <require Dvendor="ARM:82" Dname="ARMCM1"/>
2313       <require Cclass="CMSIS" Cgroup="CORE"/>
2314     </condition>
2315     <condition id="ARMCM1 CMSIS GCC">
2316       <description>Generic ARM Cortex-M1 device startup and depends on CMSIS Core requiring GCC</description>
2317       <require condition="ARMCM1 CMSIS"/>
2318       <require condition="GCC"/>
2319     </condition>
2320
2321     <condition id="ARMCM3 CMSIS">
2322       <description>Generic Arm Cortex-M3 device startup and depends on CMSIS Core</description>
2323       <require Dvendor="ARM:82" Dname="ARMCM3"/>
2324       <require Cclass="CMSIS" Cgroup="CORE"/>
2325     </condition>
2326     <condition id="ARMCM3 CMSIS GCC">
2327       <description>Generic Arm Cortex-M3 device startup and depends on CMSIS Core requiring GCC</description>
2328       <require condition="ARMCM3 CMSIS"/>
2329       <require condition="GCC"/>
2330     </condition>
2331
2332     <condition id="ARMCM4 CMSIS">
2333       <description>Generic Arm Cortex-M4 device startup and depends on CMSIS Core</description>
2334       <require Dvendor="ARM:82" Dname="ARMCM4*"/>
2335       <require Cclass="CMSIS" Cgroup="CORE"/>
2336     </condition>
2337     <condition id="ARMCM4 CMSIS GCC">
2338       <description>Generic Arm Cortex-M4 device startup and depends on CMSIS Core requiring GCC</description>
2339       <require condition="ARMCM4 CMSIS"/>
2340       <require condition="GCC"/>
2341     </condition>
2342
2343     <condition id="ARMCM7 CMSIS">
2344       <description>Generic Arm Cortex-M7 device startup and depends on CMSIS Core</description>
2345       <require Dvendor="ARM:82" Dname="ARMCM7*"/>
2346       <require Cclass="CMSIS" Cgroup="CORE"/>
2347     </condition>
2348     <condition id="ARMCM7 CMSIS GCC">
2349       <description>Generic Arm Cortex-M7 device startup and depends on CMSIS Core requiring GCC</description>
2350       <require condition="ARMCM7 CMSIS"/>
2351       <require condition="GCC"/>
2352     </condition>
2353
2354     <condition id="ARMCM23 CMSIS">
2355       <description>Generic Arm Cortex-M23 device startup and depends on CMSIS Core</description>
2356       <require Dvendor="ARM:82" Dname="ARMCM23*"/>
2357       <require Cclass="CMSIS" Cgroup="CORE"/>
2358     </condition>
2359     <condition id="ARMCM23 CMSIS GCC">
2360       <description>Generic Arm Cortex-M23 device startup and depends on CMSIS Core requiring GCC</description>
2361       <require condition="ARMCM23 CMSIS"/>
2362       <require condition="GCC"/>
2363     </condition>
2364
2365     <condition id="ARMCM33 CMSIS">
2366       <description>Generic Arm Cortex-M33 device startup and depends on CMSIS Core</description>
2367       <require Dvendor="ARM:82" Dname="ARMCM33*"/>
2368       <require Cclass="CMSIS" Cgroup="CORE"/>
2369     </condition>
2370     <condition id="ARMCM33 CMSIS GCC">
2371       <description>Generic Arm Cortex-M33 device startup and depends on CMSIS Core requiring GCC</description>
2372       <require condition="ARMCM33 CMSIS"/>
2373       <require condition="GCC"/>
2374     </condition>
2375
2376     <condition id="ARMCM35P CMSIS">
2377       <description>Generic Arm Cortex-M35P device startup and depends on CMSIS Core</description>
2378       <require Dvendor="ARM:82" Dname="ARMCM35P*"/>
2379       <require Cclass="CMSIS" Cgroup="CORE"/>
2380     </condition>
2381     <condition id="ARMCM35P CMSIS GCC">
2382       <description>Generic Arm Cortex-M35P device startup and depends on CMSIS Core requiring GCC</description>
2383       <require condition="ARMCM35P CMSIS"/>
2384       <require condition="GCC"/>
2385     </condition>
2386
2387     <condition id="ARMSC000 CMSIS">
2388       <description>Generic Arm SC000 device startup and depends on CMSIS Core</description>
2389       <require Dvendor="ARM:82" Dname="ARMSC000"/>
2390       <require Cclass="CMSIS" Cgroup="CORE"/>
2391     </condition>
2392     <condition id="ARMSC000 CMSIS GCC">
2393       <description>Generic Arm SC000 device startup and depends on CMSIS Core requiring GCC</description>
2394       <require condition="ARMSC000 CMSIS"/>
2395       <require condition="GCC"/>
2396     </condition>
2397
2398     <condition id="ARMSC300 CMSIS">
2399       <description>Generic Arm SC300 device startup and depends on CMSIS Core</description>
2400       <require Dvendor="ARM:82" Dname="ARMSC300"/>
2401       <require Cclass="CMSIS" Cgroup="CORE"/>
2402     </condition>
2403     <condition id="ARMSC300 CMSIS GCC">
2404       <description>Generic Arm SC300 device startup and dependson CMSIS Core requiring GCC</description>
2405       <require condition="ARMSC300 CMSIS"/>
2406       <require condition="GCC"/>
2407     </condition>
2408
2409     <condition id="ARMv8MBL CMSIS">
2410       <description>Generic Armv8-M Baseline device startup and depends on CMSIS Core</description>
2411       <require Dvendor="ARM:82" Dname="ARMv8MBL"/>
2412       <require Cclass="CMSIS" Cgroup="CORE"/>
2413     </condition>
2414     <condition id="ARMv8MBL CMSIS GCC">
2415       <description>Generic Armv8-M Baseline device startup and depends on CMSIS Core requiring GCC</description>
2416       <require condition="ARMv8MBL CMSIS"/>
2417       <require condition="GCC"/>
2418     </condition>
2419
2420     <condition id="ARMv8MML CMSIS">
2421       <description>Generic Armv8-M Mainline device startup and depends on CMSIS Core</description>
2422       <require Dvendor="ARM:82" Dname="ARMv8MML*"/>
2423       <require Cclass="CMSIS" Cgroup="CORE"/>
2424     </condition>
2425     <condition id="ARMv8MML CMSIS GCC">
2426       <description>Generic Armv8-M Mainline device startup and depends on CMSIS Core requiring GCC</description>
2427       <require condition="ARMv8MML CMSIS"/>
2428       <require condition="GCC"/>
2429     </condition>
2430
2431     <condition id="ARMv81MML CMSIS">
2432       <description>Generic Armv8.1-M Mainline device startup and depends on CMSIS Core</description>
2433       <require Dvendor="ARM:82" Dname="ARMv81MML*"/>
2434       <require Cclass="CMSIS" Cgroup="CORE"/>
2435     </condition>
2436
2437     <condition id="ARMCA5 CMSIS">
2438       <description>Generic Arm Cortex-A5 device startup and depends on CMSIS Core</description>
2439       <require Dvendor="ARM:82" Dname="ARMCA5"/>
2440       <require Cclass="CMSIS" Cgroup="CORE"/>
2441     </condition>
2442
2443     <condition id="ARMCA7 CMSIS">
2444       <description>Generic Arm Cortex-A7 device startup and depends on CMSIS Core</description>
2445       <require Dvendor="ARM:82" Dname="ARMCA7"/>
2446       <require Cclass="CMSIS" Cgroup="CORE"/>
2447     </condition>
2448
2449     <condition id="ARMCA9 CMSIS">
2450       <description>Generic Arm Cortex-A9 device startup and depends on CMSIS Core</description>
2451       <require Dvendor="ARM:82" Dname="ARMCA9"/>
2452       <require Cclass="CMSIS" Cgroup="CORE"/>
2453     </condition>
2454
2455     <!-- CMSIS DSP -->
2456     <condition id="CMSIS DSP">
2457       <description>Components required for DSP</description>
2458       <require condition="ARMv6_7_8-M Device"/>
2459       <require condition="ARMCC GCC IAR"/>
2460       <require Cclass="CMSIS" Cgroup="CORE"/>
2461     </condition>
2462
2463     <!-- CMSIS NN -->
2464     <condition id="CMSIS NN">
2465       <description>Components required for NN</description>
2466       <require condition="CMSIS DSP"/>
2467     </condition>
2468
2469     <!-- RTOS RTX -->
2470     <condition id="RTOS RTX">
2471       <description>Components required for RTOS RTX</description>
2472       <require condition="ARMv6_7-M Device"/>
2473       <require condition="ARMCC GCC IAR"/>
2474       <require Cclass="Device" Cgroup="Startup"/>
2475       <deny    Cclass="CMSIS"  Cgroup="RTOS2" Csub="Keil RTX5"/>
2476     </condition>
2477     <condition id="RTOS RTX IFX">
2478       <description>Components required for RTOS RTX IFX</description>
2479       <require condition="ARMv6_7-M Device"/>
2480       <require condition="ARMCC GCC IAR"/>
2481       <require Dvendor="Infineon:7" Dname="XMC4*"/>
2482       <require Cclass="Device" Cgroup="Startup"/>
2483       <deny    Cclass="CMSIS"  Cgroup="RTOS2" Csub="Keil RTX5"/>
2484     </condition>
2485     <condition id="RTOS RTX5">
2486       <description>Components required for RTOS RTX5</description>
2487       <require condition="ARMv6_7_8-M Device"/>
2488       <require condition="ARMCC GCC IAR"/>
2489       <require Cclass="CMSIS"  Cgroup="RTOS2" Csub="Keil RTX5"/>
2490     </condition>
2491     <condition id="RTOS2 RTX5">
2492       <description>Components required for RTOS2 RTX5</description>
2493       <require condition="ARMv6_7_8-M Device"/>
2494       <require condition="ARMCC GCC IAR"/>
2495       <require Cclass="CMSIS"  Cgroup="CORE"/>
2496       <require Cclass="Device" Cgroup="Startup"/>
2497     </condition>
2498     <condition id="RTOS2 RTX5 v7-A">
2499       <description>Components required for RTOS2 RTX5 on Armv7-A</description>
2500       <require condition="ARMv7-A Device"/>
2501       <require condition="ARMCC GCC IAR"/>
2502       <require Cclass="CMSIS"  Cgroup="CORE"/>
2503       <require Cclass="Device" Cgroup="Startup"/>
2504       <require Cclass="Device" Cgroup="OS Tick"/>
2505       <require Cclass="Device" Cgroup="IRQ Controller"/>
2506     </condition>
2507     <condition id="RTOS2 RTX5 Lib">
2508       <description>Components required for RTOS2 RTX5 Library</description>
2509       <require condition="ARMv6_7_8-M Device"/>
2510       <require condition="ARMCC GCC IAR"/>
2511       <require Cclass="CMSIS"  Cgroup="CORE"/>
2512       <require Cclass="Device" Cgroup="Startup"/>
2513     </condition>
2514     <condition id="RTOS2 RTX5 NS">
2515       <description>Components required for RTOS2 RTX5 in Non-Secure Domain</description>
2516       <require condition="ARMv8-M TZ Device"/>
2517       <require condition="ARMCC GCC IAR"/>
2518       <require Cclass="CMSIS"  Cgroup="CORE"/>
2519       <require Cclass="Device" Cgroup="Startup"/>
2520     </condition>
2521
2522     <!-- OS Tick -->
2523     <condition id="OS Tick PTIM">
2524       <description>Components required for OS Tick Private Timer</description>
2525       <require condition="CA5_CA9"/>
2526       <require Cclass="Device" Cgroup="IRQ Controller"/>
2527     </condition>
2528
2529     <condition id="OS Tick GTIM">
2530       <description>Components required for OS Tick Generic Physical Timer</description>
2531       <require condition="CA7"/>
2532       <require Cclass="Device" Cgroup="IRQ Controller"/>
2533     </condition>
2534
2535   </conditions>
2536
2537   <components>
2538     <!-- CMSIS-Core component -->
2539     <component Cclass="CMSIS" Cgroup="CORE" Cversion="5.1.3"  condition="ARMv6_7_8-M Device" >
2540       <description>CMSIS-CORE for Cortex-M, SC000, SC300, ARMv8-M, ARMv8.1-M</description>
2541       <files>
2542         <!-- CPU independent -->
2543         <file category="doc"     name="CMSIS/Documentation/Core/html/index.html"/>
2544         <file category="include" name="CMSIS/Core/Include/"/>
2545         <file category="header"  name="CMSIS/Core/Include/tz_context.h" condition="ARMv8-M TZ Device"/>
2546         <!-- Code template -->
2547         <file category="sourceC" attr="template" condition="ARMv8-M TZ Device" name="CMSIS/Core/Template/ARMv8-M/main_s.c"     version="1.1.0" select="Secure mode 'main' module for ARMv8-M"/>
2548         <file category="sourceC" attr="template" condition="ARMv8-M TZ Device" name="CMSIS/Core/Template/ARMv8-M/tz_context.c" version="1.1.0" select="RTOS Context Management (TrustZone for ARMv8-M)" />
2549       </files>
2550     </component>
2551
2552     <component Cclass="CMSIS" Cgroup="CORE" Cversion="1.1.2"  condition="ARMv7-A Device" >
2553       <description>CMSIS-CORE for Cortex-A</description>
2554       <files>
2555         <!-- CPU independent -->
2556         <file category="doc"     name="CMSIS/Documentation/Core_A/html/index.html"/>
2557         <file category="include" name="CMSIS/Core_A/Include/"/>
2558       </files>
2559     </component>
2560
2561     <!-- CMSIS-Startup components -->
2562     <!-- Cortex-M0 -->
2563     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM0 CMSIS">
2564       <description>System and Startup for Generic Arm Cortex-M0 device</description>
2565       <files>
2566         <!-- include folder / device header file -->
2567         <file category="header"  name="Device/ARM/ARMCM0/Include/ARMCM0.h"/>
2568         <!-- startup / system file -->
2569         <file category="sourceAsm"    name="Device/ARM/ARMCM0/Source/ARM/startup_ARMCM0.s" version="1.0.0" attr="config" condition="ARMCC"/>
2570         <file category="sourceAsm"    name="Device/ARM/ARMCM0/Source/GCC/startup_ARMCM0.S" version="1.0.0" attr="config" condition="GCC"/>
2571         <file category="linkerScript" name="Device/ARM/ARMCM0/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2572         <file category="sourceAsm"    name="Device/ARM/ARMCM0/Source/IAR/startup_ARMCM0.s" version="1.0.0" attr="config" condition="IAR"/>
2573         <file category="sourceC"      name="Device/ARM/ARMCM0/Source/system_ARMCM0.c"      version="1.0.0" attr="config"/>
2574       </files>
2575     </component>
2576     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM0 CMSIS GCC">
2577       <description>System and Startup for Generic Arm Cortex-M0 device</description>
2578       <files>
2579         <!-- include folder / device header file -->
2580         <file category="header"  name="Device/ARM/ARMCM0/Include/ARMCM0.h"/>
2581         <!-- startup / system file -->
2582         <file category="sourceC"      name="Device/ARM/ARMCM0/Source/GCC/startup_ARMCM0.c" version="1.0.0" attr="config" condition="GCC"/>
2583         <file category="linkerScript" name="Device/ARM/ARMCM0/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2584         <file category="sourceC"      name="Device/ARM/ARMCM0/Source/system_ARMCM0.c"      version="1.0.0" attr="config"/>
2585       </files>
2586     </component>
2587
2588     <!-- Cortex-M0+ -->
2589     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM0+ CMSIS">
2590       <description>System and Startup for Generic Arm Cortex-M0+ device</description>
2591       <files>
2592         <!-- include folder / device header file -->
2593         <file category="header"  name="Device/ARM/ARMCM0plus/Include/ARMCM0plus.h"/>
2594         <!-- startup / system file -->
2595         <file category="sourceAsm"    name="Device/ARM/ARMCM0plus/Source/ARM/startup_ARMCM0plus.s" version="1.0.0" attr="config" condition="ARMCC"/>
2596         <file category="sourceAsm"    name="Device/ARM/ARMCM0plus/Source/GCC/startup_ARMCM0plus.S" version="1.0.0" attr="config" condition="GCC"/>
2597         <file category="linkerScript" name="Device/ARM/ARMCM0plus/Source/GCC/gcc_arm.ld"           version="1.0.0" attr="config" condition="GCC"/>
2598         <file category="sourceAsm"    name="Device/ARM/ARMCM0plus/Source/IAR/startup_ARMCM0plus.s" version="1.0.0" attr="config" condition="IAR"/>
2599         <file category="sourceC"      name="Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c"      version="1.0.0" attr="config"/>
2600       </files>
2601     </component>
2602     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM0+ CMSIS GCC">
2603       <description>System and Startup for Generic Arm Cortex-M0+ device</description>
2604       <files>
2605         <!-- include folder / device header file -->
2606         <file category="header"  name="Device/ARM/ARMCM0plus/Include/ARMCM0plus.h"/>
2607         <!-- startup / system file -->
2608         <file category="sourceC"      name="Device/ARM/ARMCM0plus/Source/GCC/startup_ARMCM0plus.c" version="1.0.0" attr="config" condition="GCC"/>
2609         <file category="linkerScript" name="Device/ARM/ARMCM0plus/Source/GCC/gcc_arm.ld"           version="1.0.0" attr="config" condition="GCC"/>
2610         <file category="sourceC"      name="Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c"      version="1.0.0" attr="config"/>
2611       </files>
2612     </component>
2613
2614     <!-- Cortex-M1 -->
2615     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM1 CMSIS">
2616       <description>System and Startup for Generic Arm Cortex-M1 device</description>
2617       <files>
2618         <!-- include folder / device header file -->
2619         <file category="header"  name="Device/ARM/ARMCM1/Include/ARMCM1.h"/>
2620         <!-- startup / system file -->
2621         <file category="sourceAsm"    name="Device/ARM/ARMCM1/Source/ARM/startup_ARMCM1.s" version="1.0.0" attr="config" condition="ARMCC"/>
2622         <file category="sourceAsm"    name="Device/ARM/ARMCM1/Source/GCC/startup_ARMCM1.S" version="1.0.0" attr="config" condition="GCC"/>
2623         <file category="linkerScript" name="Device/ARM/ARMCM1/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2624         <file category="sourceAsm"    name="Device/ARM/ARMCM1/Source/IAR/startup_ARMCM1.s" version="1.0.0" attr="config" condition="IAR"/>
2625         <file category="sourceC"      name="Device/ARM/ARMCM1/Source/system_ARMCM1.c"      version="1.0.0" attr="config"/>
2626       </files>
2627     </component>
2628     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM1 CMSIS GCC">
2629       <description>System and Startup for Generic Arm Cortex-M1 device</description>
2630       <files>
2631         <!-- include folder / device header file -->
2632         <file category="header"  name="Device/ARM/ARMCM1/Include/ARMCM1.h"/>
2633         <!-- startup / system file -->
2634         <file category="sourceC"      name="Device/ARM/ARMCM1/Source/GCC/startup_ARMCM1.c" version="1.0.0" attr="config" condition="GCC"/>
2635         <file category="linkerScript" name="Device/ARM/ARMCM1/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2636         <file category="sourceC"      name="Device/ARM/ARMCM1/Source/system_ARMCM1.c"      version="1.0.0" attr="config"/>
2637       </files>
2638     </component>
2639
2640     <!-- Cortex-M3 -->
2641     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM3 CMSIS">
2642       <description>System and Startup for Generic Arm Cortex-M3 device</description>
2643       <files>
2644         <!-- include folder / device header file -->
2645         <file category="header"  name="Device/ARM/ARMCM3/Include/ARMCM3.h"/>
2646         <!-- startup / system file -->
2647         <file category="sourceAsm"    name="Device/ARM/ARMCM3/Source/ARM/startup_ARMCM3.s" version="1.0.0" attr="config" condition="ARMCC"/>
2648         <file category="sourceAsm"    name="Device/ARM/ARMCM3/Source/GCC/startup_ARMCM3.S" version="1.0.0" attr="config" condition="GCC"/>
2649         <file category="linkerScript" name="Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2650         <file category="sourceAsm"    name="Device/ARM/ARMCM3/Source/IAR/startup_ARMCM3.s" version="1.0.0" attr="config" condition="IAR"/>
2651         <file category="sourceC"      name="Device/ARM/ARMCM3/Source/system_ARMCM3.c"      version="1.0.0" attr="config"/>
2652       </files>
2653     </component>
2654     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM3 CMSIS GCC">
2655       <description>System and Startup for Generic Arm Cortex-M3 device</description>
2656       <files>
2657         <!-- include folder / device header file -->
2658         <file category="header"  name="Device/ARM/ARMCM3/Include/ARMCM3.h"/>
2659         <!-- startup / system file -->
2660         <file category="sourceC"      name="Device/ARM/ARMCM3/Source/GCC/startup_ARMCM3.c" version="1.0.0" attr="config" condition="GCC"/>
2661         <file category="linkerScript" name="Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2662         <file category="sourceC"      name="Device/ARM/ARMCM3/Source/system_ARMCM3.c"      version="1.0.0" attr="config"/>
2663       </files>
2664     </component>
2665
2666     <!-- Cortex-M4 -->
2667     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM4 CMSIS">
2668       <description>System and Startup for Generic Arm Cortex-M4 device</description>
2669       <files>
2670         <!-- include folder / device header file -->
2671         <file category="include" name="Device/ARM/ARMCM4/Include/"/>
2672         <!-- startup / system file -->
2673         <file category="sourceAsm"    name="Device/ARM/ARMCM4/Source/ARM/startup_ARMCM4.s" version="1.0.0" attr="config" condition="ARMCC"/>
2674         <file category="sourceAsm"    name="Device/ARM/ARMCM4/Source/GCC/startup_ARMCM4.S" version="1.0.0" attr="config" condition="GCC"/>
2675         <file category="linkerScript" name="Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2676         <file category="sourceAsm"    name="Device/ARM/ARMCM4/Source/IAR/startup_ARMCM4.s" version="1.0.0" attr="config" condition="IAR"/>
2677         <file category="sourceC"      name="Device/ARM/ARMCM4/Source/system_ARMCM4.c"      version="1.0.0" attr="config"/>
2678       </files>
2679     </component>
2680     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM4 CMSIS GCC">
2681       <description>System and Startup for Generic Arm Cortex-M4 device</description>
2682       <files>
2683         <!-- include folder / device header file -->
2684         <file category="include" name="Device/ARM/ARMCM4/Include/"/>
2685         <!-- startup / system file -->
2686         <file category="sourceC"      name="Device/ARM/ARMCM4/Source/GCC/startup_ARMCM4.c" version="1.0.0" attr="config" condition="GCC"/>
2687         <file category="linkerScript" name="Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2688         <file category="sourceC"      name="Device/ARM/ARMCM4/Source/system_ARMCM4.c"      version="1.0.0" attr="config"/>
2689       </files>
2690     </component>
2691
2692     <!-- Cortex-M7 -->
2693     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM7 CMSIS">
2694       <description>System and Startup for Generic Arm Cortex-M7 device</description>
2695       <files>
2696         <!-- include folder / device header file -->
2697         <file category="include"  name="Device/ARM/ARMCM7/Include/"/>
2698         <!-- startup / system file -->
2699         <file category="sourceAsm"    name="Device/ARM/ARMCM7/Source/ARM/startup_ARMCM7.s" version="1.0.0" attr="config" condition="ARMCC"/>
2700         <file category="sourceAsm"    name="Device/ARM/ARMCM7/Source/GCC/startup_ARMCM7.S" version="1.0.0" attr="config" condition="GCC"/>
2701         <file category="linkerScript" name="Device/ARM/ARMCM7/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2702         <file category="sourceAsm"    name="Device/ARM/ARMCM7/Source/IAR/startup_ARMCM7.s" version="1.0.0" attr="config" condition="IAR"/>
2703         <file category="sourceC"      name="Device/ARM/ARMCM7/Source/system_ARMCM7.c"      version="1.0.0" attr="config"/>
2704       </files>
2705     </component>
2706     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM7 CMSIS GCC">
2707       <description>System and Startup for Generic Arm Cortex-M7 device</description>
2708       <files>
2709         <!-- include folder / device header file -->
2710         <file category="include"  name="Device/ARM/ARMCM7/Include/"/>
2711         <!-- startup / system file -->
2712         <file category="sourceC"      name="Device/ARM/ARMCM7/Source/GCC/startup_ARMCM7.c" version="1.0.0" attr="config" condition="GCC"/>
2713         <file category="linkerScript" name="Device/ARM/ARMCM7/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2714         <file category="sourceC"      name="Device/ARM/ARMCM7/Source/system_ARMCM7.c"      version="1.0.0" attr="config"/>
2715       </files>
2716     </component>
2717
2718     <!-- Cortex-M23 -->
2719     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.0" condition="ARMCM23 CMSIS">
2720       <description>System and Startup for Generic Arm Cortex-M23 device</description>
2721       <files>
2722         <!-- include folder / device header file -->
2723         <file category="include"      name="Device/ARM/ARMCM23/Include/"/>
2724         <!-- startup / system file -->
2725         <file category="sourceAsm"    name="Device/ARM/ARMCM23/Source/ARM/startup_ARMCM23.s" version="1.0.0" attr="config" condition="ARMCC"/>
2726         <file category="sourceAsm"    name="Device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.S" version="1.0.0" attr="config" condition="GCC"/>
2727         <file category="linkerScript" name="Device/ARM/ARMCM23/Source/GCC/gcc_arm.ld"        version="1.0.0" attr="config" condition="GCC"/>
2728         <file category="sourceAsm"    name="Device/ARM/ARMCM23/Source/IAR/startup_ARMCM23.s" version="1.0.0" attr="config" condition="IAR"/>
2729         <file category="sourceC"      name="Device/ARM/ARMCM23/Source/system_ARMCM23.c"      version="1.0.0" attr="config"/>
2730         <!-- SAU configuration -->
2731         <file category="header"       name="Device/ARM/ARMCM23/Include/Template/partition_ARMCM23.h" version="1.0.0" attr="config" condition="ARMv8-M TZ Device"/>
2732       </files>
2733     </component>
2734     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.0" condition="ARMCM23 CMSIS GCC">
2735       <description>System and Startup for Generic Arm Cortex-M23 device</description>
2736       <files>
2737         <!-- include folder / device header file -->
2738         <file category="include"  name="Device/ARM/ARMCM23/Include/"/>
2739         <!-- startup / system file -->
2740         <file category="sourceC"      name="Device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.c" version="1.0.0" attr="config" condition="GCC"/>
2741         <file category="linkerScript" name="Device/ARM/ARMCM23/Source/GCC/gcc_arm.ld"        version="1.0.0" attr="config" condition="GCC"/>
2742         <file category="sourceC"      name="Device/ARM/ARMCM23/Source/system_ARMCM23.c"      version="1.0.0" attr="config"/>
2743         <!-- SAU configuration -->
2744         <file category="header"       name="Device/ARM/ARMCM23/Include/Template/partition_ARMCM23.h" version="1.0.0" attr="config" condition="ARMv8-M TZ Device"/>
2745       </files>
2746     </component>
2747
2748     <!-- Cortex-M33 -->
2749     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.1.0" condition="ARMCM33 CMSIS">
2750       <description>System and Startup for Generic Arm Cortex-M33 device</description>
2751       <files>
2752         <!-- include folder / device header file -->
2753         <file category="include"      name="Device/ARM/ARMCM33/Include/"/>
2754         <!-- startup / system file -->
2755         <file category="sourceAsm"    name="Device/ARM/ARMCM33/Source/ARM/startup_ARMCM33.s"         version="1.0.0" attr="config" condition="ARMCC"/>
2756         <file category="sourceAsm"    name="Device/ARM/ARMCM33/Source/GCC/startup_ARMCM33.S"         version="1.0.0" attr="config" condition="GCC"/>
2757         <file category="linkerScript" name="Device/ARM/ARMCM33/Source/GCC/gcc_arm.ld"                version="1.0.0" attr="config" condition="GCC"/>
2758         <file category="sourceAsm"    name="Device/ARM/ARMCM33/Source/IAR/startup_ARMCM33.s"         version="1.0.0" attr="config" condition="IAR"/>
2759         <file category="sourceC"      name="Device/ARM/ARMCM33/Source/system_ARMCM33.c"              version="1.0.0" attr="config"/>
2760         <!-- SAU configuration -->
2761         <file category="header"       name="Device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2762       </files>
2763     </component>
2764     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.1.0" condition="ARMCM33 CMSIS GCC">
2765       <description>System and Startup for Generic Arm Cortex-M33 device</description>
2766       <files>
2767         <!-- include folder / device header file -->
2768         <file category="include"  name="Device/ARM/ARMCM33/Include/"/>
2769         <!-- startup / system file -->
2770         <file category="sourceC"      name="Device/ARM/ARMCM33/Source/GCC/startup_ARMCM33.c"         version="1.0.0" attr="config" condition="GCC"/>
2771         <file category="linkerScript" name="Device/ARM/ARMCM33/Source/GCC/gcc_arm.ld"                version="1.0.0" attr="config" condition="GCC"/>
2772         <file category="sourceC"      name="Device/ARM/ARMCM33/Source/system_ARMCM33.c"              version="1.0.0" attr="config"/>
2773         <!-- SAU configuration -->
2774         <file category="header"       name="Device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2775       </files>
2776     </component>
2777
2778     <!-- Cortex-M35P -->
2779     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.1.0" condition="ARMCM35P CMSIS">
2780       <description>System and Startup for Generic Arm Cortex-M35P device</description>
2781       <files>
2782         <!-- include folder / device header file -->
2783         <file category="include"      name="Device/ARM/ARMCM35P/Include/"/>
2784         <!-- startup / system file -->
2785         <file category="sourceAsm"    name="Device/ARM/ARMCM35P/Source/ARM/startup_ARMCM35P.s"         version="1.0.0" attr="config" condition="ARMCC"/>
2786         <file category="sourceAsm"    name="Device/ARM/ARMCM35P/Source/GCC/startup_ARMCM35P.S"         version="1.0.0" attr="config" condition="GCC"/>
2787         <file category="linkerScript" name="Device/ARM/ARMCM35P/Source/GCC/gcc_arm.ld"                 version="1.0.0" attr="config" condition="GCC"/>
2788         <file category="sourceAsm"    name="Device/ARM/ARMCM35P/Source/IAR/startup_ARMCM35P.s"         version="1.0.0" attr="config" condition="IAR"/>
2789         <file category="sourceC"      name="Device/ARM/ARMCM35P/Source/system_ARMCM35P.c"              version="1.0.0" attr="config"/>
2790         <!-- SAU configuration -->
2791         <file category="header"       name="Device/ARM/ARMCM35P/Include/Template/partition_ARMCM35P.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2792       </files>
2793     </component>
2794     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.1.0" condition="ARMCM35P CMSIS GCC">
2795       <description>System and Startup for Generic Arm Cortex-M35P device</description>
2796       <files>
2797         <!-- include folder / device header file -->
2798         <file category="include"  name="Device/ARM/ARMCM35P/Include/"/>
2799         <!-- startup / system file -->
2800         <file category="sourceC"      name="Device/ARM/ARMCM35P/Source/GCC/startup_ARMCM35P.c"         version="1.0.0" attr="config" condition="GCC"/>
2801         <file category="linkerScript" name="Device/ARM/ARMCM35P/Source/GCC/gcc_arm.ld"                 version="1.0.0" attr="config" condition="GCC"/>
2802         <file category="sourceC"      name="Device/ARM/ARMCM35P/Source/system_ARMCM35P.c"              version="1.0.0" attr="config"/>
2803         <!-- SAU configuration -->
2804         <file category="header"       name="Device/ARM/ARMCM35P/Include/Template/partition_ARMCM35P.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2805       </files>
2806     </component>
2807
2808     <!-- Cortex-SC000 -->
2809     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMSC000 CMSIS">
2810       <description>System and Startup for Generic Arm SC000 device</description>
2811       <files>
2812         <!-- include folder / device header file -->
2813         <file category="header"  name="Device/ARM/ARMSC000/Include/ARMSC000.h"/>
2814         <!-- startup / system file -->
2815         <file category="sourceAsm"    name="Device/ARM/ARMSC000/Source/ARM/startup_ARMSC000.s" version="1.0.0" attr="config" condition="ARMCC"/>
2816         <file category="sourceAsm"    name="Device/ARM/ARMSC000/Source/GCC/startup_ARMSC000.S" version="1.0.0" attr="config" condition="GCC"/>
2817         <file category="linkerScript" name="Device/ARM/ARMSC000/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2818         <file category="sourceAsm"    name="Device/ARM/ARMSC000/Source/IAR/startup_ARMSC000.s" version="1.0.0" attr="config" condition="IAR"/>
2819         <file category="sourceC"      name="Device/ARM/ARMSC000/Source/system_ARMSC000.c"      version="1.0.0" attr="config"/>
2820       </files>
2821     </component>
2822     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMSC000 CMSIS GCC">
2823       <description>System and Startup for Generic Arm SC000 device</description>
2824       <files>
2825         <!-- include folder / device header file -->
2826         <file category="header"  name="Device/ARM/ARMSC000/Include/ARMSC000.h"/>
2827         <!-- startup / system file -->
2828         <file category="sourceC"      name="Device/ARM/ARMSC000/Source/GCC/startup_ARMSC000.c" version="1.0.0" attr="config" condition="GCC"/>
2829         <file category="linkerScript" name="Device/ARM/ARMSC000/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2830         <file category="sourceC"      name="Device/ARM/ARMSC000/Source/system_ARMSC000.c"      version="1.0.0" attr="config"/>
2831       </files>
2832     </component>
2833
2834     <!-- Cortex-SC300 -->
2835     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMSC300 CMSIS">
2836       <description>System and Startup for Generic Arm SC300 device</description>
2837       <files>
2838         <!-- include folder / device header file -->
2839         <file category="header"  name="Device/ARM/ARMSC300/Include/ARMSC300.h"/>
2840         <!-- startup / system file -->
2841         <file category="sourceAsm"    name="Device/ARM/ARMSC300/Source/ARM/startup_ARMSC300.s" version="1.0.0" attr="config" condition="ARMCC"/>
2842         <file category="sourceAsm"    name="Device/ARM/ARMSC300/Source/GCC/startup_ARMSC300.S" version="1.0.0" attr="config" condition="GCC"/>
2843         <file category="linkerScript" name="Device/ARM/ARMSC300/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2844         <file category="sourceAsm"    name="Device/ARM/ARMSC300/Source/IAR/startup_ARMSC300.s" version="1.0.0" attr="config" condition="IAR"/>
2845         <file category="sourceC"      name="Device/ARM/ARMSC300/Source/system_ARMSC300.c"      version="1.0.0" attr="config"/>
2846       </files>
2847     </component>
2848     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMSC300 CMSIS GCC">
2849       <description>System and Startup for Generic Arm SC300 device</description>
2850       <files>
2851         <!-- include folder / device header file -->
2852         <file category="header"  name="Device/ARM/ARMSC300/Include/ARMSC300.h"/>
2853         <!-- startup / system file -->
2854         <file category="sourceC"      name="Device/ARM/ARMSC300/Source/GCC/startup_ARMSC300.c" version="1.0.0" attr="config" condition="GCC"/>
2855         <file category="linkerScript" name="Device/ARM/ARMSC300/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2856         <file category="sourceC"      name="Device/ARM/ARMSC300/Source/system_ARMSC300.c"      version="1.0.0" attr="config"/>
2857       </files>
2858     </component>
2859
2860     <!-- ARMv8MBL -->
2861     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.0" condition="ARMv8MBL CMSIS">
2862       <description>System and Startup for Generic Armv8-M Baseline device</description>
2863       <files>
2864         <!-- include folder / device header file -->
2865         <file category="include"      name="Device/ARM/ARMv8MBL/Include/"/>
2866         <!-- startup / system file -->
2867         <file category="sourceAsm"    name="Device/ARM/ARMv8MBL/Source/ARM/startup_ARMv8MBL.s" version="1.0.0" attr="config" condition="ARMCC"/>
2868         <file category="sourceAsm"    name="Device/ARM/ARMv8MBL/Source/GCC/startup_ARMv8MBL.S" version="1.0.0" attr="config" condition="GCC"/>
2869         <file category="linkerScript" name="Device/ARM/ARMv8MBL/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2870         <file category="sourceC"      name="Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c"      version="1.0.0" attr="config" condition="ARMCC GCC"/>
2871         <!-- SAU configuration -->
2872         <file category="header"       name="Device/ARM/ARMv8MBL/Include/Template/partition_ARMv8MBL.h" version="1.0.0" attr="config"/>
2873       </files>
2874     </component>
2875     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.0" condition="ARMv8MBL CMSIS GCC">
2876       <description>System and Startup for Generic Armv8-M Baseline device</description>
2877       <files>
2878         <!-- include folder / device header file -->
2879         <file category="include"  name="Device/ARM/ARMv8MBL/Include/"/>
2880         <!-- startup / system file -->
2881         <file category="sourceC"      name="Device/ARM/ARMv8MBL/Source/GCC/startup_ARMv8MBL.c" version="1.0.0" attr="config" condition="GCC"/>
2882         <file category="linkerScript" name="Device/ARM/ARMv8MBL/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2883         <file category="sourceC"      name="Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c"      version="1.0.0" attr="config"/>
2884         <!-- SAU configuration -->
2885         <file category="header"       name="Device/ARM/ARMv8MBL/Include/Template/partition_ARMv8MBL.h" version="1.0.0" attr="config" condition="ARMv8-M TZ Device"/>
2886       </files>
2887     </component>
2888
2889     <!-- ARMv8MML -->
2890     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.1.0" condition="ARMv8MML CMSIS">
2891       <description>System and Startup for Generic Armv8-M Mainline device</description>
2892       <files>
2893         <!-- include folder / device header file -->
2894         <file category="include"      name="Device/ARM/ARMv8MML/Include/"/>
2895         <!-- startup / system file -->
2896         <file category="sourceAsm"    name="Device/ARM/ARMv8MML/Source/ARM/startup_ARMv8MML.s"         version="1.0.0" attr="config" condition="ARMCC"/>
2897         <file category="sourceAsm"    name="Device/ARM/ARMv8MML/Source/GCC/startup_ARMv8MML.S"         version="1.0.0" attr="config" condition="GCC"/>
2898         <file category="linkerScript" name="Device/ARM/ARMv8MML/Source/GCC/gcc_arm.ld"                 version="1.0.0" attr="config" condition="GCC"/>
2899         <file category="sourceC"      name="Device/ARM/ARMv8MML/Source/system_ARMv8MML.c"              version="1.0.0" attr="config" condition="ARMCC GCC"/>
2900         <!-- SAU configuration -->
2901         <file category="header"       name="Device/ARM/ARMv8MML/Include/Template/partition_ARMv8MML.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2902       </files>
2903     </component>
2904     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.1.0" condition="ARMv8MML CMSIS GCC">
2905       <description>System and Startup for Generic Armv8-M Mainline device</description>
2906       <files>
2907         <!-- include folder / device header file -->
2908         <file category="include"      name="Device/ARM/ARMv8MML/Include/"/>
2909         <!-- startup / system file -->
2910         <file category="sourceC"      name="Device/ARM/ARMv8MML/Source/GCC/startup_ARMv8MML.c"         version="1.0.0" attr="config" condition="GCC"/>
2911         <file category="linkerScript" name="Device/ARM/ARMv8MML/Source/GCC/gcc_arm.ld"                 version="1.0.0" attr="config" condition="GCC"/>
2912         <file category="sourceC"      name="Device/ARM/ARMv8MML/Source/system_ARMv8MML.c"              version="1.0.0" attr="config"/>
2913         <!-- SAU configuration -->
2914         <file category="header"       name="Device/ARM/ARMv8MML/Include/Template/partition_ARMv8MML.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2915       </files>
2916     </component>
2917
2918     <!-- ARMv81MML -->
2919     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.0" condition="ARMv81MML CMSIS">
2920       <description>System and Startup for Generic Armv8.1-M Mainline device</description>
2921       <files>
2922         <!-- include folder / device header file -->
2923         <file category="include"      name="Device/ARM/ARMv81MML/Include/"/>
2924         <file category="header"       name="Device/ARM/ARMv81MML/Include/ARMv81MML_DSP_DP_MVE_FP.h"/>
2925         <!-- startup / system file -->
2926         <file category="sourceAsm"    name="Device/ARM/ARMv81MML/Source/ARM/startup_ARMv81MML.s"         version="1.0.0" attr="config" condition="ARMCC"/>
2927         <file category="linkerScript" name="Device/ARM/ARMv81MML/Source/ARM/ARMv81MML.sct"               version="1.0.0" attr="config" condition="ARMCC"/>
2928         <file category="sourceAsm"    name="Device/ARM/ARMv81MML/Source/GCC/startup_ARMv81MML.S"         version="1.0.0" attr="config" condition="GCC"/>
2929         <file category="linkerScript" name="Device/ARM/ARMv81MML/Source/GCC/gcc_arm.ld"                  version="1.0.0" attr="config" condition="GCC"/>
2930         <file category="sourceAsm"    name="Device/ARM/ARMv81MML/Source/IAR/startup_ARMv81MML.s"         version="1.0.0" attr="config" condition="IAR"/>
2931         <file category="sourceC"      name="Device/ARM/ARMv81MML/Source/system_ARMv81MML.c"              version="1.0.0" attr="config"/>
2932         <!-- SAU configuration -->
2933         <file category="header"       name="Device/ARM/ARMv81MML/Include/Template/partition_ARMv81MML.h" version="1.0.0" attr="config" condition="ARMv8-M TZ Device"/>
2934       </files>
2935     </component>
2936     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.0" condition="ARMv81MML CMSIS">
2937       <description>System and Startup for Generic Armv8.1-M Mainline device</description>
2938       <files>
2939         <!-- include folder / device header file -->
2940         <file category="include"      name="Device/ARM/ARMv81MML/Include/"/>
2941         <!-- startup / system file -->
2942         <file category="sourceC"      name="Device/ARM/ARMv81MML/Source/ARM/startup_ARMv81MML.c"         version="1.0.0" attr="config" condition="ARMCC"/>
2943         <file category="linkerScript" name="Device/ARM/ARMv81MML/Source/ARM/ARMv81MML.sct"               version="1.0.0" attr="config" condition="ARMCC"/>
2944         <file category="sourceC"      name="Device/ARM/ARMv81MML/Source/GCC/startup_ARMv81MML.c"         version="1.0.0" attr="config" condition="GCC"/>
2945         <file category="linkerScript" name="Device/ARM/ARMv81MML/Source/GCC/gcc_arm.ld"                  version="1.0.0" attr="config" condition="GCC"/>
2946         <file category="sourceC"      name="Device/ARM/ARMv81MML/Source/IAR/startup_ARMv81MML.c"         version="1.0.0" attr="config" condition="IAR"/>
2947         <file category="sourceC"      name="Device/ARM/ARMv81MML/Source/system_ARMv81MML.c"              version="1.0.0" attr="config"/>
2948         <!-- SAU configuration -->
2949         <file category="header"       name="Device/ARM/ARMv81MML/Include/Template/partition_ARMv81MML.h" version="1.0.0" attr="config" condition="ARMv8-M TZ Device"/>
2950       </files>
2951     </component>
2952
2953     <!-- Cortex-A5 -->
2954     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.0" condition="ARMCA5 CMSIS">
2955       <description>System and Startup for Generic Arm Cortex-A5 device</description>
2956       <files>
2957         <!-- include folder / device header file -->
2958         <file category="include"      name="Device/ARM/ARMCA5/Include/"/>
2959         <!-- startup / system / mmu files -->
2960         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/AC5/startup_ARMCA5.c" version="1.0.0" attr="config" condition="ARMCC5"/>
2961         <file category="linkerScript" name="Device/ARM/ARMCA5/Source/AC5/ARMCA5.sct"       version="1.0.0" attr="config" condition="ARMCC5"/>
2962         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/AC6/startup_ARMCA5.c" version="1.0.0" attr="config" condition="ARMCC6"/>
2963         <file category="linkerScript" name="Device/ARM/ARMCA5/Source/AC6/ARMCA5.sct"       version="1.0.0" attr="config" condition="ARMCC6"/>
2964         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/GCC/startup_ARMCA5.c" version="1.0.0" attr="config" condition="GCC"/>
2965         <file category="other"        name="Device/ARM/ARMCA5/Source/GCC/ARMCA5.ld"        version="1.0.0" attr="config" condition="GCC"/>
2966         <file category="sourceAsm"    name="Device/ARM/ARMCA5/Source/IAR/startup_ARMCA5.s" version="1.0.0" attr="config" condition="IAR"/>
2967         <file category="linkerScript" name="Device/ARM/ARMCA5/Source/IAR/ARMCA5.icf"       version="1.0.0" attr="config" condition="IAR"/>
2968         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/system_ARMCA5.c"      version="1.0.0" attr="config"/>
2969         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/mmu_ARMCA5.c"         version="1.0.0" attr="config"/>
2970         <file category="header"       name="Device/ARM/ARMCA5/Include/system_ARMCA5.h"     version="1.0.0" attr="config"/>
2971         <file category="header"       name="Device/ARM/ARMCA5/Include/mem_ARMCA5.h"        version="1.0.0" attr="config"/>
2972
2973       </files>
2974     </component>
2975
2976     <!-- Cortex-A7 -->
2977     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.0" condition="ARMCA7 CMSIS">
2978       <description>System and Startup for Generic Arm Cortex-A7 device</description>
2979       <files>
2980         <!-- include folder / device header file -->
2981         <file category="include"      name="Device/ARM/ARMCA7/Include/"/>
2982         <!-- startup / system / mmu files -->
2983         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/AC5/startup_ARMCA7.c" version="1.0.0" attr="config" condition="ARMCC5"/>
2984         <file category="linkerScript" name="Device/ARM/ARMCA7/Source/AC5/ARMCA7.sct"       version="1.0.0" attr="config" condition="ARMCC5"/>
2985         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/AC6/startup_ARMCA7.c" version="1.0.0" attr="config" condition="ARMCC6"/>
2986         <file category="linkerScript" name="Device/ARM/ARMCA7/Source/AC6/ARMCA7.sct"       version="1.0.0" attr="config" condition="ARMCC6"/>
2987         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/GCC/startup_ARMCA7.c" version="1.0.0" attr="config" condition="GCC"/>
2988         <file category="other"        name="Device/ARM/ARMCA7/Source/GCC/ARMCA7.ld"        version="1.0.0" attr="config" condition="GCC"/>
2989         <file category="sourceAsm"    name="Device/ARM/ARMCA7/Source/IAR/startup_ARMCA7.s" version="1.0.0" attr="config" condition="IAR"/>
2990         <file category="linkerScript" name="Device/ARM/ARMCA7/Source/IAR/ARMCA7.icf"       version="1.0.0" attr="config" condition="IAR"/>
2991         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/system_ARMCA7.c"      version="1.0.0" attr="config"/>
2992         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/mmu_ARMCA7.c"         version="1.0.0" attr="config"/>
2993         <file category="header"       name="Device/ARM/ARMCA7/Include/system_ARMCA7.h"     version="1.0.0" attr="config"/>
2994         <file category="header"       name="Device/ARM/ARMCA7/Include/mem_ARMCA7.h"        version="1.0.0" attr="config"/>
2995       </files>
2996     </component>
2997
2998     <!-- Cortex-A9 -->
2999     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCA9 CMSIS">
3000       <description>System and Startup for Generic Arm Cortex-A9 device</description>
3001       <files>
3002         <!-- include folder / device header file -->
3003         <file category="include"  name="Device/ARM/ARMCA9/Include/"/>
3004         <!-- startup / system / mmu files -->
3005         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/AC5/startup_ARMCA9.c" version="1.0.0" attr="config" condition="ARMCC5"/>
3006         <file category="linkerScript" name="Device/ARM/ARMCA9/Source/AC5/ARMCA9.sct"       version="1.0.0" attr="config" condition="ARMCC5"/>
3007         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/AC6/startup_ARMCA9.c" version="1.0.0" attr="config" condition="ARMCC6"/>
3008         <file category="linkerScript" name="Device/ARM/ARMCA9/Source/AC6/ARMCA9.sct"       version="1.0.0" attr="config" condition="ARMCC6"/>
3009         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/GCC/startup_ARMCA9.c" version="1.0.0" attr="config" condition="GCC"/>
3010         <file category="other"        name="Device/ARM/ARMCA9/Source/GCC/ARMCA9.ld"        version="1.0.0" attr="config" condition="GCC"/>
3011         <file category="sourceAsm"    name="Device/ARM/ARMCA9/Source/IAR/startup_ARMCA9.s" version="1.0.0" attr="config" condition="IAR"/>
3012         <file category="linkerScript" name="Device/ARM/ARMCA9/Source/IAR/ARMCA9.icf"       version="1.0.0" attr="config" condition="IAR"/>
3013         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/system_ARMCA9.c"      version="1.0.0" attr="config"/>
3014         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/mmu_ARMCA9.c"         version="1.0.0" attr="config"/>
3015         <file category="header"       name="Device/ARM/ARMCA9/Include/system_ARMCA9.h"     version="1.0.0" attr="config"/>
3016         <file category="header"       name="Device/ARM/ARMCA9/Include/mem_ARMCA9.h"        version="1.0.0" attr="config"/>
3017       </files>
3018     </component>
3019
3020     <!-- IRQ Controller -->
3021     <component Cclass="Device" Cgroup="IRQ Controller" Csub="GIC" Capiversion="1.0.0" Cversion="1.0.1" condition="ARMv7-A Device">
3022       <description>IRQ Controller implementation using GIC</description>
3023       <files>
3024         <file category="sourceC" name="CMSIS/Core_A/Source/irq_ctrl_gic.c"/>
3025       </files>
3026     </component>
3027
3028     <!-- OS Tick -->
3029     <component Cclass="Device" Cgroup="OS Tick" Csub="Private Timer" Capiversion="1.0.1" Cversion="1.0.2" condition="OS Tick PTIM">
3030       <description>OS Tick implementation using Private Timer</description>
3031       <files>
3032         <file category="sourceC" name="CMSIS/RTOS2/Source/os_tick_ptim.c"/>
3033       </files>
3034     </component>
3035
3036     <component Cclass="Device" Cgroup="OS Tick" Csub="Generic Physical Timer" Capiversion="1.0.1" Cversion="1.0.1" condition="OS Tick GTIM">
3037       <description>OS Tick implementation using Generic Physical Timer</description>
3038       <files>
3039         <file category="sourceC" name="CMSIS/RTOS2/Source/os_tick_gtim.c"/>
3040       </files>
3041     </component>
3042
3043     <!-- CMSIS-DSP component -->
3044     <component Cclass="CMSIS" Cgroup="DSP" Cversion="1.5.2" condition="CMSIS DSP">
3045       <description>CMSIS-DSP Library for Cortex-M, SC000, and SC300</description>
3046       <files>
3047         <!-- CPU independent -->
3048         <file category="doc" name="CMSIS/Documentation/DSP/html/index.html"/>
3049         <file category="header" name="CMSIS/DSP/Include/arm_math.h"/>
3050
3051         <!-- CPU and Compiler dependent -->
3052         <!-- ARMCC -->
3053         <file category="library" condition="CM0_LE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM0l_math.lib"      src="CMSIS/DSP/Source/ARM"/>
3054         <file category="library" condition="CM0_BE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM0b_math.lib"      src="CMSIS/DSP/Source/ARM"/>
3055         <file category="library" condition="CM1_LE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM0l_math.lib"      src="CMSIS/DSP/Source/ARM"/>
3056         <file category="library" condition="CM1_BE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM0b_math.lib"      src="CMSIS/DSP/Source/ARM"/>
3057         <file category="library" condition="CM3_LE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM3l_math.lib"      src="CMSIS/DSP/Source/ARM"/>
3058         <file category="library" condition="CM3_BE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM3b_math.lib"      src="CMSIS/DSP/Source/ARM"/>
3059         <file category="library" condition="CM4_LE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM4l_math.lib"      src="CMSIS/DSP/Source/ARM"/>
3060         <file category="library" condition="CM4_BE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM4b_math.lib"      src="CMSIS/DSP/Source/ARM"/>
3061         <file category="library" condition="CM4_FP_LE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM4lf_math.lib"     src="CMSIS/DSP/Source/ARM"/>
3062         <file category="library" condition="CM4_FP_BE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM4bf_math.lib"     src="CMSIS/DSP/Source/ARM"/>
3063         <file category="library" condition="CM7_LE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM7l_math.lib"      src="CMSIS/DSP/Source/ARM"/>
3064         <file category="library" condition="CM7_BE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM7b_math.lib"      src="CMSIS/DSP/Source/ARM"/>
3065         <file category="library" condition="CM7_SP_LE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM7lfsp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
3066         <file category="library" condition="CM7_SP_BE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM7bfsp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
3067         <file category="library" condition="CM7_DP_LE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM7lfdp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
3068         <file category="library" condition="CM7_DP_BE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM7bfdp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
3069
3070         <file category="library" condition="CM23_LE_ARMCC"                  name="CMSIS/Lib/ARM/arm_ARMv8MBLl_math.lib"      src="CMSIS/DSP/Source/ARM"/>
3071         <file category="library" condition="CM33_NODSP_NOFPU_LE_ARMCC"      name="CMSIS/Lib/ARM/arm_ARMv8MMLl_math.lib"      src="CMSIS/DSP/Source/ARM"/>
3072         <file category="library" condition="CM33_DSP_NOFPU_LE_ARMCC"        name="CMSIS/Lib/ARM/arm_ARMv8MMLld_math.lib"     src="CMSIS/DSP/Source/ARM"/>
3073         <file category="library" condition="CM33_NODSP_SP_LE_ARMCC"         name="CMSIS/Lib/ARM/arm_ARMv8MMLlfsp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
3074         <file category="library" condition="CM33_DSP_SP_LE_ARMCC"           name="CMSIS/Lib/ARM/arm_ARMv8MMLldfsp_math.lib"  src="CMSIS/DSP/Source/ARM"/>
3075         <file category="library" condition="CM35P_NODSP_NOFPU_LE_ARMCC"     name="CMSIS/Lib/ARM/arm_ARMv8MMLl_math.lib"      src="CMSIS/DSP/Source/ARM"/>
3076         <file category="library" condition="CM35P_DSP_NOFPU_LE_ARMCC"       name="CMSIS/Lib/ARM/arm_ARMv8MMLld_math.lib"     src="CMSIS/DSP/Source/ARM"/>
3077         <file category="library" condition="CM35P_NODSP_SP_LE_ARMCC"        name="CMSIS/Lib/ARM/arm_ARMv8MMLlfsp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
3078         <file category="library" condition="CM35P_DSP_SP_LE_ARMCC"          name="CMSIS/Lib/ARM/arm_ARMv8MMLldfsp_math.lib"  src="CMSIS/DSP/Source/ARM"/>
3079         <file category="library" condition="ARMv8MBL_LE_ARMCC"              name="CMSIS/Lib/ARM/arm_ARMv8MBLl_math.lib"      src="CMSIS/DSP/Source/ARM"/>
3080         <file category="library" condition="ARMv8MML_NODSP_NOFPU_LE_ARMCC"  name="CMSIS/Lib/ARM/arm_ARMv8MMLl_math.lib"      src="CMSIS/DSP/Source/ARM"/>
3081         <file category="library" condition="ARMv8MML_DSP_NOFPU_LE_ARMCC"    name="CMSIS/Lib/ARM/arm_ARMv8MMLld_math.lib"     src="CMSIS/DSP/Source/ARM"/>
3082         <file category="library" condition="ARMv8MML_NODSP_SP_LE_ARMCC"     name="CMSIS/Lib/ARM/arm_ARMv8MMLlfsp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
3083         <file category="library" condition="ARMv8MML_DSP_SP_LE_ARMCC"       name="CMSIS/Lib/ARM/arm_ARMv8MMLldfsp_math.lib"  src="CMSIS/DSP/Source/ARM"/>
3084         <!--file category="library" condition="ARMv8MML_DP_NOFPU_LE_ARMCC"     name="CMSIS/Lib/ARM/arm_ARMv8MMLlfdp_math.lib"   src="CMSIS/DSP/Source/ARM"/-->
3085         <!--file category="library" condition="ARMv8MML_DSP_DP_LE_ARMCC"       name="CMSIS/Lib/ARM/arm_ARMv8MMLldfdp_math.lib"  src="CMSIS/DSP/Source/ARM"/-->
3086
3087         <!-- GCC -->
3088         <file category="library" condition="CM0_LE_GCC"               name="CMSIS/Lib/GCC/libarm_cortexM0l_math.a"     src="CMSIS/DSP/Source/GCC"/>
3089         <file category="library" condition="CM1_LE_GCC"               name="CMSIS/Lib/GCC/libarm_cortexM0l_math.a"     src="CMSIS/DSP/Source/GCC"/>
3090         <file category="library" condition="CM3_LE_GCC"               name="CMSIS/Lib/GCC/libarm_cortexM3l_math.a"     src="CMSIS/DSP/Source/GCC"/>
3091         <file category="library" condition="CM4_LE_GCC"               name="CMSIS/Lib/GCC/libarm_cortexM4l_math.a"     src="CMSIS/DSP/Source/GCC"/>
3092         <file category="library" condition="CM4_FP_LE_GCC"            name="CMSIS/Lib/GCC/libarm_cortexM4lf_math.a"    src="CMSIS/DSP/Source/GCC"/>
3093         <file category="library" condition="CM7_LE_GCC"               name="CMSIS/Lib/GCC/libarm_cortexM7l_math.a"     src="CMSIS/DSP/Source/GCC"/>
3094         <file category="library" condition="CM7_SP_LE_GCC"            name="CMSIS/Lib/GCC/libarm_cortexM7lfsp_math.a"  src="CMSIS/DSP/Source/GCC"/>
3095         <file category="library" condition="CM7_DP_LE_GCC"            name="CMSIS/Lib/GCC/libarm_cortexM7lfdp_math.a"  src="CMSIS/DSP/Source/GCC"/>
3096
3097         <file category="library" condition="CM23_LE_GCC"                    name="CMSIS/Lib/GCC/libarm_ARMv8MBLl_math.a"     src="CMSIS/DSP/Source/GCC"/>
3098         <file category="library" condition="CM33_NODSP_NOFPU_LE_GCC"        name="CMSIS/Lib/GCC/libarm_ARMv8MMLl_math.a"     src="CMSIS/DSP/Source/GCC"/>
3099         <file category="library" condition="CM33_DSP_NOFPU_LE_GCC"          name="CMSIS/Lib/GCC/libarm_ARMv8MMLld_math.a"    src="CMSIS/DSP/Source/GCC"/>
3100         <file category="library" condition="CM33_NODSP_SP_LE_GCC"           name="CMSIS/Lib/GCC/libarm_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP/Source/GCC"/>
3101         <file category="library" condition="CM33_DSP_SP_LE_GCC"             name="CMSIS/Lib/GCC/libarm_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
3102         <file category="library" condition="CM35P_NODSP_NOFPU_LE_GCC"       name="CMSIS/Lib/GCC/libarm_ARMv8MMLl_math.a"     src="CMSIS/DSP/Source/GCC"/>
3103         <file category="library" condition="CM35P_DSP_NOFPU_LE_GCC"         name="CMSIS/Lib/GCC/libarm_ARMv8MMLld_math.a"    src="CMSIS/DSP/Source/GCC"/>
3104         <file category="library" condition="CM35P_NODSP_SP_LE_GCC"          name="CMSIS/Lib/GCC/libarm_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP/Source/GCC"/>
3105         <file category="library" condition="CM35P_DSP_SP_LE_GCC"            name="CMSIS/Lib/GCC/libarm_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
3106         <file category="library" condition="ARMv8MBL_LE_GCC"                name="CMSIS/Lib/GCC/libarm_ARMv8MBLl_math.a"     src="CMSIS/DSP/Source/GCC"/>
3107         <file category="library" condition="ARMv8MML_NODSP_NOFPU_LE_GCC"    name="CMSIS/Lib/GCC/libarm_ARMv8MMLl_math.a"     src="CMSIS/DSP/Source/GCC"/>
3108         <file category="library" condition="ARMv8MML_DSP_NOFPU_LE_GCC"      name="CMSIS/Lib/GCC/libarm_ARMv8MMLld_math.a"    src="CMSIS/DSP/Source/GCC"/>
3109         <file category="library" condition="ARMv8MML_NODSP_SP_LE_GCC"       name="CMSIS/Lib/GCC/libarm_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP/Source/GCC"/>
3110         <file category="library" condition="ARMv8MML_DSP_SP_LE_GCC"         name="CMSIS/Lib/GCC/libarm_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
3111         <!--file category="library" condition="ARMv8MML_DP_NOFPU_LE_GCC"       name="CMSIS/Lib/GCC/libarm_ARMv8MMLlfdp_math.a"  src="CMSIS/DSP/Source/GCC"/-->
3112         <!--file category="library" condition="ARMv8MML_DSP_DP_LE_GCC"         name="CMSIS/Lib/GCC/libarm_ARMv8MMLldfdp_math.a" src="CMSIS/DSP/Source/GCC"/-->
3113
3114         <!-- IAR -->
3115         <file category="library" condition="CM0_LE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM0l_math.a"     src="CMSIS/DSP/Source/IAR"/>
3116         <file category="library" condition="CM0_BE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM0b_math.a"     src="CMSIS/DSP/Source/IAR"/>
3117         <file category="library" condition="CM1_LE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM0l_math.a"     src="CMSIS/DSP/Source/IAR"/>
3118         <file category="library" condition="CM1_BE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM0b_math.a"     src="CMSIS/DSP/Source/IAR"/>
3119         <file category="library" condition="CM3_LE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM3l_math.a"     src="CMSIS/DSP/Source/IAR"/>
3120         <file category="library" condition="CM3_BE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM3b_math.a"     src="CMSIS/DSP/Source/IAR"/>
3121         <file category="library" condition="CM4_LE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM4l_math.a"     src="CMSIS/DSP/Source/IAR"/>
3122         <file category="library" condition="CM4_BE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM4b_math.a"     src="CMSIS/DSP/Source/IAR"/>
3123         <file category="library" condition="CM4_FP_LE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM4lf_math.a"    src="CMSIS/DSP/Source/IAR"/>
3124         <file category="library" condition="CM4_FP_BE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM4bf_math.a"    src="CMSIS/DSP/Source/IAR"/>
3125         <file category="library" condition="CM7_LE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM7l_math.a"     src="CMSIS/DSP/Source/IAR"/>
3126         <file category="library" condition="CM7_BE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM7b_math.a"     src="CMSIS/DSP/Source/IAR"/>
3127         <file category="library" condition="CM7_DP_LE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM7lf_math.a"    src="CMSIS/DSP/Source/IAR"/>
3128         <file category="library" condition="CM7_DP_BE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM7bf_math.a"    src="CMSIS/DSP/Source/IAR"/>
3129         <file category="library" condition="CM7_SP_LE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM7ls_math.a"    src="CMSIS/DSP/Source/IAR"/>
3130         <file category="library" condition="CM7_SP_BE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM7bs_math.a"    src="CMSIS/DSP/Source/IAR"/>
3131
3132         <file category="library" condition="CM23_LE_IAR"              name="CMSIS/Lib/IAR/iar_ARMv8MBLl_math.a"     src="CMSIS/DSP/Source/IAR"/>
3133         <file category="library" condition="CM33_NODSP_NOFPU_LE_IAR"        name="CMSIS/Lib/IAR/iar_ARMv8MMLl_math.a"     src="CMSIS/DSP/Source/IAR"/>
3134         <file category="library" condition="CM33_DSP_NOFPU_LE_IAR"    name="CMSIS/Lib/IAR/iar_ARMv8MMLld_math.a"    src="CMSIS/DSP/Source/IAR"/>
3135         <file category="library" condition="CM33_NODSP_SP_LE_IAR"           name="CMSIS/Lib/IAR/iar_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP/Source/IAR"/>
3136         <file category="library" condition="CM33_DSP_SP_LE_IAR"       name="CMSIS/Lib/IAR/iar_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
3137         <file category="library" condition="CM35P_NODSP_NOFPU_LE_IAR"       name="CMSIS/Lib/IAR/iar_ARMv8MMLl_math.a"     src="CMSIS/DSP/Source/IAR"/>
3138         <file category="library" condition="CM35P_DSP_NOFPU_LE_IAR"         name="CMSIS/Lib/IAR/iar_ARMv8MMLld_math.a"    src="CMSIS/DSP/Source/IAR"/>
3139         <file category="library" condition="CM35P_NODSP_SP_LE_IAR"          name="CMSIS/Lib/IAR/iar_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP/Source/IAR"/>
3140         <file category="library" condition="CM35P_DSP_SP_LE_IAR"            name="CMSIS/Lib/IAR/iar_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
3141         <file category="library" condition="ARMv8MBL_LE_IAR"          name="CMSIS/Lib/IAR/iar_ARMv8MBLl_math.a"     src="CMSIS/DSP/Source/IAR"/>
3142         <file category="library" condition="ARMv8MML_NODSP_NOFPU_LE_IAR"    name="CMSIS/Lib/IAR/iar_ARMv8MMLl_math.a"     src="CMSIS/DSP/Source/IAR"/>
3143         <file category="library" condition="ARMv8MML_DSP_NOFPU_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLld_math.a"    src="CMSIS/DSP/Source/IAR"/>
3144         <file category="library" condition="ARMv8MML_NODSP_SP_LE_IAR"       name="CMSIS/Lib/IAR/iar_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP/Source/IAR"/>
3145         <file category="library" condition="ARMv8MML_DSP_SP_LE_IAR"   name="CMSIS/Lib/IAR/iar_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
3146      <!--file category="library" condition="ARMv8MML_DP_NOFPU_LE_IAR"       name="CMSIS/Lib/IAR/iar_ARMv8MMLlfdp_math.a"  src="CMSIS/DSP/Source/IAR"/-->
3147         <!--file category="library" condition="ARMv8MML_DSP_DP_LE_IAR"   name="CMSIS/Lib/IAR/iar_ARMv8MMLldfdp_math.a" src="CMSIS/DSP/Source/IAR"/-->
3148
3149       </files>
3150     </component>
3151
3152     <!-- CMSIS-NN component -->
3153     <component Cclass="CMSIS" Cgroup="NN Lib" Cversion="1.1.0" condition="CMSIS NN">
3154       <description>CMSIS-NN Neural Network Library</description>
3155       <files>
3156         <file category="doc" name="CMSIS/Documentation/NN/html/index.html"/>
3157         <file category="header" name="CMSIS/NN/Include/arm_nnfunctions.h"/>
3158
3159         <file category="source" name="CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c"/>
3160         <file category="source" name="CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c"/>
3161         <file category="source" name="CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c"/>
3162         <file category="source" name="CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c"/>
3163
3164         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c"/>
3165         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c"/>
3166         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c"/>
3167         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c"/>
3168         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c"/>
3169         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c"/>
3170         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c"/>
3171         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c"/>
3172         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c"/>
3173         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c"/>
3174         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c"/>
3175         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c"/>
3176
3177         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c"/>
3178         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c"/>
3179         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c"/>
3180         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c"/>
3181         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c"/>
3182         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c"/>
3183
3184         <file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c"/>
3185         <file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c"/>
3186         <file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c"/>
3187         <file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.c"/>
3188         <file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.c"/>
3189
3190         <file category="source" name="CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c"/>
3191
3192         <file category="source" name="CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.c"/>
3193         <file category="source" name="CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.c"/>
3194       </files>
3195     </component>
3196
3197     <!-- CMSIS-RTOS Keil RTX component -->
3198     <component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX" Cversion="4.81.1" Capiversion="1.0.0" isDefaultVariant="1" condition="RTOS RTX">
3199       <description>CMSIS-RTOS RTX implementation for Cortex-M, SC000, and SC300</description>
3200       <RTE_Components_h>
3201         <!-- the following content goes into file 'RTE_Components.h' -->
3202         #define RTE_CMSIS_RTOS                  /* CMSIS-RTOS */
3203         #define RTE_CMSIS_RTOS_RTX              /* CMSIS-RTOS Keil RTX */
3204       </RTE_Components_h>
3205       <files>
3206         <!-- CPU independent -->
3207         <file category="doc" name="CMSIS/Documentation/RTOS/html/rtxImplementation.html"/>
3208         <file category="header" name="CMSIS/RTOS/RTX/INC/cmsis_os.h"/>
3209         <file category="source" attr="config"   name="CMSIS/RTOS/RTX/Templates/RTX_Conf_CM.c" version="4.70.1"/>
3210
3211         <!-- RTX templates -->
3212         <file category="header" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/osObjects.h" select="CMSIS-RTOS 'main' function"/>
3213         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/main.c"      select="CMSIS-RTOS 'main' function"/>
3214         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MailQueue.c" select="CMSIS-RTOS Mail Queue"/>
3215         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MemPool.c"   select="CMSIS-RTOS Memory Pool"/>
3216         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MsgQueue.c"  select="CMSIS-RTOS Message Queue"/>
3217         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Mutex.c"     select="CMSIS-RTOS Mutex"/>
3218         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Semaphore.c" select="CMSIS-RTOS Semaphore"/>
3219         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Thread.c"    select="CMSIS-RTOS Thread"/>
3220         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Timer.c"     select="CMSIS-RTOS Timer"/>
3221         <!-- tool-chain specific template file -->
3222         <file category="source" attr="template" condition="ARMCC" name="CMSIS/RTOS/RTX/SRC/ARM/SVC_Table.s" select="CMSIS-RTOS User SVC"/>
3223         <file category="source" attr="template" condition="GCC"   name="CMSIS/RTOS/RTX/SRC/GCC/SVC_Table.S" select="CMSIS-RTOS User SVC"/>
3224         <file category="source" attr="template" condition="IAR"   name="CMSIS/RTOS/RTX/SRC/IAR/SVC_Table.s" select="CMSIS-RTOS User SVC"/>
3225
3226         <!-- CPU and Compiler dependent -->
3227         <!-- ARMCC -->
3228         <file category="library" condition="CM0_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
3229         <file category="library" condition="CM0_BE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3230         <file category="library" condition="CM1_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
3231         <file category="library" condition="CM1_BE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3232         <file category="library" condition="CM3_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
3233         <file category="library" condition="CM3_BE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3234         <file category="library" condition="CM4_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
3235         <file category="library" condition="CM4_BE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3236         <file category="library" condition="CM4_FP_LE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
3237         <file category="library" condition="CM4_FP_BE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3238         <file category="library" condition="CM7_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
3239         <file category="library" condition="CM7_BE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3240         <file category="library" condition="CM7_FP_LE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
3241         <file category="library" condition="CM7_FP_BE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3242         <!-- GCC -->
3243         <file category="library" condition="CM0_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
3244         <file category="library" condition="CM0_BE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3245         <file category="library" condition="CM1_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
3246         <file category="library" condition="CM1_BE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3247         <file category="library" condition="CM3_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
3248         <file category="library" condition="CM3_BE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3249         <file category="library" condition="CM4_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
3250         <file category="library" condition="CM4_BE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3251         <file category="library" condition="CM4_FP_LE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
3252         <file category="library" condition="CM4_FP_BE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3253         <file category="library" condition="CM7_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
3254         <file category="library" condition="CM7_BE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3255         <file category="library" condition="CM7_FP_LE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
3256         <file category="library" condition="CM7_FP_BE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3257         <!-- IAR -->
3258         <file category="library" condition="CM0_LE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
3259         <file category="library" condition="CM0_BE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
3260         <file category="library" condition="CM1_LE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
3261         <file category="library" condition="CM1_BE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
3262         <file category="library" condition="CM3_LE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
3263         <file category="library" condition="CM3_BE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
3264         <file category="library" condition="CM4_LE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
3265         <file category="library" condition="CM4_BE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
3266         <file category="library" condition="CM4_FP_LE_IAR"   name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
3267         <file category="library" condition="CM4_FP_BE_IAR"   name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
3268         <file category="library" condition="CM7_LE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
3269         <file category="library" condition="CM7_BE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
3270         <file category="library" condition="CM7_FP_LE_IAR"   name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
3271         <file category="library" condition="CM7_FP_BE_IAR"   name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
3272       </files>
3273     </component>
3274     <!-- CMSIS-RTOS Keil RTX component (IFX variant) -->
3275     <component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX" Cvariant="IFX" Cversion="4.81.1" Capiversion="1.0.0" condition="RTOS RTX IFX">
3276       <description>CMSIS-RTOS RTX implementation for Infineon XMC4 series affected by PMU_CM.001 errata</description>
3277       <RTE_Components_h>
3278         <!-- the following content goes into file 'RTE_Components.h' -->
3279         #define RTE_CMSIS_RTOS                  /* CMSIS-RTOS */
3280         #define RTE_CMSIS_RTOS_RTX              /* CMSIS-RTOS Keil RTX */
3281       </RTE_Components_h>
3282       <files>
3283         <!-- CPU independent -->
3284         <file category="doc" name="CMSIS/Documentation/RTOS/html/rtxImplementation.html"/>
3285         <file category="header" name="CMSIS/RTOS/RTX/INC/cmsis_os.h"/>
3286         <file category="source" attr="config"   name="CMSIS/RTOS/RTX/Templates/RTX_Conf_CM.c" version="4.70.1"/>
3287
3288         <!-- RTX templates -->
3289         <file category="header" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/osObjects.h" select="CMSIS-RTOS 'main' function"/>
3290         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/main.c"      select="CMSIS-RTOS 'main' function"/>
3291         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MailQueue.c" select="CMSIS-RTOS Mail Queue"/>
3292         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MemPool.c"   select="CMSIS-RTOS Memory Pool"/>
3293         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MsgQueue.c"  select="CMSIS-RTOS Message Queue"/>
3294         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Mutex.c"     select="CMSIS-RTOS Mutex"/>
3295         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Semaphore.c" select="CMSIS-RTOS Semaphore"/>
3296         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Thread.c"    select="CMSIS-RTOS Thread"/>
3297         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Timer.c"     select="CMSIS-RTOS Timer"/>
3298         <!-- tool-chain specific template file -->
3299         <file category="source" attr="template" condition="ARMCC" name="CMSIS/RTOS/RTX/SRC/ARM/SVC_Table.s" select="CMSIS-RTOS User SVC"/>
3300         <file category="source" attr="template" condition="GCC"   name="CMSIS/RTOS/RTX/SRC/GCC/SVC_Table.S" select="CMSIS-RTOS User SVC"/>
3301         <file category="source" attr="template" condition="IAR"   name="CMSIS/RTOS/RTX/SRC/IAR/SVC_Table.s" select="CMSIS-RTOS User SVC"/>
3302
3303         <!-- CPU and Compiler dependent -->
3304         <!-- ARMCC -->
3305         <file category="library" condition="CM4_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_IFX.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3306         <file category="library" condition="CM4_FP_LE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_IFX.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3307         <!-- GCC -->
3308         <file category="library" condition="CM4_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_IFX.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3309         <file category="library" condition="CM4_FP_LE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_IFX.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3310         <!-- IAR -->
3311       </files>
3312     </component>
3313
3314     <!-- CMSIS-RTOS Keil RTX5 component -->
3315     <component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX5" Cversion="5.5.0" Capiversion="1.0.0" condition="RTOS RTX5">
3316       <description>CMSIS-RTOS RTX5 implementation for Cortex-M, SC000, and SC300</description>
3317       <RTE_Components_h>
3318         <!-- the following content goes into file 'RTE_Components.h' -->
3319         #define RTE_CMSIS_RTOS                  /* CMSIS-RTOS */
3320         #define RTE_CMSIS_RTOS_RTX5             /* CMSIS-RTOS Keil RTX5 */
3321       </RTE_Components_h>
3322       <files>
3323         <!-- RTX header file -->
3324         <file category="header" name="CMSIS/RTOS2/RTX/Include1/cmsis_os.h"/>
3325         <!-- RTX compatibility module for API V1 -->
3326         <file category="source" name="CMSIS/RTOS2/RTX/Library/cmsis_os1.c"/>
3327       </files>
3328     </component>
3329
3330     <!-- CMSIS-RTOS2 Keil RTX5 component -->
3331     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cversion="5.5.0" Capiversion="2.1.3" condition="RTOS2 RTX5 Lib">
3332       <description>CMSIS-RTOS2 RTX5 for Cortex-M, SC000, C300 and Armv8-M (Library)</description>
3333       <RTE_Components_h>
3334         <!-- the following content goes into file 'RTE_Components.h' -->
3335         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
3336         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
3337       </RTE_Components_h>
3338       <files>
3339         <!-- RTX documentation -->
3340         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
3341
3342         <!-- RTX header files -->
3343         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
3344
3345         <!-- RTX configuration -->
3346         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.5.0"/>
3347         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
3348
3349         <!-- RTX templates -->
3350         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.1.0" select="CMSIS-RTOS2 'main' function"/>
3351         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
3352         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
3353         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
3354         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
3355         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
3356         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
3357         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
3358         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
3359         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
3360
3361         <!-- RTX library configuration -->
3362         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
3363
3364         <!-- RTX libraries (CPU and Compiler dependent) -->
3365         <!-- ARMCC -->
3366         <file category="library" condition="CM0_LE_ARMCC"         name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM0.lib"    src="CMSIS/RTOS2/RTX/Source"/>
3367         <file category="library" condition="CM1_LE_ARMCC"         name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM0.lib"    src="CMSIS/RTOS2/RTX/Source"/>
3368         <file category="library" condition="CM3_LE_ARMCC"         name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM3.lib"    src="CMSIS/RTOS2/RTX/Source"/>
3369         <file category="library" condition="CM4_LE_ARMCC"         name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM3.lib"    src="CMSIS/RTOS2/RTX/Source"/>
3370         <file category="library" condition="CM4_FP_LE_ARMCC"      name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM4F.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3371         <file category="library" condition="CM7_LE_ARMCC"         name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM3.lib"    src="CMSIS/RTOS2/RTX/Source"/>
3372         <file category="library" condition="CM7_FP_LE_ARMCC"      name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM4F.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3373         <file category="library" condition="CM23_LE_ARMCC"        name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MB.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3374         <file category="library" condition="CM33_LE_ARMCC"        name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3375         <file category="library" condition="CM33_FP_LE_ARMCC"     name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib"  src="CMSIS/RTOS2/RTX/Source"/>
3376         <file category="library" condition="CM35P_LE_ARMCC"       name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3377         <file category="library" condition="CM35P_FP_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib"  src="CMSIS/RTOS2/RTX/Source"/>
3378         <file category="library" condition="ARMv8MBL_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MB.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3379         <file category="library" condition="ARMv8MML_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3380         <file category="library" condition="ARMv8MML_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib"  src="CMSIS/RTOS2/RTX/Source"/>
3381         <!-- GCC -->
3382         <file category="library" condition="CM0_LE_GCC"           name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM0.a"   src="CMSIS/RTOS2/RTX/Source"/>
3383         <file category="library" condition="CM1_LE_GCC"           name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM0.a"   src="CMSIS/RTOS2/RTX/Source"/>
3384         <file category="library" condition="CM3_LE_GCC"           name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a"   src="CMSIS/RTOS2/RTX/Source"/>
3385         <file category="library" condition="CM4_LE_GCC"           name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a"   src="CMSIS/RTOS2/RTX/Source"/>
3386         <file category="library" condition="CM4_FP_LE_GCC"        name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM4F.a"  src="CMSIS/RTOS2/RTX/Source"/>
3387         <file category="library" condition="CM7_LE_GCC"           name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a"   src="CMSIS/RTOS2/RTX/Source"/>
3388         <file category="library" condition="CM7_FP_LE_GCC"        name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM4F.a"  src="CMSIS/RTOS2/RTX/Source"/>
3389         <file category="library" condition="CM23_LE_GCC"          name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MB.a"  src="CMSIS/RTOS2/RTX/Source"/>
3390         <file category="library" condition="CM33_LE_GCC"          name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a"  src="CMSIS/RTOS2/RTX/Source"/>
3391         <file category="library" condition="CM33_FP_LE_GCC"       name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
3392         <file category="library" condition="CM35P_LE_GCC"         name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a"  src="CMSIS/RTOS2/RTX/Source"/>
3393         <file category="library" condition="CM35P_FP_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
3394         <file category="library" condition="ARMv8MBL_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MB.a"  src="CMSIS/RTOS2/RTX/Source"/>
3395         <file category="library" condition="ARMv8MML_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a"  src="CMSIS/RTOS2/RTX/Source"/>
3396         <file category="library" condition="ARMv8MML_FP_LE_GCC"   name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
3397         <!-- IAR -->
3398         <file category="library" condition="CM0_LE_IAR"           name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM0.a"      src="CMSIS/RTOS2/RTX/Source"/>
3399         <file category="library" condition="CM1_LE_IAR"           name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM0.a"      src="CMSIS/RTOS2/RTX/Source"/>
3400         <file category="library" condition="CM3_LE_IAR"           name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM3.a"      src="CMSIS/RTOS2/RTX/Source"/>
3401         <file category="library" condition="CM4_LE_IAR"           name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM3.a"      src="CMSIS/RTOS2/RTX/Source"/>
3402         <file category="library" condition="CM4_FP_LE_IAR"        name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM4F.a"     src="CMSIS/RTOS2/RTX/Source"/>
3403         <file category="library" condition="CM7_LE_IAR"           name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM3.a"      src="CMSIS/RTOS2/RTX/Source"/>
3404         <file category="library" condition="CM7_FP_LE_IAR"        name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM4F.a"     src="CMSIS/RTOS2/RTX/Source"/>
3405         <file category="library" condition="CM23_LE_IAR"          name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MB.a"     src="CMSIS/RTOS2/RTX/Source"/>
3406         <file category="library" condition="CM33_LE_IAR"          name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MM.a"     src="CMSIS/RTOS2/RTX/Source"/>
3407         <file category="library" condition="CM33_FP_LE_IAR"       name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMF.a"    src="CMSIS/RTOS2/RTX/Source"/>
3408         <file category="library" condition="CM35P_LE_IAR"         name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MM.a"     src="CMSIS/RTOS2/RTX/Source"/>
3409         <file category="library" condition="CM35P_FP_LE_IAR"      name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMF.a"    src="CMSIS/RTOS2/RTX/Source"/>
3410         <file category="library" condition="ARMv8MBL_LE_IAR"      name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MB.a"     src="CMSIS/RTOS2/RTX/Source"/>
3411         <file category="library" condition="ARMv8MML_LE_IAR"      name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MM.a"     src="CMSIS/RTOS2/RTX/Source"/>
3412         <file category="library" condition="ARMv8MML_FP_LE_IAR"   name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMF.a"    src="CMSIS/RTOS2/RTX/Source"/>
3413       </files>
3414     </component>
3415     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library_NS" Cversion="5.5.0" Capiversion="2.1.3" condition="RTOS2 RTX5 NS">
3416       <description>CMSIS-RTOS2 RTX5 for Armv8-M Non-Secure Domain (Library)</description>
3417       <RTE_Components_h>
3418         <!-- the following content goes into file 'RTE_Components.h' -->
3419         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
3420         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
3421         #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS  /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */
3422       </RTE_Components_h>
3423       <files>
3424         <!-- RTX documentation -->
3425         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
3426
3427         <!-- RTX header files -->
3428         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
3429
3430         <!-- RTX configuration -->
3431         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.5.0"/>
3432         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
3433
3434         <!-- RTX templates -->
3435         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.1.0" select="CMSIS-RTOS2 'main' function"/>
3436         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
3437         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
3438         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
3439         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
3440         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
3441         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
3442         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
3443         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
3444         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
3445
3446         <!-- RTX library configuration -->
3447         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
3448
3449         <!-- RTX libraries (CPU and Compiler dependent) -->
3450         <!-- ARMCC -->
3451         <file category="library" condition="CM23_LE_ARMCC"        name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MBN.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3452         <file category="library" condition="CM33_LE_ARMCC"        name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3453         <file category="library" condition="CM33_FP_LE_ARMCC"     name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib"  src="CMSIS/RTOS2/RTX/Source"/>
3454         <file category="library" condition="CM35P_LE_ARMCC"       name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3455         <file category="library" condition="CM35P_FP_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib"  src="CMSIS/RTOS2/RTX/Source"/>
3456         <file category="library" condition="ARMv8MBL_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MBN.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3457         <file category="library" condition="ARMv8MML_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3458         <file category="library" condition="ARMv8MML_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib"  src="CMSIS/RTOS2/RTX/Source"/>
3459         <!-- GCC -->
3460         <file category="library" condition="CM23_LE_GCC"          name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MBN.a"  src="CMSIS/RTOS2/RTX/Source"/>
3461         <file category="library" condition="CM33_LE_GCC"          name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a"  src="CMSIS/RTOS2/RTX/Source"/>
3462         <file category="library" condition="CM33_FP_LE_GCC"       name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
3463         <file category="library" condition="CM35P_LE_GCC"         name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a"  src="CMSIS/RTOS2/RTX/Source"/>
3464         <file category="library" condition="CM35P_FP_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
3465         <file category="library" condition="ARMv8MBL_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MBN.a"  src="CMSIS/RTOS2/RTX/Source"/>
3466         <file category="library" condition="ARMv8MML_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a"  src="CMSIS/RTOS2/RTX/Source"/>
3467         <file category="library" condition="ARMv8MML_FP_LE_GCC"   name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
3468         <!-- IAR -->
3469         <file category="library" condition="CM23_LE_IAR"          name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MBN.a"     src="CMSIS/RTOS2/RTX/Source"/>
3470         <file category="library" condition="CM33_LE_IAR"          name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMN.a"     src="CMSIS/RTOS2/RTX/Source"/>
3471         <file category="library" condition="CM33_FP_LE_IAR"       name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMFN.a"    src="CMSIS/RTOS2/RTX/Source"/>
3472         <file category="library" condition="CM35P_LE_IAR"         name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMN.a"     src="CMSIS/RTOS2/RTX/Source"/>
3473         <file category="library" condition="CM35P_FP_LE_IAR"      name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMFN.a"    src="CMSIS/RTOS2/RTX/Source"/>
3474         <file category="library" condition="ARMv8MBL_LE_IAR"      name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MBN.a"     src="CMSIS/RTOS2/RTX/Source"/>
3475         <file category="library" condition="ARMv8MML_LE_IAR"      name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMN.a"     src="CMSIS/RTOS2/RTX/Source"/>
3476         <file category="library" condition="ARMv8MML_FP_LE_IAR"   name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMFN.a"    src="CMSIS/RTOS2/RTX/Source"/>
3477       </files>
3478     </component>
3479     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cversion="5.5.0" Capiversion="2.1.3" condition="RTOS2 RTX5">
3480       <description>CMSIS-RTOS2 RTX5 for Cortex-M, SC000, C300 and Armv8-M (Source)</description>
3481       <RTE_Components_h>
3482         <!-- the following content goes into file 'RTE_Components.h' -->
3483         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
3484         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
3485         #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
3486       </RTE_Components_h>
3487       <files>
3488         <!-- RTX documentation -->
3489         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
3490
3491         <!-- RTX header files -->
3492         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
3493
3494         <!-- RTX configuration -->
3495         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.5.0"/>
3496         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
3497
3498         <!-- RTX templates -->
3499         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.1.0" select="CMSIS-RTOS2 'main' function"/>
3500         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
3501         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
3502         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
3503         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
3504         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
3505         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
3506         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
3507         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
3508         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
3509
3510         <!-- RTX sources (core) -->
3511         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_kernel.c"/>
3512         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_thread.c"/>
3513         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_delay.c"/>
3514         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_timer.c"/>
3515         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evflags.c"/>
3516         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mutex.c"/>
3517         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_semaphore.c"/>
3518         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_memory.c"/>
3519         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mempool.c"/>
3520         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c"/>
3521         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_system.c"/>
3522         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evr.c"/>
3523         <!-- RTX sources (library configuration) -->
3524         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
3525         <!-- RTX sources (handlers ARMCC) -->
3526         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm0.s"         condition="CM0_ARMCC"/>
3527         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm0.s"         condition="CM1_ARMCC"/>
3528         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm3.s"         condition="CM3_ARMCC"/>
3529         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm3.s"         condition="CM4_ARMCC"/>
3530         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm4f.s"        condition="CM4_FP_ARMCC"/>
3531         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm3.s"         condition="CM7_ARMCC"/>
3532         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm4f.s"        condition="CM7_FP_ARMCC"/>
3533         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl.s"    condition="CM23_ARMCC"/>
3534         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="CM33_ARMCC"/>
3535         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="CM33_FP_ARMCC"/>
3536         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="CM35P_ARMCC"/>
3537         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="CM35P_FP_ARMCC"/>
3538         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl.s"    condition="ARMv8MBL_ARMCC"/>
3539         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="ARMv8MML_ARMCC"/>
3540         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="ARMv8MML_FP_ARMCC"/>
3541         <!-- RTX sources (handlers GCC) -->
3542         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm0.S"         condition="CM0_GCC"/>
3543         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm0.S"         condition="CM1_GCC"/>
3544         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm3.S"         condition="CM3_GCC"/>
3545         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm3.S"         condition="CM4_GCC"/>
3546         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm4f.S"        condition="CM4_FP_GCC"/>
3547         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm3.S"         condition="CM7_GCC"/>
3548         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm4f.S"        condition="CM7_FP_GCC"/>
3549         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S"    condition="CM23_GCC"/>
3550         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S"    condition="CM33_GCC"/>
3551         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp.S" condition="CM33_FP_GCC"/>
3552         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S"    condition="CM35P_GCC"/>
3553         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp.S" condition="CM35P_FP_GCC"/>
3554         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S"    condition="ARMv8MBL_GCC"/>
3555         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S"    condition="ARMv8MML_GCC"/>
3556         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp.S" condition="ARMv8MML_FP_GCC"/>
3557         <!-- RTX sources (handlers IAR) -->
3558         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm0.s"         condition="CM0_IAR"/>
3559         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm0.s"         condition="CM1_IAR"/>
3560         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm3.s"         condition="CM3_IAR"/>
3561         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm3.s"         condition="CM4_IAR"/>
3562         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm4f.s"        condition="CM4_FP_IAR"/>
3563         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm3.s"         condition="CM7_IAR"/>
3564         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm4f.s"        condition="CM7_FP_IAR"/>
3565         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s"    condition="CM23_IAR"/>
3566         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="CM33_IAR"/>
3567         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="CM33_FP_IAR"/>
3568         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="CM35P_IAR"/>
3569         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="CM35P_FP_IAR"/>
3570         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s"    condition="ARMv8MBL_IAR"/>
3571         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="ARMv8MML_IAR"/>
3572         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="ARMv8MML_FP_IAR"/>
3573         <!-- OS Tick (SysTick) -->
3574         <file category="source" name="CMSIS/RTOS2/Source/os_systick.c"/>
3575       </files>
3576     </component>
3577     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cversion="5.5.0" Capiversion="2.1.3" condition="RTOS2 RTX5 v7-A">
3578       <description>CMSIS-RTOS2 RTX5 for Armv7-A (Source)</description>
3579       <RTE_Components_h>
3580         <!-- the following content goes into file 'RTE_Components.h' -->
3581         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
3582         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
3583         #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
3584       </RTE_Components_h>
3585       <files>
3586         <!-- RTX documentation -->
3587         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
3588
3589         <!-- RTX header files -->
3590         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
3591
3592         <!-- RTX configuration -->
3593         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.5.0"/>
3594         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
3595
3596         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/handlers.c"    version="5.1.0"/>
3597
3598         <!-- RTX templates -->
3599         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.1.0" select="CMSIS-RTOS2 'main' function"/>
3600         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
3601         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
3602         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
3603         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
3604         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
3605         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
3606         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
3607         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
3608         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
3609
3610         <!-- RTX sources (core) -->
3611         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_kernel.c"/>
3612         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_thread.c"/>
3613         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_delay.c"/>
3614         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_timer.c"/>
3615         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evflags.c"/>
3616         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mutex.c"/>
3617         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_semaphore.c"/>
3618         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_memory.c"/>
3619         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mempool.c"/>
3620         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c"/>
3621         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_system.c"/>
3622         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evr.c"/>
3623         <!-- RTX sources (library configuration) -->
3624         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
3625         <!-- RTX sources (handlers ARMCC) -->
3626         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_ca.s"          condition="CA_ARMCC5"/>
3627         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_ca.S"          condition="CA_ARMCC6"/>
3628         <!-- RTX sources (handlers GCC) -->
3629         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_ca.S"          condition="CA_GCC"/>
3630         <!-- RTX sources (handlers IAR) -->
3631         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_ca.s"          condition="CA_IAR"/>
3632       </files>
3633     </component>
3634     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source_NS" Cversion="5.5.0" Capiversion="2.1.3" condition="RTOS2 RTX5 NS">
3635       <description>CMSIS-RTOS2 RTX5 for Armv8-M Non-Secure Domain (Source)</description>
3636       <RTE_Components_h>
3637         <!-- the following content goes into file 'RTE_Components.h' -->
3638         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
3639         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
3640         #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
3641         #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS  /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */
3642       </RTE_Components_h>
3643       <files>
3644         <!-- RTX documentation -->
3645         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
3646
3647         <!-- RTX header files -->
3648         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
3649
3650         <!-- RTX configuration -->
3651         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.5.0"/>
3652         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
3653
3654         <!-- RTX templates -->
3655         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.1.0" select="CMSIS-RTOS2 'main' function"/>
3656         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
3657         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
3658         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
3659         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
3660         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
3661         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
3662         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
3663         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
3664         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
3665
3666         <!-- RTX sources (core) -->
3667         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_kernel.c"/>
3668         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_thread.c"/>
3669         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_delay.c"/>
3670         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_timer.c"/>
3671         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evflags.c"/>
3672         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mutex.c"/>
3673         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_semaphore.c"/>
3674         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_memory.c"/>
3675         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mempool.c"/>
3676         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c"/>
3677         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_system.c"/>
3678         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evr.c"/>
3679         <!-- RTX sources (library configuration) -->
3680         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
3681         <!-- RTX sources (ARMCC handlers) -->
3682         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl_ns.s"    condition="CM23_ARMCC"/>
3683         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="CM33_ARMCC"/>
3684         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="CM33_FP_ARMCC"/>
3685         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="CM35P_ARMCC"/>
3686         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="CM35P_FP_ARMCC"/>
3687         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl_ns.s"    condition="ARMv8MBL_ARMCC"/>
3688         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="ARMv8MML_ARMCC"/>
3689         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="ARMv8MML_FP_ARMCC"/>
3690         <!-- RTX sources (GCC handlers) -->
3691         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl_ns.S"    condition="CM23_GCC"/>
3692         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_ns.S"    condition="CM33_GCC"/>
3693         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp_ns.S" condition="CM33_FP_GCC"/>
3694         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_ns.S"    condition="CM35P_GCC"/>
3695         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp_ns.S" condition="CM35P_FP_GCC"/>
3696         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl_ns.S"    condition="ARMv8MBL_GCC"/>
3697         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_ns.S"    condition="ARMv8MML_GCC"/>
3698         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp_ns.S" condition="ARMv8MML_FP_GCC"/>
3699         <!-- RTX sources (IAR handlers) -->
3700         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl_ns.s"    condition="CM23_IAR"/>
3701         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="CM33_IAR"/>
3702         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="CM33_FP_IAR"/>
3703         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="CM35P_IAR"/>
3704         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="CM35P_FP_IAR"/>
3705         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl_ns.s"    condition="ARMv8MBL_IAR"/>
3706         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="ARMv8MML_IAR"/>
3707         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="ARMv8MML_FP_IAR"/>
3708         <!-- OS Tick (SysTick) -->
3709         <file category="source" name="CMSIS/RTOS2/Source/os_systick.c"/>
3710       </files>
3711     </component>
3712
3713   </components>
3714
3715   <boards>
3716     <board name="uVision Simulator" vendor="Keil">
3717       <description>uVision Simulator</description>
3718       <mountedDevice    deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0"/>
3719       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0P"/>
3720       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0P_MPU"/>
3721       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM1"/>
3722       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM3"/>
3723       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM4"/>
3724       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM4_FP"/>
3725       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7"/>
3726       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7_SP"/>
3727       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7_DP"/>
3728       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MBL"/>
3729       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML"/>
3730       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML_SP"/>
3731       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML_DP"/>
3732       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM23"/>
3733       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM23_TZ"/>
3734       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33"/>
3735       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_TZ"/>
3736       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_DSP_FP"/>
3737       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_DSP_FP_TZ"/>
3738       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P"/>
3739       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P_TZ"/>
3740       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P_DSP_FP"/>
3741       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P_DSP_FP_TZ"/>
3742     </board>
3743
3744     <board name="EWARM Simulator" vendor="IAR">
3745       <description>EWARM Simulator</description>
3746       <mountedDevice    deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0"/>
3747       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0P"/>
3748       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0P_MPU"/>
3749       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM1"/>
3750       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM3"/>
3751       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM4"/>
3752       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM4_FP"/>
3753       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7"/>
3754       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7_SP"/>
3755       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7_DP"/>
3756       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MBL"/>
3757       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML"/>
3758       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML_SP"/>
3759       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML_DP"/>
3760       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM23"/>
3761       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM23_TZ"/>
3762       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33"/>
3763       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_TZ"/>
3764       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_DSP_FP"/>
3765       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_DSP_FP_TZ"/>
3766       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P"/>
3767       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P_TZ"/>
3768       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P_DSP_FP"/>
3769       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P_DSP_FP_TZ"/>
3770     </board>
3771   </boards>
3772
3773   <examples>
3774     <example name="DSP_Lib Class Marks example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_class_marks_example">
3775       <description>DSP_Lib Class Marks example</description>
3776       <board name="uVision Simulator" vendor="Keil"/>
3777       <project>
3778         <environment name="uv" load="arm_class_marks_example.uvprojx"/>
3779       </project>
3780       <attributes>
3781         <component Cclass="CMSIS" Cgroup="CORE"/>
3782         <component Cclass="CMSIS" Cgroup="DSP"/>
3783         <component Cclass="Device" Cgroup="Startup"/>
3784         <category>Getting Started</category>
3785       </attributes>
3786     </example>
3787
3788     <example name="DSP_Lib Convolution example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_convolution_example">
3789       <description>DSP_Lib Convolution example</description>
3790       <board name="uVision Simulator" vendor="Keil"/>
3791       <project>
3792         <environment name="uv" load="arm_convolution_example.uvprojx"/>
3793       </project>
3794       <attributes>
3795         <component Cclass="CMSIS" Cgroup="CORE"/>
3796         <component Cclass="CMSIS" Cgroup="DSP"/>
3797         <component Cclass="Device" Cgroup="Startup"/>
3798         <category>Getting Started</category>
3799       </attributes>
3800     </example>
3801
3802     <example name="DSP_Lib Dotproduct example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_dotproduct_example">
3803       <description>DSP_Lib Dotproduct example</description>
3804       <board name="uVision Simulator" vendor="Keil"/>
3805       <project>
3806         <environment name="uv" load="arm_dotproduct_example.uvprojx"/>
3807       </project>
3808       <attributes>
3809         <component Cclass="CMSIS" Cgroup="CORE"/>
3810         <component Cclass="CMSIS" Cgroup="DSP"/>
3811         <component Cclass="Device" Cgroup="Startup"/>
3812         <category>Getting Started</category>
3813       </attributes>
3814     </example>
3815
3816     <example name="DSP_Lib FFT Bin example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_fft_bin_example">
3817       <description>DSP_Lib FFT Bin example</description>
3818       <board name="uVision Simulator" vendor="Keil"/>
3819       <project>
3820         <environment name="uv" load="arm_fft_bin_example.uvprojx"/>
3821       </project>
3822       <attributes>
3823         <component Cclass="CMSIS" Cgroup="CORE"/>
3824         <component Cclass="CMSIS" Cgroup="DSP"/>
3825         <component Cclass="Device" Cgroup="Startup"/>
3826         <category>Getting Started</category>
3827       </attributes>
3828     </example>
3829
3830     <example name="DSP_Lib FIR example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_fir_example">
3831       <description>DSP_Lib FIR example</description>
3832       <board name="uVision Simulator" vendor="Keil"/>
3833       <project>
3834         <environment name="uv" load="arm_fir_example.uvprojx"/>
3835       </project>
3836       <attributes>
3837         <component Cclass="CMSIS" Cgroup="CORE"/>
3838         <component Cclass="CMSIS" Cgroup="DSP"/>
3839         <component Cclass="Device" Cgroup="Startup"/>
3840         <category>Getting Started</category>
3841       </attributes>
3842     </example>
3843
3844     <example name="DSP_Lib Graphic Equalizer example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example">
3845       <description>DSP_Lib Graphic Equalizer example</description>
3846       <board name="uVision Simulator" vendor="Keil"/>
3847       <project>
3848         <environment name="uv" load="arm_graphic_equalizer_example.uvprojx"/>
3849       </project>
3850       <attributes>
3851         <component Cclass="CMSIS" Cgroup="CORE"/>
3852         <component Cclass="CMSIS" Cgroup="DSP"/>
3853         <component Cclass="Device" Cgroup="Startup"/>
3854         <category>Getting Started</category>
3855       </attributes>
3856     </example>
3857
3858     <example name="DSP_Lib Linear Interpolation example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_linear_interp_example">
3859       <description>DSP_Lib Linear Interpolation example</description>
3860       <board name="uVision Simulator" vendor="Keil"/>
3861       <project>
3862         <environment name="uv" load="arm_linear_interp_example.uvprojx"/>
3863       </project>
3864       <attributes>
3865         <component Cclass="CMSIS" Cgroup="CORE"/>
3866         <component Cclass="CMSIS" Cgroup="DSP"/>
3867         <component Cclass="Device" Cgroup="Startup"/>
3868         <category>Getting Started</category>
3869       </attributes>
3870     </example>
3871
3872     <example name="DSP_Lib Matrix example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_matrix_example">
3873       <description>DSP_Lib Matrix example</description>
3874       <board name="uVision Simulator" vendor="Keil"/>
3875       <project>
3876         <environment name="uv" load="arm_matrix_example.uvprojx"/>
3877       </project>
3878       <attributes>
3879         <component Cclass="CMSIS" Cgroup="CORE"/>
3880         <component Cclass="CMSIS" Cgroup="DSP"/>
3881         <component Cclass="Device" Cgroup="Startup"/>
3882         <category>Getting Started</category>
3883       </attributes>
3884     </example>
3885
3886     <example name="DSP_Lib Signal Convergence example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_signal_converge_example">
3887       <description>DSP_Lib Signal Convergence example</description>
3888       <board name="uVision Simulator" vendor="Keil"/>
3889       <project>
3890         <environment name="uv" load="arm_signal_converge_example.uvprojx"/>
3891       </project>
3892       <attributes>
3893         <component Cclass="CMSIS" Cgroup="CORE"/>
3894         <component Cclass="CMSIS" Cgroup="DSP"/>
3895         <component Cclass="Device" Cgroup="Startup"/>
3896         <category>Getting Started</category>
3897       </attributes>
3898     </example>
3899
3900     <example name="DSP_Lib Sinus/Cosinus example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_sin_cos_example">
3901       <description>DSP_Lib Sinus/Cosinus example</description>
3902       <board name="uVision Simulator" vendor="Keil"/>
3903       <project>
3904         <environment name="uv" load="arm_sin_cos_example.uvprojx"/>
3905       </project>
3906       <attributes>
3907         <component Cclass="CMSIS" Cgroup="CORE"/>
3908         <component Cclass="CMSIS" Cgroup="DSP"/>
3909         <component Cclass="Device" Cgroup="Startup"/>
3910         <category>Getting Started</category>
3911       </attributes>
3912     </example>
3913
3914     <example name="DSP_Lib Variance example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_variance_example">
3915       <description>DSP_Lib Variance example</description>
3916       <board name="uVision Simulator" vendor="Keil"/>
3917       <project>
3918         <environment name="uv" load="arm_variance_example.uvprojx"/>
3919       </project>
3920       <attributes>
3921         <component Cclass="CMSIS" Cgroup="CORE"/>
3922         <component Cclass="CMSIS" Cgroup="DSP"/>
3923         <component Cclass="Device" Cgroup="Startup"/>
3924         <category>Getting Started</category>
3925       </attributes>
3926     </example>
3927
3928     <example name="NN Library CIFAR10" doc="readme.txt" folder="CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10">
3929       <description>Neural Network CIFAR10 example</description>
3930       <board name="uVision Simulator" vendor="Keil"/>
3931       <project>
3932         <environment name="uv" load="arm_nnexamples_cifar10.uvprojx"/>
3933       </project>
3934       <attributes>
3935         <component Cclass="CMSIS" Cgroup="CORE"/>
3936         <component Cclass="CMSIS" Cgroup="DSP"/>
3937         <component Cclass="CMSIS" Cgroup="NN Lib"/>
3938         <component Cclass="Device" Cgroup="Startup"/>
3939         <category>Getting Started</category>
3940       </attributes>
3941     </example>
3942
3943     <example name="NN-example-cifar10" doc="readme_iar.txt" folder="CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10">
3944       <description>Neural Network CIFAR10 example</description>
3945       <board name="EWARM Simulator" vendor="IAR"/>
3946       <project>
3947         <environment name="iar" load="NN-example-cifar10.ewp"/>
3948       </project>
3949       <attributes>
3950         <component Cclass="CMSIS" Cgroup="CORE"/>
3951         <component Cclass="CMSIS" Cgroup="DSP"/>
3952         <component Cclass="CMSIS" Cgroup="NN Lib"/>
3953         <component Cclass="Device" Cgroup="Startup"/>
3954         <category>Getting Started</category>
3955       </attributes>
3956     </example>
3957
3958     <example name="NN Library GRU" doc="readme.txt" folder="CMSIS/NN/Examples/ARM/arm_nn_examples/gru">
3959       <description>Neural Network GRU example</description>
3960       <board name="uVision Simulator" vendor="Keil"/>
3961       <project>
3962         <environment name="uv" load="arm_nnexamples_gru.uvprojx"/>
3963       </project>
3964       <attributes>
3965         <component Cclass="CMSIS" Cgroup="CORE"/>
3966         <component Cclass="CMSIS" Cgroup="DSP"/>
3967         <component Cclass="CMSIS" Cgroup="NN Lib"/>
3968         <component Cclass="Device" Cgroup="Startup"/>
3969         <category>Getting Started</category>
3970       </attributes>
3971     </example>
3972
3973     <example name="NN-example-gru" doc="readme_iar.txt" folder="CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-gru">
3974       <description>Neural Network GRU example</description>
3975       <board name="EWARM Simulator" vendor="IAR"/>
3976       <project>
3977         <environment name="iar" load="NN-example-gru.ewp"/>
3978       </project>
3979       <attributes>
3980         <component Cclass="CMSIS" Cgroup="CORE"/>
3981         <component Cclass="CMSIS" Cgroup="DSP"/>
3982         <component Cclass="CMSIS" Cgroup="NN Lib"/>
3983         <component Cclass="Device" Cgroup="Startup"/>
3984         <category>Getting Started</category>
3985       </attributes>
3986     </example>
3987
3988     <example name="CMSIS-RTOS2 Blinky" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/Blinky">
3989       <description>CMSIS-RTOS2 Blinky example</description>
3990       <board name="uVision Simulator" vendor="Keil"/>
3991       <project>
3992         <environment name="uv" load="Blinky.uvprojx"/>
3993       </project>
3994       <attributes>
3995         <component Cclass="CMSIS" Cgroup="CORE"/>
3996         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3997         <component Cclass="Device" Cgroup="Startup"/>
3998         <category>Getting Started</category>
3999       </attributes>
4000     </example>
4001
4002     <example name="CMSIS-RTOS2 RTX5 Migration" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/Migration">
4003       <description>CMSIS-RTOS2 mixed API v1 and v2</description>
4004       <board name="uVision Simulator" vendor="Keil"/>
4005       <project>
4006         <environment name="uv" load="Blinky.uvprojx"/>
4007       </project>
4008       <attributes>
4009         <component Cclass="CMSIS" Cgroup="CORE"/>
4010         <component Cclass="CMSIS" Cgroup="RTOS2"/>
4011         <component Cclass="Device" Cgroup="Startup"/>
4012         <category>Getting Started</category>
4013       </attributes>
4014     </example>
4015
4016     <example name="CMSIS-RTOS2 RTX5 Message Queue" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/MsgQueue">
4017       <description>CMSIS-RTOS2 Message Queue Example</description>
4018       <board name="uVision Simulator" vendor="Keil"/>
4019       <project>
4020         <environment name="uv" load="MsqQueue.uvprojx"/>
4021       </project>
4022       <attributes>
4023         <component Cclass="CMSIS" Cgroup="CORE"/>
4024         <component Cclass="CMSIS" Cgroup="RTOS2"/>
4025         <component Cclass="Compiler" Cgroup="EventRecorder"/>
4026         <component Cclass="Device" Cgroup="Startup"/>
4027         <category>Getting Started</category>
4028       </attributes>
4029     </example>
4030
4031     <example name="CMSIS-RTOS2 RTX5 Memory Pool" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/MemPool">
4032       <description>CMSIS-RTOS2 Memory Pool Example</description>
4033       <board name="uVision Simulator" vendor="Keil"/>
4034       <project>
4035         <environment name="uv" load="MemPool.uvprojx"/>
4036       </project>
4037       <attributes>
4038         <component Cclass="CMSIS" Cgroup="CORE"/>
4039         <component Cclass="CMSIS" Cgroup="RTOS2"/>
4040         <component Cclass="Compiler" Cgroup="EventRecorder"/>
4041         <component Cclass="Device" Cgroup="Startup"/>
4042         <category>Getting Started</category>
4043       </attributes>
4044     </example>
4045
4046     <example name="TrustZone for ARMv8-M No RTOS" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/NoRTOS">
4047       <description>Bare-metal secure/non-secure example without RTOS</description>
4048       <board name="uVision Simulator" vendor="Keil"/>
4049       <project>
4050         <environment name="uv" load="NoRTOS.uvmpw"/>
4051       </project>
4052       <attributes>
4053         <component Cclass="CMSIS" Cgroup="CORE"/>
4054         <component Cclass="CMSIS" Cgroup="RTOS2"/>
4055         <component Cclass="Device" Cgroup="Startup"/>
4056         <category>Getting Started</category>
4057       </attributes>
4058     </example>
4059
4060     <example name="TrustZone for ARMv8-M RTOS"  doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS">
4061       <description>Secure/non-secure RTOS example with thread context management</description>
4062       <board name="uVision Simulator" vendor="Keil"/>
4063       <project>
4064         <environment name="uv" load="RTOS.uvmpw"/>
4065       </project>
4066       <attributes>
4067         <component Cclass="CMSIS" Cgroup="CORE"/>
4068         <component Cclass="CMSIS" Cgroup="RTOS2"/>
4069         <component Cclass="Device" Cgroup="Startup"/>
4070         <category>Getting Started</category>
4071       </attributes>
4072     </example>
4073
4074     <example name="TrustZone for ARMv8-M RTOS Security Tests"  doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults">
4075       <description>Secure/non-secure RTOS example with security test cases and system recovery</description>
4076       <board name="uVision Simulator" vendor="Keil"/>
4077       <project>
4078         <environment name="uv" load="RTOS_Faults.uvmpw"/>
4079       </project>
4080       <attributes>
4081         <component Cclass="CMSIS" Cgroup="CORE"/>
4082         <component Cclass="CMSIS" Cgroup="RTOS2"/>
4083         <component Cclass="Device" Cgroup="Startup"/>
4084         <category>Getting Started</category>
4085       </attributes>
4086     </example>
4087
4088   </examples>
4089
4090 </package>