begriffs open source - cmsis/blob - ARM.CMSIS.pdsc

   1 <?xml version="1.0" encoding="UTF-8"?>
   2
   3 <package schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="PACK.xsd">
   4   <name>CMSIS</name>
   5   <description>CMSIS (Cortex Microcontroller Software Interface Standard)</description>
   6   <vendor>ARM</vendor>
   7   <!-- <license>license.txt</license> -->
   8   <url>http://www.keil.com/pack/</url>
   9
  10   <releases>
  11     <release version="5.5.0-dev2">
  12       Active development ...
  13       CMSIS-Core(M):
  14         - Reworked Stack/Heap configuration for ARM startup files.
  15         - Added Cortex-M35P device support.
  16       CMSIS-RTOS2:
  17         - RTX 5.5.0 (see revision history for details)
  18       DSP_Lib:
  19         - updated arm_math.h
  20         - reduced ARM_MATH_CMx macros
  21         - added GitHub pull requests
  22     </release>
  23     <release version="5.4.0" date="2018-08-01">
  24       Aligned pack structure with repository.
  25       The following folders are deprecated:
  26         - CMSIS/Include/
  27         - CMSIS/DSP_Lib/
  28
  29       CMSIS-Core(M): 5.1.2 (see revision history for details)
  30         - Added Cortex-M1 support (beta).
  31       CMSIS-Core(A): 1.1.2 (see revision history for details)
  32       CMSIS-NN: 1.1.0
  33         - Added new math functions.
  34       CMSIS-RTOS2:
  35         - API 2.1.3 (see revision history for details)
  36         - RTX 5.4.0 (see revision history for details)
  37           * Updated exception handling on Cortex-A
  38       CMSIS-Driver:
  39         - Flash Driver API V2.2.0
  40       Utilities:
  41         - SVDConv 3.3.21
  42         - PackChk 1.3.71
  43     </release>
  44     <release version="5.3.0" date="2018-02-22">
  45       Updated Arm company brand.
  46       CMSIS-Core(M): 5.1.1 (see revision history for details)
  47       CMSIS-Core(A): 1.1.1 (see revision history for details)
  48       CMSIS-DAP: 2.0.0 (see revision history for details)
  49       CMSIS-NN: 1.0.0
  50         - Initial contribution of the bare metal Neural Network Library.
  51       CMSIS-RTOS2:
  52         - RTX 5.3.0 (see revision history for details)
  53         - OS Tick API 1.0.1
  54     </release>
  55     <release version="5.2.0" date="2017-11-16">
  56       CMSIS-Core(M): 5.1.0 (see revision history for details)
  57         - Added MPU Functions for ARMv8-M for Cortex-M23/M33.
  58         - Added compiler_iccarm.h to replace compiler_iar.h shipped with the compiler.
  59       CMSIS-Core(A): 1.1.0 (see revision history for details)
  60         - Added compiler_iccarm.h.
  61         - Added additional access functions for physical timer.
  62       CMSIS-DAP: 1.2.0 (see revision history for details)
  63       CMSIS-DSP: 1.5.2 (see revision history for details)
  64       CMSIS-Driver: 2.6.0 (see revision history for details)
  65         - CAN Driver API V1.2.0
  66         - NAND Driver API V2.3.0
  67       CMSIS-RTOS:
  68         - RTX: added variant for Infineon XMC4 series affected by PMU_CM.001 errata.
  69       CMSIS-RTOS2:
  70         - API 2.1.2 (see revision history for details)
  71         - RTX 5.2.3 (see revision history for details)
  72       Devices:
  73         - Added GCC startup and linker script for Cortex-A9.
  74         - Added device ARMCM0plus_MPU for Cortex-M0+ with MPU.
  75         - Added IAR startup code for Cortex-A9
  76     </release>
  77     <release version="5.1.1" date="2017-09-19">
  78       CMSIS-RTOS2:
  79       - RTX 5.2.1 (see revision history for details)
  80     </release>
  81     <release version="5.1.0" date="2017-08-04">
  82       CMSIS-Core(M): 5.0.2 (see revision history for details)
  83       - Changed Version Control macros to be core agnostic.
  84       - Added MPU Functions for ARMv7-M for Cortex-M0+/M3/M4/M7.
  85       CMSIS-Core(A): 1.0.0 (see revision history for details)
  86       - Initial release
  87       - IRQ Controller API 1.0.0
  88       CMSIS-Driver: 2.05 (see revision history for details)
  89       - All typedefs related to status have been made volatile.
  90       CMSIS-RTOS2:
  91       - API 2.1.1 (see revision history for details)
  92       - RTX 5.2.0 (see revision history for details)
  93       - OS Tick API 1.0.0
  94       CMSIS-DSP: 1.5.2 (see revision history for details)
  95       - Fixed GNU Compiler specific diagnostics.
  96       CMSIS-Pack: 1.5.0 (see revision history for details)
  97       - added System Description File (*.SDF) Format
  98       CMSIS-Zone: 0.0.1 (Preview)
  99       - Initial specification draft
 100     </release>
 101     <release version="5.0.1" date="2017-02-03">
 102       Package Description:
 103       - added taxonomy for Cclass RTOS
 104       CMSIS-RTOS2:
 105       - API 2.1   (see revision history for details)
 106       - RTX 5.1.0 (see revision history for details)
 107       CMSIS-Core: 5.0.1 (see revision history for details)
 108       - Added __PACKED_STRUCT macro
 109       - Added uVisior support
 110       - Updated cmsis_armcc.h: corrected macro __ARM_ARCH_6M__
 111       - Updated template for secure main function (main_s.c)
 112       - Updated template for Context Management for ARMv8-M TrustZone (tz_context.c)
 113       CMSIS-DSP: 1.5.1 (see revision history for details)
 114       - added ARMv8M DSP libraries.
 115       CMSIS-Pack:1.4.9 (see revision history for details)
 116       - added Pack Index File specification and schema file
 117     </release>
 118     <release version="5.0.0" date="2016-11-11">
 119       Changed open source license to Apache 2.0
 120       CMSIS_Core:
 121        - Added support for Cortex-M23 and Cortex-M33.
 122        - Added ARMv8-M device configurations for mainline and baseline.
 123        - Added CMSE support and thread context management for TrustZone for ARMv8-M
 124        - Added cmsis_compiler.h to unify compiler behaviour.
 125        - Updated function SCB_EnableICache (for Cortex-M7).
 126        - Added functions: NVIC_GetEnableIRQ, SCB_GetFPUType
 127       CMSIS-RTOS:
 128         - bug fix in RTX 4.82 (see revision history for details)
 129       CMSIS-RTOS2:
 130         - new API including compatibility layer to CMSIS-RTOS
 131         - reference implementation based on RTX5
 132         - supports all Cortex-M variants including TrustZone for ARMv8-M
 133       CMSIS-SVD:
 134        - reworked SVD format documentation
 135        - removed SVD file database documentation as SVD files are distributed in packs
 136        - updated SVDConv for Win32 and Linux
 137       CMSIS-DSP:
 138        - Moved DSP libraries from CMSIS/DSP/Lib to CMSIS/Lib.
 139        - Added DSP libraries build projects to CMSIS pack.
 140     </release>
 141     <release version="4.5.0" date="2015-10-28">
 142       - CMSIS-Core     4.30.0  (see revision history for details)
 143       - CMSIS-DAP      1.1.0   (unchanged)
 144       - CMSIS-Driver   2.04.0  (see revision history for details)
 145       - CMSIS-DSP      1.4.7   (no source code change [still labeled 1.4.5], see revision history for details)
 146       - CMSIS-Pack     1.4.1   (see revision history for details)
 147       - CMSIS-RTOS     4.80.0  Restored time delay parameter 'millisec' old behavior (prior V4.79) for software compatibility. (see revision history for details)
 148       - CMSIS-SVD      1.3.1   (see revision history for details)
 149     </release>
 150     <release version="4.4.0" date="2015-09-11">
 151       - CMSIS-Core     4.20   (see revision history for details)
 152       - CMSIS-DSP      1.4.6  (no source code change [still labeled 1.4.5], see revision history for details)
 153       - CMSIS-Pack     1.4.0  (adding memory attributes, algorithm style)
 154       - CMSIS-Driver   2.03.0 (adding CAN [Controller Area Network] API)
 155       - CMSIS-RTOS
 156         -- API         1.02   (unchanged)
 157         -- RTX         4.79   (see revision history for details)
 158       - CMSIS-SVD      1.3.0  (see revision history for details)
 159       - CMSIS-DAP      1.1.0  (extended with SWO support)
 160     </release>
 161     <release version="4.3.0" date="2015-03-20">
 162       - CMSIS-Core     4.10   (Cortex-M7 extended Cache Maintenance functions)
 163       - CMSIS-DSP      1.4.5  (see revision history for details)
 164       - CMSIS-Driver   2.02   (adding SAI (Serial Audio Interface) API)
 165       - CMSIS-Pack     1.3.3  (Semantic Versioning, Generator extensions)
 166       - CMSIS-RTOS
 167         -- API         1.02   (unchanged)
 168         -- RTX         4.78   (see revision history for details)
 169       - CMSIS-SVD      1.2    (unchanged)
 170     </release>
 171     <release version="4.2.0" date="2014-09-24">
 172       Adding Cortex-M7 support
 173       - CMSIS-Core     4.00  (Cortex-M7 support, corrected C++ include guards in core header files)
 174       - CMSIS-DSP      1.4.4 (Cortex-M7 support and corrected out of bound issues)
 175       - CMSIS-Pack     1.3.1 (Cortex-M7 updates, clarification, corrected batch files in Tutorial)
 176       - CMSIS-SVD      1.2   (Cortex-M7 extensions)
 177       - CMSIS-RTOS RTX 4.75  (see revision history for details)
 178     </release>
 179     <release version="4.1.1" date="2014-06-30">
 180       - fixed conditions preventing the inclusion of the DSP library in projects for Infineon XMC4000 series devices
 181     </release>
 182     <release version="4.1.0" date="2014-06-12">
 183       - CMSIS-Driver   2.02  (incompatible update)
 184       - CMSIS-Pack     1.3   (see revision history for details)
 185       - CMSIS-DSP      1.4.2 (unchanged)
 186       - CMSIS-Core     3.30  (unchanged)
 187       - CMSIS-RTOS RTX 4.74  (unchanged)
 188       - CMSIS-RTOS API 1.02  (unchanged)
 189       - CMSIS-SVD      1.10  (unchanged)
 190       PACK:
 191       - removed G++ specific files from PACK
 192       - added Component Startup variant "C Startup"
 193       - added Pack Checking Utility
 194       - updated conditions to reflect tool-chain dependency
 195       - added Taxonomy for Graphics
 196       - updated Taxonomy for unified drivers from "Drivers" to "CMSIS Drivers"
 197     </release>
 198     <release version="4.0.0">
 199       - CMSIS-Driver   2.00  Preliminary (incompatible update)
 200       - CMSIS-Pack     1.1   Preliminary
 201       - CMSIS-DSP      1.4.2 (see revision history for details)
 202       - CMSIS-Core     3.30  (see revision history for details)
 203       - CMSIS-RTOS RTX 4.74  (see revision history for details)
 204       - CMSIS-RTOS API 1.02  (unchanged)
 205       - CMSIS-SVD      1.10  (unchanged)
 206     </release>
 207     <release version="3.20.4">
 208       - CMSIS-RTOS 4.74 (see revision history for details)
 209       - PACK Extensions (Boards, Device Features, Flash Programming, Generators, Configuration Wizard). Schema version 1.1.
 210     </release>
 211     <release version="3.20.3">
 212       - CMSIS-Driver API Version 1.10 ARM prefix added (incompatible change)
 213       - CMSIS-RTOS 4.73 (see revision history for details)
 214     </release>
 215     <release version="3.20.2">
 216       - CMSIS-Pack documentation has been added
 217       - CMSIS-Drivers header and documentation have been added to PACK
 218       - CMSIS-CORE, CMSIS-DSP, CMSIS-RTOS API and CMSIS-SVD remain unchanged
 219     </release>
 220     <release version="3.20.1">
 221       - CMSIS-RTOS Keil RTX V4.72 has been added to PACK
 222       - CMSIS-CORE, CMSIS-DSP, CMSIS-RTOS API and CMSIS-SVD remain unchanged
 223     </release>
 224     <release version="3.20.0">
 225       The software portions that are deployed in the application program are now under a BSD license which allows usage
 226       of CMSIS components in any commercial or open source projects.  The Pack Description file Arm.CMSIS.pdsc describes the use cases
 227       The individual components have been update as listed below:
 228       - CMSIS-CORE adds functions for setting breakpoints, supports the latest GCC Compiler, and contains several corrections.
 229       - CMSIS-DSP library is optimized for more performance and contains several bug fixes.
 230       - CMSIS-RTOS API is extended with capabilities for short timeouts, Kernel initialization, and prepared for a C++ interface.
 231       - CMSIS-SVD is unchanged.
 232     </release>
 233   </releases>
 234
 235   <taxonomy>
 236     <description Cclass="Board Support">Generic Interfaces for Evaluation and Development Boards</description>
 237     <description Cclass="CMSIS" doc="CMSIS/Documentation/General/html/index.html">Cortex Microcontroller Software Interface Components</description>
 238     <description Cclass="Device" doc="CMSIS/Documentation/Core/html/index.html">Startup, System Setup</description>
 239     <description Cclass="CMSIS Driver" doc="CMSIS/Documentation/Driver/html/index.html">Unified Device Drivers compliant to CMSIS-Driver Specifications</description>
 240     <description Cclass="File System">File Drive Support and File System</description>
 241     <description Cclass="Graphics">Graphical User Interface</description>
 242     <description Cclass="Network">Network Stack using Internet Protocols</description>
 243     <description Cclass="USB">Universal Serial Bus Stack</description>
 244     <description Cclass="Compiler">Compiler Software Extensions</description>
 245     <description Cclass="RTOS">Real-time Operating System</description>
 246   </taxonomy>
 247
 248   <devices>
 249     <!-- ******************************  Cortex-M0  ****************************** -->
 250     <family Dfamily="ARM Cortex M0" Dvendor="ARM:82">
 251       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/index.html" title="Cortex-M0 Device Generic Users Guide"/>
 252       <description>
 253 The Cortex-M0 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 254 - simple, easy-to-use programmers model
 255 - highly efficient ultra-low power operation
 256 - excellent code density
 257 - deterministic, high-performance interrupt handling
 258 - upward compatibility with the rest of the Cortex-M processor family.
 259       </description>
 260       <!-- debug svd="Device/ARM/SVD/ARMCM0.svd"/ SVD files do not contain any peripheral -->
 261       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 262       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 263       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 264
 265       <device Dname="ARMCM0">
 266         <processor Dcore="Cortex-M0" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
 267         <compile header="Device/ARM/ARMCM0/Include/ARMCM0.h" define="ARMCM0"/>
 268       </device>
 269     </family>
 270
 271     <!-- ******************************  Cortex-M0P  ****************************** -->
 272     <family Dfamily="ARM Cortex M0 plus" Dvendor="ARM:82">
 273       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0662b/index.html" title="Cortex-M0+ Device Generic Users Guide"/>
 274       <description>
 275 The Cortex-M0+ processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 276 - simple, easy-to-use programmers model
 277 - highly efficient ultra-low power operation
 278 - excellent code density
 279 - deterministic, high-performance interrupt handling
 280 - upward compatibility with the rest of the Cortex-M processor family.
 281       </description>
 282       <!-- debug svd="Device/ARM/SVD/ARMCM0P.svd"/ SVD files do not contain any peripheral -->
 283       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 284       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 285       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 286
 287       <device Dname="ARMCM0P">
 288         <processor Dcore="Cortex-M0+" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
 289         <compile header="Device/ARM/ARMCM0plus/Include/ARMCM0plus.h" define="ARMCM0P"/>
 290       </device>
 291
 292       <device Dname="ARMCM0P_MPU">
 293         <processor Dcore="Cortex-M0+" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 294         <compile header="Device/ARM/ARMCM0plus/Include/ARMCM0plus_MPU.h" define="ARMCM0P_MPU"/>
 295       </device>
 296     </family>
 297
 298     <!-- ******************************  Cortex-M1  ****************************** -->
 299     <family Dfamily="ARM Cortex M1" Dvendor="ARM:82">
 300       <!--book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/index.html" title="Cortex-M1 Device Generic Users Guide"/-->
 301       <description>
 302 The ARM Cortex-M1 FPGA processor is intended for deeply embedded applications that require a small processor integrated into an FPGA.
 303 The ARM Cortex-M1 processor implements the ARMv6-M architecture profile.
 304       </description>
 305       <!-- debug svd="Device/ARM/SVD/ARMCM0.svd"/ SVD files do not contain any peripheral -->
 306       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 307       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 308       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 309
 310       <device Dname="ARMCM1">
 311         <processor Dcore="Cortex-M1" DcoreVersion="r1p0" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
 312         <compile header="Device/ARM/ARMCM1/Include/ARMCM1.h" define="ARMCM1"/>
 313       </device>
 314     </family>
 315
 316     <!-- ******************************  Cortex-M3  ****************************** -->
 317     <family Dfamily="ARM Cortex M3" Dvendor="ARM:82">
 318       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/index.html" title="Cortex-M3 Device Generic Users Guide"/>
 319       <description>
 320 The Cortex-M3 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 321 - simple, easy-to-use programmers model
 322 - highly efficient ultra-low power operation
 323 - excellent code density
 324 - deterministic, high-performance interrupt handling
 325 - upward compatibility with the rest of the Cortex-M processor family.
 326       </description>
 327       <!-- debug svd="Device/ARM/SVD/ARMCM3.svd"/ SVD files do not contain any peripheral -->
 328       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 329       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 330       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 331
 332       <device Dname="ARMCM3">
 333         <processor Dcore="Cortex-M3" DcoreVersion="r2p1" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 334         <compile header="Device/ARM/ARMCM3/Include/ARMCM3.h" define="ARMCM3"/>
 335       </device>
 336     </family>
 337
 338     <!-- ******************************  Cortex-M4  ****************************** -->
 339     <family Dfamily="ARM Cortex M4" Dvendor="ARM:82">
 340       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/index.html" title="Cortex-M4 Device Generic Users Guide"/>
 341       <description>
 342 The Cortex-M4 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 343 - simple, easy-to-use programmers model
 344 - highly efficient ultra-low power operation
 345 - excellent code density
 346 - deterministic, high-performance interrupt handling
 347 - upward compatibility with the rest of the Cortex-M processor family.
 348       </description>
 349       <!-- debug svd="Device/ARM/SVD/ARMCM4.svd"/ SVD files do not contain any peripheral -->
 350       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 351       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 352       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 353
 354       <device Dname="ARMCM4">
 355         <processor Dcore="Cortex-M4" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 356         <compile header="Device/ARM/ARMCM4/Include/ARMCM4.h"    define="ARMCM4"/>
 357       </device>
 358
 359       <device Dname="ARMCM4_FP">
 360         <processor Dcore="Cortex-M4" DcoreVersion="r0p1" Dfpu="SP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 361         <compile header="Device/ARM/ARMCM4/Include/ARMCM4_FP.h" define="ARMCM4_FP"/>
 362       </device>
 363     </family>
 364
 365     <!-- ******************************  Cortex-M7  ****************************** -->
 366     <family Dfamily="ARM Cortex M7" Dvendor="ARM:82">
 367       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0646b/index.html" title="Cortex-M7 Device Generic Users Guide"/>
 368       <description>
 369 The Cortex-M7 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 370 - simple, easy-to-use programmers model
 371 - highly efficient ultra-low power operation
 372 - excellent code density
 373 - deterministic, high-performance interrupt handling
 374 - upward compatibility with the rest of the Cortex-M processor family.
 375       </description>
 376       <!-- debug svd="Device/ARM/SVD/ARMCM7.svd"/ SVD files do not contain any peripheral -->
 377       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 378       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 379       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 380
 381       <device Dname="ARMCM7">
 382         <processor Dcore="Cortex-M7" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 383         <compile header="Device/ARM/ARMCM7/Include/ARMCM7.h" define="ARMCM7"/>
 384       </device>
 385
 386       <device Dname="ARMCM7_SP">
 387         <processor Dcore="Cortex-M7" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 388         <compile header="Device/ARM/ARMCM7/Include/ARMCM7_SP.h" define="ARMCM7_SP"/>
 389       </device>
 390
 391       <device Dname="ARMCM7_DP">
 392         <processor Dcore="Cortex-M7" DcoreVersion="r0p0" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 393         <compile header="Device/ARM/ARMCM7/Include/ARMCM7_DP.h" define="ARMCM7_DP"/>
 394       </device>
 395     </family>
 396
 397     <!-- ******************************  Cortex-M23  ********************** -->
 398     <family Dfamily="ARM Cortex M23" Dvendor="ARM:82">
 399       <!--book name="Device/ARM/Documents/??_dgug.pdf"       title="?? Device Generic Users Guide"/-->
 400       <description>
 401 The Arm Cortex-M23 is based on the Armv8-M baseline architecture.
 402 It is the smallest and most energy efficient Arm processor with Arm TrustZone technology.
 403 Cortex-M23 is the ideal processor for constrained embedded applications requiring efficient security.
 404       </description>
 405       <!-- debug svd="Device/ARM/SVD/ARMCM23.svd"/ SVD files do not contain any peripheral -->
 406       <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
 407       <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
 408       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 409       <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
 410       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 411
 412       <device Dname="ARMCM23">
 413         <processor Dcore="Cortex-M23" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
 414         <compile header="Device/ARM/ARMCM23/Include/ARMCM23.h" define="ARMCM23"/>
 415       </device>
 416
 417       <device Dname="ARMCM23_TZ">
 418         <processor Dcore="Cortex-M23" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 419         <compile header="Device/ARM/ARMCM23/Include/ARMCM23_TZ.h" define="ARMCM23_TZ"/>
 420       </device>
 421     </family>
 422
 423     <!-- ******************************  Cortex-M33  ****************************** -->
 424     <family Dfamily="ARM Cortex M33" Dvendor="ARM:82">
 425       <!--book name="Device/ARM/Documents/??_dgug.pdf"       title="?? Device Generic Users Guide"/-->
 426       <description>
 427 The Arm Cortex-M33 is the most configurable of all Cortex-M processors. It is a full featured microcontroller
 428 class processor based on the Armv8-M mainline architecture with Arm TrustZone security.
 429       </description>
 430       <!-- debug svd="Device/ARM/SVD/ARMCM33.svd"/ SVD files do not contain any peripheral -->
 431       <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
 432       <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
 433       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 434       <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
 435       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"          default="1"/-->
 436
 437       <device Dname="ARMCM33">
 438         <processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
 439         <description>
 440           no DSP Instructions, no Floating Point Unit, no TrustZone
 441         </description>
 442         <compile header="Device/ARM/ARMCM33/Include/ARMCM33.h" define="ARMCM33"/>
 443       </device>
 444
 445       <device Dname="ARMCM33_TZ">
 446         <processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 447         <description>
 448           no DSP Instructions, no Floating Point Unit, TrustZone
 449         </description>
 450         <compile header="Device/ARM/ARMCM33/Include/ARMCM33_TZ.h" define="ARMCM33_TZ"/>
 451       </device>
 452
 453       <device Dname="ARMCM33_DSP_FP">
 454         <processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
 455         <description>
 456           DSP Instructions, Single Precision Floating Point Unit, no TrustZone
 457         </description>
 458         <compile header="Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP.h" define="ARMCM33_DSP_FP"/>
 459       </device>
 460
 461       <device Dname="ARMCM33_DSP_FP_TZ">
 462         <processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 463         <description>
 464           DSP Instructions, Single Precision Floating Point Unit, TrustZone
 465         </description>
 466         <compile header="Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h" define="ARMCM33_DSP_FP_TZ"/>
 467       </device>
 468     </family>
 469
 470     <!-- ******************************  Cortex-M35P  ****************************** -->
 471     <family Dfamily="ARM Cortex M35P" Dvendor="ARM:82">
 472       <!--book name="Device/ARM/Documents/??_dgug.pdf"       title="?? Device Generic Users Guide"/-->
 473       <description>
 474 The Arm Cortex-M35P is the most configurable of all Cortex-M processors. It is a full featured microcontroller
 475 class processor based on the Armv8-M mainline architecture with Arm TrustZone security designed for a broad range of secure embedded applications.
 476       </description>
 477
 478       <!-- debug svd="Device/ARM/SVD/ARMCM35P.svd"/ SVD files do not contain any peripheral -->
 479       <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
 480       <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
 481       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 482       <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
 483       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"          default="1"/-->
 484
 485       <device Dname="ARMCM35P">
 486         <processor Dcore="Cortex-M35P" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
 487         <description>
 488           no DSP Instructions, no Floating Point Unit, no TrustZone
 489         </description>
 490         <compile header="Device/ARM/ARMCM35P/Include/ARMCM35P.h" define="ARMCM35P"/>
 491       </device>
 492
 493       <device Dname="ARMCM35P_TZ">
 494         <processor Dcore="Cortex-M35P" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 495         <description>
 496           no DSP Instructions, no Floating Point Unit, TrustZone
 497         </description>
 498         <compile header="Device/ARM/ARMCM35P/Include/ARMCM35P_TZ.h" define="ARMCM35P_TZ"/>
 499       </device>
 500
 501       <device Dname="ARMCM35P_DSP_FP">
 502         <processor Dcore="Cortex-M35P" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
 503         <description>
 504           DSP Instructions, Single Precision Floating Point Unit, no TrustZone
 505         </description>
 506         <compile header="Device/ARM/ARMCM35P/Include/ARMCM35P_DSP_FP.h" define="ARMCM35P_DSP_FP"/>
 507       </device>
 508
 509       <device Dname="ARMCM35P_DSP_FP_TZ">
 510         <processor Dcore="Cortex-M35P" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 511         <description>
 512           DSP Instructions, Single Precision Floating Point Unit, TrustZone
 513         </description>
 514         <compile header="Device/ARM/ARMCM35P/Include/ARMCM35P_DSP_FP_TZ.h" define="ARMCM35P_DSP_FP_TZ"/>
 515       </device>
 516     </family>
 517
 518     <!-- ******************************  ARMSC000  ****************************** -->
 519     <family Dfamily="ARM SC000" Dvendor="ARM:82">
 520       <description>
 521 The Arm SC000 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including:
 522 - simple, easy-to-use programmers model
 523 - highly efficient ultra-low power operation
 524 - excellent code density
 525 - deterministic, high-performance interrupt handling
 526       </description>
 527       <!-- debug svd="Device/ARM/SVD/ARMSC000.svd"/ SVD files do not contain any peripheral -->
 528       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 529       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 530       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 531
 532       <device Dname="ARMSC000">
 533         <processor Dcore="SC000" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
 534         <compile header="Device/ARM/ARMSC000/Include/ARMSC000.h" define="ARMSC000"/>
 535       </device>
 536     </family>
 537
 538     <!-- ******************************  ARMSC300  ****************************** -->
 539     <family Dfamily="ARM SC300" Dvendor="ARM:82">
 540       <description>
 541 The ARM SC300 processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including:
 542 - simple, easy-to-use programmers model
 543 - highly efficient ultra-low power operation
 544 - excellent code density
 545 - deterministic, high-performance interrupt handling
 546       </description>
 547       <!-- debug svd="Device/ARM/SVD/ARMSC300.svd"/ SVD files do not contain any peripheral -->
 548       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 549       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 550       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 551
 552       <device Dname="ARMSC300">
 553         <processor Dcore="SC300" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
 554         <compile header="Device/ARM/ARMSC300/Include/ARMSC300.h" define="ARMSC300"/>
 555       </device>
 556     </family>
 557
 558     <!-- ******************************  ARMv8-M Baseline  ********************** -->
 559     <family Dfamily="ARMv8-M Baseline" Dvendor="ARM:82">
 560       <!--book name="Device/ARM/Documents/ARMv8MBL_dgug.pdf"       title="ARMv8MBL Device Generic Users Guide"/-->
 561       <description>
 562 Armv8-M Baseline based device with TrustZone
 563       </description>
 564       <!-- debug svd="Device/ARM/SVD/ARMv8MBL.svd"/ SVD files do not contain any peripheral -->
 565       <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
 566       <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
 567       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 568       <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
 569       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 570
 571       <device Dname="ARMv8MBL">
 572         <processor Dcore="ARMV8MBL" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 573         <compile header="Device/ARM/ARMv8MBL/Include/ARMv8MBL.h" define="ARMv8MBL"/>
 574       </device>
 575     </family>
 576
 577     <!-- ******************************  ARMv8-M Mainline  ****************************** -->
 578     <family Dfamily="ARMv8-M Mainline" Dvendor="ARM:82">
 579       <!--book name="Device/ARM/Documents/ARMv8MML_dgug.pdf"       title="ARMv8MML Device Generic Users Guide"/-->
 580       <description>
 581 Armv8-M Mainline based device with TrustZone
 582       </description>
 583       <!-- debug svd="Device/ARM/SVD/ARMv8MML.svd"/ SVD files do not contain any peripheral -->
 584       <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
 585       <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
 586       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 587       <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
 588       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 589
 590       <device Dname="ARMv8MML">
 591         <processor Dcore="ARMV8MML" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 592         <description>
 593           no DSP Instructions, no Floating Point Unit, TrustZone
 594         </description>
 595         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML.h" define="ARMv8MML"/>
 596       </device>
 597
 598       <device Dname="ARMv8MML_DSP">
 599         <processor Dcore="ARMV8MML" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 600         <description>
 601           DSP Instructions, no Floating Point Unit, TrustZone
 602         </description>
 603         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DSP.h" define="ARMv8MML_DSP"/>
 604       </device>
 605
 606       <device Dname="ARMv8MML_SP">
 607         <processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 608         <description>
 609           no DSP Instructions, Single Precision Floating Point Unit, TrustZone
 610         </description>
 611         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_SP.h" define="ARMv8MML_SP"/>
 612       </device>
 613
 614       <device Dname="ARMv8MML_DSP_SP">
 615         <processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 616         <description>
 617           DSP Instructions, Single Precision Floating Point Unit, TrustZone
 618         </description>
 619         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_SP.h" define="ARMv8MML_DSP_SP"/>
 620       </device>
 621
 622       <device Dname="ARMv8MML_DP">
 623         <processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="DP_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 624         <description>
 625           no DSP Instructions, Double Precision Floating Point Unit, TrustZone
 626         </description>
 627         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DP.h" define="ARMv8MML_DP"/>
 628       </device>
 629
 630       <device Dname="ARMv8MML_DSP_DP">
 631         <processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="DP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 632         <description>
 633           DSP Instructions, Double Precision Floating Point Unit, TrustZone
 634         </description>
 635         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h" define="ARMv8MML_DSP_DP"/>
 636       </device>
 637     </family>
 638
 639     <!-- ******************************  Cortex-A5  ****************************** -->
 640     <family Dfamily="ARM Cortex A5" Dvendor="ARM:82">
 641       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0433c/index.html" title="Cortex-A5 Technical Reference Manual"/>
 642       <description>
 643 The Arm Cortex-A5 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full
 644 virtual memory capabilities. The Cortex-A5 processor implements the Armv7-A architecture profile and can execute 32-bit
 645 Arm instructions and 16-bit and 32-bit Thumb instructions. The Cortex-A5 is the smallest member of the Cortex-A processor family.
 646       </description>
 647
 648       <memory id="IROM1"                                start="0x80000000" size="0x00200000" startup="1" default="1"/>
 649       <memory id="IRAM1"                                start="0x80200000" size="0x00200000" init   ="0" default="1"/>
 650
 651       <device Dname="ARMCA5">
 652         <processor Dcore="Cortex-A5" DcoreVersion="r0p1" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable"/>
 653         <compile header="Device/ARM/ARMCA5/Include/ARMCA5.h" define="ARMCA5"/>
 654       </device>
 655     </family>
 656
 657     <!-- ******************************  Cortex-A7  ****************************** -->
 658     <family Dfamily="ARM Cortex A7" Dvendor="ARM:82">
 659       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/index.html" title="Cortex-A7 MPCore Technical Reference Manual"/>
 660       <description>
 661 The Cortex-A7 MPCore processor is a high-performance, low-power processor that implements the Armv7-A architecture.
 662 The Cortex-A7 MPCore processor has one to four processors in a single multiprocessor device with a L1 cache subsystem,
 663 an optional integrated GIC, and an optional L2 cache controller.
 664       </description>
 665
 666       <memory id="IROM1"                                start="0x80000000" size="0x00200000" startup="1" default="1"/>
 667       <memory id="IRAM1"                                start="0x80200000" size="0x00200000" init   ="0" default="1"/>
 668
 669       <device Dname="ARMCA7">
 670         <processor Dcore="Cortex-A7" DcoreVersion="r0p5" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable"/>
 671         <compile header="Device/ARM/ARMCA7/Include/ARMCA7.h" define="ARMCA7"/>
 672       </device>
 673     </family>
 674
 675     <!-- ******************************  Cortex-A9  ****************************** -->
 676     <family Dfamily="ARM Cortex A9" Dvendor="ARM:82">
 677       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.100511_0401_10_en/index.html" title="Cortex-A9 Technical Reference Manual"/>
 678       <description>
 679 The Cortex-A9 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full virtual memory capabilities.
 680 The Cortex-A9 processor implements the Armv7-A architecture and runs 32-bit Arm instructions, 16-bit and 32-bit Thumb instructions,
 681 and 8-bit Java bytecodes in Jazelle state.
 682       </description>
 683
 684       <memory id="IROM1"                                start="0x80000000" size="0x00200000" startup="1" default="1"/>
 685       <memory id="IRAM1"                                start="0x80200000" size="0x00200000" init   ="0" default="1"/>
 686
 687       <device Dname="ARMCA9">
 688         <processor Dcore="Cortex-A9" DcoreVersion="r4p1" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable"/>
 689         <compile header="Device/ARM/ARMCA9/Include/ARMCA9.h" define="ARMCA9"/>
 690       </device>
 691     </family>
 692   </devices>
 693
 694
 695   <apis>
 696     <!-- CMSIS Device API -->
 697     <api Cclass="Device" Cgroup="IRQ Controller" Capiversion="1.0.0" exclusive="1">
 698       <description>Device interrupt controller interface</description>
 699       <files>
 700         <file category="header" name="CMSIS/Core_A/Include/irq_ctrl.h"/>
 701       </files>
 702     </api>
 703     <api Cclass="Device" Cgroup="OS Tick" Capiversion="1.0.1" exclusive="1">
 704       <description>RTOS Kernel system tick timer interface</description>
 705       <files>
 706         <file category="header" name="CMSIS/RTOS2/Include/os_tick.h"/>
 707       </files>
 708     </api>
 709     <!-- CMSIS-RTOS API -->
 710     <api Cclass="CMSIS" Cgroup="RTOS" Capiversion="1.0.0" exclusive="1">
 711       <description>CMSIS-RTOS API for Cortex-M, SC000, and SC300</description>
 712       <files>
 713         <file category="doc" name="CMSIS/Documentation/RTOS/html/index.html"/>
 714       </files>
 715     </api>
 716     <api Cclass="CMSIS" Cgroup="RTOS2" Capiversion="2.1.3" exclusive="1">
 717       <description>CMSIS-RTOS API for Cortex-M, SC000, and SC300</description>
 718       <files>
 719         <file category="doc" name="CMSIS/Documentation/RTOS2/html/index.html"/>
 720         <file category="header" name="CMSIS/RTOS2/Include/cmsis_os2.h"/>
 721       </files>
 722     </api>
 723     <!-- CMSIS Driver API -->
 724     <api Cclass="CMSIS Driver" Cgroup="USART" Capiversion="2.3.0" exclusive="0">
 725       <description>USART Driver API for Cortex-M</description>
 726       <files>
 727         <file category="doc" name="CMSIS/Documentation/Driver/html/group__usart__interface__gr.html" />
 728         <file category="header" name="CMSIS/Driver/Include/Driver_USART.h" />
 729       </files>
 730     </api>
 731     <api Cclass="CMSIS Driver" Cgroup="SPI" Capiversion="2.2.0" exclusive="0">
 732       <description>SPI Driver API for Cortex-M</description>
 733       <files>
 734         <file category="doc" name="CMSIS/Documentation/Driver/html/group__spi__interface__gr.html" />
 735         <file category="header" name="CMSIS/Driver/Include/Driver_SPI.h" />
 736       </files>
 737     </api>
 738     <api Cclass="CMSIS Driver" Cgroup="SAI" Capiversion="1.1.0" exclusive="0">
 739       <description>SAI Driver API for Cortex-M</description>
 740       <files>
 741         <file category="doc" name="CMSIS/Documentation/Driver/html/group__sai__interface__gr.html"/>
 742         <file category="header" name="CMSIS/Driver/Include/Driver_SAI.h" />
 743       </files>
 744     </api>
 745     <api Cclass="CMSIS Driver" Cgroup="I2C" Capiversion="2.3.0" exclusive="0">
 746       <description>I2C Driver API for Cortex-M</description>
 747       <files>
 748         <file category="doc" name="CMSIS/Documentation/Driver/html/group__i2c__interface__gr.html"/>
 749         <file category="header" name="CMSIS/Driver/Include/Driver_I2C.h" />
 750       </files>
 751     </api>
 752     <api Cclass="CMSIS Driver" Cgroup="CAN" Capiversion="1.2.0" exclusive="0">
 753       <description>CAN Driver API for Cortex-M</description>
 754       <files>
 755         <file category="doc" name="CMSIS/Documentation/Driver/html/group__can__interface__gr.html"/>
 756         <file category="header" name="CMSIS/Driver/Include/Driver_CAN.h" />
 757       </files>
 758     </api>
 759     <api Cclass="CMSIS Driver" Cgroup="Flash" Capiversion="2.2.0" exclusive="0">
 760       <description>Flash Driver API for Cortex-M</description>
 761       <files>
 762         <file category="doc" name="CMSIS/Documentation/Driver/html/group__flash__interface__gr.html" />
 763         <file category="header" name="CMSIS/Driver/Include/Driver_Flash.h" />
 764       </files>
 765     </api>
 766     <api Cclass="CMSIS Driver" Cgroup="MCI" Capiversion="2.3.0" exclusive="0">
 767       <description>MCI Driver API for Cortex-M</description>
 768       <files>
 769         <file category="doc" name="CMSIS/Documentation/Driver/html/group__mci__interface__gr.html" />
 770         <file category="header" name="CMSIS/Driver/Include/Driver_MCI.h" />
 771       </files>
 772     </api>
 773     <api Cclass="CMSIS Driver" Cgroup="NAND" Capiversion="2.3.0" exclusive="0">
 774       <description>NAND Flash Driver API for Cortex-M</description>
 775       <files>
 776         <file category="doc" name="CMSIS/Documentation/Driver/html/group__nand__interface__gr.html" />
 777         <file category="header" name="CMSIS/Driver/Include/Driver_NAND.h" />
 778       </files>
 779     </api>
 780     <api Cclass="CMSIS Driver" Cgroup="Ethernet" Capiversion="2.1.0" exclusive="0">
 781       <description>Ethernet MAC and PHY Driver API for Cortex-M</description>
 782       <files>
 783         <file category="doc" name="CMSIS/Documentation/Driver/html/group__eth__interface__gr.html" />
 784         <file category="header" name="CMSIS/Driver/Include/Driver_ETH_MAC.h" />
 785         <file category="header" name="CMSIS/Driver/Include/Driver_ETH_PHY.h" />
 786       </files>
 787     </api>
 788     <api Cclass="CMSIS Driver" Cgroup="Ethernet MAC" Capiversion="2.1.0" exclusive="0">
 789       <description>Ethernet MAC Driver API for Cortex-M</description>
 790       <files>
 791         <file category="doc" name="CMSIS/Documentation/Driver/html/group__eth__mac__interface__gr.html" />
 792         <file category="header" name="CMSIS/Driver/Include/Driver_ETH_MAC.h" />
 793       </files>
 794     </api>
 795     <api Cclass="CMSIS Driver" Cgroup="Ethernet PHY" Capiversion="2.1.0" exclusive="0">
 796       <description>Ethernet PHY Driver API for Cortex-M</description>
 797       <files>
 798         <file category="doc" name="CMSIS/Documentation/Driver/html/group__eth__phy__interface__gr.html" />
 799         <file category="header" name="CMSIS/Driver/Include/Driver_ETH_PHY.h" />
 800       </files>
 801     </api>
 802     <api Cclass="CMSIS Driver" Cgroup="USB Device" Capiversion="2.2.0" exclusive="0">
 803       <description>USB Device Driver API for Cortex-M</description>
 804       <files>
 805         <file category="doc" name="CMSIS/Documentation/Driver/html/group__usbd__interface__gr.html" />
 806         <file category="header" name="CMSIS/Driver/Include/Driver_USBD.h" />
 807       </files>
 808     </api>
 809     <api Cclass="CMSIS Driver" Cgroup="USB Host" Capiversion="2.2.0" exclusive="0">
 810       <description>USB Host Driver API for Cortex-M</description>
 811       <files>
 812         <file category="doc" name="CMSIS/Documentation/Driver/html/group__usbh__interface__gr.html" />
 813         <file category="header" name="CMSIS/Driver/Include/Driver_USBH.h" />
 814       </files>
 815     </api>
 816   </apis>
 817
 818   <!-- conditions are dependency rules that can apply to a component or an individual file -->
 819   <conditions>
 820     <!-- compiler -->
 821     <condition id="ARMCC6">
 822       <accept Tcompiler="ARMCC" Toptions="AC6"/>
 823       <accept Tcompiler="ARMCC" Toptions="AC6LTO"/>
 824     </condition>
 825     <condition id="ARMCC5">
 826       <require Tcompiler="ARMCC" Toptions="AC5"/>
 827     </condition>
 828     <condition id="ARMCC">
 829       <require Tcompiler="ARMCC"/>
 830     </condition>
 831     <condition id="GCC">
 832       <require Tcompiler="GCC"/>
 833     </condition>
 834     <condition id="IAR">
 835       <require Tcompiler="IAR"/>
 836     </condition>
 837     <condition id="ARMCC GCC">
 838       <accept Tcompiler="ARMCC"/>
 839       <accept Tcompiler="GCC"/>
 840     </condition>
 841     <condition id="ARMCC GCC IAR">
 842       <accept Tcompiler="ARMCC"/>
 843       <accept Tcompiler="GCC"/>
 844       <accept Tcompiler="IAR"/>
 845     </condition>
 846
 847     <!-- Arm architecture -->
 848     <condition id="ARMv6-M Device">
 849       <description>Armv6-M architecture based device</description>
 850       <accept Dcore="Cortex-M0"/>
 851       <accept Dcore="Cortex-M1"/>
 852       <accept Dcore="Cortex-M0+"/>
 853       <accept Dcore="SC000"/>
 854     </condition>
 855     <condition id="ARMv7-M Device">
 856       <description>Armv7-M architecture based device</description>
 857       <accept Dcore="Cortex-M3"/>
 858       <accept Dcore="Cortex-M4"/>
 859       <accept Dcore="Cortex-M7"/>
 860       <accept Dcore="SC300"/>
 861     </condition>
 862     <condition id="ARMv8-M Device">
 863       <description>Armv8-M architecture based device</description>
 864       <accept Dcore="ARMV8MBL"/>
 865       <accept Dcore="ARMV8MML"/>
 866       <accept Dcore="Cortex-M23"/>
 867       <accept Dcore="Cortex-M33"/>
 868       <accept Dcore="Cortex-M35P"/>
 869     </condition>
 870     <condition id="ARMv8-M TZ Device">
 871       <description>Armv8-M architecture based device with TrustZone</description>
 872       <require condition="ARMv8-M Device"/>
 873       <require Dtz="TZ"/>
 874     </condition>
 875     <condition id="ARMv6_7-M Device">
 876       <description>Armv6_7-M architecture based device</description>
 877       <accept condition="ARMv6-M Device"/>
 878       <accept condition="ARMv7-M Device"/>
 879     </condition>
 880     <condition id="ARMv6_7_8-M Device">
 881       <description>Armv6_7_8-M architecture based device</description>
 882       <accept condition="ARMv6-M Device"/>
 883       <accept condition="ARMv7-M Device"/>
 884       <accept condition="ARMv8-M Device"/>
 885     </condition>
 886     <condition id="ARMv7-A Device">
 887       <description>Armv7-A architecture based device</description>
 888       <accept Dcore="Cortex-A5"/>
 889       <accept Dcore="Cortex-A7"/>
 890       <accept Dcore="Cortex-A9"/>
 891     </condition>
 892
 893     <!-- ARM core -->
 894     <condition id="CM0">
 895       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device</description>
 896       <accept Dcore="Cortex-M0"/>
 897       <accept Dcore="Cortex-M0+"/>
 898       <accept Dcore="SC000"/>
 899     </condition>
 900     <condition id="CM1">
 901       <description>Cortex-M1</description>
 902       <require Dcore="Cortex-M1"/>
 903     </condition>
 904     <condition id="CM3">
 905       <description>Cortex-M3 or SC300 processor based device</description>
 906       <accept Dcore="Cortex-M3"/>
 907       <accept Dcore="SC300"/>
 908     </condition>
 909     <condition id="CM4">
 910       <description>Cortex-M4 processor based device</description>
 911       <require Dcore="Cortex-M4" Dfpu="NO_FPU"/>
 912     </condition>
 913     <condition id="CM4_FP">
 914       <description>Cortex-M4 processor based device using Floating Point Unit</description>
 915       <accept Dcore="Cortex-M4" Dfpu="FPU"/>
 916       <accept Dcore="Cortex-M4" Dfpu="SP_FPU"/>
 917       <accept Dcore="Cortex-M4" Dfpu="DP_FPU"/>
 918     </condition>
 919     <condition id="CM7">
 920       <description>Cortex-M7 processor based device</description>
 921       <require Dcore="Cortex-M7" Dfpu="NO_FPU"/>
 922     </condition>
 923     <condition id="CM7_FP">
 924       <description>Cortex-M7 processor based device using Floating Point Unit</description>
 925       <accept Dcore="Cortex-M7" Dfpu="SP_FPU"/>
 926       <accept Dcore="Cortex-M7" Dfpu="DP_FPU"/>
 927     </condition>
 928     <condition id="CM7_SP">
 929       <description>Cortex-M7 processor based device using Floating Point Unit (SP)</description>
 930       <require Dcore="Cortex-M7" Dfpu="SP_FPU"/>
 931     </condition>
 932     <condition id="CM7_DP">
 933       <description>Cortex-M7 processor based device using Floating Point Unit (DP)</description>
 934       <require Dcore="Cortex-M7" Dfpu="DP_FPU"/>
 935     </condition>
 936     <condition id="CM23">
 937       <description>Cortex-M23 processor based device</description>
 938       <require Dcore="Cortex-M23"/>
 939     </condition>
 940     <condition id="CM33">
 941       <description>Cortex-M33 processor based device</description>
 942       <require Dcore="Cortex-M33" Dfpu="NO_FPU"/>
 943     </condition>
 944     <condition id="CM33_FP">
 945       <description>Cortex-M33 processor based device using Floating Point Unit</description>
 946       <require Dcore="Cortex-M33" Dfpu="SP_FPU"/>
 947     </condition>
 948     <condition id="CM35P">
 949       <description>Cortex-M35P processor based device</description>
 950       <require Dcore="Cortex-M35P" Dfpu="NO_FPU"/>
 951     </condition>
 952     <condition id="CM35P_FP">
 953       <description>Cortex-M35P processor based device using Floating Point Unit</description>
 954       <require Dcore="Cortex-M35P" Dfpu="SP_FPU"/>
 955     </condition>
 956     <condition id="ARMv8MBL">
 957       <description>Armv8-M Baseline processor based device</description>
 958       <require Dcore="ARMV8MBL"/>
 959     </condition>
 960     <condition id="ARMv8MML">
 961       <description>Armv8-M Mainline processor based device</description>
 962       <require Dcore="ARMV8MML" Dfpu="NO_FPU"/>
 963     </condition>
 964     <condition id="ARMv8MML_FP">
 965       <description>Armv8-M Mainline processor based device using Floating Point Unit</description>
 966       <accept Dcore="ARMV8MML" Dfpu="SP_FPU"/>
 967       <accept Dcore="ARMV8MML" Dfpu="DP_FPU"/>
 968     </condition>
 969
 970     <condition id="CM33_NODSP_NOFPU">
 971       <description>CM33, no DSP, no FPU</description>
 972       <require Dcore="Cortex-M33" Ddsp="NO_DSP" Dfpu="NO_FPU"/>
 973     </condition>
 974     <condition id="CM33_DSP_NOFPU">
 975       <description>CM33, DSP, no FPU</description>
 976       <require Dcore="Cortex-M33" Ddsp="DSP" Dfpu="NO_FPU"/>
 977     </condition>
 978     <condition id="CM33_NODSP_SP">
 979       <description>CM33, no DSP, SP FPU</description>
 980       <require Dcore="Cortex-M33" Ddsp="NO_DSP" Dfpu="SP_FPU"/>
 981     </condition>
 982     <condition id="CM33_DSP_SP">
 983       <description>CM33, DSP, SP FPU</description>
 984       <require Dcore="Cortex-M33" Ddsp="DSP" Dfpu="SP_FPU"/>
 985     </condition>
 986
 987     <condition id="CM35P_NODSP_NOFPU">
 988       <description>CM35P, no DSP, no FPU</description>
 989       <require Dcore="Cortex-M35P" Ddsp="NO_DSP" Dfpu="NO_FPU"/>
 990     </condition>
 991     <condition id="CM35P_DSP_NOFPU">
 992       <description>CM35P, DSP, no FPU</description>
 993       <require Dcore="Cortex-M35P" Ddsp="DSP" Dfpu="NO_FPU"/>
 994     </condition>
 995     <condition id="CM35P_NODSP_SP">
 996       <description>CM35P, no DSP, SP FPU</description>
 997       <require Dcore="Cortex-M35P" Ddsp="NO_DSP" Dfpu="SP_FPU"/>
 998     </condition>
 999     <condition id="CM35P_DSP_SP">
1000       <description>CM35P, DSP, SP FPU</description>
1001       <require Dcore="Cortex-M35P" Ddsp="DSP" Dfpu="SP_FPU"/>
1002     </condition>
1003
1004     <condition id="ARMv8MML_NODSP_NOFPU">
1005       <description>Armv8-M Mainline, no DSP, no FPU</description>
1006       <require Dcore="ARMV8MML" Ddsp="NO_DSP" Dfpu="NO_FPU"/>
1007     </condition>
1008     <condition id="ARMv8MML_DSP_NOFPU">
1009       <description>Armv8-M Mainline, DSP, no FPU</description>
1010       <require Dcore="ARMV8MML" Ddsp="DSP" Dfpu="NO_FPU"/>
1011     </condition>
1012     <condition id="ARMv8MML_NODSP_SP">
1013       <description>Armv8-M Mainline, no DSP, SP FPU</description>
1014       <require Dcore="ARMV8MML" Ddsp="NO_DSP" Dfpu="SP_FPU"/>
1015     </condition>
1016     <condition id="ARMv8MML_DSP_SP">
1017       <description>Armv8-M Mainline, DSP, SP FPU</description>
1018       <require Dcore="ARMV8MML" Ddsp="DSP" Dfpu="SP_FPU"/>
1019     </condition>
1020
1021     <condition id="CA5_CA9">
1022       <description>Cortex-A5 or Cortex-A9 processor based device</description>
1023       <accept Dcore="Cortex-A5"/>
1024       <accept Dcore="Cortex-A9"/>
1025     </condition>
1026
1027     <condition id="CA7">
1028       <description>Cortex-A7 processor based device</description>
1029       <accept Dcore="Cortex-A7"/>
1030     </condition>
1031
1032     <!-- ARMCC compiler -->
1033     <condition id="CA_ARMCC5">
1034       <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the Arm Compiler 5</description>
1035       <require condition="ARMv7-A Device"/>
1036       <require condition="ARMCC5"/>
1037     </condition>
1038     <condition id="CA_ARMCC6">
1039       <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the Arm Compiler 6</description>
1040       <require condition="ARMv7-A Device"/>
1041       <require condition="ARMCC6"/>
1042     </condition>
1043
1044     <condition id="CM0_ARMCC">
1045       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device for the Arm Compiler</description>
1046       <require condition="CM0"/>
1047       <require Tcompiler="ARMCC"/>
1048     </condition>
1049     <condition id="CM0_LE_ARMCC">
1050       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the Arm Compiler</description>
1051       <require condition="CM0_ARMCC"/>
1052       <require Dendian="Little-endian"/>
1053     </condition>
1054     <condition id="CM0_BE_ARMCC">
1055       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the Arm Compiler</description>
1056       <require condition="CM0_ARMCC"/>
1057       <require Dendian="Big-endian"/>
1058     </condition>
1059
1060     <condition id="CM1_ARMCC">
1061       <description>Cortex-M1 based device for the Arm Compiler</description>
1062       <require condition="CM1"/>
1063       <require Tcompiler="ARMCC"/>
1064     </condition>
1065     <condition id="CM1_LE_ARMCC">
1066       <description>Cortex-M1 based device in little endian mode for the Arm Compiler</description>
1067       <require condition="CM1_ARMCC"/>
1068       <require Dendian="Little-endian"/>
1069     </condition>
1070     <condition id="CM1_BE_ARMCC">
1071       <description>Cortex-M1 based device in big endian mode for the Arm Compiler</description>
1072       <require condition="CM1_ARMCC"/>
1073       <require Dendian="Big-endian"/>
1074     </condition>
1075
1076     <condition id="CM3_ARMCC">
1077       <description>Cortex-M3 or SC300 processor based device for the Arm Compiler</description>
1078       <require condition="CM3"/>
1079       <require Tcompiler="ARMCC"/>
1080     </condition>
1081     <condition id="CM3_LE_ARMCC">
1082       <description>Cortex-M3 or SC300 processor based device in little endian mode for the Arm Compiler</description>
1083       <require condition="CM3_ARMCC"/>
1084       <require Dendian="Little-endian"/>
1085     </condition>
1086     <condition id="CM3_BE_ARMCC">
1087       <description>Cortex-M3 or SC300 processor based device in big endian mode for the Arm Compiler</description>
1088       <require condition="CM3_ARMCC"/>
1089       <require Dendian="Big-endian"/>
1090     </condition>
1091
1092     <condition id="CM4_ARMCC">
1093       <description>Cortex-M4 processor based device for the Arm Compiler</description>
1094       <require condition="CM4"/>
1095       <require Tcompiler="ARMCC"/>
1096     </condition>
1097     <condition id="CM4_LE_ARMCC">
1098       <description>Cortex-M4 processor based device in little endian mode for the Arm Compiler</description>
1099       <require condition="CM4_ARMCC"/>
1100       <require Dendian="Little-endian"/>
1101     </condition>
1102     <condition id="CM4_BE_ARMCC">
1103       <description>Cortex-M4 processor based device in big endian mode for the Arm Compiler</description>
1104       <require condition="CM4_ARMCC"/>
1105       <require Dendian="Big-endian"/>
1106     </condition>
1107
1108     <condition id="CM4_FP_ARMCC">
1109       <description>Cortex-M4 processor based device using Floating Point Unit for the Arm Compiler</description>
1110       <require condition="CM4_FP"/>
1111       <require Tcompiler="ARMCC"/>
1112     </condition>
1113     <condition id="CM4_FP_LE_ARMCC">
1114       <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
1115       <require condition="CM4_FP_ARMCC"/>
1116       <require Dendian="Little-endian"/>
1117     </condition>
1118     <condition id="CM4_FP_BE_ARMCC">
1119       <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
1120       <require condition="CM4_FP_ARMCC"/>
1121       <require Dendian="Big-endian"/>
1122     </condition>
1123
1124     <condition id="CM7_ARMCC">
1125       <description>Cortex-M7 processor based device for the Arm Compiler</description>
1126       <require condition="CM7"/>
1127       <require Tcompiler="ARMCC"/>
1128     </condition>
1129     <condition id="CM7_LE_ARMCC">
1130       <description>Cortex-M7 processor based device in little endian mode for the Arm Compiler</description>
1131       <require condition="CM7_ARMCC"/>
1132       <require Dendian="Little-endian"/>
1133     </condition>
1134     <condition id="CM7_BE_ARMCC">
1135       <description>Cortex-M7 processor based device in big endian mode for the Arm Compiler</description>
1136       <require condition="CM7_ARMCC"/>
1137       <require Dendian="Big-endian"/>
1138     </condition>
1139
1140     <condition id="CM7_FP_ARMCC">
1141       <description>Cortex-M7 processor based device using Floating Point Unit for the Arm Compiler</description>
1142       <require condition="CM7_FP"/>
1143       <require Tcompiler="ARMCC"/>
1144     </condition>
1145     <condition id="CM7_FP_LE_ARMCC">
1146       <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
1147       <require condition="CM7_FP_ARMCC"/>
1148       <require Dendian="Little-endian"/>
1149     </condition>
1150     <condition id="CM7_FP_BE_ARMCC">
1151       <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
1152       <require condition="CM7_FP_ARMCC"/>
1153       <require Dendian="Big-endian"/>
1154     </condition>
1155
1156     <condition id="CM7_SP_ARMCC">
1157       <description>Cortex-M7 processor based device using Floating Point Unit (SP) for the Arm Compiler</description>
1158       <require condition="CM7_SP"/>
1159       <require Tcompiler="ARMCC"/>
1160     </condition>
1161     <condition id="CM7_SP_LE_ARMCC">
1162       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the Arm Compiler</description>
1163       <require condition="CM7_SP_ARMCC"/>
1164       <require Dendian="Little-endian"/>
1165     </condition>
1166     <condition id="CM7_SP_BE_ARMCC">
1167       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the Arm Compiler</description>
1168       <require condition="CM7_SP_ARMCC"/>
1169       <require Dendian="Big-endian"/>
1170     </condition>
1171
1172     <condition id="CM7_DP_ARMCC">
1173       <description>Cortex-M7 processor based device using Floating Point Unit (DP) for the Arm Compiler</description>
1174       <require condition="CM7_DP"/>
1175       <require Tcompiler="ARMCC"/>
1176     </condition>
1177     <condition id="CM7_DP_LE_ARMCC">
1178       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the Arm Compiler</description>
1179       <require condition="CM7_DP_ARMCC"/>
1180       <require Dendian="Little-endian"/>
1181     </condition>
1182     <condition id="CM7_DP_BE_ARMCC">
1183       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the Arm Compiler</description>
1184       <require condition="CM7_DP_ARMCC"/>
1185       <require Dendian="Big-endian"/>
1186     </condition>
1187
1188     <condition id="CM23_ARMCC">
1189       <description>Cortex-M23 processor based device for the Arm Compiler</description>
1190       <require condition="CM23"/>
1191       <require Tcompiler="ARMCC"/>
1192     </condition>
1193     <condition id="CM23_LE_ARMCC">
1194       <description>Cortex-M23 processor based device in little endian mode for the Arm Compiler</description>
1195       <require condition="CM23_ARMCC"/>
1196       <require Dendian="Little-endian"/>
1197     </condition>
1198     <condition id="CM23_BE_ARMCC">
1199       <description>Cortex-M23 processor based device in big endian mode for the Arm Compiler</description>
1200       <require condition="CM23_ARMCC"/>
1201       <require Dendian="Big-endian"/>
1202     </condition>
1203
1204     <condition id="CM33_ARMCC">
1205       <description>Cortex-M33 processor based device for the Arm Compiler</description>
1206       <require condition="CM33"/>
1207       <require Tcompiler="ARMCC"/>
1208     </condition>
1209     <condition id="CM33_LE_ARMCC">
1210       <description>Cortex-M33 processor based device in little endian mode for the Arm Compiler</description>
1211       <require condition="CM33_ARMCC"/>
1212       <require Dendian="Little-endian"/>
1213     </condition>
1214     <condition id="CM33_BE_ARMCC">
1215       <description>Cortex-M33 processor based device in big endian mode for the Arm Compiler</description>
1216       <require condition="CM33_ARMCC"/>
1217       <require Dendian="Big-endian"/>
1218     </condition>
1219
1220     <condition id="CM33_FP_ARMCC">
1221       <description>Cortex-M33 processor based device using Floating Point Unit for the Arm Compiler</description>
1222       <require condition="CM33_FP"/>
1223       <require Tcompiler="ARMCC"/>
1224     </condition>
1225     <condition id="CM33_FP_LE_ARMCC">
1226       <description>Cortex-M33 processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
1227       <require condition="CM33_FP_ARMCC"/>
1228       <require Dendian="Little-endian"/>
1229     </condition>
1230     <condition id="CM33_FP_BE_ARMCC">
1231       <description>Cortex-M33 processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
1232       <require condition="CM33_FP_ARMCC"/>
1233       <require Dendian="Big-endian"/>
1234     </condition>
1235
1236     <condition id="CM33_NODSP_NOFPU_ARMCC">
1237       <description>Cortex-M33 processor, no DSP, no FPU, Arm Compiler</description>
1238       <require condition="CM33_NODSP_NOFPU"/>
1239       <require Tcompiler="ARMCC"/>
1240     </condition>
1241     <condition id="CM33_DSP_NOFPU_ARMCC">
1242       <description>Cortex-M33 processor, DSP, no FPU, Arm Compiler</description>
1243       <require condition="CM33_DSP_NOFPU"/>
1244       <require Tcompiler="ARMCC"/>
1245     </condition>
1246     <condition id="CM33_NODSP_SP_ARMCC">
1247       <description>Cortex-M33 processor, no DSP, SP FPU, Arm Compiler</description>
1248       <require condition="CM33_NODSP_SP"/>
1249       <require Tcompiler="ARMCC"/>
1250     </condition>
1251     <condition id="CM33_DSP_SP_ARMCC">
1252       <description>Cortex-M33 processor, DSP, SP FPU, Arm Compiler</description>
1253       <require condition="CM33_DSP_SP"/>
1254       <require Tcompiler="ARMCC"/>
1255     </condition>
1256     <condition id="CM33_NODSP_NOFPU_LE_ARMCC">
1257       <description>Cortex-M33 processor, little endian, no DSP, no FPU, Arm Compiler</description>
1258       <require condition="CM33_NODSP_NOFPU_ARMCC"/>
1259       <require Dendian="Little-endian"/>
1260     </condition>
1261     <condition id="CM33_DSP_NOFPU_LE_ARMCC">
1262       <description>Cortex-M33 processor, little endian, DSP, no FPU, Arm Compiler</description>
1263       <require condition="CM33_DSP_NOFPU_ARMCC"/>
1264       <require Dendian="Little-endian"/>
1265     </condition>
1266     <condition id="CM33_NODSP_SP_LE_ARMCC">
1267       <description>Cortex-M33 processor, little endian, no DSP, SP FPU, Arm Compiler</description>
1268       <require condition="CM33_NODSP_SP_ARMCC"/>
1269       <require Dendian="Little-endian"/>
1270     </condition>
1271     <condition id="CM33_DSP_SP_LE_ARMCC">
1272       <description>Cortex-M33 processor, little endian, DSP, SP FPU, Arm Compiler</description>
1273       <require condition="CM33_DSP_SP_ARMCC"/>
1274       <require Dendian="Little-endian"/>
1275     </condition>
1276
1277     <condition id="CM35P_ARMCC">
1278       <description>Cortex-M35P processor based device for the Arm Compiler</description>
1279       <require condition="CM35P"/>
1280       <require Tcompiler="ARMCC"/>
1281     </condition>
1282     <condition id="CM35P_LE_ARMCC">
1283       <description>Cortex-M35P processor based device in little endian mode for the Arm Compiler</description>
1284       <require condition="CM35P_ARMCC"/>
1285       <require Dendian="Little-endian"/>
1286     </condition>
1287     <condition id="CM35P_BE_ARMCC">
1288       <description>Cortex-M35P processor based device in big endian mode for the Arm Compiler</description>
1289       <require condition="CM35P_ARMCC"/>
1290       <require Dendian="Big-endian"/>
1291     </condition>
1292
1293     <condition id="CM35P_FP_ARMCC">
1294       <description>Cortex-M35P processor based device using Floating Point Unit for the Arm Compiler</description>
1295       <require condition="CM35P_FP"/>
1296       <require Tcompiler="ARMCC"/>
1297     </condition>
1298     <condition id="CM35P_FP_LE_ARMCC">
1299       <description>Cortex-M35P processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
1300       <require condition="CM35P_FP_ARMCC"/>
1301       <require Dendian="Little-endian"/>
1302     </condition>
1303     <condition id="CM35P_FP_BE_ARMCC">
1304       <description>Cortex-M35P processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
1305       <require condition="CM35P_FP_ARMCC"/>
1306       <require Dendian="Big-endian"/>
1307     </condition>
1308
1309     <condition id="CM35P_NODSP_NOFPU_ARMCC">
1310       <description>Cortex-M35P processor, no DSP, no FPU, Arm Compiler</description>
1311       <require condition="CM35P_NODSP_NOFPU"/>
1312       <require Tcompiler="ARMCC"/>
1313     </condition>
1314     <condition id="CM35P_DSP_NOFPU_ARMCC">
1315       <description>Cortex-M35P processor, DSP, no FPU, Arm Compiler</description>
1316       <require condition="CM35P_DSP_NOFPU"/>
1317       <require Tcompiler="ARMCC"/>
1318     </condition>
1319     <condition id="CM35P_NODSP_SP_ARMCC">
1320       <description>Cortex-M35P processor, no DSP, SP FPU, Arm Compiler</description>
1321       <require condition="CM35P_NODSP_SP"/>
1322       <require Tcompiler="ARMCC"/>
1323     </condition>
1324     <condition id="CM35P_DSP_SP_ARMCC">
1325       <description>Cortex-M35P processor, DSP, SP FPU, Arm Compiler</description>
1326       <require condition="CM35P_DSP_SP"/>
1327       <require Tcompiler="ARMCC"/>
1328     </condition>
1329     <condition id="CM35P_NODSP_NOFPU_LE_ARMCC">
1330       <description>Cortex-M35P processor, little endian, no DSP, no FPU, Arm Compiler</description>
1331       <require condition="CM35P_NODSP_NOFPU_ARMCC"/>
1332       <require Dendian="Little-endian"/>
1333     </condition>
1334     <condition id="CM35P_DSP_NOFPU_LE_ARMCC">
1335       <description>Cortex-M35P processor, little endian, DSP, no FPU, Arm Compiler</description>
1336       <require condition="CM35P_DSP_NOFPU_ARMCC"/>
1337       <require Dendian="Little-endian"/>
1338     </condition>
1339     <condition id="CM35P_NODSP_SP_LE_ARMCC">
1340       <description>Cortex-M35P processor, little endian, no DSP, SP FPU, Arm Compiler</description>
1341       <require condition="CM35P_NODSP_SP_ARMCC"/>
1342       <require Dendian="Little-endian"/>
1343     </condition>
1344     <condition id="CM35P_DSP_SP_LE_ARMCC">
1345       <description>Cortex-M35P processor, little endian, DSP, SP FPU, Arm Compiler</description>
1346       <require condition="CM35P_DSP_SP_ARMCC"/>
1347       <require Dendian="Little-endian"/>
1348     </condition>
1349
1350     <condition id="ARMv8MBL_ARMCC">
1351       <description>Armv8-M Baseline processor based device for the Arm Compiler</description>
1352       <require condition="ARMv8MBL"/>
1353       <require Tcompiler="ARMCC"/>
1354     </condition>
1355     <condition id="ARMv8MBL_LE_ARMCC">
1356       <description>Armv8-M Baseline processor based device in little endian mode for the Arm Compiler</description>
1357       <require condition="ARMv8MBL_ARMCC"/>
1358       <require Dendian="Little-endian"/>
1359     </condition>
1360     <condition id="ARMv8MBL_BE_ARMCC">
1361       <description>Armv8-M Baseline processor based device in big endian mode for the Arm Compiler</description>
1362       <require condition="ARMv8MBL_ARMCC"/>
1363       <require Dendian="Big-endian"/>
1364     </condition>
1365
1366     <condition id="ARMv8MML_ARMCC">
1367       <description>Armv8-M Mainline processor based device for the Arm Compiler</description>
1368       <require condition="ARMv8MML"/>
1369       <require Tcompiler="ARMCC"/>
1370     </condition>
1371     <condition id="ARMv8MML_LE_ARMCC">
1372       <description>Armv8-M Mainline processor based device in little endian mode for the Arm Compiler</description>
1373       <require condition="ARMv8MML_ARMCC"/>
1374       <require Dendian="Little-endian"/>
1375     </condition>
1376     <condition id="ARMv8MML_BE_ARMCC">
1377       <description>Armv8-M Mainline processor based device in big endian mode for the Arm Compiler</description>
1378       <require condition="ARMv8MML_ARMCC"/>
1379       <require Dendian="Big-endian"/>
1380     </condition>
1381
1382     <condition id="ARMv8MML_FP_ARMCC">
1383       <description>Armv8-M Mainline processor based device using Floating Point Unit for the Arm Compiler</description>
1384       <require condition="ARMv8MML_FP"/>
1385       <require Tcompiler="ARMCC"/>
1386     </condition>
1387     <condition id="ARMv8MML_FP_LE_ARMCC">
1388       <description>Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
1389       <require condition="ARMv8MML_FP_ARMCC"/>
1390       <require Dendian="Little-endian"/>
1391     </condition>
1392     <condition id="ARMv8MML_FP_BE_ARMCC">
1393       <description>Armv8-M Mainline processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
1394       <require condition="ARMv8MML_FP_ARMCC"/>
1395       <require Dendian="Big-endian"/>
1396     </condition>
1397
1398     <condition id="ARMv8MML_NODSP_NOFPU_ARMCC">
1399       <description>Armv8-M Mainline, no DSP, no FPU, Arm Compiler</description>
1400       <require condition="ARMv8MML_NODSP_NOFPU"/>
1401       <require Tcompiler="ARMCC"/>
1402     </condition>
1403     <condition id="ARMv8MML_DSP_NOFPU_ARMCC">
1404       <description>Armv8-M Mainline, DSP, no FPU, Arm Compiler</description>
1405       <require condition="ARMv8MML_DSP_NOFPU"/>
1406       <require Tcompiler="ARMCC"/>
1407     </condition>
1408     <condition id="ARMv8MML_NODSP_SP_ARMCC">
1409       <description>Armv8-M Mainline, no DSP, SP FPU, Arm Compiler</description>
1410       <require condition="ARMv8MML_NODSP_SP"/>
1411       <require Tcompiler="ARMCC"/>
1412     </condition>
1413     <condition id="ARMv8MML_DSP_SP_ARMCC">
1414       <description>Armv8-M Mainline, DSP, SP FPU, Arm Compiler</description>
1415       <require condition="ARMv8MML_DSP_SP"/>
1416       <require Tcompiler="ARMCC"/>
1417     </condition>
1418     <condition id="ARMv8MML_NODSP_NOFPU_LE_ARMCC">
1419       <description>Armv8-M Mainline, little endian, no DSP, no FPU, Arm Compiler</description>
1420       <require condition="ARMv8MML_NODSP_NOFPU_ARMCC"/>
1421       <require Dendian="Little-endian"/>
1422     </condition>
1423     <condition id="ARMv8MML_DSP_NOFPU_LE_ARMCC">
1424       <description>Armv8-M Mainline, little endian, DSP, no FPU, Arm Compiler</description>
1425       <require condition="ARMv8MML_DSP_NOFPU_ARMCC"/>
1426       <require Dendian="Little-endian"/>
1427     </condition>
1428     <condition id="ARMv8MML_NODSP_SP_LE_ARMCC">
1429       <description>Armv8-M Mainline, little endian, no DSP, SP FPU, Arm Compiler</description>
1430       <require condition="ARMv8MML_NODSP_SP_ARMCC"/>
1431       <require Dendian="Little-endian"/>
1432     </condition>
1433     <condition id="ARMv8MML_DSP_SP_LE_ARMCC">
1434       <description>Armv8-M Mainline, little endian, DSP, SP FPU, Arm Compiler</description>
1435       <require condition="ARMv8MML_DSP_SP_ARMCC"/>
1436       <require Dendian="Little-endian"/>
1437     </condition>
1438
1439     <!-- GCC compiler -->
1440     <condition id="CA_GCC">
1441       <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the GCC Compiler</description>
1442       <require condition="ARMv7-A Device"/>
1443       <require Tcompiler="GCC"/>
1444     </condition>
1445
1446     <condition id="CM0_GCC">
1447       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device for the GCC Compiler</description>
1448       <require condition="CM0"/>
1449       <require Tcompiler="GCC"/>
1450     </condition>
1451     <condition id="CM0_LE_GCC">
1452       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the GCC Compiler</description>
1453       <require condition="CM0_GCC"/>
1454       <require Dendian="Little-endian"/>
1455     </condition>
1456     <condition id="CM0_BE_GCC">
1457       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the GCC Compiler</description>
1458       <require condition="CM0_GCC"/>
1459       <require Dendian="Big-endian"/>
1460     </condition>
1461
1462     <condition id="CM1_GCC">
1463       <description>Cortex-M1 based device for the GCC Compiler</description>
1464       <require condition="CM1"/>
1465       <require Tcompiler="GCC"/>
1466     </condition>
1467     <condition id="CM1_LE_GCC">
1468       <description>Cortex-M1 based device in little endian mode for the GCC Compiler</description>
1469       <require condition="CM1_GCC"/>
1470       <require Dendian="Little-endian"/>
1471     </condition>
1472     <condition id="CM1_BE_GCC">
1473       <description>Cortex-M1 based device in big endian mode for the GCC Compiler</description>
1474       <require condition="CM1_GCC"/>
1475       <require Dendian="Big-endian"/>
1476     </condition>
1477
1478     <condition id="CM3_GCC">
1479       <description>Cortex-M3 or SC300 processor based device for the GCC Compiler</description>
1480       <require condition="CM3"/>
1481       <require Tcompiler="GCC"/>
1482     </condition>
1483     <condition id="CM3_LE_GCC">
1484       <description>Cortex-M3 or SC300 processor based device in little endian mode for the GCC Compiler</description>
1485       <require condition="CM3_GCC"/>
1486       <require Dendian="Little-endian"/>
1487     </condition>
1488     <condition id="CM3_BE_GCC">
1489       <description>Cortex-M3 or SC300 processor based device in big endian mode for the GCC Compiler</description>
1490       <require condition="CM3_GCC"/>
1491       <require Dendian="Big-endian"/>
1492     </condition>
1493
1494     <condition id="CM4_GCC">
1495       <description>Cortex-M4 processor based device for the GCC Compiler</description>
1496       <require condition="CM4"/>
1497       <require Tcompiler="GCC"/>
1498     </condition>
1499     <condition id="CM4_LE_GCC">
1500       <description>Cortex-M4 processor based device in little endian mode for the GCC Compiler</description>
1501       <require condition="CM4_GCC"/>
1502       <require Dendian="Little-endian"/>
1503     </condition>
1504     <condition id="CM4_BE_GCC">
1505       <description>Cortex-M4 processor based device in big endian mode for the GCC Compiler</description>
1506       <require condition="CM4_GCC"/>
1507       <require Dendian="Big-endian"/>
1508     </condition>
1509
1510     <condition id="CM4_FP_GCC">
1511       <description>Cortex-M4 processor based device using Floating Point Unit for the GCC Compiler</description>
1512       <require condition="CM4_FP"/>
1513       <require Tcompiler="GCC"/>
1514     </condition>
1515     <condition id="CM4_FP_LE_GCC">
1516       <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
1517       <require condition="CM4_FP_GCC"/>
1518       <require Dendian="Little-endian"/>
1519     </condition>
1520     <condition id="CM4_FP_BE_GCC">
1521       <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
1522       <require condition="CM4_FP_GCC"/>
1523       <require Dendian="Big-endian"/>
1524     </condition>
1525
1526     <condition id="CM7_GCC">
1527       <description>Cortex-M7 processor based device for the GCC Compiler</description>
1528       <require condition="CM7"/>
1529       <require Tcompiler="GCC"/>
1530     </condition>
1531     <condition id="CM7_LE_GCC">
1532       <description>Cortex-M7 processor based device in little endian mode for the GCC Compiler</description>
1533       <require condition="CM7_GCC"/>
1534       <require Dendian="Little-endian"/>
1535     </condition>
1536     <condition id="CM7_BE_GCC">
1537       <description>Cortex-M7 processor based device in big endian mode for the GCC Compiler</description>
1538       <require condition="CM7_GCC"/>
1539       <require Dendian="Big-endian"/>
1540     </condition>
1541
1542     <condition id="CM7_FP_GCC">
1543       <description>Cortex-M7 processor based device using Floating Point Unit for the GCC Compiler</description>
1544       <require condition="CM7_FP"/>
1545       <require Tcompiler="GCC"/>
1546     </condition>
1547     <condition id="CM7_FP_LE_GCC">
1548       <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
1549       <require condition="CM7_FP_GCC"/>
1550       <require Dendian="Little-endian"/>
1551     </condition>
1552     <condition id="CM7_FP_BE_GCC">
1553       <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
1554       <require condition="CM7_FP_GCC"/>
1555       <require Dendian="Big-endian"/>
1556     </condition>
1557
1558     <condition id="CM7_SP_GCC">
1559       <description>Cortex-M7 processor based device using Floating Point Unit (SP) for the GCC Compiler</description>
1560       <require condition="CM7_SP"/>
1561       <require Tcompiler="GCC"/>
1562     </condition>
1563     <condition id="CM7_SP_LE_GCC">
1564       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the GCC Compiler</description>
1565       <require condition="CM7_SP_GCC"/>
1566       <require Dendian="Little-endian"/>
1567     </condition>
1568     <condition id="CM7_SP_BE_GCC">
1569       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the GCC Compiler</description>
1570       <require condition="CM7_SP_GCC"/>
1571       <require Dendian="Big-endian"/>
1572     </condition>
1573
1574     <condition id="CM7_DP_GCC">
1575       <description>Cortex-M7 processor based device using Floating Point Unit (DP) for the GCC Compiler</description>
1576       <require condition="CM7_DP"/>
1577       <require Tcompiler="GCC"/>
1578     </condition>
1579     <condition id="CM7_DP_LE_GCC">
1580       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the GCC Compiler</description>
1581       <require condition="CM7_DP_GCC"/>
1582       <require Dendian="Little-endian"/>
1583     </condition>
1584     <condition id="CM7_DP_BE_GCC">
1585       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the GCC Compiler</description>
1586       <require condition="CM7_DP_GCC"/>
1587       <require Dendian="Big-endian"/>
1588     </condition>
1589
1590     <condition id="CM23_GCC">
1591       <description>Cortex-M23 processor based device for the GCC Compiler</description>
1592       <require condition="CM23"/>
1593       <require Tcompiler="GCC"/>
1594     </condition>
1595     <condition id="CM23_LE_GCC">
1596       <description>Cortex-M23 processor based device in little endian mode for the GCC Compiler</description>
1597       <require condition="CM23_GCC"/>
1598       <require Dendian="Little-endian"/>
1599     </condition>
1600     <condition id="CM23_BE_GCC">
1601       <description>Cortex-M23 processor based device in big endian mode for the GCC Compiler</description>
1602       <require condition="CM23_GCC"/>
1603       <require Dendian="Big-endian"/>
1604     </condition>
1605
1606     <condition id="CM33_GCC">
1607       <description>Cortex-M33 processor based device for the GCC Compiler</description>
1608       <require condition="CM33"/>
1609       <require Tcompiler="GCC"/>
1610     </condition>
1611     <condition id="CM33_LE_GCC">
1612       <description>Cortex-M33 processor based device in little endian mode for the GCC Compiler</description>
1613       <require condition="CM33_GCC"/>
1614       <require Dendian="Little-endian"/>
1615     </condition>
1616     <condition id="CM33_BE_GCC">
1617       <description>Cortex-M33 processor based device in big endian mode for the GCC Compiler</description>
1618       <require condition="CM33_GCC"/>
1619       <require Dendian="Big-endian"/>
1620     </condition>
1621
1622     <condition id="CM33_FP_GCC">
1623       <description>Cortex-M33 processor based device using Floating Point Unit for the GCC Compiler</description>
1624       <require condition="CM33_FP"/>
1625       <require Tcompiler="GCC"/>
1626     </condition>
1627     <condition id="CM33_FP_LE_GCC">
1628       <description>Cortex-M33 processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
1629       <require condition="CM33_FP_GCC"/>
1630       <require Dendian="Little-endian"/>
1631     </condition>
1632     <condition id="CM33_FP_BE_GCC">
1633       <description>Cortex-M33 processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
1634       <require condition="CM33_FP_GCC"/>
1635       <require Dendian="Big-endian"/>
1636     </condition>
1637
1638     <condition id="CM33_NODSP_NOFPU_GCC">
1639       <description>CM33, no DSP, no FPU, GCC Compiler</description>
1640       <require condition="CM33_NODSP_NOFPU"/>
1641       <require Tcompiler="GCC"/>
1642     </condition>
1643     <condition id="CM33_DSP_NOFPU_GCC">
1644       <description>CM33, DSP, no FPU, GCC Compiler</description>
1645       <require condition="CM33_DSP_NOFPU"/>
1646       <require Tcompiler="GCC"/>
1647     </condition>
1648     <condition id="CM33_NODSP_SP_GCC">
1649       <description>CM33, no DSP, SP FPU, GCC Compiler</description>
1650       <require condition="CM33_NODSP_SP"/>
1651       <require Tcompiler="GCC"/>
1652     </condition>
1653     <condition id="CM33_DSP_SP_GCC">
1654       <description>CM33, DSP, SP FPU, GCC Compiler</description>
1655       <require condition="CM33_DSP_SP"/>
1656       <require Tcompiler="GCC"/>
1657     </condition>
1658     <condition id="CM33_NODSP_NOFPU_LE_GCC">
1659       <description>CM33, little endian, no DSP, no FPU, GCC Compiler</description>
1660       <require condition="CM33_NODSP_NOFPU_GCC"/>
1661       <require Dendian="Little-endian"/>
1662     </condition>
1663     <condition id="CM33_DSP_NOFPU_LE_GCC">
1664       <description>CM33, little endian, DSP, no FPU, GCC Compiler</description>
1665       <require condition="CM33_DSP_NOFPU_GCC"/>
1666       <require Dendian="Little-endian"/>
1667     </condition>
1668     <condition id="CM33_NODSP_SP_LE_GCC">
1669       <description>CM33, little endian, no DSP, SP FPU, GCC Compiler</description>
1670       <require condition="CM33_NODSP_SP_GCC"/>
1671       <require Dendian="Little-endian"/>
1672     </condition>
1673     <condition id="CM33_DSP_SP_LE_GCC">
1674       <description>CM33, little endian, DSP, SP FPU, GCC Compiler</description>
1675       <require condition="CM33_DSP_SP_GCC"/>
1676       <require Dendian="Little-endian"/>
1677     </condition>
1678
1679     <condition id="CM35P_GCC">
1680       <description>Cortex-M35P processor based device for the GCC Compiler</description>
1681       <require condition="CM35P"/>
1682       <require Tcompiler="GCC"/>
1683     </condition>
1684     <condition id="CM35P_LE_GCC">
1685       <description>Cortex-M35P processor based device in little endian mode for the GCC Compiler</description>
1686       <require condition="CM35P_GCC"/>
1687       <require Dendian="Little-endian"/>
1688     </condition>
1689     <condition id="CM35P_BE_GCC">
1690       <description>Cortex-M35P processor based device in big endian mode for the GCC Compiler</description>
1691       <require condition="CM35P_GCC"/>
1692       <require Dendian="Big-endian"/>
1693     </condition>
1694
1695     <condition id="CM35P_FP_GCC">
1696       <description>Cortex-M35P processor based device using Floating Point Unit for the GCC Compiler</description>
1697       <require condition="CM35P_FP"/>
1698       <require Tcompiler="GCC"/>
1699     </condition>
1700     <condition id="CM35P_FP_LE_GCC">
1701       <description>Cortex-M35P processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
1702       <require condition="CM35P_FP_GCC"/>
1703       <require Dendian="Little-endian"/>
1704     </condition>
1705     <condition id="CM35P_FP_BE_GCC">
1706       <description>Cortex-M35P processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
1707       <require condition="CM35P_FP_GCC"/>
1708       <require Dendian="Big-endian"/>
1709     </condition>
1710
1711     <condition id="CM35P_NODSP_NOFPU_GCC">
1712       <description>CM35P, no DSP, no FPU, GCC Compiler</description>
1713       <require condition="CM35P_NODSP_NOFPU"/>
1714       <require Tcompiler="GCC"/>
1715     </condition>
1716     <condition id="CM35P_DSP_NOFPU_GCC">
1717       <description>CM35P, DSP, no FPU, GCC Compiler</description>
1718       <require condition="CM35P_DSP_NOFPU"/>
1719       <require Tcompiler="GCC"/>
1720     </condition>
1721     <condition id="CM35P_NODSP_SP_GCC">
1722       <description>CM35P, no DSP, SP FPU, GCC Compiler</description>
1723       <require condition="CM35P_NODSP_SP"/>
1724       <require Tcompiler="GCC"/>
1725     </condition>
1726     <condition id="CM35P_DSP_SP_GCC">
1727       <description>CM35P, DSP, SP FPU, GCC Compiler</description>
1728       <require condition="CM35P_DSP_SP"/>
1729       <require Tcompiler="GCC"/>
1730     </condition>
1731     <condition id="CM35P_NODSP_NOFPU_LE_GCC">
1732       <description>CM35P, little endian, no DSP, no FPU, GCC Compiler</description>
1733       <require condition="CM35P_NODSP_NOFPU_GCC"/>
1734       <require Dendian="Little-endian"/>
1735     </condition>
1736     <condition id="CM35P_DSP_NOFPU_LE_GCC">
1737       <description>CM35P, little endian, DSP, no FPU, GCC Compiler</description>
1738       <require condition="CM35P_DSP_NOFPU_GCC"/>
1739       <require Dendian="Little-endian"/>
1740     </condition>
1741     <condition id="CM35P_NODSP_SP_LE_GCC">
1742       <description>CM35P, little endian, no DSP, SP FPU, GCC Compiler</description>
1743       <require condition="CM35P_NODSP_SP_GCC"/>
1744       <require Dendian="Little-endian"/>
1745     </condition>
1746     <condition id="CM35P_DSP_SP_LE_GCC">
1747       <description>CM35P, little endian, DSP, SP FPU, GCC Compiler</description>
1748       <require condition="CM35P_DSP_SP_GCC"/>
1749       <require Dendian="Little-endian"/>
1750     </condition>
1751
1752     <condition id="ARMv8MBL_GCC">
1753       <description>Armv8-M Baseline processor based device for the GCC Compiler</description>
1754       <require condition="ARMv8MBL"/>
1755       <require Tcompiler="GCC"/>
1756     </condition>
1757     <condition id="ARMv8MBL_LE_GCC">
1758       <description>Armv8-M Baseline processor based device in little endian mode for the GCC Compiler</description>
1759       <require condition="ARMv8MBL_GCC"/>
1760       <require Dendian="Little-endian"/>
1761     </condition>
1762     <condition id="ARMv8MBL_BE_GCC">
1763       <description>Armv8-M Baseline processor based device in big endian mode for the GCC Compiler</description>
1764       <require condition="ARMv8MBL_GCC"/>
1765       <require Dendian="Big-endian"/>
1766     </condition>
1767
1768     <condition id="ARMv8MML_GCC">
1769       <description>Armv8-M Mainline processor based device for the GCC Compiler</description>
1770       <require condition="ARMv8MML"/>
1771       <require Tcompiler="GCC"/>
1772     </condition>
1773     <condition id="ARMv8MML_LE_GCC">
1774       <description>Armv8-M Mainline processor based device in little endian mode for the GCC Compiler</description>
1775       <require condition="ARMv8MML_GCC"/>
1776       <require Dendian="Little-endian"/>
1777     </condition>
1778     <condition id="ARMv8MML_BE_GCC">
1779       <description>Armv8-M Mainline processor based device in big endian mode for the GCC Compiler</description>
1780       <require condition="ARMv8MML_GCC"/>
1781       <require Dendian="Big-endian"/>
1782     </condition>
1783
1784     <condition id="ARMv8MML_FP_GCC">
1785       <description>Armv8-M Mainline processor based device using Floating Point Unit for the GCC Compiler</description>
1786       <require condition="ARMv8MML_FP"/>
1787       <require Tcompiler="GCC"/>
1788     </condition>
1789     <condition id="ARMv8MML_FP_LE_GCC">
1790       <description>Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
1791       <require condition="ARMv8MML_FP_GCC"/>
1792       <require Dendian="Little-endian"/>
1793     </condition>
1794     <condition id="ARMv8MML_FP_BE_GCC">
1795       <description>Armv8-M Mainline processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
1796       <require condition="ARMv8MML_FP_GCC"/>
1797       <require Dendian="Big-endian"/>
1798     </condition>
1799
1800     <condition id="ARMv8MML_NODSP_NOFPU_GCC">
1801       <description>Armv8-M Mainline, no DSP, no FPU, GCC Compiler</description>
1802       <require condition="ARMv8MML_NODSP_NOFPU"/>
1803       <require Tcompiler="GCC"/>
1804     </condition>
1805     <condition id="ARMv8MML_DSP_NOFPU_GCC">
1806       <description>Armv8-M Mainline, DSP, no FPU, GCC Compiler</description>
1807       <require condition="ARMv8MML_DSP_NOFPU"/>
1808       <require Tcompiler="GCC"/>
1809     </condition>
1810     <condition id="ARMv8MML_NODSP_SP_GCC">
1811       <description>Armv8-M Mainline, no DSP, SP FPU, GCC Compiler</description>
1812       <require condition="ARMv8MML_NODSP_SP"/>
1813       <require Tcompiler="GCC"/>
1814     </condition>
1815     <condition id="ARMv8MML_DSP_SP_GCC">
1816       <description>Armv8-M Mainline, DSP, SP FPU, GCC Compiler</description>
1817       <require condition="ARMv8MML_DSP_SP"/>
1818       <require Tcompiler="GCC"/>
1819     </condition>
1820     <condition id="ARMv8MML_NODSP_NOFPU_LE_GCC">
1821       <description>Armv8-M Mainline, little endian, no DSP, no FPU, GCC Compiler</description>
1822       <require condition="ARMv8MML_NODSP_NOFPU_GCC"/>
1823       <require Dendian="Little-endian"/>
1824     </condition>
1825     <condition id="ARMv8MML_DSP_NOFPU_LE_GCC">
1826       <description>Armv8-M Mainline, little endian, DSP, no FPU, GCC Compiler</description>
1827       <require condition="ARMv8MML_DSP_NOFPU_GCC"/>
1828       <require Dendian="Little-endian"/>
1829     </condition>
1830     <condition id="ARMv8MML_NODSP_SP_LE_GCC">
1831       <description>Armv8-M Mainline, little endian, no DSP, SP FPU, GCC Compiler</description>
1832       <require condition="ARMv8MML_NODSP_SP_GCC"/>
1833       <require Dendian="Little-endian"/>
1834     </condition>
1835     <condition id="ARMv8MML_DSP_SP_LE_GCC">
1836       <description>Armv8-M Mainline, little endian, DSP, SP FPU, GCC Compiler</description>
1837       <require condition="ARMv8MML_DSP_SP_GCC"/>
1838       <require Dendian="Little-endian"/>
1839     </condition>
1840
1841     <!-- IAR compiler -->
1842     <condition id="CA_IAR">
1843       <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the IAR Compiler</description>
1844       <require condition="ARMv7-A Device"/>
1845       <require Tcompiler="IAR"/>
1846     </condition>
1847
1848     <condition id="CM0_IAR">
1849       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device for the IAR Compiler</description>
1850       <require condition="CM0"/>
1851       <require Tcompiler="IAR"/>
1852     </condition>
1853     <condition id="CM0_LE_IAR">
1854       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the IAR Compiler</description>
1855       <require condition="CM0_IAR"/>
1856       <require Dendian="Little-endian"/>
1857     </condition>
1858     <condition id="CM0_BE_IAR">
1859       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the IAR Compiler</description>
1860       <require condition="CM0_IAR"/>
1861       <require Dendian="Big-endian"/>
1862     </condition>
1863
1864     <condition id="CM1_IAR">
1865       <description>Cortex-M1 based device for the IAR Compiler</description>
1866       <require condition="CM1"/>
1867       <require Tcompiler="IAR"/>
1868     </condition>
1869     <condition id="CM1_LE_IAR">
1870       <description>Cortex-M1 based device in little endian mode for the IAR Compiler</description>
1871       <require condition="CM1_IAR"/>
1872       <require Dendian="Little-endian"/>
1873     </condition>
1874     <condition id="CM1_BE_IAR">
1875       <description>Cortex-M1 based device in big endian mode for the IAR Compiler</description>
1876       <require condition="CM1_IAR"/>
1877       <require Dendian="Big-endian"/>
1878     </condition>
1879
1880     <condition id="CM3_IAR">
1881       <description>Cortex-M3 or SC300 processor based device for the IAR Compiler</description>
1882       <require condition="CM3"/>
1883       <require Tcompiler="IAR"/>
1884     </condition>
1885     <condition id="CM3_LE_IAR">
1886       <description>Cortex-M3 or SC300 processor based device in little endian mode for the IAR Compiler</description>
1887       <require condition="CM3_IAR"/>
1888       <require Dendian="Little-endian"/>
1889     </condition>
1890     <condition id="CM3_BE_IAR">
1891       <description>Cortex-M3 or SC300 processor based device in big endian mode for the IAR Compiler</description>
1892       <require condition="CM3_IAR"/>
1893       <require Dendian="Big-endian"/>
1894     </condition>
1895
1896     <condition id="CM4_IAR">
1897       <description>Cortex-M4 processor based device for the IAR Compiler</description>
1898       <require condition="CM4"/>
1899       <require Tcompiler="IAR"/>
1900     </condition>
1901     <condition id="CM4_LE_IAR">
1902       <description>Cortex-M4 processor based device in little endian mode for the IAR Compiler</description>
1903       <require condition="CM4_IAR"/>
1904       <require Dendian="Little-endian"/>
1905     </condition>
1906     <condition id="CM4_BE_IAR">
1907       <description>Cortex-M4 processor based device in big endian mode for the IAR Compiler</description>
1908       <require condition="CM4_IAR"/>
1909       <require Dendian="Big-endian"/>
1910     </condition>
1911
1912     <condition id="CM4_FP_IAR">
1913       <description>Cortex-M4 processor based device using Floating Point Unit for the IAR Compiler</description>
1914       <require condition="CM4_FP"/>
1915       <require Tcompiler="IAR"/>
1916     </condition>
1917     <condition id="CM4_FP_LE_IAR">
1918       <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
1919       <require condition="CM4_FP_IAR"/>
1920       <require Dendian="Little-endian"/>
1921     </condition>
1922     <condition id="CM4_FP_BE_IAR">
1923       <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
1924       <require condition="CM4_FP_IAR"/>
1925       <require Dendian="Big-endian"/>
1926     </condition>
1927
1928     <condition id="CM7_IAR">
1929       <description>Cortex-M7 processor based device for the IAR Compiler</description>
1930       <require condition="CM7"/>
1931       <require Tcompiler="IAR"/>
1932     </condition>
1933     <condition id="CM7_LE_IAR">
1934       <description>Cortex-M7 processor based device in little endian mode for the IAR Compiler</description>
1935       <require condition="CM7_IAR"/>
1936       <require Dendian="Little-endian"/>
1937     </condition>
1938     <condition id="CM7_BE_IAR">
1939       <description>Cortex-M7 processor based device in big endian mode for the IAR Compiler</description>
1940       <require condition="CM7_IAR"/>
1941       <require Dendian="Big-endian"/>
1942     </condition>
1943
1944     <condition id="CM7_FP_IAR">
1945       <description>Cortex-M7 processor based device using Floating Point Unit for the IAR Compiler</description>
1946       <require condition="CM7_FP"/>
1947       <require Tcompiler="IAR"/>
1948     </condition>
1949     <condition id="CM7_FP_LE_IAR">
1950       <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
1951       <require condition="CM7_FP_IAR"/>
1952       <require Dendian="Little-endian"/>
1953     </condition>
1954     <condition id="CM7_FP_BE_IAR">
1955       <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
1956       <require condition="CM7_FP_IAR"/>
1957       <require Dendian="Big-endian"/>
1958     </condition>
1959
1960     <condition id="CM7_SP_IAR">
1961       <description>Cortex-M7 processor based device using Floating Point Unit (SP) for the IAR Compiler</description>
1962       <require condition="CM7_SP"/>
1963       <require Tcompiler="IAR"/>
1964     </condition>
1965     <condition id="CM7_SP_LE_IAR">
1966       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the IAR Compiler</description>
1967       <require condition="CM7_SP_IAR"/>
1968       <require Dendian="Little-endian"/>
1969     </condition>
1970     <condition id="CM7_SP_BE_IAR">
1971       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the IAR Compiler</description>
1972       <require condition="CM7_SP_IAR"/>
1973       <require Dendian="Big-endian"/>
1974     </condition>
1975
1976     <condition id="CM7_DP_IAR">
1977       <description>Cortex-M7 processor based device using Floating Point Unit (DP) for the IAR Compiler</description>
1978       <require condition="CM7_DP"/>
1979       <require Tcompiler="IAR"/>
1980     </condition>
1981     <condition id="CM7_DP_LE_IAR">
1982       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the IAR Compiler</description>
1983       <require condition="CM7_DP_IAR"/>
1984       <require Dendian="Little-endian"/>
1985     </condition>
1986     <condition id="CM7_DP_BE_IAR">
1987       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the IAR Compiler</description>
1988       <require condition="CM7_DP_IAR"/>
1989       <require Dendian="Big-endian"/>
1990     </condition>
1991
1992     <condition id="CM23_IAR">
1993       <description>Cortex-M23 processor based device for the IAR Compiler</description>
1994       <require condition="CM23"/>
1995       <require Tcompiler="IAR"/>
1996     </condition>
1997     <condition id="CM23_LE_IAR">
1998       <description>Cortex-M23 processor based device in little endian mode for the IAR Compiler</description>
1999       <require condition="CM23_IAR"/>
2000       <require Dendian="Little-endian"/>
2001     </condition>
2002     <condition id="CM23_BE_IAR">
2003       <description>Cortex-M23 processor based device in big endian mode for the IAR Compiler</description>
2004       <require condition="CM23_IAR"/>
2005       <require Dendian="Big-endian"/>
2006     </condition>
2007
2008     <condition id="CM33_IAR">
2009       <description>Cortex-M33 processor based device for the IAR Compiler</description>
2010       <require condition="CM33"/>
2011       <require Tcompiler="IAR"/>
2012     </condition>
2013     <condition id="CM33_LE_IAR">
2014       <description>Cortex-M33 processor based device in little endian mode for the IAR Compiler</description>
2015       <require condition="CM33_IAR"/>
2016       <require Dendian="Little-endian"/>
2017     </condition>
2018     <condition id="CM33_BE_IAR">
2019       <description>Cortex-M33 processor based device in big endian mode for the IAR Compiler</description>
2020       <require condition="CM33_IAR"/>
2021       <require Dendian="Big-endian"/>
2022     </condition>
2023
2024     <condition id="CM33_FP_IAR">
2025       <description>Cortex-M33 processor based device using Floating Point Unit for the IAR Compiler</description>
2026       <require condition="CM33_FP"/>
2027       <require Tcompiler="IAR"/>
2028     </condition>
2029     <condition id="CM33_FP_LE_IAR">
2030       <description>Cortex-M33 processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
2031       <require condition="CM33_FP_IAR"/>
2032       <require Dendian="Little-endian"/>
2033     </condition>
2034     <condition id="CM33_FP_BE_IAR">
2035       <description>Cortex-M33 processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
2036       <require condition="CM33_FP_IAR"/>
2037       <require Dendian="Big-endian"/>
2038     </condition>
2039
2040     <condition id="CM33_NODSP_NOFPU_IAR">
2041       <description>CM33, no DSP, no FPU, IAR Compiler</description>
2042       <require condition="CM33_NODSP_NOFPU"/>
2043       <require Tcompiler="IAR"/>
2044     </condition>
2045     <condition id="CM33_DSP_NOFPU_IAR">
2046       <description>CM33, DSP, no FPU, IAR Compiler</description>
2047       <require condition="CM33_DSP_NOFPU"/>
2048       <require Tcompiler="IAR"/>
2049     </condition>
2050     <condition id="CM33_NODSP_SP_IAR">
2051       <description>CM33, no DSP, SP FPU, IAR Compiler</description>
2052       <require condition="CM33_NODSP_SP"/>
2053       <require Tcompiler="IAR"/>
2054     </condition>
2055     <condition id="CM33_DSP_SP_IAR">
2056       <description>CM33, DSP, SP FPU, IAR Compiler</description>
2057       <require condition="CM33_DSP_SP"/>
2058       <require Tcompiler="IAR"/>
2059     </condition>
2060     <condition id="CM33_NODSP_NOFPU_LE_IAR">
2061       <description>CM33, little endian, no DSP, no FPU, IAR Compiler</description>
2062       <require condition="CM33_NODSP_NOFPU_IAR"/>
2063       <require Dendian="Little-endian"/>
2064     </condition>
2065     <condition id="CM33_DSP_NOFPU_LE_IAR">
2066       <description>CM33, little endian, DSP, no FPU, IAR Compiler</description>
2067       <require condition="CM33_DSP_NOFPU_IAR"/>
2068       <require Dendian="Little-endian"/>
2069     </condition>
2070     <condition id="CM33_NODSP_SP_LE_IAR">
2071       <description>CM33, little endian, no DSP, SP FPU, IAR Compiler</description>
2072       <require condition="CM33_NODSP_SP_IAR"/>
2073       <require Dendian="Little-endian"/>
2074     </condition>
2075     <condition id="CM33_DSP_SP_LE_IAR">
2076       <description>CM33, little endian, DSP, SP FPU, IAR Compiler</description>
2077       <require condition="CM33_DSP_SP_IAR"/>
2078       <require Dendian="Little-endian"/>
2079     </condition>
2080
2081     <condition id="CM35P_IAR">
2082       <description>Cortex-M35P processor based device for the IAR Compiler</description>
2083       <require condition="CM35P"/>
2084       <require Tcompiler="IAR"/>
2085     </condition>
2086     <condition id="CM35P_LE_IAR">
2087       <description>Cortex-M35P processor based device in little endian mode for the IAR Compiler</description>
2088       <require condition="CM35P_IAR"/>
2089       <require Dendian="Little-endian"/>
2090     </condition>
2091     <condition id="CM35P_BE_IAR">
2092       <description>Cortex-M35P processor based device in big endian mode for the IAR Compiler</description>
2093       <require condition="CM35P_IAR"/>
2094       <require Dendian="Big-endian"/>
2095     </condition>
2096
2097     <condition id="CM35P_FP_IAR">
2098       <description>Cortex-M35P processor based device using Floating Point Unit for the IAR Compiler</description>
2099       <require condition="CM35P_FP"/>
2100       <require Tcompiler="IAR"/>
2101     </condition>
2102     <condition id="CM35P_FP_LE_IAR">
2103       <description>Cortex-M35P processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
2104       <require condition="CM35P_FP_IAR"/>
2105       <require Dendian="Little-endian"/>
2106     </condition>
2107     <condition id="CM35P_FP_BE_IAR">
2108       <description>Cortex-M35P processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
2109       <require condition="CM35P_FP_IAR"/>
2110       <require Dendian="Big-endian"/>
2111     </condition>
2112
2113     <condition id="CM35P_NODSP_NOFPU_IAR">
2114       <description>CM35P, no DSP, no FPU, IAR Compiler</description>
2115       <require condition="CM35P_NODSP_NOFPU"/>
2116       <require Tcompiler="IAR"/>
2117     </condition>
2118     <condition id="CM35P_DSP_NOFPU_IAR">
2119       <description>CM35P, DSP, no FPU, IAR Compiler</description>
2120       <require condition="CM35P_DSP_NOFPU"/>
2121       <require Tcompiler="IAR"/>
2122     </condition>
2123     <condition id="CM35P_NODSP_SP_IAR">
2124       <description>CM35P, no DSP, SP FPU, IAR Compiler</description>
2125       <require condition="CM35P_NODSP_SP"/>
2126       <require Tcompiler="IAR"/>
2127     </condition>
2128     <condition id="CM35P_DSP_SP_IAR">
2129       <description>CM35P, DSP, SP FPU, IAR Compiler</description>
2130       <require condition="CM35P_DSP_SP"/>
2131       <require Tcompiler="IAR"/>
2132     </condition>
2133     <condition id="CM35P_NODSP_NOFPU_LE_IAR">
2134       <description>CM35P, little endian, no DSP, no FPU, IAR Compiler</description>
2135       <require condition="CM35P_NODSP_NOFPU_IAR"/>
2136       <require Dendian="Little-endian"/>
2137     </condition>
2138     <condition id="CM35P_DSP_NOFPU_LE_IAR">
2139       <description>CM35P, little endian, DSP, no FPU, IAR Compiler</description>
2140       <require condition="CM35P_DSP_NOFPU_IAR"/>
2141       <require Dendian="Little-endian"/>
2142     </condition>
2143     <condition id="CM35P_NODSP_SP_LE_IAR">
2144       <description>CM35P, little endian, no DSP, SP FPU, IAR Compiler</description>
2145       <require condition="CM35P_NODSP_SP_IAR"/>
2146       <require Dendian="Little-endian"/>
2147     </condition>
2148     <condition id="CM35P_DSP_SP_LE_IAR">
2149       <description>CM35P, little endian, DSP, SP FPU, IAR Compiler</description>
2150       <require condition="CM35P_DSP_SP_IAR"/>
2151       <require Dendian="Little-endian"/>
2152     </condition>
2153
2154     <condition id="ARMv8MBL_IAR">
2155       <description>Armv8-M Baseline processor based device for the IAR Compiler</description>
2156       <require condition="ARMv8MBL"/>
2157       <require Tcompiler="IAR"/>
2158     </condition>
2159     <condition id="ARMv8MBL_LE_IAR">
2160       <description>Armv8-M Baseline processor based device in little endian mode for the IAR Compiler</description>
2161       <require condition="ARMv8MBL_IAR"/>
2162       <require Dendian="Little-endian"/>
2163     </condition>
2164     <condition id="ARMv8MBL_BE_IAR">
2165       <description>Armv8-M Baseline processor based device in big endian mode for the IAR Compiler</description>
2166       <require condition="ARMv8MBL_IAR"/>
2167       <require Dendian="Big-endian"/>
2168     </condition>
2169
2170     <condition id="ARMv8MML_IAR">
2171       <description>Armv8-M Mainline processor based device for the IAR Compiler</description>
2172       <require condition="ARMv8MML"/>
2173       <require Tcompiler="IAR"/>
2174     </condition>
2175     <condition id="ARMv8MML_LE_IAR">
2176       <description>Armv8-M Mainline processor based device in little endian mode for the IAR Compiler</description>
2177       <require condition="ARMv8MML_IAR"/>
2178       <require Dendian="Little-endian"/>
2179     </condition>
2180     <condition id="ARMv8MML_BE_IAR">
2181       <description>Armv8-M Mainline processor based device in big endian mode for the IAR Compiler</description>
2182       <require condition="ARMv8MML_IAR"/>
2183       <require Dendian="Big-endian"/>
2184     </condition>
2185
2186     <condition id="ARMv8MML_FP_IAR">
2187       <description>Armv8-M Mainline processor based device using Floating Point Unit for the IAR Compiler</description>
2188       <require condition="ARMv8MML_FP"/>
2189       <require Tcompiler="IAR"/>
2190     </condition>
2191     <condition id="ARMv8MML_FP_LE_IAR">
2192       <description>Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
2193       <require condition="ARMv8MML_FP_IAR"/>
2194       <require Dendian="Little-endian"/>
2195     </condition>
2196     <condition id="ARMv8MML_FP_BE_IAR">
2197       <description>Armv8-M Mainline processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
2198       <require condition="ARMv8MML_FP_IAR"/>
2199       <require Dendian="Big-endian"/>
2200     </condition>
2201
2202     <condition id="ARMv8MML_NODSP_NOFPU_IAR">
2203       <description>Armv8-M Mainline, no DSP, no FPU, IAR Compiler</description>
2204       <require condition="ARMv8MML_NODSP_NOFPU"/>
2205       <require Tcompiler="IAR"/>
2206     </condition>
2207     <condition id="ARMv8MML_DSP_NOFPU_IAR">
2208       <description>Armv8-M Mainline, DSP, no FPU, IAR Compiler</description>
2209       <require condition="ARMv8MML_DSP_NOFPU"/>
2210       <require Tcompiler="IAR"/>
2211     </condition>
2212     <condition id="ARMv8MML_NODSP_SP_IAR">
2213       <description>Armv8-M Mainline, no DSP, SP FPU, IAR Compiler</description>
2214       <require condition="ARMv8MML_NODSP_SP"/>
2215       <require Tcompiler="IAR"/>
2216     </condition>
2217     <condition id="ARMv8MML_DSP_SP_IAR">
2218       <description>Armv8-M Mainline, DSP, SP FPU, IAR Compiler</description>
2219       <require condition="ARMv8MML_DSP_SP"/>
2220       <require Tcompiler="IAR"/>
2221     </condition>
2222     <condition id="ARMv8MML_NODSP_NOFPU_LE_IAR">
2223       <description>Armv8-M Mainline, little endian, no DSP, no FPU, IAR Compiler</description>
2224       <require condition="ARMv8MML_NODSP_NOFPU_IAR"/>
2225       <require Dendian="Little-endian"/>
2226     </condition>
2227     <condition id="ARMv8MML_DSP_NOFPU_LE_IAR">
2228       <description>Armv8-M Mainline, little endian, DSP, no FPU, IAR Compiler</description>
2229       <require condition="ARMv8MML_DSP_NOFPU_IAR"/>
2230       <require Dendian="Little-endian"/>
2231     </condition>
2232     <condition id="ARMv8MML_NODSP_SP_LE_IAR">
2233       <description>Armv8-M Mainline, little endian, no DSP, SP FPU, IAR Compiler</description>
2234       <require condition="ARMv8MML_NODSP_SP_IAR"/>
2235       <require Dendian="Little-endian"/>
2236     </condition>
2237     <condition id="ARMv8MML_DSP_SP_LE_IAR">
2238       <description>Armv8-M Mainline, little endian, DSP, SP FPU, IAR Compiler</description>
2239       <require condition="ARMv8MML_DSP_SP_IAR"/>
2240       <require Dendian="Little-endian"/>
2241     </condition>
2242
2243     <!-- conditions selecting single devices and CMSIS Core -->
2244     <!-- used for component startup, GCC version is used for C-Startup -->
2245     <condition id="ARMCM0 CMSIS">
2246       <description>Generic Arm Cortex-M0 device startup and depends on CMSIS Core</description>
2247       <require Dvendor="ARM:82" Dname="ARMCM0"/>
2248       <require Cclass="CMSIS" Cgroup="CORE"/>
2249     </condition>
2250     <condition id="ARMCM0 CMSIS GCC">
2251       <description>Generic ARM Cortex-M0 device startup and depends on CMSIS Core requiring GCC</description>
2252       <require condition="ARMCM0 CMSIS"/>
2253       <require condition="GCC"/>
2254     </condition>
2255
2256     <condition id="ARMCM0+ CMSIS">
2257       <description>Generic Arm Cortex-M0+ device startup and depends on CMSIS Core</description>
2258       <require Dvendor="ARM:82" Dname="ARMCM0P*"/>
2259       <require Cclass="CMSIS" Cgroup="CORE"/>
2260     </condition>
2261     <condition id="ARMCM0+ CMSIS GCC">
2262       <description>Generic Arm Cortex-M0+ device startup and depends CMSIS Core requiring GCC</description>
2263       <require condition="ARMCM0+ CMSIS"/>
2264       <require condition="GCC"/>
2265     </condition>
2266
2267     <condition id="ARMCM1 CMSIS">
2268       <description>Generic Arm Cortex-M1 device startup and depends on CMSIS Core</description>
2269       <require Dvendor="ARM:82" Dname="ARMCM1"/>
2270       <require Cclass="CMSIS" Cgroup="CORE"/>
2271     </condition>
2272     <condition id="ARMCM1 CMSIS GCC">
2273       <description>Generic ARM Cortex-M1 device startup and depends on CMSIS Core requiring GCC</description>
2274       <require condition="ARMCM1 CMSIS"/>
2275       <require condition="GCC"/>
2276     </condition>
2277
2278     <condition id="ARMCM3 CMSIS">
2279       <description>Generic Arm Cortex-M3 device startup and depends on CMSIS Core</description>
2280       <require Dvendor="ARM:82" Dname="ARMCM3"/>
2281       <require Cclass="CMSIS" Cgroup="CORE"/>
2282     </condition>
2283     <condition id="ARMCM3 CMSIS GCC">
2284       <description>Generic Arm Cortex-M3 device startup and depends on CMSIS Core requiring GCC</description>
2285       <require condition="ARMCM3 CMSIS"/>
2286       <require condition="GCC"/>
2287     </condition>
2288
2289     <condition id="ARMCM4 CMSIS">
2290       <description>Generic Arm Cortex-M4 device startup and depends on CMSIS Core</description>
2291       <require Dvendor="ARM:82" Dname="ARMCM4*"/>
2292       <require Cclass="CMSIS" Cgroup="CORE"/>
2293     </condition>
2294     <condition id="ARMCM4 CMSIS GCC">
2295       <description>Generic Arm Cortex-M4 device startup and depends on CMSIS Core requiring GCC</description>
2296       <require condition="ARMCM4 CMSIS"/>
2297       <require condition="GCC"/>
2298     </condition>
2299
2300     <condition id="ARMCM7 CMSIS">
2301       <description>Generic Arm Cortex-M7 device startup and depends on CMSIS Core</description>
2302       <require Dvendor="ARM:82" Dname="ARMCM7*"/>
2303       <require Cclass="CMSIS" Cgroup="CORE"/>
2304     </condition>
2305     <condition id="ARMCM7 CMSIS GCC">
2306       <description>Generic Arm Cortex-M7 device startup and depends on CMSIS Core requiring GCC</description>
2307       <require condition="ARMCM7 CMSIS"/>
2308       <require condition="GCC"/>
2309     </condition>
2310
2311     <condition id="ARMCM23 CMSIS">
2312       <description>Generic Arm Cortex-M23 device startup and depends on CMSIS Core</description>
2313       <require Dvendor="ARM:82" Dname="ARMCM23*"/>
2314       <require Cclass="CMSIS" Cgroup="CORE"/>
2315     </condition>
2316     <condition id="ARMCM23 CMSIS GCC">
2317       <description>Generic Arm Cortex-M23 device startup and depends on CMSIS Core requiring GCC</description>
2318       <require condition="ARMCM23 CMSIS"/>
2319       <require condition="GCC"/>
2320     </condition>
2321
2322     <condition id="ARMCM33 CMSIS">
2323       <description>Generic Arm Cortex-M33 device startup and depends on CMSIS Core</description>
2324       <require Dvendor="ARM:82" Dname="ARMCM33*"/>
2325       <require Cclass="CMSIS" Cgroup="CORE"/>
2326     </condition>
2327     <condition id="ARMCM33 CMSIS GCC">
2328       <description>Generic Arm Cortex-M33 device startup and depends on CMSIS Core requiring GCC</description>
2329       <require condition="ARMCM33 CMSIS"/>
2330       <require condition="GCC"/>
2331     </condition>
2332
2333     <condition id="ARMCM35P CMSIS">
2334       <description>Generic Arm Cortex-M35P device startup and depends on CMSIS Core</description>
2335       <require Dvendor="ARM:82" Dname="ARMCM35P*"/>
2336       <require Cclass="CMSIS" Cgroup="CORE"/>
2337     </condition>
2338     <condition id="ARMCM35P CMSIS GCC">
2339       <description>Generic Arm Cortex-M35P device startup and depends on CMSIS Core requiring GCC</description>
2340       <require condition="ARMCM35P CMSIS"/>
2341       <require condition="GCC"/>
2342     </condition>
2343
2344     <condition id="ARMSC000 CMSIS">
2345       <description>Generic Arm SC000 device startup and depends on CMSIS Core</description>
2346       <require Dvendor="ARM:82" Dname="ARMSC000"/>
2347       <require Cclass="CMSIS" Cgroup="CORE"/>
2348     </condition>
2349     <condition id="ARMSC000 CMSIS GCC">
2350       <description>Generic Arm SC000 device startup and depends on CMSIS Core requiring GCC</description>
2351       <require condition="ARMSC000 CMSIS"/>
2352       <require condition="GCC"/>
2353     </condition>
2354
2355     <condition id="ARMSC300 CMSIS">
2356       <description>Generic Arm SC300 device startup and depends on CMSIS Core</description>
2357       <require Dvendor="ARM:82" Dname="ARMSC300"/>
2358       <require Cclass="CMSIS" Cgroup="CORE"/>
2359     </condition>
2360     <condition id="ARMSC300 CMSIS GCC">
2361       <description>Generic Arm SC300 device startup and dependson CMSIS Core requiring GCC</description>
2362       <require condition="ARMSC300 CMSIS"/>
2363       <require condition="GCC"/>
2364     </condition>
2365
2366     <condition id="ARMv8MBL CMSIS">
2367       <description>Generic Armv8-M Baseline device startup and depends on CMSIS Core</description>
2368       <require Dvendor="ARM:82" Dname="ARMv8MBL"/>
2369       <require Cclass="CMSIS" Cgroup="CORE"/>
2370     </condition>
2371     <condition id="ARMv8MBL CMSIS GCC">
2372       <description>Generic Armv8-M Baseline device startup and depends on CMSIS Core requiring GCC</description>
2373       <require condition="ARMv8MBL CMSIS"/>
2374       <require condition="GCC"/>
2375     </condition>
2376
2377     <condition id="ARMv8MML CMSIS">
2378       <description>Generic Armv8-M Mainline device startup and depends on CMSIS Core</description>
2379       <require Dvendor="ARM:82" Dname="ARMv8MML*"/>
2380       <require Cclass="CMSIS" Cgroup="CORE"/>
2381     </condition>
2382     <condition id="ARMv8MML CMSIS GCC">
2383       <description>Generic Armv8-M Mainline device startup and depends on CMSIS Core requiring GCC</description>
2384       <require condition="ARMv8MML CMSIS"/>
2385       <require condition="GCC"/>
2386     </condition>
2387
2388     <condition id="ARMCA5 CMSIS">
2389       <description>Generic Arm Cortex-A5 device startup and depends on CMSIS Core</description>
2390       <require Dvendor="ARM:82" Dname="ARMCA5"/>
2391       <require Cclass="CMSIS" Cgroup="CORE"/>
2392     </condition>
2393
2394     <condition id="ARMCA7 CMSIS">
2395       <description>Generic Arm Cortex-A7 device startup and depends on CMSIS Core</description>
2396       <require Dvendor="ARM:82" Dname="ARMCA7"/>
2397       <require Cclass="CMSIS" Cgroup="CORE"/>
2398     </condition>
2399
2400     <condition id="ARMCA9 CMSIS">
2401       <description>Generic Arm Cortex-A9 device startup and depends on CMSIS Core</description>
2402       <require Dvendor="ARM:82" Dname="ARMCA9"/>
2403       <require Cclass="CMSIS" Cgroup="CORE"/>
2404     </condition>
2405
2406     <!-- CMSIS DSP -->
2407     <condition id="CMSIS DSP">
2408       <description>Components required for DSP</description>
2409       <require condition="ARMv6_7_8-M Device"/>
2410       <require condition="ARMCC GCC IAR"/>
2411       <require Cclass="CMSIS" Cgroup="CORE"/>
2412     </condition>
2413
2414     <!-- CMSIS NN -->
2415     <condition id="CMSIS NN">
2416       <description>Components required for NN</description>
2417       <require condition="CMSIS DSP"/>
2418     </condition>
2419
2420     <!-- RTOS RTX -->
2421     <condition id="RTOS RTX">
2422       <description>Components required for RTOS RTX</description>
2423       <require condition="ARMv6_7-M Device"/>
2424       <require condition="ARMCC GCC IAR"/>
2425       <require Cclass="Device" Cgroup="Startup"/>
2426       <deny    Cclass="CMSIS"  Cgroup="RTOS2" Csub="Keil RTX5"/>
2427     </condition>
2428     <condition id="RTOS RTX IFX">
2429       <description>Components required for RTOS RTX IFX</description>
2430       <require condition="ARMv6_7-M Device"/>
2431       <require condition="ARMCC GCC IAR"/>
2432       <require Dvendor="Infineon:7" Dname="XMC4*"/>
2433       <require Cclass="Device" Cgroup="Startup"/>
2434       <deny    Cclass="CMSIS"  Cgroup="RTOS2" Csub="Keil RTX5"/>
2435     </condition>
2436     <condition id="RTOS RTX5">
2437       <description>Components required for RTOS RTX5</description>
2438       <require condition="ARMv6_7_8-M Device"/>
2439       <require condition="ARMCC GCC IAR"/>
2440       <require Cclass="CMSIS"  Cgroup="RTOS2" Csub="Keil RTX5"/>
2441     </condition>
2442     <condition id="RTOS2 RTX5">
2443       <description>Components required for RTOS2 RTX5</description>
2444       <require condition="ARMv6_7_8-M Device"/>
2445       <require condition="ARMCC GCC IAR"/>
2446       <require Cclass="CMSIS"  Cgroup="CORE"/>
2447       <require Cclass="Device" Cgroup="Startup"/>
2448     </condition>
2449     <condition id="RTOS2 RTX5 v7-A">
2450       <description>Components required for RTOS2 RTX5 on Armv7-A</description>
2451       <require condition="ARMv7-A Device"/>
2452       <require condition="ARMCC GCC IAR"/>
2453       <require Cclass="CMSIS"  Cgroup="CORE"/>
2454       <require Cclass="Device" Cgroup="Startup"/>
2455       <require Cclass="Device" Cgroup="OS Tick"/>
2456       <require Cclass="Device" Cgroup="IRQ Controller"/>
2457     </condition>
2458     <condition id="RTOS2 RTX5 Lib">
2459       <description>Components required for RTOS2 RTX5 Library</description>
2460       <require condition="ARMv6_7_8-M Device"/>
2461       <require condition="ARMCC GCC IAR"/>
2462       <require Cclass="CMSIS"  Cgroup="CORE"/>
2463       <require Cclass="Device" Cgroup="Startup"/>
2464     </condition>
2465     <condition id="RTOS2 RTX5 NS">
2466       <description>Components required for RTOS2 RTX5 in Non-Secure Domain</description>
2467       <require condition="ARMv8-M TZ Device"/>
2468       <require condition="ARMCC GCC IAR"/>
2469       <require Cclass="CMSIS"  Cgroup="CORE"/>
2470       <require Cclass="Device" Cgroup="Startup"/>
2471     </condition>
2472
2473     <!-- OS Tick -->
2474     <condition id="OS Tick PTIM">
2475       <description>Components required for OS Tick Private Timer</description>
2476       <require condition="CA5_CA9"/>
2477       <require Cclass="Device" Cgroup="IRQ Controller"/>
2478     </condition>
2479
2480     <condition id="OS Tick GTIM">
2481       <description>Components required for OS Tick Generic Physical Timer</description>
2482       <require condition="CA7"/>
2483       <require Cclass="Device" Cgroup="IRQ Controller"/>
2484     </condition>
2485
2486   </conditions>
2487
2488   <components>
2489     <!-- CMSIS-Core component -->
2490     <component Cclass="CMSIS" Cgroup="CORE" Cversion="5.1.2"  condition="ARMv6_7_8-M Device" >
2491       <description>CMSIS-CORE for Cortex-M, SC000, SC300, ARMv8-M</description>
2492       <files>
2493         <!-- CPU independent -->
2494         <file category="doc"     name="CMSIS/Documentation/Core/html/index.html"/>
2495         <file category="include" name="CMSIS/Core/Include/"/>
2496         <file category="header"  name="CMSIS/Core/Include/tz_context.h" condition="ARMv8-M TZ Device"/>
2497         <!-- Code template -->
2498         <file category="sourceC" attr="template" condition="ARMv8-M TZ Device" name="CMSIS/Core/Template/ARMv8-M/main_s.c"     version="1.1.0" select="Secure mode 'main' module for ARMv8-M"/>
2499         <file category="sourceC" attr="template" condition="ARMv8-M TZ Device" name="CMSIS/Core/Template/ARMv8-M/tz_context.c" version="1.1.0" select="RTOS Context Management (TrustZone for ARMv8-M)" />
2500       </files>
2501     </component>
2502
2503     <component Cclass="CMSIS" Cgroup="CORE" Cversion="1.1.2"  condition="ARMv7-A Device" >
2504       <description>CMSIS-CORE for Cortex-A</description>
2505       <files>
2506         <!-- CPU independent -->
2507         <file category="doc"     name="CMSIS/Documentation/Core_A/html/index.html"/>
2508         <file category="include" name="CMSIS/Core_A/Include/"/>
2509       </files>
2510     </component>
2511
2512     <!-- CMSIS-Startup components -->
2513     <!-- Cortex-M0 -->
2514     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM0 CMSIS">
2515       <description>System and Startup for Generic Arm Cortex-M0 device</description>
2516       <files>
2517         <!-- include folder / device header file -->
2518         <file category="header"  name="Device/ARM/ARMCM0/Include/ARMCM0.h"/>
2519         <!-- startup / system file -->
2520         <file category="sourceAsm"    name="Device/ARM/ARMCM0/Source/ARM/startup_ARMCM0.s" version="1.0.0" attr="config" condition="ARMCC"/>
2521         <file category="sourceAsm"    name="Device/ARM/ARMCM0/Source/GCC/startup_ARMCM0.S" version="1.0.0" attr="config" condition="GCC"/>
2522         <file category="linkerScript" name="Device/ARM/ARMCM0/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2523         <file category="sourceAsm"    name="Device/ARM/ARMCM0/Source/IAR/startup_ARMCM0.s" version="1.0.0" attr="config" condition="IAR"/>
2524         <file category="sourceC"      name="Device/ARM/ARMCM0/Source/system_ARMCM0.c"      version="1.0.0" attr="config"/>
2525       </files>
2526     </component>
2527     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM0 CMSIS GCC">
2528       <description>System and Startup for Generic Arm Cortex-M0 device</description>
2529       <files>
2530         <!-- include folder / device header file -->
2531         <file category="header"  name="Device/ARM/ARMCM0/Include/ARMCM0.h"/>
2532         <!-- startup / system file -->
2533         <file category="sourceC"      name="Device/ARM/ARMCM0/Source/GCC/startup_ARMCM0.c" version="1.0.0" attr="config" condition="GCC"/>
2534         <file category="linkerScript" name="Device/ARM/ARMCM0/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2535         <file category="sourceC"      name="Device/ARM/ARMCM0/Source/system_ARMCM0.c"      version="1.0.0" attr="config"/>
2536       </files>
2537     </component>
2538
2539     <!-- Cortex-M0+ -->
2540     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM0+ CMSIS">
2541       <description>System and Startup for Generic Arm Cortex-M0+ device</description>
2542       <files>
2543         <!-- include folder / device header file -->
2544         <file category="header"  name="Device/ARM/ARMCM0plus/Include/ARMCM0plus.h"/>
2545         <!-- startup / system file -->
2546         <file category="sourceAsm"    name="Device/ARM/ARMCM0plus/Source/ARM/startup_ARMCM0plus.s" version="1.0.0" attr="config" condition="ARMCC"/>
2547         <file category="sourceAsm"    name="Device/ARM/ARMCM0plus/Source/GCC/startup_ARMCM0plus.S" version="1.0.0" attr="config" condition="GCC"/>
2548         <file category="linkerScript" name="Device/ARM/ARMCM0plus/Source/GCC/gcc_arm.ld"           version="1.0.0" attr="config" condition="GCC"/>
2549         <file category="sourceAsm"    name="Device/ARM/ARMCM0plus/Source/IAR/startup_ARMCM0plus.s" version="1.0.0" attr="config" condition="IAR"/>
2550         <file category="sourceC"      name="Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c"      version="1.0.0" attr="config"/>
2551       </files>
2552     </component>
2553     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM0+ CMSIS GCC">
2554       <description>System and Startup for Generic Arm Cortex-M0+ device</description>
2555       <files>
2556         <!-- include folder / device header file -->
2557         <file category="header"  name="Device/ARM/ARMCM0plus/Include/ARMCM0plus.h"/>
2558         <!-- startup / system file -->
2559         <file category="sourceC"      name="Device/ARM/ARMCM0plus/Source/GCC/startup_ARMCM0plus.c" version="1.0.0" attr="config" condition="GCC"/>
2560         <file category="linkerScript" name="Device/ARM/ARMCM0plus/Source/GCC/gcc_arm.ld"           version="1.0.0" attr="config" condition="GCC"/>
2561         <file category="sourceC"      name="Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c"      version="1.0.0" attr="config"/>
2562       </files>
2563     </component>
2564
2565     <!-- Cortex-M1 -->
2566     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM1 CMSIS">
2567       <description>System and Startup for Generic Arm Cortex-M1 device</description>
2568       <files>
2569         <!-- include folder / device header file -->
2570         <file category="header"  name="Device/ARM/ARMCM1/Include/ARMCM1.h"/>
2571         <!-- startup / system file -->
2572         <file category="sourceAsm"    name="Device/ARM/ARMCM1/Source/ARM/startup_ARMCM1.s" version="1.0.0" attr="config" condition="ARMCC"/>
2573         <file category="sourceAsm"    name="Device/ARM/ARMCM1/Source/GCC/startup_ARMCM1.S" version="1.0.0" attr="config" condition="GCC"/>
2574         <file category="linkerScript" name="Device/ARM/ARMCM1/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2575         <file category="sourceAsm"    name="Device/ARM/ARMCM1/Source/IAR/startup_ARMCM1.s" version="1.0.0" attr="config" condition="IAR"/>
2576         <file category="sourceC"      name="Device/ARM/ARMCM1/Source/system_ARMCM1.c"      version="1.0.0" attr="config"/>
2577       </files>
2578     </component>
2579     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM1 CMSIS GCC">
2580       <description>System and Startup for Generic Arm Cortex-M1 device</description>
2581       <files>
2582         <!-- include folder / device header file -->
2583         <file category="header"  name="Device/ARM/ARMCM1/Include/ARMCM1.h"/>
2584         <!-- startup / system file -->
2585         <file category="sourceC"      name="Device/ARM/ARMCM1/Source/GCC/startup_ARMCM1.c" version="1.0.0" attr="config" condition="GCC"/>
2586         <file category="linkerScript" name="Device/ARM/ARMCM1/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2587         <file category="sourceC"      name="Device/ARM/ARMCM1/Source/system_ARMCM1.c"      version="1.0.0" attr="config"/>
2588       </files>
2589     </component>
2590
2591     <!-- Cortex-M3 -->
2592     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM3 CMSIS">
2593       <description>System and Startup for Generic Arm Cortex-M3 device</description>
2594       <files>
2595         <!-- include folder / device header file -->
2596         <file category="header"  name="Device/ARM/ARMCM3/Include/ARMCM3.h"/>
2597         <!-- startup / system file -->
2598         <file category="sourceAsm"    name="Device/ARM/ARMCM3/Source/ARM/startup_ARMCM3.s" version="1.0.0" attr="config" condition="ARMCC"/>
2599         <file category="sourceAsm"    name="Device/ARM/ARMCM3/Source/GCC/startup_ARMCM3.S" version="1.0.0" attr="config" condition="GCC"/>
2600         <file category="linkerScript" name="Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2601         <file category="sourceAsm"    name="Device/ARM/ARMCM3/Source/IAR/startup_ARMCM3.s" version="1.0.0" attr="config" condition="IAR"/>
2602         <file category="sourceC"      name="Device/ARM/ARMCM3/Source/system_ARMCM3.c"      version="1.0.0" attr="config"/>
2603       </files>
2604     </component>
2605     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM3 CMSIS GCC">
2606       <description>System and Startup for Generic Arm Cortex-M3 device</description>
2607       <files>
2608         <!-- include folder / device header file -->
2609         <file category="header"  name="Device/ARM/ARMCM3/Include/ARMCM3.h"/>
2610         <!-- startup / system file -->
2611         <file category="sourceC"      name="Device/ARM/ARMCM3/Source/GCC/startup_ARMCM3.c" version="1.0.0" attr="config" condition="GCC"/>
2612         <file category="linkerScript" name="Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2613         <file category="sourceC"      name="Device/ARM/ARMCM3/Source/system_ARMCM3.c"      version="1.0.0" attr="config"/>
2614       </files>
2615     </component>
2616
2617     <!-- Cortex-M4 -->
2618     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM4 CMSIS">
2619       <description>System and Startup for Generic Arm Cortex-M4 device</description>
2620       <files>
2621         <!-- include folder / device header file -->
2622         <file category="include" name="Device/ARM/ARMCM4/Include/"/>
2623         <!-- startup / system file -->
2624         <file category="sourceAsm"    name="Device/ARM/ARMCM4/Source/ARM/startup_ARMCM4.s" version="1.0.0" attr="config" condition="ARMCC"/>
2625         <file category="sourceAsm"    name="Device/ARM/ARMCM4/Source/GCC/startup_ARMCM4.S" version="1.0.0" attr="config" condition="GCC"/>
2626         <file category="linkerScript" name="Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2627         <file category="sourceAsm"    name="Device/ARM/ARMCM4/Source/IAR/startup_ARMCM4.s" version="1.0.0" attr="config" condition="IAR"/>
2628         <file category="sourceC"      name="Device/ARM/ARMCM4/Source/system_ARMCM4.c"      version="1.0.0" attr="config"/>
2629       </files>
2630     </component>
2631     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM4 CMSIS GCC">
2632       <description>System and Startup for Generic Arm Cortex-M4 device</description>
2633       <files>
2634         <!-- include folder / device header file -->
2635         <file category="include" name="Device/ARM/ARMCM4/Include/"/>
2636         <!-- startup / system file -->
2637         <file category="sourceC"      name="Device/ARM/ARMCM4/Source/GCC/startup_ARMCM4.c" version="1.0.0" attr="config" condition="GCC"/>
2638         <file category="linkerScript" name="Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2639         <file category="sourceC"      name="Device/ARM/ARMCM4/Source/system_ARMCM4.c"      version="1.0.0" attr="config"/>
2640       </files>
2641     </component>
2642
2643     <!-- Cortex-M7 -->
2644     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM7 CMSIS">
2645       <description>System and Startup for Generic Arm Cortex-M7 device</description>
2646       <files>
2647         <!-- include folder / device header file -->
2648         <file category="include"  name="Device/ARM/ARMCM7/Include/"/>
2649         <!-- startup / system file -->
2650         <file category="sourceAsm"    name="Device/ARM/ARMCM7/Source/ARM/startup_ARMCM7.s" version="1.0.0" attr="config" condition="ARMCC"/>
2651         <file category="sourceAsm"    name="Device/ARM/ARMCM7/Source/GCC/startup_ARMCM7.S" version="1.0.0" attr="config" condition="GCC"/>
2652         <file category="linkerScript" name="Device/ARM/ARMCM7/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2653         <file category="sourceAsm"    name="Device/ARM/ARMCM7/Source/IAR/startup_ARMCM7.s" version="1.0.0" attr="config" condition="IAR"/>
2654         <file category="sourceC"      name="Device/ARM/ARMCM7/Source/system_ARMCM7.c"      version="1.0.0" attr="config"/>
2655       </files>
2656     </component>
2657     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM7 CMSIS GCC">
2658       <description>System and Startup for Generic Arm Cortex-M7 device</description>
2659       <files>
2660         <!-- include folder / device header file -->
2661         <file category="include"  name="Device/ARM/ARMCM7/Include/"/>
2662         <!-- startup / system file -->
2663         <file category="sourceC"      name="Device/ARM/ARMCM7/Source/GCC/startup_ARMCM7.c" version="1.0.0" attr="config" condition="GCC"/>
2664         <file category="linkerScript" name="Device/ARM/ARMCM7/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2665         <file category="sourceC"      name="Device/ARM/ARMCM7/Source/system_ARMCM7.c"      version="1.0.0" attr="config"/>
2666       </files>
2667     </component>
2668
2669     <!-- Cortex-M23 -->
2670     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.0" condition="ARMCM23 CMSIS">
2671       <description>System and Startup for Generic Arm Cortex-M23 device</description>
2672       <files>
2673         <!-- include folder / device header file -->
2674         <file category="include"      name="Device/ARM/ARMCM23/Include/"/>
2675         <!-- startup / system file -->
2676         <file category="sourceAsm"    name="Device/ARM/ARMCM23/Source/ARM/startup_ARMCM23.s" version="1.0.0" attr="config" condition="ARMCC"/>
2677         <file category="sourceAsm"    name="Device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.S" version="1.0.0" attr="config" condition="GCC"/>
2678         <file category="linkerScript" name="Device/ARM/ARMCM23/Source/GCC/gcc_arm.ld"        version="1.0.0" attr="config" condition="GCC"/>
2679         <file category="sourceAsm"    name="Device/ARM/ARMCM23/Source/IAR/startup_ARMCM23.s" version="1.0.0" attr="config" condition="IAR"/>
2680         <file category="sourceC"      name="Device/ARM/ARMCM23/Source/system_ARMCM23.c"      version="1.0.0" attr="config"/>
2681         <!-- SAU configuration -->
2682         <file category="header"       name="Device/ARM/ARMCM23/Include/Template/partition_ARMCM23.h" version="1.0.0" attr="config" condition="ARMv8-M TZ Device"/>
2683       </files>
2684     </component>
2685     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.0" condition="ARMCM23 CMSIS GCC">
2686       <description>System and Startup for Generic Arm Cortex-M23 device</description>
2687       <files>
2688         <!-- include folder / device header file -->
2689         <file category="include"  name="Device/ARM/ARMCM23/Include/"/>
2690         <!-- startup / system file -->
2691         <file category="sourceC"      name="Device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.c" version="1.0.0" attr="config" condition="GCC"/>
2692         <file category="linkerScript" name="Device/ARM/ARMCM23/Source/GCC/gcc_arm.ld"        version="1.0.0" attr="config" condition="GCC"/>
2693         <file category="sourceC"      name="Device/ARM/ARMCM23/Source/system_ARMCM23.c"      version="1.0.0" attr="config"/>
2694         <!-- SAU configuration -->
2695         <file category="header"       name="Device/ARM/ARMCM23/Include/Template/partition_ARMCM23.h" version="1.0.0" attr="config" condition="ARMv8-M TZ Device"/>
2696       </files>
2697     </component>
2698
2699     <!-- Cortex-M33 -->
2700     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.1.0" condition="ARMCM33 CMSIS">
2701       <description>System and Startup for Generic Arm Cortex-M33 device</description>
2702       <files>
2703         <!-- include folder / device header file -->
2704         <file category="include"      name="Device/ARM/ARMCM33/Include/"/>
2705         <!-- startup / system file -->
2706         <file category="sourceAsm"    name="Device/ARM/ARMCM33/Source/ARM/startup_ARMCM33.s"         version="1.0.0" attr="config" condition="ARMCC"/>
2707         <file category="sourceAsm"    name="Device/ARM/ARMCM33/Source/GCC/startup_ARMCM33.S"         version="1.0.0" attr="config" condition="GCC"/>
2708         <file category="linkerScript" name="Device/ARM/ARMCM33/Source/GCC/gcc_arm.ld"                version="1.0.0" attr="config" condition="GCC"/>
2709         <file category="sourceAsm"    name="Device/ARM/ARMCM33/Source/IAR/startup_ARMCM33.s"         version="1.0.0" attr="config" condition="IAR"/>
2710         <file category="sourceC"      name="Device/ARM/ARMCM33/Source/system_ARMCM33.c"              version="1.0.0" attr="config"/>
2711         <!-- SAU configuration -->
2712         <file category="header"       name="Device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2713       </files>
2714     </component>
2715     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.1.0" condition="ARMCM33 CMSIS GCC">
2716       <description>System and Startup for Generic Arm Cortex-M33 device</description>
2717       <files>
2718         <!-- include folder / device header file -->
2719         <file category="include"  name="Device/ARM/ARMCM33/Include/"/>
2720         <!-- startup / system file -->
2721         <file category="sourceC"      name="Device/ARM/ARMCM33/Source/GCC/startup_ARMCM33.c"         version="1.0.0" attr="config" condition="GCC"/>
2722         <file category="linkerScript" name="Device/ARM/ARMCM33/Source/GCC/gcc_arm.ld"                version="1.0.0" attr="config" condition="GCC"/>
2723         <file category="sourceC"      name="Device/ARM/ARMCM33/Source/system_ARMCM33.c"              version="1.0.0" attr="config"/>
2724         <!-- SAU configuration -->
2725         <file category="header"       name="Device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2726       </files>
2727     </component>
2728
2729     <!-- Cortex-M35P -->
2730     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.1.0" condition="ARMCM35P CMSIS">
2731       <description>System and Startup for Generic Arm Cortex-M35P device</description>
2732       <files>
2733         <!-- include folder / device header file -->
2734         <file category="include"      name="Device/ARM/ARMCM35P/Include/"/>
2735         <!-- startup / system file -->
2736         <file category="sourceAsm"    name="Device/ARM/ARMCM35P/Source/ARM/startup_ARMCM35P.s"         version="1.0.0" attr="config" condition="ARMCC"/>
2737         <file category="sourceAsm"    name="Device/ARM/ARMCM35P/Source/GCC/startup_ARMCM35P.S"         version="1.0.0" attr="config" condition="GCC"/>
2738         <file category="linkerScript" name="Device/ARM/ARMCM35P/Source/GCC/gcc_arm.ld"                 version="1.0.0" attr="config" condition="GCC"/>
2739         <file category="sourceAsm"    name="Device/ARM/ARMCM35P/Source/IAR/startup_ARMCM35P.s"         version="1.0.0" attr="config" condition="IAR"/>
2740         <file category="sourceC"      name="Device/ARM/ARMCM35P/Source/system_ARMCM35P.c"              version="1.0.0" attr="config"/>
2741         <!-- SAU configuration -->
2742         <file category="header"       name="Device/ARM/ARMCM35P/Include/Template/partition_ARMCM35P.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2743       </files>
2744     </component>
2745     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.1.0" condition="ARMCM35P CMSIS GCC">
2746       <description>System and Startup for Generic Arm Cortex-M35P device</description>
2747       <files>
2748         <!-- include folder / device header file -->
2749         <file category="include"  name="Device/ARM/ARMCM35P/Include/"/>
2750         <!-- startup / system file -->
2751         <file category="sourceC"      name="Device/ARM/ARMCM35P/Source/GCC/startup_ARMCM35P.c"         version="1.0.0" attr="config" condition="GCC"/>
2752         <file category="linkerScript" name="Device/ARM/ARMCM35P/Source/GCC/gcc_arm.ld"                 version="1.0.0" attr="config" condition="GCC"/>
2753         <file category="sourceC"      name="Device/ARM/ARMCM35P/Source/system_ARMCM35P.c"              version="1.0.0" attr="config"/>
2754         <!-- SAU configuration -->
2755         <file category="header"       name="Device/ARM/ARMCM35P/Include/Template/partition_ARMCM35P.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2756       </files>
2757     </component>
2758
2759     <!-- Cortex-SC000 -->
2760     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMSC000 CMSIS">
2761       <description>System and Startup for Generic Arm SC000 device</description>
2762       <files>
2763         <!-- include folder / device header file -->
2764         <file category="header"  name="Device/ARM/ARMSC000/Include/ARMSC000.h"/>
2765         <!-- startup / system file -->
2766         <file category="sourceAsm"    name="Device/ARM/ARMSC000/Source/ARM/startup_ARMSC000.s" version="1.0.0" attr="config" condition="ARMCC"/>
2767         <file category="sourceAsm"    name="Device/ARM/ARMSC000/Source/GCC/startup_ARMSC000.S" version="1.0.0" attr="config" condition="GCC"/>
2768         <file category="linkerScript" name="Device/ARM/ARMSC000/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2769         <file category="sourceAsm"    name="Device/ARM/ARMSC000/Source/IAR/startup_ARMSC000.s" version="1.0.0" attr="config" condition="IAR"/>
2770         <file category="sourceC"      name="Device/ARM/ARMSC000/Source/system_ARMSC000.c"      version="1.0.0" attr="config"/>
2771       </files>
2772     </component>
2773     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMSC000 CMSIS GCC">
2774       <description>System and Startup for Generic Arm SC000 device</description>
2775       <files>
2776         <!-- include folder / device header file -->
2777         <file category="header"  name="Device/ARM/ARMSC000/Include/ARMSC000.h"/>
2778         <!-- startup / system file -->
2779         <file category="sourceC"      name="Device/ARM/ARMSC000/Source/GCC/startup_ARMSC000.c" version="1.0.0" attr="config" condition="GCC"/>
2780         <file category="linkerScript" name="Device/ARM/ARMSC000/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2781         <file category="sourceC"      name="Device/ARM/ARMSC000/Source/system_ARMSC000.c"      version="1.0.0" attr="config"/>
2782       </files>
2783     </component>
2784
2785     <!-- Cortex-SC300 -->
2786     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMSC300 CMSIS">
2787       <description>System and Startup for Generic Arm SC300 device</description>
2788       <files>
2789         <!-- include folder / device header file -->
2790         <file category="header"  name="Device/ARM/ARMSC300/Include/ARMSC300.h"/>
2791         <!-- startup / system file -->
2792         <file category="sourceAsm"    name="Device/ARM/ARMSC300/Source/ARM/startup_ARMSC300.s" version="1.0.0" attr="config" condition="ARMCC"/>
2793         <file category="sourceAsm"    name="Device/ARM/ARMSC300/Source/GCC/startup_ARMSC300.S" version="1.0.0" attr="config" condition="GCC"/>
2794         <file category="linkerScript" name="Device/ARM/ARMSC300/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2795         <file category="sourceAsm"    name="Device/ARM/ARMSC300/Source/IAR/startup_ARMSC300.s" version="1.0.0" attr="config" condition="IAR"/>
2796         <file category="sourceC"      name="Device/ARM/ARMSC300/Source/system_ARMSC300.c"      version="1.0.0" attr="config"/>
2797       </files>
2798     </component>
2799     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMSC300 CMSIS GCC">
2800       <description>System and Startup for Generic Arm SC300 device</description>
2801       <files>
2802         <!-- include folder / device header file -->
2803         <file category="header"  name="Device/ARM/ARMSC300/Include/ARMSC300.h"/>
2804         <!-- startup / system file -->
2805         <file category="sourceC"      name="Device/ARM/ARMSC300/Source/GCC/startup_ARMSC300.c" version="1.0.0" attr="config" condition="GCC"/>
2806         <file category="linkerScript" name="Device/ARM/ARMSC300/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2807         <file category="sourceC"      name="Device/ARM/ARMSC300/Source/system_ARMSC300.c"      version="1.0.0" attr="config"/>
2808       </files>
2809     </component>
2810
2811     <!-- ARMv8MBL -->
2812     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.0" condition="ARMv8MBL CMSIS">
2813       <description>System and Startup for Generic Armv8-M Baseline device</description>
2814       <files>
2815         <!-- include folder / device header file -->
2816         <file category="include"      name="Device/ARM/ARMv8MBL/Include/"/>
2817         <!-- startup / system file -->
2818         <file category="sourceAsm"    name="Device/ARM/ARMv8MBL/Source/ARM/startup_ARMv8MBL.s" version="1.0.0" attr="config" condition="ARMCC"/>
2819         <file category="sourceAsm"    name="Device/ARM/ARMv8MBL/Source/GCC/startup_ARMv8MBL.S" version="1.0.0" attr="config" condition="GCC"/>
2820         <file category="linkerScript" name="Device/ARM/ARMv8MBL/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2821         <file category="sourceC"      name="Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c"      version="1.0.0" attr="config" condition="ARMCC GCC"/>
2822         <!-- SAU configuration -->
2823         <file category="header"       name="Device/ARM/ARMv8MBL/Include/Template/partition_ARMv8MBL.h" version="1.0.0" attr="config"/>
2824       </files>
2825     </component>
2826     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.0" condition="ARMv8MBL CMSIS GCC">
2827       <description>System and Startup for Generic Armv8-M Baseline device</description>
2828       <files>
2829         <!-- include folder / device header file -->
2830         <file category="include"  name="Device/ARM/ARMv8MBL/Include/"/>
2831         <!-- startup / system file -->
2832         <file category="sourceC"      name="Device/ARM/ARMv8MBL/Source/GCC/startup_ARMv8MBL.c" version="1.0.0" attr="config" condition="GCC"/>
2833         <file category="linkerScript" name="Device/ARM/ARMv8MBL/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2834         <file category="sourceC"      name="Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c"      version="1.0.0" attr="config"/>
2835         <!-- SAU configuration -->
2836         <file category="header"       name="Device/ARM/ARMv8MBL/Include/Template/partition_ARMv8MBL.h" version="1.0.0" attr="config" condition="ARMv8-M TZ Device"/>
2837       </files>
2838     </component>
2839
2840     <!-- ARMv8MML -->
2841     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.1.0" condition="ARMv8MML CMSIS">
2842       <description>System and Startup for Generic Armv8-M Mainline device</description>
2843       <files>
2844         <!-- include folder / device header file -->
2845         <file category="include"      name="Device/ARM/ARMv8MML/Include/"/>
2846         <!-- startup / system file -->
2847         <file category="sourceAsm"    name="Device/ARM/ARMv8MML/Source/ARM/startup_ARMv8MML.s"         version="1.0.0" attr="config" condition="ARMCC"/>
2848         <file category="sourceAsm"    name="Device/ARM/ARMv8MML/Source/GCC/startup_ARMv8MML.S"         version="1.0.0" attr="config" condition="GCC"/>
2849         <file category="linkerScript" name="Device/ARM/ARMv8MML/Source/GCC/gcc_arm.ld"                 version="1.0.0" attr="config" condition="GCC"/>
2850         <file category="sourceC"      name="Device/ARM/ARMv8MML/Source/system_ARMv8MML.c"              version="1.0.0" attr="config" condition="ARMCC GCC"/>
2851         <!-- SAU configuration -->
2852         <file category="header"       name="Device/ARM/ARMv8MML/Include/Template/partition_ARMv8MML.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2853       </files>
2854     </component>
2855     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.1.0" condition="ARMv8MML CMSIS GCC">
2856       <description>System and Startup for Generic Armv8-M Mainline device</description>
2857       <files>
2858         <!-- include folder / device header file -->
2859         <file category="include"      name="Device/ARM/ARMv8MML/Include/"/>
2860         <!-- startup / system file -->
2861         <file category="sourceC"      name="Device/ARM/ARMv8MML/Source/GCC/startup_ARMv8MML.c"         version="1.0.0" attr="config" condition="GCC"/>
2862         <file category="linkerScript" name="Device/ARM/ARMv8MML/Source/GCC/gcc_arm.ld"                 version="1.0.0" attr="config" condition="GCC"/>
2863         <file category="sourceC"      name="Device/ARM/ARMv8MML/Source/system_ARMv8MML.c"              version="1.0.0" attr="config"/>
2864         <!-- SAU configuration -->
2865         <file category="header"       name="Device/ARM/ARMv8MML/Include/Template/partition_ARMv8MML.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2866       </files>
2867     </component>
2868
2869     <!-- Cortex-A5 -->
2870     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.0" condition="ARMCA5 CMSIS">
2871       <description>System and Startup for Generic Arm Cortex-A5 device</description>
2872       <files>
2873         <!-- include folder / device header file -->
2874         <file category="include"      name="Device/ARM/ARMCA5/Include/"/>
2875         <!-- startup / system / mmu files -->
2876         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/AC5/startup_ARMCA5.c" version="1.0.0" attr="config" condition="ARMCC5"/>
2877         <file category="linkerScript" name="Device/ARM/ARMCA5/Source/AC5/ARMCA5.sct"       version="1.0.0" attr="config" condition="ARMCC5"/>
2878         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/AC6/startup_ARMCA5.c" version="1.0.0" attr="config" condition="ARMCC6"/>
2879         <file category="linkerScript" name="Device/ARM/ARMCA5/Source/AC6/ARMCA5.sct"       version="1.0.0" attr="config" condition="ARMCC6"/>
2880         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/GCC/startup_ARMCA5.c" version="1.0.0" attr="config" condition="GCC"/>
2881         <file category="other"        name="Device/ARM/ARMCA5/Source/GCC/ARMCA5.ld"        version="1.0.0" attr="config" condition="GCC"/>
2882         <file category="sourceAsm"    name="Device/ARM/ARMCA5/Source/IAR/startup_ARMCA5.s" version="1.0.0" attr="config" condition="IAR"/>
2883         <file category="linkerScript" name="Device/ARM/ARMCA5/Source/IAR/ARMCA5.icf"       version="1.0.0" attr="config" condition="IAR"/>
2884         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/system_ARMCA5.c"      version="1.0.0" attr="config"/>
2885         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/mmu_ARMCA5.c"         version="1.0.0" attr="config"/>
2886         <file category="header"       name="Device/ARM/ARMCA5/Include/system_ARMCA5.h"     version="1.0.0" attr="config"/>
2887         <file category="header"       name="Device/ARM/ARMCA5/Include/mem_ARMCA5.h"        version="1.0.0" attr="config"/>
2888
2889       </files>
2890     </component>
2891
2892     <!-- Cortex-A7 -->
2893     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.0" condition="ARMCA7 CMSIS">
2894       <description>System and Startup for Generic Arm Cortex-A7 device</description>
2895       <files>
2896         <!-- include folder / device header file -->
2897         <file category="include"      name="Device/ARM/ARMCA7/Include/"/>
2898         <!-- startup / system / mmu files -->
2899         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/AC5/startup_ARMCA7.c" version="1.0.0" attr="config" condition="ARMCC5"/>
2900         <file category="linkerScript" name="Device/ARM/ARMCA7/Source/AC5/ARMCA7.sct"       version="1.0.0" attr="config" condition="ARMCC5"/>
2901         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/AC6/startup_ARMCA7.c" version="1.0.0" attr="config" condition="ARMCC6"/>
2902         <file category="linkerScript" name="Device/ARM/ARMCA7/Source/AC6/ARMCA7.sct"       version="1.0.0" attr="config" condition="ARMCC6"/>
2903         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/GCC/startup_ARMCA7.c" version="1.0.0" attr="config" condition="GCC"/>
2904         <file category="other"        name="Device/ARM/ARMCA7/Source/GCC/ARMCA7.ld"        version="1.0.0" attr="config" condition="GCC"/>
2905         <file category="sourceAsm"    name="Device/ARM/ARMCA7/Source/IAR/startup_ARMCA7.s" version="1.0.0" attr="config" condition="IAR"/>
2906         <file category="linkerScript" name="Device/ARM/ARMCA7/Source/IAR/ARMCA7.icf"       version="1.0.0" attr="config" condition="IAR"/>
2907         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/system_ARMCA7.c"      version="1.0.0" attr="config"/>
2908         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/mmu_ARMCA7.c"         version="1.0.0" attr="config"/>
2909         <file category="header"       name="Device/ARM/ARMCA7/Include/system_ARMCA7.h"     version="1.0.0" attr="config"/>
2910         <file category="header"       name="Device/ARM/ARMCA7/Include/mem_ARMCA7.h"        version="1.0.0" attr="config"/>
2911       </files>
2912     </component>
2913
2914     <!-- Cortex-A9 -->
2915     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCA9 CMSIS">
2916       <description>System and Startup for Generic Arm Cortex-A9 device</description>
2917       <files>
2918         <!-- include folder / device header file -->
2919         <file category="include"  name="Device/ARM/ARMCA9/Include/"/>
2920         <!-- startup / system / mmu files -->
2921         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/AC5/startup_ARMCA9.c" version="1.0.0" attr="config" condition="ARMCC5"/>
2922         <file category="linkerScript" name="Device/ARM/ARMCA9/Source/AC5/ARMCA9.sct"       version="1.0.0" attr="config" condition="ARMCC5"/>
2923         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/AC6/startup_ARMCA9.c" version="1.0.0" attr="config" condition="ARMCC6"/>
2924         <file category="linkerScript" name="Device/ARM/ARMCA9/Source/AC6/ARMCA9.sct"       version="1.0.0" attr="config" condition="ARMCC6"/>
2925         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/GCC/startup_ARMCA9.c" version="1.0.0" attr="config" condition="GCC"/>
2926         <file category="other"        name="Device/ARM/ARMCA9/Source/GCC/ARMCA9.ld"        version="1.0.0" attr="config" condition="GCC"/>
2927         <file category="sourceAsm"    name="Device/ARM/ARMCA9/Source/IAR/startup_ARMCA9.s" version="1.0.0" attr="config" condition="IAR"/>
2928         <file category="linkerScript" name="Device/ARM/ARMCA9/Source/IAR/ARMCA9.icf"       version="1.0.0" attr="config" condition="IAR"/>
2929         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/system_ARMCA9.c"      version="1.0.0" attr="config"/>
2930         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/mmu_ARMCA9.c"         version="1.0.0" attr="config"/>
2931         <file category="header"       name="Device/ARM/ARMCA9/Include/system_ARMCA9.h"     version="1.0.0" attr="config"/>
2932         <file category="header"       name="Device/ARM/ARMCA9/Include/mem_ARMCA9.h"        version="1.0.0" attr="config"/>
2933       </files>
2934     </component>
2935
2936     <!-- IRQ Controller -->
2937     <component Cclass="Device" Cgroup="IRQ Controller" Csub="GIC" Capiversion="1.0.0" Cversion="1.0.1" condition="ARMv7-A Device">
2938       <description>IRQ Controller implementation using GIC</description>
2939       <files>
2940         <file category="sourceC" name="CMSIS/Core_A/Source/irq_ctrl_gic.c"/>
2941       </files>
2942     </component>
2943
2944     <!-- OS Tick -->
2945     <component Cclass="Device" Cgroup="OS Tick" Csub="Private Timer" Capiversion="1.0.1" Cversion="1.0.2" condition="OS Tick PTIM">
2946       <description>OS Tick implementation using Private Timer</description>
2947       <files>
2948         <file category="sourceC" name="CMSIS/RTOS2/Source/os_tick_ptim.c"/>
2949       </files>
2950     </component>
2951
2952     <component Cclass="Device" Cgroup="OS Tick" Csub="Generic Physical Timer" Capiversion="1.0.1" Cversion="1.0.1" condition="OS Tick GTIM">
2953       <description>OS Tick implementation using Generic Physical Timer</description>
2954       <files>
2955         <file category="sourceC" name="CMSIS/RTOS2/Source/os_tick_gtim.c"/>
2956       </files>
2957     </component>
2958
2959     <!-- CMSIS-DSP component -->
2960     <component Cclass="CMSIS" Cgroup="DSP" Cversion="1.5.2" condition="CMSIS DSP">
2961       <description>CMSIS-DSP Library for Cortex-M, SC000, and SC300</description>
2962       <files>
2963         <!-- CPU independent -->
2964         <file category="doc" name="CMSIS/Documentation/DSP/html/index.html"/>
2965         <file category="header" name="CMSIS/DSP/Include/arm_math.h"/>
2966
2967         <!-- CPU and Compiler dependent -->
2968         <!-- ARMCC -->
2969         <file category="library" condition="CM0_LE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM0l_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2970         <file category="library" condition="CM0_BE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM0b_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2971         <file category="library" condition="CM1_LE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM0l_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2972         <file category="library" condition="CM1_BE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM0b_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2973         <file category="library" condition="CM3_LE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM3l_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2974         <file category="library" condition="CM3_BE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM3b_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2975         <file category="library" condition="CM4_LE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM4l_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2976         <file category="library" condition="CM4_BE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM4b_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2977         <file category="library" condition="CM4_FP_LE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM4lf_math.lib"     src="CMSIS/DSP/Source/ARM"/>
2978         <file category="library" condition="CM4_FP_BE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM4bf_math.lib"     src="CMSIS/DSP/Source/ARM"/>
2979         <file category="library" condition="CM7_LE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM7l_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2980         <file category="library" condition="CM7_BE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM7b_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2981         <file category="library" condition="CM7_SP_LE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM7lfsp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
2982         <file category="library" condition="CM7_SP_BE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM7bfsp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
2983         <file category="library" condition="CM7_DP_LE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM7lfdp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
2984         <file category="library" condition="CM7_DP_BE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM7bfdp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
2985
2986         <file category="library" condition="CM23_LE_ARMCC"                  name="CMSIS/Lib/ARM/arm_ARMv8MBLl_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2987         <file category="library" condition="CM33_NODSP_NOFPU_LE_ARMCC"      name="CMSIS/Lib/ARM/arm_ARMv8MMLl_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2988         <file category="library" condition="CM33_DSP_NOFPU_LE_ARMCC"        name="CMSIS/Lib/ARM/arm_ARMv8MMLld_math.lib"     src="CMSIS/DSP/Source/ARM"/>
2989         <file category="library" condition="CM33_NODSP_SP_LE_ARMCC"         name="CMSIS/Lib/ARM/arm_ARMv8MMLlfsp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
2990         <file category="library" condition="CM33_DSP_SP_LE_ARMCC"           name="CMSIS/Lib/ARM/arm_ARMv8MMLldfsp_math.lib"  src="CMSIS/DSP/Source/ARM"/>
2991         <file category="library" condition="CM35P_NODSP_NOFPU_LE_ARMCC"     name="CMSIS/Lib/ARM/arm_ARMv8MMLl_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2992         <file category="library" condition="CM35P_DSP_NOFPU_LE_ARMCC"       name="CMSIS/Lib/ARM/arm_ARMv8MMLld_math.lib"     src="CMSIS/DSP/Source/ARM"/>
2993         <file category="library" condition="CM35P_NODSP_SP_LE_ARMCC"        name="CMSIS/Lib/ARM/arm_ARMv8MMLlfsp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
2994         <file category="library" condition="CM35P_DSP_SP_LE_ARMCC"          name="CMSIS/Lib/ARM/arm_ARMv8MMLldfsp_math.lib"  src="CMSIS/DSP/Source/ARM"/>
2995         <file category="library" condition="ARMv8MBL_LE_ARMCC"              name="CMSIS/Lib/ARM/arm_ARMv8MBLl_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2996         <file category="library" condition="ARMv8MML_NODSP_NOFPU_LE_ARMCC"  name="CMSIS/Lib/ARM/arm_ARMv8MMLl_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2997         <file category="library" condition="ARMv8MML_DSP_NOFPU_LE_ARMCC"    name="CMSIS/Lib/ARM/arm_ARMv8MMLld_math.lib"     src="CMSIS/DSP/Source/ARM"/>
2998         <file category="library" condition="ARMv8MML_NODSP_SP_LE_ARMCC"     name="CMSIS/Lib/ARM/arm_ARMv8MMLlfsp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
2999         <file category="library" condition="ARMv8MML_DSP_SP_LE_ARMCC"       name="CMSIS/Lib/ARM/arm_ARMv8MMLldfsp_math.lib"  src="CMSIS/DSP/Source/ARM"/>
3000         <!--file category="library" condition="ARMv8MML_DP_NOFPU_LE_ARMCC"     name="CMSIS/Lib/ARM/arm_ARMv8MMLlfdp_math.lib"   src="CMSIS/DSP/Source/ARM"/-->
3001         <!--file category="library" condition="ARMv8MML_DSP_DP_LE_ARMCC"       name="CMSIS/Lib/ARM/arm_ARMv8MMLldfdp_math.lib"  src="CMSIS/DSP/Source/ARM"/-->
3002
3003         <!-- GCC -->
3004         <file category="library" condition="CM0_LE_GCC"               name="CMSIS/Lib/GCC/libarm_cortexM0l_math.a"     src="CMSIS/DSP/Source/GCC"/>
3005         <file category="library" condition="CM1_LE_GCC"               name="CMSIS/Lib/GCC/libarm_cortexM0l_math.a"     src="CMSIS/DSP/Source/GCC"/>
3006         <file category="library" condition="CM3_LE_GCC"               name="CMSIS/Lib/GCC/libarm_cortexM3l_math.a"     src="CMSIS/DSP/Source/GCC"/>
3007         <file category="library" condition="CM4_LE_GCC"               name="CMSIS/Lib/GCC/libarm_cortexM4l_math.a"     src="CMSIS/DSP/Source/GCC"/>
3008         <file category="library" condition="CM4_FP_LE_GCC"            name="CMSIS/Lib/GCC/libarm_cortexM4lf_math.a"    src="CMSIS/DSP/Source/GCC"/>
3009         <file category="library" condition="CM7_LE_GCC"               name="CMSIS/Lib/GCC/libarm_cortexM7l_math.a"     src="CMSIS/DSP/Source/GCC"/>
3010         <file category="library" condition="CM7_SP_LE_GCC"            name="CMSIS/Lib/GCC/libarm_cortexM7lfsp_math.a"  src="CMSIS/DSP/Source/GCC"/>
3011         <file category="library" condition="CM7_DP_LE_GCC"            name="CMSIS/Lib/GCC/libarm_cortexM7lfdp_math.a"  src="CMSIS/DSP/Source/GCC"/>
3012
3013         <file category="library" condition="CM23_LE_GCC"                    name="CMSIS/Lib/GCC/libarm_ARMv8MBLl_math.a"     src="CMSIS/DSP/Source/GCC"/>
3014         <file category="library" condition="CM33_NODSP_NOFPU_LE_GCC"        name="CMSIS/Lib/GCC/libarm_ARMv8MMLl_math.a"     src="CMSIS/DSP/Source/GCC"/>
3015         <file category="library" condition="CM33_DSP_NOFPU_LE_GCC"          name="CMSIS/Lib/GCC/libarm_ARMv8MMLld_math.a"    src="CMSIS/DSP/Source/GCC"/>
3016         <file category="library" condition="CM33_NODSP_SP_LE_GCC"           name="CMSIS/Lib/GCC/libarm_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP/Source/GCC"/>
3017         <file category="library" condition="CM33_DSP_SP_LE_GCC"             name="CMSIS/Lib/GCC/libarm_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
3018         <file category="library" condition="CM35P_NODSP_NOFPU_LE_GCC"       name="CMSIS/Lib/GCC/libarm_ARMv8MMLl_math.a"     src="CMSIS/DSP/Source/GCC"/>
3019         <file category="library" condition="CM35P_DSP_NOFPU_LE_GCC"         name="CMSIS/Lib/GCC/libarm_ARMv8MMLld_math.a"    src="CMSIS/DSP/Source/GCC"/>
3020         <file category="library" condition="CM35P_NODSP_SP_LE_GCC"          name="CMSIS/Lib/GCC/libarm_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP/Source/GCC"/>
3021         <file category="library" condition="CM35P_DSP_SP_LE_GCC"            name="CMSIS/Lib/GCC/libarm_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
3022         <file category="library" condition="ARMv8MBL_LE_GCC"                name="CMSIS/Lib/GCC/libarm_ARMv8MBLl_math.a"     src="CMSIS/DSP/Source/GCC"/>
3023         <file category="library" condition="ARMv8MML_NODSP_NOFPU_LE_GCC"    name="CMSIS/Lib/GCC/libarm_ARMv8MMLl_math.a"     src="CMSIS/DSP/Source/GCC"/>
3024         <file category="library" condition="ARMv8MML_DSP_NOFPU_LE_GCC"      name="CMSIS/Lib/GCC/libarm_ARMv8MMLld_math.a"    src="CMSIS/DSP/Source/GCC"/>
3025         <file category="library" condition="ARMv8MML_NODSP_SP_LE_GCC"       name="CMSIS/Lib/GCC/libarm_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP/Source/GCC"/>
3026         <file category="library" condition="ARMv8MML_DSP_SP_LE_GCC"         name="CMSIS/Lib/GCC/libarm_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
3027         <!--file category="library" condition="ARMv8MML_DP_NOFPU_LE_GCC"       name="CMSIS/Lib/GCC/libarm_ARMv8MMLlfdp_math.a"  src="CMSIS/DSP/Source/GCC"/-->
3028         <!--file category="library" condition="ARMv8MML_DSP_DP_LE_GCC"         name="CMSIS/Lib/GCC/libarm_ARMv8MMLldfdp_math.a" src="CMSIS/DSP/Source/GCC"/-->
3029
3030         <!-- IAR -->
3031         <file category="library" condition="CM0_LE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM0l_math.a"     src="CMSIS/DSP/Source/IAR"/>
3032         <file category="library" condition="CM0_BE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM0b_math.a"     src="CMSIS/DSP/Source/IAR"/>
3033         <file category="library" condition="CM1_LE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM0l_math.a"     src="CMSIS/DSP/Source/IAR"/>
3034         <file category="library" condition="CM1_BE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM0b_math.a"     src="CMSIS/DSP/Source/IAR"/>
3035         <file category="library" condition="CM3_LE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM3l_math.a"     src="CMSIS/DSP/Source/IAR"/>
3036         <file category="library" condition="CM3_BE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM3b_math.a"     src="CMSIS/DSP/Source/IAR"/>
3037         <file category="library" condition="CM4_LE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM4l_math.a"     src="CMSIS/DSP/Source/IAR"/>
3038         <file category="library" condition="CM4_BE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM4b_math.a"     src="CMSIS/DSP/Source/IAR"/>
3039         <file category="library" condition="CM4_FP_LE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM4lf_math.a"    src="CMSIS/DSP/Source/IAR"/>
3040         <file category="library" condition="CM4_FP_BE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM4bf_math.a"    src="CMSIS/DSP/Source/IAR"/>
3041         <file category="library" condition="CM7_LE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM7l_math.a"     src="CMSIS/DSP/Source/IAR"/>
3042         <file category="library" condition="CM7_BE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM7b_math.a"     src="CMSIS/DSP/Source/IAR"/>
3043         <file category="library" condition="CM7_DP_LE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM7lf_math.a"    src="CMSIS/DSP/Source/IAR"/>
3044         <file category="library" condition="CM7_DP_BE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM7bf_math.a"    src="CMSIS/DSP/Source/IAR"/>
3045         <file category="library" condition="CM7_SP_LE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM7ls_math.a"    src="CMSIS/DSP/Source/IAR"/>
3046         <file category="library" condition="CM7_SP_BE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM7bs_math.a"    src="CMSIS/DSP/Source/IAR"/>
3047
3048         <file category="library" condition="CM23_LE_IAR"              name="CMSIS/Lib/IAR/iar_ARMv8MBLl_math.a"     src="CMSIS/DSP/Source/IAR"/>
3049         <file category="library" condition="CM33_NODSP_NOFPU_LE_IAR"        name="CMSIS/Lib/IAR/iar_ARMv8MMLl_math.a"     src="CMSIS/DSP/Source/IAR"/>
3050         <file category="library" condition="CM33_DSP_NOFPU_LE_IAR"    name="CMSIS/Lib/IAR/iar_ARMv8MMLld_math.a"    src="CMSIS/DSP/Source/IAR"/>
3051         <file category="library" condition="CM33_NODSP_SP_LE_IAR"           name="CMSIS/Lib/IAR/iar_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP/Source/IAR"/>
3052         <file category="library" condition="CM33_DSP_SP_LE_IAR"       name="CMSIS/Lib/IAR/iar_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
3053         <file category="library" condition="CM35P_NODSP_NOFPU_LE_IAR"       name="CMSIS/Lib/IAR/iar_ARMv8MMLl_math.a"     src="CMSIS/DSP/Source/IAR"/>
3054         <file category="library" condition="CM35P_DSP_NOFPU_LE_IAR"         name="CMSIS/Lib/IAR/iar_ARMv8MMLld_math.a"    src="CMSIS/DSP/Source/IAR"/>
3055         <file category="library" condition="CM35P_NODSP_SP_LE_IAR"          name="CMSIS/Lib/IAR/iar_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP/Source/IAR"/>
3056         <file category="library" condition="CM35P_DSP_SP_LE_IAR"            name="CMSIS/Lib/IAR/iar_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
3057         <file category="library" condition="ARMv8MBL_LE_IAR"          name="CMSIS/Lib/IAR/iar_ARMv8MBLl_math.a"     src="CMSIS/DSP/Source/IAR"/>
3058         <file category="library" condition="ARMv8MML_NODSP_NOFPU_LE_IAR"    name="CMSIS/Lib/IAR/iar_ARMv8MMLl_math.a"     src="CMSIS/DSP/Source/IAR"/>
3059         <file category="library" condition="ARMv8MML_DSP_NOFPU_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLld_math.a"    src="CMSIS/DSP/Source/IAR"/>
3060         <file category="library" condition="ARMv8MML_NODSP_SP_LE_IAR"       name="CMSIS/Lib/IAR/iar_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP/Source/IAR"/>
3061         <file category="library" condition="ARMv8MML_DSP_SP_LE_IAR"   name="CMSIS/Lib/IAR/iar_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
3062      <!--file category="library" condition="ARMv8MML_DP_NOFPU_LE_IAR"       name="CMSIS/Lib/IAR/iar_ARMv8MMLlfdp_math.a"  src="CMSIS/DSP/Source/IAR"/-->
3063         <!--file category="library" condition="ARMv8MML_DSP_DP_LE_IAR"   name="CMSIS/Lib/IAR/iar_ARMv8MMLldfdp_math.a" src="CMSIS/DSP/Source/IAR"/-->
3064
3065       </files>
3066     </component>
3067
3068     <!-- CMSIS-NN component -->
3069     <component Cclass="CMSIS" Cgroup="NN Lib" Cversion="1.1.0" condition="CMSIS NN">
3070       <description>CMSIS-NN Neural Network Library</description>
3071       <files>
3072         <file category="doc" name="CMSIS/Documentation/NN/html/index.html"/>
3073         <file category="header" name="CMSIS/NN/Include/arm_nnfunctions.h"/>
3074
3075         <file category="source" name="CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c"/>
3076         <file category="source" name="CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c"/>
3077         <file category="source" name="CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c"/>
3078         <file category="source" name="CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c"/>
3079
3080         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c"/>
3081         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c"/>
3082         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c"/>
3083         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c"/>
3084         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c"/>
3085         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c"/>
3086         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c"/>
3087         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c"/>
3088         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c"/>
3089         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c"/>
3090         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c"/>
3091         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c"/>
3092
3093         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c"/>
3094         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c"/>
3095         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c"/>
3096         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c"/>
3097         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c"/>
3098         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c"/>
3099
3100         <file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c"/>
3101         <file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c"/>
3102         <file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c"/>
3103         <file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.c"/>
3104         <file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.c"/>
3105
3106         <file category="source" name="CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c"/>
3107
3108         <file category="source" name="CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.c"/>
3109         <file category="source" name="CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.c"/>
3110       </files>
3111     </component>
3112
3113     <!-- CMSIS-RTOS Keil RTX component -->
3114     <component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX" Cversion="4.81.1" Capiversion="1.0.0" isDefaultVariant="1" condition="RTOS RTX">
3115       <description>CMSIS-RTOS RTX implementation for Cortex-M, SC000, and SC300</description>
3116       <RTE_Components_h>
3117         <!-- the following content goes into file 'RTE_Components.h' -->
3118         #define RTE_CMSIS_RTOS                  /* CMSIS-RTOS */
3119         #define RTE_CMSIS_RTOS_RTX              /* CMSIS-RTOS Keil RTX */
3120       </RTE_Components_h>
3121       <files>
3122         <!-- CPU independent -->
3123         <file category="doc" name="CMSIS/Documentation/RTOS/html/rtxImplementation.html"/>
3124         <file category="header" name="CMSIS/RTOS/RTX/INC/cmsis_os.h"/>
3125         <file category="source" attr="config"   name="CMSIS/RTOS/RTX/Templates/RTX_Conf_CM.c" version="4.70.1"/>
3126
3127         <!-- RTX templates -->
3128         <file category="header" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/osObjects.h" select="CMSIS-RTOS 'main' function"/>
3129         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/main.c"      select="CMSIS-RTOS 'main' function"/>
3130         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MailQueue.c" select="CMSIS-RTOS Mail Queue"/>
3131         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MemPool.c"   select="CMSIS-RTOS Memory Pool"/>
3132         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MsgQueue.c"  select="CMSIS-RTOS Message Queue"/>
3133         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Mutex.c"     select="CMSIS-RTOS Mutex"/>
3134         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Semaphore.c" select="CMSIS-RTOS Semaphore"/>
3135         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Thread.c"    select="CMSIS-RTOS Thread"/>
3136         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Timer.c"     select="CMSIS-RTOS Timer"/>
3137         <!-- tool-chain specific template file -->
3138         <file category="source" attr="template" condition="ARMCC" name="CMSIS/RTOS/RTX/SRC/ARM/SVC_Table.s" select="CMSIS-RTOS User SVC"/>
3139         <file category="source" attr="template" condition="GCC"   name="CMSIS/RTOS/RTX/SRC/GCC/SVC_Table.S" select="CMSIS-RTOS User SVC"/>
3140         <file category="source" attr="template" condition="IAR"   name="CMSIS/RTOS/RTX/SRC/IAR/SVC_Table.s" select="CMSIS-RTOS User SVC"/>
3141
3142         <!-- CPU and Compiler dependent -->
3143         <!-- ARMCC -->
3144         <file category="library" condition="CM0_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
3145         <file category="library" condition="CM0_BE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3146         <file category="library" condition="CM1_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
3147         <file category="library" condition="CM1_BE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3148         <file category="library" condition="CM3_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
3149         <file category="library" condition="CM3_BE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3150         <file category="library" condition="CM4_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
3151         <file category="library" condition="CM4_BE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3152         <file category="library" condition="CM4_FP_LE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
3153         <file category="library" condition="CM4_FP_BE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3154         <file category="library" condition="CM7_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
3155         <file category="library" condition="CM7_BE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3156         <file category="library" condition="CM7_FP_LE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
3157         <file category="library" condition="CM7_FP_BE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3158         <!-- GCC -->
3159         <file category="library" condition="CM0_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
3160         <file category="library" condition="CM0_BE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3161         <file category="library" condition="CM1_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
3162         <file category="library" condition="CM1_BE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3163         <file category="library" condition="CM3_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
3164         <file category="library" condition="CM3_BE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3165         <file category="library" condition="CM4_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
3166         <file category="library" condition="CM4_BE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3167         <file category="library" condition="CM4_FP_LE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
3168         <file category="library" condition="CM4_FP_BE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3169         <file category="library" condition="CM7_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
3170         <file category="library" condition="CM7_BE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3171         <file category="library" condition="CM7_FP_LE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
3172         <file category="library" condition="CM7_FP_BE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3173         <!-- IAR -->
3174         <file category="library" condition="CM0_LE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
3175         <file category="library" condition="CM0_BE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
3176         <file category="library" condition="CM1_LE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
3177         <file category="library" condition="CM1_BE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
3178         <file category="library" condition="CM3_LE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
3179         <file category="library" condition="CM3_BE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
3180         <file category="library" condition="CM4_LE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
3181         <file category="library" condition="CM4_BE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
3182         <file category="library" condition="CM4_FP_LE_IAR"   name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
3183         <file category="library" condition="CM4_FP_BE_IAR"   name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
3184         <file category="library" condition="CM7_LE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
3185         <file category="library" condition="CM7_BE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
3186         <file category="library" condition="CM7_FP_LE_IAR"   name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
3187         <file category="library" condition="CM7_FP_BE_IAR"   name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
3188       </files>
3189     </component>
3190     <!-- CMSIS-RTOS Keil RTX component (IFX variant) -->
3191     <component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX" Cvariant="IFX" Cversion="4.81.1" Capiversion="1.0.0" condition="RTOS RTX IFX">
3192       <description>CMSIS-RTOS RTX implementation for Infineon XMC4 series affected by PMU_CM.001 errata</description>
3193       <RTE_Components_h>
3194         <!-- the following content goes into file 'RTE_Components.h' -->
3195         #define RTE_CMSIS_RTOS                  /* CMSIS-RTOS */
3196         #define RTE_CMSIS_RTOS_RTX              /* CMSIS-RTOS Keil RTX */
3197       </RTE_Components_h>
3198       <files>
3199         <!-- CPU independent -->
3200         <file category="doc" name="CMSIS/Documentation/RTOS/html/rtxImplementation.html"/>
3201         <file category="header" name="CMSIS/RTOS/RTX/INC/cmsis_os.h"/>
3202         <file category="source" attr="config"   name="CMSIS/RTOS/RTX/Templates/RTX_Conf_CM.c" version="4.70.1"/>
3203
3204         <!-- RTX templates -->
3205         <file category="header" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/osObjects.h" select="CMSIS-RTOS 'main' function"/>
3206         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/main.c"      select="CMSIS-RTOS 'main' function"/>
3207         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MailQueue.c" select="CMSIS-RTOS Mail Queue"/>
3208         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MemPool.c"   select="CMSIS-RTOS Memory Pool"/>
3209         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MsgQueue.c"  select="CMSIS-RTOS Message Queue"/>
3210         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Mutex.c"     select="CMSIS-RTOS Mutex"/>
3211         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Semaphore.c" select="CMSIS-RTOS Semaphore"/>
3212         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Thread.c"    select="CMSIS-RTOS Thread"/>
3213         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Timer.c"     select="CMSIS-RTOS Timer"/>
3214         <!-- tool-chain specific template file -->
3215         <file category="source" attr="template" condition="ARMCC" name="CMSIS/RTOS/RTX/SRC/ARM/SVC_Table.s" select="CMSIS-RTOS User SVC"/>
3216         <file category="source" attr="template" condition="GCC"   name="CMSIS/RTOS/RTX/SRC/GCC/SVC_Table.S" select="CMSIS-RTOS User SVC"/>
3217         <file category="source" attr="template" condition="IAR"   name="CMSIS/RTOS/RTX/SRC/IAR/SVC_Table.s" select="CMSIS-RTOS User SVC"/>
3218
3219         <!-- CPU and Compiler dependent -->
3220         <!-- ARMCC -->
3221         <file category="library" condition="CM4_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_IFX.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3222         <file category="library" condition="CM4_FP_LE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_IFX.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3223         <!-- GCC -->
3224         <file category="library" condition="CM4_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_IFX.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3225         <file category="library" condition="CM4_FP_LE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_IFX.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3226         <!-- IAR -->
3227       </files>
3228     </component>
3229
3230     <!-- CMSIS-RTOS Keil RTX5 component -->
3231     <component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX5" Cversion="5.5.0" Capiversion="1.0.0" condition="RTOS RTX5">
3232       <description>CMSIS-RTOS RTX5 implementation for Cortex-M, SC000, and SC300</description>
3233       <RTE_Components_h>
3234         <!-- the following content goes into file 'RTE_Components.h' -->
3235         #define RTE_CMSIS_RTOS                  /* CMSIS-RTOS */
3236         #define RTE_CMSIS_RTOS_RTX5             /* CMSIS-RTOS Keil RTX5 */
3237       </RTE_Components_h>
3238       <files>
3239         <!-- RTX header file -->
3240         <file category="header" name="CMSIS/RTOS2/RTX/Include1/cmsis_os.h"/>
3241         <!-- RTX compatibility module for API V1 -->
3242         <file category="source" name="CMSIS/RTOS2/RTX/Library/cmsis_os1.c"/>
3243       </files>
3244     </component>
3245
3246     <!-- CMSIS-RTOS2 Keil RTX5 component -->
3247     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cversion="5.5.0" Capiversion="2.1.3" condition="RTOS2 RTX5 Lib">
3248       <description>CMSIS-RTOS2 RTX5 for Cortex-M, SC000, C300 and Armv8-M (Library)</description>
3249       <RTE_Components_h>
3250         <!-- the following content goes into file 'RTE_Components.h' -->
3251         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
3252         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
3253       </RTE_Components_h>
3254       <files>
3255         <!-- RTX documentation -->
3256         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
3257
3258         <!-- RTX header files -->
3259         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
3260
3261         <!-- RTX configuration -->
3262         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.5.0"/>
3263         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
3264
3265         <!-- RTX templates -->
3266         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.1.0" select="CMSIS-RTOS2 'main' function"/>
3267         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
3268         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
3269         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
3270         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
3271         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
3272         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
3273         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
3274         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
3275         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
3276
3277         <!-- RTX library configuration -->
3278         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
3279
3280         <!-- RTX libraries (CPU and Compiler dependent) -->
3281         <!-- ARMCC -->
3282         <file category="library" condition="CM0_LE_ARMCC"         name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM0.lib"    src="CMSIS/RTOS2/RTX/Source"/>
3283         <file category="library" condition="CM1_LE_ARMCC"         name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM0.lib"    src="CMSIS/RTOS2/RTX/Source"/>
3284         <file category="library" condition="CM3_LE_ARMCC"         name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM3.lib"    src="CMSIS/RTOS2/RTX/Source"/>
3285         <file category="library" condition="CM4_LE_ARMCC"         name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM3.lib"    src="CMSIS/RTOS2/RTX/Source"/>
3286         <file category="library" condition="CM4_FP_LE_ARMCC"      name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM4F.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3287         <file category="library" condition="CM7_LE_ARMCC"         name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM3.lib"    src="CMSIS/RTOS2/RTX/Source"/>
3288         <file category="library" condition="CM7_FP_LE_ARMCC"      name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM4F.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3289         <file category="library" condition="CM23_LE_ARMCC"        name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MB.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3290         <file category="library" condition="CM33_LE_ARMCC"        name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3291         <file category="library" condition="CM33_FP_LE_ARMCC"     name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib"  src="CMSIS/RTOS2/RTX/Source"/>
3292         <file category="library" condition="CM35P_LE_ARMCC"       name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3293         <file category="library" condition="CM35P_FP_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib"  src="CMSIS/RTOS2/RTX/Source"/>
3294         <file category="library" condition="ARMv8MBL_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MB.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3295         <file category="library" condition="ARMv8MML_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3296         <file category="library" condition="ARMv8MML_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib"  src="CMSIS/RTOS2/RTX/Source"/>
3297         <!-- GCC -->
3298         <file category="library" condition="CM0_LE_GCC"           name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM0.a"   src="CMSIS/RTOS2/RTX/Source"/>
3299         <file category="library" condition="CM1_LE_GCC"           name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM0.a"   src="CMSIS/RTOS2/RTX/Source"/>
3300         <file category="library" condition="CM3_LE_GCC"           name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a"   src="CMSIS/RTOS2/RTX/Source"/>
3301         <file category="library" condition="CM4_LE_GCC"           name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a"   src="CMSIS/RTOS2/RTX/Source"/>
3302         <file category="library" condition="CM4_FP_LE_GCC"        name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM4F.a"  src="CMSIS/RTOS2/RTX/Source"/>
3303         <file category="library" condition="CM7_LE_GCC"           name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a"   src="CMSIS/RTOS2/RTX/Source"/>
3304         <file category="library" condition="CM7_FP_LE_GCC"        name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM4F.a"  src="CMSIS/RTOS2/RTX/Source"/>
3305         <file category="library" condition="CM23_LE_GCC"          name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MB.a"  src="CMSIS/RTOS2/RTX/Source"/>
3306         <file category="library" condition="CM33_LE_GCC"          name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a"  src="CMSIS/RTOS2/RTX/Source"/>
3307         <file category="library" condition="CM33_FP_LE_GCC"       name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
3308         <file category="library" condition="CM35P_LE_GCC"         name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a"  src="CMSIS/RTOS2/RTX/Source"/>
3309         <file category="library" condition="CM35P_FP_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
3310         <file category="library" condition="ARMv8MBL_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MB.a"  src="CMSIS/RTOS2/RTX/Source"/>
3311         <file category="library" condition="ARMv8MML_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a"  src="CMSIS/RTOS2/RTX/Source"/>
3312         <file category="library" condition="ARMv8MML_FP_LE_GCC"   name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
3313         <!-- IAR -->
3314         <file category="library" condition="CM0_LE_IAR"           name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM0.a"      src="CMSIS/RTOS2/RTX/Source"/>
3315         <file category="library" condition="CM1_LE_IAR"           name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM0.a"      src="CMSIS/RTOS2/RTX/Source"/>
3316         <file category="library" condition="CM3_LE_IAR"           name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM3.a"      src="CMSIS/RTOS2/RTX/Source"/>
3317         <file category="library" condition="CM4_LE_IAR"           name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM3.a"      src="CMSIS/RTOS2/RTX/Source"/>
3318         <file category="library" condition="CM4_FP_LE_IAR"        name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM4F.a"     src="CMSIS/RTOS2/RTX/Source"/>
3319         <file category="library" condition="CM7_LE_IAR"           name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM3.a"      src="CMSIS/RTOS2/RTX/Source"/>
3320         <file category="library" condition="CM7_FP_LE_IAR"        name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM4F.a"     src="CMSIS/RTOS2/RTX/Source"/>
3321         <file category="library" condition="CM23_LE_IAR"          name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MB.a"     src="CMSIS/RTOS2/RTX/Source"/>
3322         <file category="library" condition="CM33_LE_IAR"          name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MM.a"     src="CMSIS/RTOS2/RTX/Source"/>
3323         <file category="library" condition="CM33_FP_LE_IAR"       name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMF.a"    src="CMSIS/RTOS2/RTX/Source"/>
3324         <file category="library" condition="CM35P_LE_IAR"         name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MM.a"     src="CMSIS/RTOS2/RTX/Source"/>
3325         <file category="library" condition="CM35P_FP_LE_IAR"      name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMF.a"    src="CMSIS/RTOS2/RTX/Source"/>
3326         <file category="library" condition="ARMv8MBL_LE_IAR"      name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MB.a"     src="CMSIS/RTOS2/RTX/Source"/>
3327         <file category="library" condition="ARMv8MML_LE_IAR"      name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MM.a"     src="CMSIS/RTOS2/RTX/Source"/>
3328         <file category="library" condition="ARMv8MML_FP_LE_IAR"   name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMF.a"    src="CMSIS/RTOS2/RTX/Source"/>
3329       </files>
3330     </component>
3331     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library_NS" Cversion="5.5.0" Capiversion="2.1.3" condition="RTOS2 RTX5 NS">
3332       <description>CMSIS-RTOS2 RTX5 for Armv8-M Non-Secure Domain (Library)</description>
3333       <RTE_Components_h>
3334         <!-- the following content goes into file 'RTE_Components.h' -->
3335         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
3336         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
3337         #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS  /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */
3338       </RTE_Components_h>
3339       <files>
3340         <!-- RTX documentation -->
3341         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
3342
3343         <!-- RTX header files -->
3344         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
3345
3346         <!-- RTX configuration -->
3347         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.5.0"/>
3348         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
3349
3350         <!-- RTX templates -->
3351         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.1.0" select="CMSIS-RTOS2 'main' function"/>
3352         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
3353         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
3354         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
3355         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
3356         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
3357         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
3358         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
3359         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
3360         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
3361
3362         <!-- RTX library configuration -->
3363         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
3364
3365         <!-- RTX libraries (CPU and Compiler dependent) -->
3366         <!-- ARMCC -->
3367         <file category="library" condition="CM23_LE_ARMCC"        name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MBN.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3368         <file category="library" condition="CM33_LE_ARMCC"        name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3369         <file category="library" condition="CM33_FP_LE_ARMCC"     name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib"  src="CMSIS/RTOS2/RTX/Source"/>
3370         <file category="library" condition="CM35P_LE_ARMCC"       name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3371         <file category="library" condition="CM35P_FP_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib"  src="CMSIS/RTOS2/RTX/Source"/>
3372         <file category="library" condition="ARMv8MBL_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MBN.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3373         <file category="library" condition="ARMv8MML_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3374         <file category="library" condition="ARMv8MML_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib"  src="CMSIS/RTOS2/RTX/Source"/>
3375         <!-- GCC -->
3376         <file category="library" condition="CM23_LE_GCC"          name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MBN.a"  src="CMSIS/RTOS2/RTX/Source"/>
3377         <file category="library" condition="CM33_LE_GCC"          name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a"  src="CMSIS/RTOS2/RTX/Source"/>
3378         <file category="library" condition="CM33_FP_LE_GCC"       name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
3379         <file category="library" condition="CM35P_LE_GCC"         name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a"  src="CMSIS/RTOS2/RTX/Source"/>
3380         <file category="library" condition="CM35P_FP_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
3381         <file category="library" condition="ARMv8MBL_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MBN.a"  src="CMSIS/RTOS2/RTX/Source"/>
3382         <file category="library" condition="ARMv8MML_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a"  src="CMSIS/RTOS2/RTX/Source"/>
3383         <file category="library" condition="ARMv8MML_FP_LE_GCC"   name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
3384         <!-- IAR -->
3385         <file category="library" condition="CM23_LE_IAR"          name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MBN.a"     src="CMSIS/RTOS2/RTX/Source"/>
3386         <file category="library" condition="CM33_LE_IAR"          name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMN.a"     src="CMSIS/RTOS2/RTX/Source"/>
3387         <file category="library" condition="CM33_FP_LE_IAR"       name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMFN.a"    src="CMSIS/RTOS2/RTX/Source"/>
3388         <file category="library" condition="CM35P_LE_IAR"         name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMN.a"     src="CMSIS/RTOS2/RTX/Source"/>
3389         <file category="library" condition="CM35P_FP_LE_IAR"      name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMFN.a"    src="CMSIS/RTOS2/RTX/Source"/>
3390         <file category="library" condition="ARMv8MBL_LE_IAR"      name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MBN.a"     src="CMSIS/RTOS2/RTX/Source"/>
3391         <file category="library" condition="ARMv8MML_LE_IAR"      name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMN.a"     src="CMSIS/RTOS2/RTX/Source"/>
3392         <file category="library" condition="ARMv8MML_FP_LE_IAR"   name="CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMFN.a"    src="CMSIS/RTOS2/RTX/Source"/>
3393       </files>
3394     </component>
3395     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cversion="5.5.0" Capiversion="2.1.3" condition="RTOS2 RTX5">
3396       <description>CMSIS-RTOS2 RTX5 for Cortex-M, SC000, C300 and Armv8-M (Source)</description>
3397       <RTE_Components_h>
3398         <!-- the following content goes into file 'RTE_Components.h' -->
3399         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
3400         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
3401         #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
3402       </RTE_Components_h>
3403       <files>
3404         <!-- RTX documentation -->
3405         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
3406
3407         <!-- RTX header files -->
3408         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
3409
3410         <!-- RTX configuration -->
3411         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.5.0"/>
3412         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
3413
3414         <!-- RTX templates -->
3415         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.1.0" select="CMSIS-RTOS2 'main' function"/>
3416         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
3417         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
3418         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
3419         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
3420         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
3421         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
3422         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
3423         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
3424         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
3425
3426         <!-- RTX sources (core) -->
3427         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_kernel.c"/>
3428         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_thread.c"/>
3429         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_delay.c"/>
3430         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_timer.c"/>
3431         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evflags.c"/>
3432         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mutex.c"/>
3433         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_semaphore.c"/>
3434         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_memory.c"/>
3435         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mempool.c"/>
3436         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c"/>
3437         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_system.c"/>
3438         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evr.c"/>
3439         <!-- RTX sources (library configuration) -->
3440         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
3441         <!-- RTX sources (handlers ARMCC) -->
3442         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm0.s"         condition="CM0_ARMCC"/>
3443         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm0.s"         condition="CM1_ARMCC"/>
3444         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm3.s"         condition="CM3_ARMCC"/>
3445         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm3.s"         condition="CM4_ARMCC"/>
3446         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm4f.s"        condition="CM4_FP_ARMCC"/>
3447         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm3.s"         condition="CM7_ARMCC"/>
3448         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm4f.s"        condition="CM7_FP_ARMCC"/>
3449         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl.s"    condition="CM23_ARMCC"/>
3450         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="CM33_ARMCC"/>
3451         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="CM33_FP_ARMCC"/>
3452         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="CM35P_ARMCC"/>
3453         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="CM35P_FP_ARMCC"/>
3454         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl.s"    condition="ARMv8MBL_ARMCC"/>
3455         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="ARMv8MML_ARMCC"/>
3456         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="ARMv8MML_FP_ARMCC"/>
3457         <!-- RTX sources (handlers GCC) -->
3458         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm0.S"         condition="CM0_GCC"/>
3459         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm0.S"         condition="CM1_GCC"/>
3460         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm3.S"         condition="CM3_GCC"/>
3461         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm3.S"         condition="CM4_GCC"/>
3462         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm4f.S"        condition="CM4_FP_GCC"/>
3463         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm3.S"         condition="CM7_GCC"/>
3464         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm4f.S"        condition="CM7_FP_GCC"/>
3465         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S"    condition="CM23_GCC"/>
3466         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S"    condition="CM33_GCC"/>
3467         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp.S" condition="CM33_FP_GCC"/>
3468         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S"    condition="CM35P_GCC"/>
3469         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp.S" condition="CM35P_FP_GCC"/>
3470         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S"    condition="ARMv8MBL_GCC"/>
3471         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S"    condition="ARMv8MML_GCC"/>
3472         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp.S" condition="ARMv8MML_FP_GCC"/>
3473         <!-- RTX sources (handlers IAR) -->
3474         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm0.s"         condition="CM0_IAR"/>
3475         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm0.s"         condition="CM1_IAR"/>
3476         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm3.s"         condition="CM3_IAR"/>
3477         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm3.s"         condition="CM4_IAR"/>
3478         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm4f.s"        condition="CM4_FP_IAR"/>
3479         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm3.s"         condition="CM7_IAR"/>
3480         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm4f.s"        condition="CM7_FP_IAR"/>
3481         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s"    condition="CM23_IAR"/>
3482         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="CM33_IAR"/>
3483         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="CM33_FP_IAR"/>
3484         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="CM35P_IAR"/>
3485         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="CM35P_FP_IAR"/>
3486         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s"    condition="ARMv8MBL_IAR"/>
3487         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="ARMv8MML_IAR"/>
3488         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="ARMv8MML_FP_IAR"/>
3489         <!-- OS Tick (SysTick) -->
3490         <file category="source" name="CMSIS/RTOS2/Source/os_systick.c"/>
3491       </files>
3492     </component>
3493     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cversion="5.5.0" Capiversion="2.1.3" condition="RTOS2 RTX5 v7-A">
3494       <description>CMSIS-RTOS2 RTX5 for Armv7-A (Source)</description>
3495       <RTE_Components_h>
3496         <!-- the following content goes into file 'RTE_Components.h' -->
3497         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
3498         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
3499         #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
3500       </RTE_Components_h>
3501       <files>
3502         <!-- RTX documentation -->
3503         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
3504
3505         <!-- RTX header files -->
3506         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
3507
3508         <!-- RTX configuration -->
3509         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.5.0"/>
3510         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
3511
3512         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/handlers.c"    version="5.1.0"/>
3513
3514         <!-- RTX templates -->
3515         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.1.0" select="CMSIS-RTOS2 'main' function"/>
3516         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
3517         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
3518         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
3519         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
3520         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
3521         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
3522         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
3523         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
3524         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
3525
3526         <!-- RTX sources (core) -->
3527         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_kernel.c"/>
3528         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_thread.c"/>
3529         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_delay.c"/>
3530         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_timer.c"/>
3531         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evflags.c"/>
3532         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mutex.c"/>
3533         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_semaphore.c"/>
3534         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_memory.c"/>
3535         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mempool.c"/>
3536         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c"/>
3537         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_system.c"/>
3538         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evr.c"/>
3539         <!-- RTX sources (library configuration) -->
3540         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
3541         <!-- RTX sources (handlers ARMCC) -->
3542         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_ca.s"          condition="CA_ARMCC5"/>
3543         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_ca.S"          condition="CA_ARMCC6"/>
3544         <!-- RTX sources (handlers GCC) -->
3545         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_ca.S"          condition="CA_GCC"/>
3546         <!-- RTX sources (handlers IAR) -->
3547         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_ca.s"          condition="CA_IAR"/>
3548       </files>
3549     </component>
3550     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source_NS" Cversion="5.5.0" Capiversion="2.1.3" condition="RTOS2 RTX5 NS">
3551       <description>CMSIS-RTOS2 RTX5 for Armv8-M Non-Secure Domain (Source)</description>
3552       <RTE_Components_h>
3553         <!-- the following content goes into file 'RTE_Components.h' -->
3554         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
3555         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
3556         #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
3557         #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS  /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */
3558       </RTE_Components_h>
3559       <files>
3560         <!-- RTX documentation -->
3561         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
3562
3563         <!-- RTX header files -->
3564         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
3565
3566         <!-- RTX configuration -->
3567         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.5.0"/>
3568         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
3569
3570         <!-- RTX templates -->
3571         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.1.0" select="CMSIS-RTOS2 'main' function"/>
3572         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
3573         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
3574         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
3575         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
3576         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
3577         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
3578         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
3579         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
3580         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
3581
3582         <!-- RTX sources (core) -->
3583         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_kernel.c"/>
3584         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_thread.c"/>
3585         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_delay.c"/>
3586         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_timer.c"/>
3587         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evflags.c"/>
3588         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mutex.c"/>
3589         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_semaphore.c"/>
3590         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_memory.c"/>
3591         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mempool.c"/>
3592         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c"/>
3593         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_system.c"/>
3594         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evr.c"/>
3595         <!-- RTX sources (library configuration) -->
3596         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
3597         <!-- RTX sources (ARMCC handlers) -->
3598         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl_ns.s"    condition="CM23_ARMCC"/>
3599         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="CM33_ARMCC"/>
3600         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="CM33_FP_ARMCC"/>
3601         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="CM35P_ARMCC"/>
3602         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="CM35P_FP_ARMCC"/>
3603         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl_ns.s"    condition="ARMv8MBL_ARMCC"/>
3604         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="ARMv8MML_ARMCC"/>
3605         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="ARMv8MML_FP_ARMCC"/>
3606         <!-- RTX sources (GCC handlers) -->
3607         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl_ns.S"    condition="CM23_GCC"/>
3608         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_ns.S"    condition="CM33_GCC"/>
3609         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp_ns.S" condition="CM33_FP_GCC"/>
3610         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_ns.S"    condition="CM35P_GCC"/>
3611         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp_ns.S" condition="CM35P_FP_GCC"/>
3612         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl_ns.S"    condition="ARMv8MBL_GCC"/>
3613         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_ns.S"    condition="ARMv8MML_GCC"/>
3614         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp_ns.S" condition="ARMv8MML_FP_GCC"/>
3615         <!-- RTX sources (IAR handlers) -->
3616         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl_ns.s"    condition="CM23_IAR"/>
3617         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="CM33_IAR"/>
3618         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="CM33_FP_IAR"/>
3619         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="CM35P_IAR"/>
3620         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="CM35P_FP_IAR"/>
3621         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl_ns.s"    condition="ARMv8MBL_IAR"/>
3622         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="ARMv8MML_IAR"/>
3623         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="ARMv8MML_FP_IAR"/>
3624         <!-- OS Tick (SysTick) -->
3625         <file category="source" name="CMSIS/RTOS2/Source/os_systick.c"/>
3626       </files>
3627     </component>
3628
3629   </components>
3630
3631   <boards>
3632     <board name="uVision Simulator" vendor="Keil">
3633       <description>uVision Simulator</description>
3634       <mountedDevice    deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0"/>
3635       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0P"/>
3636       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0P_MPU"/>
3637       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM1"/>
3638       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM3"/>
3639       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM4"/>
3640       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM4_FP"/>
3641       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7"/>
3642       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7_SP"/>
3643       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7_DP"/>
3644       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MBL"/>
3645       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML"/>
3646       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML_SP"/>
3647       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML_DP"/>
3648       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM23"/>
3649       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM23_TZ"/>
3650       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33"/>
3651       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_TZ"/>
3652       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_DSP_FP"/>
3653       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_DSP_FP_TZ"/>
3654       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P"/>
3655       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P_TZ"/>
3656       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P_DSP_FP"/>
3657       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P_DSP_FP_TZ"/>
3658     </board>
3659
3660     <board name="EWARM Simulator" vendor="IAR">
3661       <description>EWARM Simulator</description>
3662       <mountedDevice    deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0"/>
3663       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0P"/>
3664       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0P_MPU"/>
3665       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM1"/>
3666       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM3"/>
3667       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM4"/>
3668       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM4_FP"/>
3669       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7"/>
3670       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7_SP"/>
3671       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7_DP"/>
3672       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MBL"/>
3673       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML"/>
3674       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML_SP"/>
3675       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML_DP"/>
3676       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM23"/>
3677       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM23_TZ"/>
3678       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33"/>
3679       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_TZ"/>
3680       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_DSP_FP"/>
3681       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_DSP_FP_TZ"/>
3682       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P"/>
3683       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P_TZ"/>
3684       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P_DSP_FP"/>
3685       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P_DSP_FP_TZ"/>
3686     </board>
3687   </boards>
3688
3689   <examples>
3690     <example name="DSP_Lib Class Marks example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_class_marks_example">
3691       <description>DSP_Lib Class Marks example</description>
3692       <board name="uVision Simulator" vendor="Keil"/>
3693       <project>
3694         <environment name="uv" load="arm_class_marks_example.uvprojx"/>
3695       </project>
3696       <attributes>
3697         <component Cclass="CMSIS" Cgroup="CORE"/>
3698         <component Cclass="CMSIS" Cgroup="DSP"/>
3699         <component Cclass="Device" Cgroup="Startup"/>
3700         <category>Getting Started</category>
3701       </attributes>
3702     </example>
3703
3704     <example name="DSP_Lib Convolution example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_convolution_example">
3705       <description>DSP_Lib Convolution example</description>
3706       <board name="uVision Simulator" vendor="Keil"/>
3707       <project>
3708         <environment name="uv" load="arm_convolution_example.uvprojx"/>
3709       </project>
3710       <attributes>
3711         <component Cclass="CMSIS" Cgroup="CORE"/>
3712         <component Cclass="CMSIS" Cgroup="DSP"/>
3713         <component Cclass="Device" Cgroup="Startup"/>
3714         <category>Getting Started</category>
3715       </attributes>
3716     </example>
3717
3718     <example name="DSP_Lib Dotproduct example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_dotproduct_example">
3719       <description>DSP_Lib Dotproduct example</description>
3720       <board name="uVision Simulator" vendor="Keil"/>
3721       <project>
3722         <environment name="uv" load="arm_dotproduct_example.uvprojx"/>
3723       </project>
3724       <attributes>
3725         <component Cclass="CMSIS" Cgroup="CORE"/>
3726         <component Cclass="CMSIS" Cgroup="DSP"/>
3727         <component Cclass="Device" Cgroup="Startup"/>
3728         <category>Getting Started</category>
3729       </attributes>
3730     </example>
3731
3732     <example name="DSP_Lib FFT Bin example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_fft_bin_example">
3733       <description>DSP_Lib FFT Bin example</description>
3734       <board name="uVision Simulator" vendor="Keil"/>
3735       <project>
3736         <environment name="uv" load="arm_fft_bin_example.uvprojx"/>
3737       </project>
3738       <attributes>
3739         <component Cclass="CMSIS" Cgroup="CORE"/>
3740         <component Cclass="CMSIS" Cgroup="DSP"/>
3741         <component Cclass="Device" Cgroup="Startup"/>
3742         <category>Getting Started</category>
3743       </attributes>
3744     </example>
3745
3746     <example name="DSP_Lib FIR example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_fir_example">
3747       <description>DSP_Lib FIR example</description>
3748       <board name="uVision Simulator" vendor="Keil"/>
3749       <project>
3750         <environment name="uv" load="arm_fir_example.uvprojx"/>
3751       </project>
3752       <attributes>
3753         <component Cclass="CMSIS" Cgroup="CORE"/>
3754         <component Cclass="CMSIS" Cgroup="DSP"/>
3755         <component Cclass="Device" Cgroup="Startup"/>
3756         <category>Getting Started</category>
3757       </attributes>
3758     </example>
3759
3760     <example name="DSP_Lib Graphic Equalizer example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example">
3761       <description>DSP_Lib Graphic Equalizer example</description>
3762       <board name="uVision Simulator" vendor="Keil"/>
3763       <project>
3764         <environment name="uv" load="arm_graphic_equalizer_example.uvprojx"/>
3765       </project>
3766       <attributes>
3767         <component Cclass="CMSIS" Cgroup="CORE"/>
3768         <component Cclass="CMSIS" Cgroup="DSP"/>
3769         <component Cclass="Device" Cgroup="Startup"/>
3770         <category>Getting Started</category>
3771       </attributes>
3772     </example>
3773
3774     <example name="DSP_Lib Linear Interpolation example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_linear_interp_example">
3775       <description>DSP_Lib Linear Interpolation example</description>
3776       <board name="uVision Simulator" vendor="Keil"/>
3777       <project>
3778         <environment name="uv" load="arm_linear_interp_example.uvprojx"/>
3779       </project>
3780       <attributes>
3781         <component Cclass="CMSIS" Cgroup="CORE"/>
3782         <component Cclass="CMSIS" Cgroup="DSP"/>
3783         <component Cclass="Device" Cgroup="Startup"/>
3784         <category>Getting Started</category>
3785       </attributes>
3786     </example>
3787
3788     <example name="DSP_Lib Matrix example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_matrix_example">
3789       <description>DSP_Lib Matrix example</description>
3790       <board name="uVision Simulator" vendor="Keil"/>
3791       <project>
3792         <environment name="uv" load="arm_matrix_example.uvprojx"/>
3793       </project>
3794       <attributes>
3795         <component Cclass="CMSIS" Cgroup="CORE"/>
3796         <component Cclass="CMSIS" Cgroup="DSP"/>
3797         <component Cclass="Device" Cgroup="Startup"/>
3798         <category>Getting Started</category>
3799       </attributes>
3800     </example>
3801
3802     <example name="DSP_Lib Signal Convergence example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_signal_converge_example">
3803       <description>DSP_Lib Signal Convergence example</description>
3804       <board name="uVision Simulator" vendor="Keil"/>
3805       <project>
3806         <environment name="uv" load="arm_signal_converge_example.uvprojx"/>
3807       </project>
3808       <attributes>
3809         <component Cclass="CMSIS" Cgroup="CORE"/>
3810         <component Cclass="CMSIS" Cgroup="DSP"/>
3811         <component Cclass="Device" Cgroup="Startup"/>
3812         <category>Getting Started</category>
3813       </attributes>
3814     </example>
3815
3816     <example name="DSP_Lib Sinus/Cosinus example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_sin_cos_example">
3817       <description>DSP_Lib Sinus/Cosinus example</description>
3818       <board name="uVision Simulator" vendor="Keil"/>
3819       <project>
3820         <environment name="uv" load="arm_sin_cos_example.uvprojx"/>
3821       </project>
3822       <attributes>
3823         <component Cclass="CMSIS" Cgroup="CORE"/>
3824         <component Cclass="CMSIS" Cgroup="DSP"/>
3825         <component Cclass="Device" Cgroup="Startup"/>
3826         <category>Getting Started</category>
3827       </attributes>
3828     </example>
3829
3830     <example name="DSP_Lib Variance example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_variance_example">
3831       <description>DSP_Lib Variance example</description>
3832       <board name="uVision Simulator" vendor="Keil"/>
3833       <project>
3834         <environment name="uv" load="arm_variance_example.uvprojx"/>
3835       </project>
3836       <attributes>
3837         <component Cclass="CMSIS" Cgroup="CORE"/>
3838         <component Cclass="CMSIS" Cgroup="DSP"/>
3839         <component Cclass="Device" Cgroup="Startup"/>
3840         <category>Getting Started</category>
3841       </attributes>
3842     </example>
3843
3844     <example name="NN Library CIFAR10" doc="readme.txt" folder="CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10">
3845       <description>Neural Network CIFAR10 example</description>
3846       <board name="uVision Simulator" vendor="Keil"/>
3847       <project>
3848         <environment name="uv" load="arm_nnexamples_cifar10.uvprojx"/>
3849       </project>
3850       <attributes>
3851         <component Cclass="CMSIS" Cgroup="CORE"/>
3852         <component Cclass="CMSIS" Cgroup="DSP"/>
3853         <component Cclass="CMSIS" Cgroup="NN Lib"/>
3854         <component Cclass="Device" Cgroup="Startup"/>
3855         <category>Getting Started</category>
3856       </attributes>
3857     </example>
3858
3859     <example name="NN-example-cifar10" doc="readme_iar.txt" folder="CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10">
3860       <description>Neural Network CIFAR10 example</description>
3861       <board name="EWARM Simulator" vendor="IAR"/>
3862       <project>
3863         <environment name="iar" load="NN-example-cifar10.ewp"/>
3864       </project>
3865       <attributes>
3866         <component Cclass="CMSIS" Cgroup="CORE"/>
3867         <component Cclass="CMSIS" Cgroup="DSP"/>
3868         <component Cclass="CMSIS" Cgroup="NN Lib"/>
3869         <component Cclass="Device" Cgroup="Startup"/>
3870         <category>Getting Started</category>
3871       </attributes>
3872     </example>
3873
3874     <example name="NN Library GRU" doc="readme.txt" folder="CMSIS/NN/Examples/ARM/arm_nn_examples/gru">
3875       <description>Neural Network GRU example</description>
3876       <board name="uVision Simulator" vendor="Keil"/>
3877       <project>
3878         <environment name="uv" load="arm_nnexamples_gru.uvprojx"/>
3879       </project>
3880       <attributes>
3881         <component Cclass="CMSIS" Cgroup="CORE"/>
3882         <component Cclass="CMSIS" Cgroup="DSP"/>
3883         <component Cclass="CMSIS" Cgroup="NN Lib"/>
3884         <component Cclass="Device" Cgroup="Startup"/>
3885         <category>Getting Started</category>
3886       </attributes>
3887     </example>
3888
3889     <example name="NN-example-gru" doc="readme_iar.txt" folder="CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-gru">
3890       <description>Neural Network GRU example</description>
3891       <board name="EWARM Simulator" vendor="IAR"/>
3892       <project>
3893         <environment name="iar" load="NN-example-gru.ewp"/>
3894       </project>
3895       <attributes>
3896         <component Cclass="CMSIS" Cgroup="CORE"/>
3897         <component Cclass="CMSIS" Cgroup="DSP"/>
3898         <component Cclass="CMSIS" Cgroup="NN Lib"/>
3899         <component Cclass="Device" Cgroup="Startup"/>
3900         <category>Getting Started</category>
3901       </attributes>
3902     </example>
3903
3904     <example name="CMSIS-RTOS2 Blinky" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/Blinky">
3905       <description>CMSIS-RTOS2 Blinky example</description>
3906       <board name="uVision Simulator" vendor="Keil"/>
3907       <project>
3908         <environment name="uv" load="Blinky.uvprojx"/>
3909       </project>
3910       <attributes>
3911         <component Cclass="CMSIS" Cgroup="CORE"/>
3912         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3913         <component Cclass="Device" Cgroup="Startup"/>
3914         <category>Getting Started</category>
3915       </attributes>
3916     </example>
3917
3918     <example name="CMSIS-RTOS2 RTX5 Migration" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/Migration">
3919       <description>CMSIS-RTOS2 mixed API v1 and v2</description>
3920       <board name="uVision Simulator" vendor="Keil"/>
3921       <project>
3922         <environment name="uv" load="Blinky.uvprojx"/>
3923       </project>
3924       <attributes>
3925         <component Cclass="CMSIS" Cgroup="CORE"/>
3926         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3927         <component Cclass="Device" Cgroup="Startup"/>
3928         <category>Getting Started</category>
3929       </attributes>
3930     </example>
3931
3932     <example name="CMSIS-RTOS2 RTX5 Message Queue" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/MsgQueue">
3933       <description>CMSIS-RTOS2 Message Queue Example</description>
3934       <board name="uVision Simulator" vendor="Keil"/>
3935       <project>
3936         <environment name="uv" load="MsqQueue.uvprojx"/>
3937       </project>
3938       <attributes>
3939         <component Cclass="CMSIS" Cgroup="CORE"/>
3940         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3941         <component Cclass="Compiler" Cgroup="EventRecorder"/>
3942         <component Cclass="Device" Cgroup="Startup"/>
3943         <category>Getting Started</category>
3944       </attributes>
3945     </example>
3946
3947     <example name="CMSIS-RTOS2 RTX5 Memory Pool" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/MemPool">
3948       <description>CMSIS-RTOS2 Memory Pool Example</description>
3949       <board name="uVision Simulator" vendor="Keil"/>
3950       <project>
3951         <environment name="uv" load="MemPool.uvprojx"/>
3952       </project>
3953       <attributes>
3954         <component Cclass="CMSIS" Cgroup="CORE"/>
3955         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3956         <component Cclass="Compiler" Cgroup="EventRecorder"/>
3957         <component Cclass="Device" Cgroup="Startup"/>
3958         <category>Getting Started</category>
3959       </attributes>
3960     </example>
3961
3962     <example name="TrustZone for ARMv8-M No RTOS" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/NoRTOS">
3963       <description>Bare-metal secure/non-secure example without RTOS</description>
3964       <board name="uVision Simulator" vendor="Keil"/>
3965       <project>
3966         <environment name="uv" load="NoRTOS.uvmpw"/>
3967       </project>
3968       <attributes>
3969         <component Cclass="CMSIS" Cgroup="CORE"/>
3970         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3971         <component Cclass="Device" Cgroup="Startup"/>
3972         <category>Getting Started</category>
3973       </attributes>
3974     </example>
3975
3976     <example name="TrustZone for ARMv8-M RTOS"  doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS">
3977       <description>Secure/non-secure RTOS example with thread context management</description>
3978       <board name="uVision Simulator" vendor="Keil"/>
3979       <project>
3980         <environment name="uv" load="RTOS.uvmpw"/>
3981       </project>
3982       <attributes>
3983         <component Cclass="CMSIS" Cgroup="CORE"/>
3984         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3985         <component Cclass="Device" Cgroup="Startup"/>
3986         <category>Getting Started</category>
3987       </attributes>
3988     </example>
3989
3990     <example name="TrustZone for ARMv8-M RTOS Security Tests"  doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults">
3991       <description>Secure/non-secure RTOS example with security test cases and system recovery</description>
3992       <board name="uVision Simulator" vendor="Keil"/>
3993       <project>
3994         <environment name="uv" load="RTOS_Faults.uvmpw"/>
3995       </project>
3996       <attributes>
3997         <component Cclass="CMSIS" Cgroup="CORE"/>
3998         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3999         <component Cclass="Device" Cgroup="Startup"/>
4000         <category>Getting Started</category>
4001       </attributes>
4002     </example>
4003
4004   </examples>
4005
4006 </package>