begriffs open source - cmsis/blob - ARM.CMSIS.pdsc

   1 <?xml version="1.0" encoding="UTF-8"?>
   2
   3 <package schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="PACK.xsd">
   4   <name>CMSIS</name>
   5   <description>CMSIS (Cortex Microcontroller Software Interface Standard)</description>
   6   <vendor>ARM</vendor>
   7   <!-- <license>license.txt</license> -->
   8   <url>http://www.keil.com/pack/</url>
   9
  10   <releases>
  11     <release version="5.3.1-dev1">
  12       Active development...
  13       CMSIS-RTOS2:
  14         - RTX 5.3.1 (see revision history for details)
  15     </release>
  16     <release version="5.3.1-dev0">
  17       Patch release scheduled for after EW18.
  18     </release>
  19     <release version="5.3.0" date="2018-02-22">
  20       Updated Arm company brand.
  21       CMSIS-Core(M): 5.1.1 (see revision history for details)
  22       CMSIS-Core(A): 1.1.1 (see revision history for details)
  23       CMSIS-DAP: 2.0.0 (see revision history for details)
  24       CMSIS-NN: 1.0.0
  25         - Initial contribution of the bare metal Neural Network Library.
  26       CMSIS-RTOS2:
  27         - RTX 5.3.0 (see revision history for details)
  28         - OS Tick API 1.0.1
  29     </release>
  30     <release version="5.2.0" date="2017-11-16">
  31       CMSIS-Core(M): 5.1.0 (see revision history for details)
  32         - Added MPU Functions for ARMv8-M for Cortex-M23/M33.
  33         - Added compiler_iccarm.h to replace compiler_iar.h shipped with the compiler.
  34       CMSIS-Core(A): 1.1.0 (see revision history for details)
  35         - Added compiler_iccarm.h.
  36         - Added additional access functions for physical timer.
  37       CMSIS-DAP: 1.2.0 (see revision history for details)
  38       CMSIS-DSP: 1.5.2 (see revision history for details)
  39       CMSIS-Driver: 2.6.0 (see revision history for details)
  40         - CAN Driver API V1.2.0
  41         - NAND Driver API V2.3.0
  42       CMSIS-RTOS:
  43         - RTX: added variant for Infineon XMC4 series affected by PMU_CM.001 errata.
  44       CMSIS-RTOS2:
  45         - API 2.1.2 (see revision history for details)
  46         - RTX 5.2.3 (see revision history for details)
  47       Devices:
  48         - Added GCC startup and linker script for Cortex-A9.
  49         - Added device ARMCM0plus_MPU for Cortex-M0+ with MPU.
  50         - Added IAR startup code for Cortex-A9
  51     </release>
  52     <release version="5.1.1" date="2017-09-19">
  53       CMSIS-RTOS2:
  54       - RTX 5.2.1 (see revision history for details)
  55     </release>
  56     <release version="5.1.0" date="2017-08-04">
  57       CMSIS-Core(M): 5.0.2 (see revision history for details)
  58       - Changed Version Control macros to be core agnostic.
  59       - Added MPU Functions for ARMv7-M for Cortex-M0+/M3/M4/M7.
  60       CMSIS-Core(A): 1.0.0 (see revision history for details)
  61       - Initial release
  62       - IRQ Controller API 1.0.0
  63       CMSIS-Driver: 2.05 (see revision history for details)
  64       - All typedefs related to status have been made volatile.
  65       CMSIS-RTOS2:
  66       - API 2.1.1 (see revision history for details)
  67       - RTX 5.2.0 (see revision history for details)
  68       - OS Tick API 1.0.0
  69       CMSIS-DSP: 1.5.2 (see revision history for details)
  70       - Fixed GNU Compiler specific diagnostics.
  71       CMSIS-PACK: 1.5.0 (see revision history for details)
  72       - added System Description File (*.SDF) Format
  73       CMSIS-Zone: 0.0.1 (Preview)
  74       - Initial specification draft
  75     </release>
  76     <release version="5.0.1" date="2017-02-03">
  77       Package Description:
  78       - added taxonomy for Cclass RTOS
  79       CMSIS-RTOS2:
  80       - API 2.1   (see revision history for details)
  81       - RTX 5.1.0 (see revision history for details)
  82       CMSIS-Core: 5.0.1 (see revision history for details)
  83       - Added __PACKED_STRUCT macro
  84       - Added uVisior support
  85       - Updated cmsis_armcc.h: corrected macro __ARM_ARCH_6M__
  86       - Updated template for secure main function (main_s.c)
  87       - Updated template for Context Management for ARMv8-M TrustZone (tz_context.c)
  88       CMSIS-DSP: 1.5.1 (see revision history for details)
  89       - added ARMv8M DSP libraries.
  90       CMSIS-PACK:1.4.9 (see revision history for details)
  91       - added Pack Index File specification and schema file
  92     </release>
  93     <release version="5.0.0" date="2016-11-11">
  94       Changed open source license to Apache 2.0
  95       CMSIS_Core:
  96        - Added support for Cortex-M23 and Cortex-M33.
  97        - Added ARMv8-M device configurations for mainline and baseline.
  98        - Added CMSE support and thread context management for TrustZone for ARMv8-M
  99        - Added cmsis_compiler.h to unify compiler behaviour.
 100        - Updated function SCB_EnableICache (for Cortex-M7).
 101        - Added functions: NVIC_GetEnableIRQ, SCB_GetFPUType
 102       CMSIS-RTOS:
 103         - bug fix in RTX 4.82 (see revision history for details)
 104       CMSIS-RTOS2:
 105         - new API including compatibility layer to CMSIS-RTOS
 106         - reference implementation based on RTX5
 107         - supports all Cortex-M variants including TrustZone for ARMv8-M
 108       CMSIS-SVD:
 109        - reworked SVD format documentation
 110        - removed SVD file database documentation as SVD files are distributed in packs
 111        - updated SVDConv for Win32 and Linux
 112       CMSIS-DSP:
 113        - Moved DSP libraries from CMSIS/DSP/Lib to CMSIS/Lib.
 114        - Added DSP libraries build projects to CMSIS pack.
 115     </release>
 116     <release version="4.5.0" date="2015-10-28">
 117       - CMSIS-Core     4.30.0  (see revision history for details)
 118       - CMSIS-DAP      1.1.0   (unchanged)
 119       - CMSIS-Driver   2.04.0  (see revision history for details)
 120       - CMSIS-DSP      1.4.7   (no source code change [still labeled 1.4.5], see revision history for details)
 121       - CMSIS-PACK     1.4.1   (see revision history for details)
 122       - CMSIS-RTOS     4.80.0  Restored time delay parameter 'millisec' old behavior (prior V4.79) for software compatibility. (see revision history for details)
 123       - CMSIS-SVD      1.3.1   (see revision history for details)
 124     </release>
 125     <release version="4.4.0" date="2015-09-11">
 126       - CMSIS-Core     4.20   (see revision history for details)
 127       - CMSIS-DSP      1.4.6  (no source code change [still labeled 1.4.5], see revision history for details)
 128       - CMSIS-PACK     1.4.0  (adding memory attributes, algorithm style)
 129       - CMSIS-Driver   2.03.0 (adding CAN [Controller Area Network] API)
 130       - CMSIS-RTOS
 131         -- API         1.02   (unchanged)
 132         -- RTX         4.79   (see revision history for details)
 133       - CMSIS-SVD      1.3.0  (see revision history for details)
 134       - CMSIS-DAP      1.1.0  (extended with SWO support)
 135     </release>
 136     <release version="4.3.0" date="2015-03-20">
 137       - CMSIS-Core     4.10   (Cortex-M7 extended Cache Maintenance functions)
 138       - CMSIS-DSP      1.4.5  (see revision history for details)
 139       - CMSIS-Driver   2.02   (adding SAI (Serial Audio Interface) API)
 140       - CMSIS-PACK     1.3.3  (Semantic Versioning, Generator extensions)
 141       - CMSIS-RTOS
 142         -- API         1.02   (unchanged)
 143         -- RTX         4.78   (see revision history for details)
 144       - CMSIS-SVD      1.2    (unchanged)
 145     </release>
 146     <release version="4.2.0" date="2014-09-24">
 147       Adding Cortex-M7 support
 148       - CMSIS-Core     4.00  (Cortex-M7 support, corrected C++ include guards in core header files)
 149       - CMSIS-DSP      1.4.4 (Cortex-M7 support and corrected out of bound issues)
 150       - CMSIS-PACK     1.3.1 (Cortex-M7 updates, clarification, corrected batch files in Tutorial)
 151       - CMSIS-SVD      1.2   (Cortex-M7 extensions)
 152       - CMSIS-RTOS RTX 4.75  (see revision history for details)
 153     </release>
 154     <release version="4.1.1" date="2014-06-30">
 155       - fixed conditions preventing the inclusion of the DSP library in projects for Infineon XMC4000 series devices
 156     </release>
 157     <release version="4.1.0" date="2014-06-12">
 158       - CMSIS-Driver   2.02  (incompatible update)
 159       - CMSIS-Pack     1.3   (see revision history for details)
 160       - CMSIS-DSP      1.4.2 (unchanged)
 161       - CMSIS-Core     3.30  (unchanged)
 162       - CMSIS-RTOS RTX 4.74  (unchanged)
 163       - CMSIS-RTOS API 1.02  (unchanged)
 164       - CMSIS-SVD      1.10  (unchanged)
 165       PACK:
 166       - removed G++ specific files from PACK
 167       - added Component Startup variant "C Startup"
 168       - added Pack Checking Utility
 169       - updated conditions to reflect tool-chain dependency
 170       - added Taxonomy for Graphics
 171       - updated Taxonomy for unified drivers from "Drivers" to "CMSIS Drivers"
 172     </release>
 173     <release version="4.0.0">
 174       - CMSIS-Driver   2.00  Preliminary (incompatible update)
 175       - CMSIS-Pack     1.1   Preliminary
 176       - CMSIS-DSP      1.4.2 (see revision history for details)
 177       - CMSIS-Core     3.30  (see revision history for details)
 178       - CMSIS-RTOS RTX 4.74  (see revision history for details)
 179       - CMSIS-RTOS API 1.02  (unchanged)
 180       - CMSIS-SVD      1.10  (unchanged)
 181     </release>
 182     <release version="3.20.4">
 183       - CMSIS-RTOS 4.74 (see revision history for details)
 184       - PACK Extensions (Boards, Device Features, Flash Programming, Generators, Configuration Wizard). Schema version 1.1.
 185     </release>
 186     <release version="3.20.3">
 187       - CMSIS-Driver API Version 1.10 ARM prefix added (incompatible change)
 188       - CMSIS-RTOS 4.73 (see revision history for details)
 189     </release>
 190     <release version="3.20.2">
 191       - CMSIS-Pack documentation has been added
 192       - CMSIS-Drivers header and documentation have been added to PACK
 193       - CMSIS-CORE, CMSIS-DSP, CMSIS-RTOS API and CMSIS-SVD remain unchanged
 194     </release>
 195     <release version="3.20.1">
 196       - CMSIS-RTOS Keil RTX V4.72 has been added to PACK
 197       - CMSIS-CORE, CMSIS-DSP, CMSIS-RTOS API and CMSIS-SVD remain unchanged
 198     </release>
 199     <release version="3.20.0">
 200       The software portions that are deployed in the application program are now under a BSD license which allows usage
 201       of CMSIS components in any commercial or open source projects.  The Pack Description file Arm.CMSIS.pdsc describes the use cases
 202       The individual components have been update as listed below:
 203       - CMSIS-CORE adds functions for setting breakpoints, supports the latest GCC Compiler, and contains several corrections.
 204       - CMSIS-DSP library is optimized for more performance and contains several bug fixes.
 205       - CMSIS-RTOS API is extended with capabilities for short timeouts, Kernel initialization, and prepared for a C++ interface.
 206       - CMSIS-SVD is unchanged.
 207     </release>
 208   </releases>
 209
 210   <taxonomy>
 211     <description Cclass="Board Support">Generic Interfaces for Evaluation and Development Boards</description>
 212     <description Cclass="CMSIS" doc="CMSIS/Documentation/General/html/index.html">Cortex Microcontroller Software Interface Components</description>
 213     <description Cclass="Device" doc="CMSIS/Documentation/Core/html/index.html">Startup, System Setup</description>
 214     <description Cclass="CMSIS Driver" doc="CMSIS/Documentation/Driver/html/index.html">Unified Device Drivers compliant to CMSIS-Driver Specifications</description>
 215     <description Cclass="File System">File Drive Support and File System</description>
 216     <description Cclass="Graphics">Graphical User Interface</description>
 217     <description Cclass="Network">Network Stack using Internet Protocols</description>
 218     <description Cclass="USB">Universal Serial Bus Stack</description>
 219     <description Cclass="Compiler">Compiler Software Extensions</description>
 220     <description Cclass="RTOS">Real-time Operating System</description>
 221   </taxonomy>
 222
 223   <devices>
 224     <!-- ******************************  Cortex-M0  ****************************** -->
 225     <family Dfamily="ARM Cortex M0" Dvendor="ARM:82">
 226       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/index.html" title="Cortex-M0 Device Generic Users Guide"/>
 227       <description>
 228 The Cortex-M0 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 229 - simple, easy-to-use programmers model
 230 - highly efficient ultra-low power operation
 231 - excellent code density
 232 - deterministic, high-performance interrupt handling
 233 - upward compatibility with the rest of the Cortex-M processor family.
 234       </description>
 235       <debug svd="Device/ARM/SVD/ARMCM0.svd"/>
 236       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 237       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 238       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 239
 240       <device Dname="ARMCM0">
 241         <processor Dcore="Cortex-M0" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
 242         <compile header="Device/ARM/ARMCM0/Include/ARMCM0.h" define="ARMCM0"/>
 243       </device>
 244     </family>
 245
 246     <!-- ******************************  Cortex-M0P  ****************************** -->
 247     <family Dfamily="ARM Cortex M0 plus" Dvendor="ARM:82">
 248       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0662b/index.html" title="Cortex-M0+ Device Generic Users Guide"/>
 249       <description>
 250 The Cortex-M0+ processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 251 - simple, easy-to-use programmers model
 252 - highly efficient ultra-low power operation
 253 - excellent code density
 254 - deterministic, high-performance interrupt handling
 255 - upward compatibility with the rest of the Cortex-M processor family.
 256       </description>
 257       <debug svd="Device/ARM/SVD/ARMCM0P.svd"/>
 258       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 259       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 260       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 261
 262       <device Dname="ARMCM0P">
 263         <processor Dcore="Cortex-M0+" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
 264         <compile header="Device/ARM/ARMCM0plus/Include/ARMCM0plus.h" define="ARMCM0P"/>
 265       </device>
 266
 267       <device Dname="ARMCM0P_MPU">
 268         <processor Dcore="Cortex-M0+" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 269         <compile header="Device/ARM/ARMCM0plus/Include/ARMCM0plus_MPU.h" define="ARMCM0P_MPU"/>
 270       </device>
 271     </family>
 272
 273     <!-- ******************************  Cortex-M3  ****************************** -->
 274     <family Dfamily="ARM Cortex M3" Dvendor="ARM:82">
 275       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/index.html" title="Cortex-M3 Device Generic Users Guide"/>
 276       <description>
 277 The Cortex-M3 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 278 - simple, easy-to-use programmers model
 279 - highly efficient ultra-low power operation
 280 - excellent code density
 281 - deterministic, high-performance interrupt handling
 282 - upward compatibility with the rest of the Cortex-M processor family.
 283       </description>
 284       <debug svd="Device/ARM/SVD/ARMCM3.svd"/>
 285       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 286       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 287       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 288
 289       <device Dname="ARMCM3">
 290         <processor Dcore="Cortex-M3" DcoreVersion="r2p1" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 291         <compile header="Device/ARM/ARMCM3/Include/ARMCM3.h" define="ARMCM3"/>
 292       </device>
 293     </family>
 294
 295     <!-- ******************************  Cortex-M4  ****************************** -->
 296     <family Dfamily="ARM Cortex M4" Dvendor="ARM:82">
 297       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/index.html" title="Cortex-M4 Device Generic Users Guide"/>
 298       <description>
 299 The Cortex-M4 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 300 - simple, easy-to-use programmers model
 301 - highly efficient ultra-low power operation
 302 - excellent code density
 303 - deterministic, high-performance interrupt handling
 304 - upward compatibility with the rest of the Cortex-M processor family.
 305       </description>
 306       <debug svd="Device/ARM/SVD/ARMCM4.svd"/>
 307       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 308       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 309       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 310
 311       <device Dname="ARMCM4">
 312         <processor Dcore="Cortex-M4" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 313         <compile header="Device/ARM/ARMCM4/Include/ARMCM4.h"    define="ARMCM4"/>
 314       </device>
 315
 316       <device Dname="ARMCM4_FP">
 317         <processor Dcore="Cortex-M4" DcoreVersion="r0p1" Dfpu="SP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 318         <compile header="Device/ARM/ARMCM4/Include/ARMCM4_FP.h" define="ARMCM4_FP"/>
 319       </device>
 320     </family>
 321
 322     <!-- ******************************  Cortex-M7  ****************************** -->
 323     <family Dfamily="ARM Cortex M7" Dvendor="ARM:82">
 324       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0646b/index.html" title="Cortex-M7 Device Generic Users Guide"/>
 325       <description>
 326 The Cortex-M7 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 327 - simple, easy-to-use programmers model
 328 - highly efficient ultra-low power operation
 329 - excellent code density
 330 - deterministic, high-performance interrupt handling
 331 - upward compatibility with the rest of the Cortex-M processor family.
 332       </description>
 333       <debug svd="Device/ARM/SVD/ARMCM7.svd"/>
 334       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 335       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 336       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 337
 338       <device Dname="ARMCM7">
 339         <processor Dcore="Cortex-M7" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 340         <compile header="Device/ARM/ARMCM7/Include/ARMCM7.h" define="ARMCM7"/>
 341       </device>
 342
 343       <device Dname="ARMCM7_SP">
 344         <processor Dcore="Cortex-M7" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 345         <compile header="Device/ARM/ARMCM7/Include/ARMCM7_SP.h" define="ARMCM7_SP"/>
 346       </device>
 347
 348       <device Dname="ARMCM7_DP">
 349         <processor Dcore="Cortex-M7" DcoreVersion="r0p0" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 350         <compile header="Device/ARM/ARMCM7/Include/ARMCM7_DP.h" define="ARMCM7_DP"/>
 351       </device>
 352     </family>
 353
 354     <!-- ******************************  Cortex-M23  ********************** -->
 355     <family Dfamily="ARM Cortex M23" Dvendor="ARM:82">
 356       <!--book name="Device/ARM/Documents/??_dgug.pdf"       title="?? Device Generic Users Guide"/-->
 357       <description>
 358 The Arm Cortex-M23 is based on the Armv8-M baseline architecture.
 359 It is the smallest and most energy efficient Arm processor with Arm TrustZone technology.
 360 Cortex-M23 is the ideal processor for constrained embedded applications requiring efficient security.
 361       </description>
 362       <debug svd="Device/ARM/SVD/ARMCM23.svd"/>
 363       <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
 364       <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
 365       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 366       <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
 367       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 368
 369       <device Dname="ARMCM23">
 370         <processor Dcore="Cortex-M23" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
 371         <compile header="Device/ARM/ARMCM23/Include/ARMCM23.h" define="ARMCM23"/>
 372       </device>
 373
 374       <device Dname="ARMCM23_TZ">
 375         <processor Dcore="Cortex-M23" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 376         <compile header="Device/ARM/ARMCM23/Include/ARMCM23_TZ.h" define="ARMCM23_TZ"/>
 377       </device>
 378     </family>
 379
 380     <!-- ******************************  Cortex-M33  ****************************** -->
 381     <family Dfamily="ARM Cortex M33" Dvendor="ARM:82">
 382       <!--book name="Device/ARM/Documents/??_dgug.pdf"       title="?? Device Generic Users Guide"/-->
 383       <description>
 384 The Arm Cortex-M33 is the most configurable of all Cortex-M processors. It is a full featured microcontroller
 385 class processor based on the Armv8-M mainline architecture with Arm TrustZone security.
 386       </description>
 387       <debug svd="Device/ARM/SVD/ARMCM33.svd"/>
 388       <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
 389       <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
 390       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 391       <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
 392       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"          default="1"/-->
 393
 394       <device Dname="ARMCM33">
 395         <processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
 396         <description>
 397           no DSP Instructions, no Floating Point Unit, no TrustZone
 398         </description>
 399         <compile header="Device/ARM/ARMCM33/Include/ARMCM33.h" define="ARMCM33"/>
 400       </device>
 401
 402       <device Dname="ARMCM33_TZ">
 403         <processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 404         <description>
 405           no DSP Instructions, no Floating Point Unit, TrustZone
 406         </description>
 407         <compile header="Device/ARM/ARMCM33/Include/ARMCM33_TZ.h" define="ARMCM33_TZ"/>
 408       </device>
 409
 410       <device Dname="ARMCM33_DSP_FP">
 411         <processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
 412         <description>
 413           DSP Instructions, Single Precision Floating Point Unit, no TrustZone
 414         </description>
 415         <compile header="Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP.h" define="ARMCM33_DSP_FP"/>
 416       </device>
 417
 418       <device Dname="ARMCM33_DSP_FP_TZ">
 419         <processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 420         <description>
 421           DSP Instructions, Single Precision Floating Point Unit, TrustZone
 422         </description>
 423         <compile header="Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h" define="ARMCM33_DSP_FP_TZ"/>
 424       </device>
 425     </family>
 426
 427     <!-- ******************************  ARMSC000  ****************************** -->
 428     <family Dfamily="ARM SC000" Dvendor="ARM:82">
 429       <description>
 430 The Arm SC000 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including:
 431 - simple, easy-to-use programmers model
 432 - highly efficient ultra-low power operation
 433 - excellent code density
 434 - deterministic, high-performance interrupt handling
 435       </description>
 436       <debug svd="Device/ARM/SVD/ARMSC000.svd"/>
 437       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 438       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 439       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 440
 441       <device Dname="ARMSC000">
 442         <processor Dcore="SC000" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
 443         <compile header="Device/ARM/ARMSC000/Include/ARMSC000.h" define="ARMSC000"/>
 444       </device>
 445     </family>
 446
 447     <!-- ******************************  ARMSC300  ****************************** -->
 448     <family Dfamily="ARM SC300" Dvendor="ARM:82">
 449       <description>
 450 The ARM SC300 processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including:
 451 - simple, easy-to-use programmers model
 452 - highly efficient ultra-low power operation
 453 - excellent code density
 454 - deterministic, high-performance interrupt handling
 455       </description>
 456       <debug svd="Device/ARM/SVD/ARMSC300.svd"/>
 457       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 458       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 459       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 460
 461       <device Dname="ARMSC300">
 462         <processor Dcore="SC300" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
 463         <compile header="Device/ARM/ARMSC300/Include/ARMSC300.h" define="ARMSC300"/>
 464       </device>
 465     </family>
 466
 467     <!-- ******************************  ARMv8-M Baseline  ********************** -->
 468     <family Dfamily="ARMv8-M Baseline" Dvendor="ARM:82">
 469       <!--book name="Device/ARM/Documents/ARMv8MBL_dgug.pdf"       title="ARMv8MBL Device Generic Users Guide"/-->
 470       <description>
 471 Armv8-M Baseline based device with TrustZone
 472       </description>
 473       <debug svd="Device/ARM/SVD/ARMv8MBL.svd"/>
 474       <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
 475       <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
 476       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 477       <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
 478       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 479
 480       <device Dname="ARMv8MBL">
 481         <processor Dcore="ARMV8MBL" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 482         <compile header="Device/ARM/ARMv8MBL/Include/ARMv8MBL.h" define="ARMv8MBL"/>
 483       </device>
 484     </family>
 485
 486     <!-- ******************************  ARMv8-M Mainline  ****************************** -->
 487     <family Dfamily="ARMv8-M Mainline" Dvendor="ARM:82">
 488       <!--book name="Device/ARM/Documents/ARMv8MML_dgug.pdf"       title="ARMv8MML Device Generic Users Guide"/-->
 489       <description>
 490 Armv8-M Mainline based device with TrustZone
 491       </description>
 492       <debug svd="Device/ARM/SVD/ARMv8MML.svd"/>
 493       <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
 494       <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
 495       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 496       <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
 497       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 498
 499       <device Dname="ARMv8MML">
 500         <processor Dcore="ARMV8MML" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 501         <description>
 502           no DSP Instructions, no Floating Point Unit, TrustZone
 503         </description>
 504         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML.h" define="ARMv8MML"/>
 505       </device>
 506
 507       <device Dname="ARMv8MML_DSP">
 508         <processor Dcore="ARMV8MML" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 509         <description>
 510           DSP Instructions, no Floating Point Unit, TrustZone
 511         </description>
 512         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DSP.h" define="ARMv8MML_DSP"/>
 513       </device>
 514
 515       <device Dname="ARMv8MML_SP">
 516         <processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 517         <description>
 518           no DSP Instructions, Single Precision Floating Point Unit, TrustZone
 519         </description>
 520         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_SP.h" define="ARMv8MML_SP"/>
 521       </device>
 522
 523       <device Dname="ARMv8MML_DSP_SP">
 524         <processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 525         <description>
 526           DSP Instructions, Single Precision Floating Point Unit, TrustZone
 527         </description>
 528         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_SP.h" define="ARMv8MML_DSP_SP"/>
 529       </device>
 530
 531       <device Dname="ARMv8MML_DP">
 532         <processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="DP_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 533         <description>
 534           no DSP Instructions, Double Precision Floating Point Unit, TrustZone
 535         </description>
 536         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DP.h" define="ARMv8MML_DP"/>
 537       </device>
 538
 539       <device Dname="ARMv8MML_DSP_DP">
 540         <processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="DP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 541         <description>
 542           DSP Instructions, Double Precision Floating Point Unit, TrustZone
 543         </description>
 544         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h" define="ARMv8MML_DSP_DP"/>
 545       </device>
 546     </family>
 547
 548     <!-- ******************************  Cortex-A5  ****************************** -->
 549     <family Dfamily="ARM Cortex A5" Dvendor="ARM:82">
 550       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0433c/index.html" title="Cortex-A5 Technical Reference Manual"/>
 551       <description>
 552 The Arm Cortex-A5 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full
 553 virtual memory capabilities. The Cortex-A5 processor implements the Armv7-A architecture profile and can execute 32-bit
 554 Arm instructions and 16-bit and 32-bit Thumb instructions. The Cortex-A5 is the smallest member of the Cortex-A processor family.
 555       </description>
 556
 557       <memory id="IROM1"                                start="0x80000000" size="0x00200000" startup="1" default="1"/>
 558       <memory id="IRAM1"                                start="0x80200000" size="0x00200000" init   ="0" default="1"/>
 559
 560       <device Dname="ARMCA5">
 561         <processor Dcore="Cortex-A5" DcoreVersion="r0p1" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable"/>
 562         <compile header="Device/ARM/ARMCA5/Include/ARMCA5.h" define="ARMCA5"/>
 563       </device>
 564     </family>
 565
 566     <!-- ******************************  Cortex-A7  ****************************** -->
 567     <family Dfamily="ARM Cortex A7" Dvendor="ARM:82">
 568       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/index.html" title="Cortex-A7 MPCore Technical Reference Manual"/>
 569       <description>
 570 The Cortex-A7 MPCore processor is a high-performance, low-power processor that implements the Armv7-A architecture.
 571 The Cortex-A7 MPCore processor has one to four processors in a single multiprocessor device with a L1 cache subsystem,
 572 an optional integrated GIC, and an optional L2 cache controller.
 573       </description>
 574
 575       <memory id="IROM1"                                start="0x80000000" size="0x00200000" startup="1" default="1"/>
 576       <memory id="IRAM1"                                start="0x80200000" size="0x00200000" init   ="0" default="1"/>
 577
 578       <device Dname="ARMCA7">
 579         <processor Dcore="Cortex-A7" DcoreVersion="r0p5" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable"/>
 580         <compile header="Device/ARM/ARMCA7/Include/ARMCA7.h" define="ARMCA7"/>
 581       </device>
 582     </family>
 583
 584     <!-- ******************************  Cortex-A9  ****************************** -->
 585     <family Dfamily="ARM Cortex A9" Dvendor="ARM:82">
 586       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.100511_0401_10_en/index.html" title="Cortex-A9 Technical Reference Manual"/>
 587       <description>
 588 The Cortex-A9 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full virtual memory capabilities.
 589 The Cortex-A9 processor implements the Armv7-A architecture and runs 32-bit Arm instructions, 16-bit and 32-bit Thumb instructions,
 590 and 8-bit Java bytecodes in Jazelle state.
 591       </description>
 592
 593       <memory id="IROM1"                                start="0x80000000" size="0x00200000" startup="1" default="1"/>
 594       <memory id="IRAM1"                                start="0x80200000" size="0x00200000" init   ="0" default="1"/>
 595
 596       <device Dname="ARMCA9">
 597         <processor Dcore="Cortex-A9" DcoreVersion="r4p1" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable"/>
 598         <compile header="Device/ARM/ARMCA9/Include/ARMCA9.h" define="ARMCA9"/>
 599       </device>
 600     </family>
 601   </devices>
 602
 603
 604   <apis>
 605     <!-- CMSIS Device API -->
 606     <api Cclass="Device" Cgroup="IRQ Controller" Capiversion="1.0.0" exclusive="1">
 607       <description>Device interrupt controller interface</description>
 608       <files>
 609         <file category="header" name="CMSIS/Core_A/Include/irq_ctrl.h"/>
 610       </files>
 611     </api>
 612     <api Cclass="Device" Cgroup="OS Tick" Capiversion="1.0.1" exclusive="1">
 613       <description>RTOS Kernel system tick timer interface</description>
 614       <files>
 615         <file category="header" name="CMSIS/RTOS2/Include/os_tick.h"/>
 616       </files>
 617     </api>
 618     <!-- CMSIS-RTOS API -->
 619     <api Cclass="CMSIS" Cgroup="RTOS" Capiversion="1.0.0" exclusive="1">
 620       <description>CMSIS-RTOS API for Cortex-M, SC000, and SC300</description>
 621       <files>
 622         <file category="doc" name="CMSIS/Documentation/RTOS/html/index.html"/>
 623       </files>
 624     </api>
 625     <api Cclass="CMSIS" Cgroup="RTOS2" Capiversion="2.1.2" exclusive="1">
 626       <description>CMSIS-RTOS API for Cortex-M, SC000, and SC300</description>
 627       <files>
 628         <file category="doc" name="CMSIS/Documentation/RTOS2/html/index.html"/>
 629         <file category="header" name="CMSIS/RTOS2/Include/cmsis_os2.h"/>
 630       </files>
 631     </api>
 632     <!-- CMSIS Driver API -->
 633     <api Cclass="CMSIS Driver" Cgroup="USART" Capiversion="2.3.0" exclusive="0">
 634       <description>USART Driver API for Cortex-M</description>
 635       <files>
 636         <file category="doc" name="CMSIS/Documentation/Driver/html/group__usart__interface__gr.html" />
 637         <file category="header" name="CMSIS/Driver/Include/Driver_USART.h" />
 638       </files>
 639     </api>
 640     <api Cclass="CMSIS Driver" Cgroup="SPI" Capiversion="2.2.0" exclusive="0">
 641       <description>SPI Driver API for Cortex-M</description>
 642       <files>
 643         <file category="doc" name="CMSIS/Documentation/Driver/html/group__spi__interface__gr.html" />
 644         <file category="header" name="CMSIS/Driver/Include/Driver_SPI.h" />
 645       </files>
 646     </api>
 647     <api Cclass="CMSIS Driver" Cgroup="SAI" Capiversion="1.1.0" exclusive="0">
 648       <description>SAI Driver API for Cortex-M</description>
 649       <files>
 650         <file category="doc" name="CMSIS/Documentation/Driver/html/group__sai__interface__gr.html"/>
 651         <file category="header" name="CMSIS/Driver/Include/Driver_SAI.h" />
 652       </files>
 653     </api>
 654     <api Cclass="CMSIS Driver" Cgroup="I2C" Capiversion="2.3.0" exclusive="0">
 655       <description>I2C Driver API for Cortex-M</description>
 656       <files>
 657         <file category="doc" name="CMSIS/Documentation/Driver/html/group__i2c__interface__gr.html"/>
 658         <file category="header" name="CMSIS/Driver/Include/Driver_I2C.h" />
 659       </files>
 660     </api>
 661     <api Cclass="CMSIS Driver" Cgroup="CAN" Capiversion="1.2.0" exclusive="0">
 662       <description>CAN Driver API for Cortex-M</description>
 663       <files>
 664         <file category="doc" name="CMSIS/Documentation/Driver/html/group__can__interface__gr.html"/>
 665         <file category="header" name="CMSIS/Driver/Include/Driver_CAN.h" />
 666       </files>
 667     </api>
 668     <api Cclass="CMSIS Driver" Cgroup="Flash" Capiversion="2.1.0" exclusive="0">
 669       <description>Flash Driver API for Cortex-M</description>
 670       <files>
 671         <file category="doc" name="CMSIS/Documentation/Driver/html/group__flash__interface__gr.html" />
 672         <file category="header" name="CMSIS/Driver/Include/Driver_Flash.h" />
 673       </files>
 674     </api>
 675     <api Cclass="CMSIS Driver" Cgroup="MCI" Capiversion="2.3.0" exclusive="0">
 676       <description>MCI Driver API for Cortex-M</description>
 677       <files>
 678         <file category="doc" name="CMSIS/Documentation/Driver/html/group__mci__interface__gr.html" />
 679         <file category="header" name="CMSIS/Driver/Include/Driver_MCI.h" />
 680       </files>
 681     </api>
 682     <api Cclass="CMSIS Driver" Cgroup="NAND" Capiversion="2.3.0" exclusive="0">
 683       <description>NAND Flash Driver API for Cortex-M</description>
 684       <files>
 685         <file category="doc" name="CMSIS/Documentation/Driver/html/group__nand__interface__gr.html" />
 686         <file category="header" name="CMSIS/Driver/Include/Driver_NAND.h" />
 687       </files>
 688     </api>
 689     <api Cclass="CMSIS Driver" Cgroup="Ethernet" Capiversion="2.1.0" exclusive="0">
 690       <description>Ethernet MAC and PHY Driver API for Cortex-M</description>
 691       <files>
 692         <file category="doc" name="CMSIS/Documentation/Driver/html/group__eth__interface__gr.html" />
 693         <file category="header" name="CMSIS/Driver/Include/Driver_ETH_MAC.h" />
 694         <file category="header" name="CMSIS/Driver/Include/Driver_ETH_PHY.h" />
 695       </files>
 696     </api>
 697     <api Cclass="CMSIS Driver" Cgroup="Ethernet MAC" Capiversion="2.1.0" exclusive="0">
 698       <description>Ethernet MAC Driver API for Cortex-M</description>
 699       <files>
 700         <file category="doc" name="CMSIS/Documentation/Driver/html/group__eth__mac__interface__gr.html" />
 701         <file category="header" name="CMSIS/Driver/Include/Driver_ETH_MAC.h" />
 702       </files>
 703     </api>
 704     <api Cclass="CMSIS Driver" Cgroup="Ethernet PHY" Capiversion="2.1.0" exclusive="0">
 705       <description>Ethernet PHY Driver API for Cortex-M</description>
 706       <files>
 707         <file category="doc" name="CMSIS/Documentation/Driver/html/group__eth__phy__interface__gr.html" />
 708         <file category="header" name="CMSIS/Driver/Include/Driver_ETH_PHY.h" />
 709       </files>
 710     </api>
 711     <api Cclass="CMSIS Driver" Cgroup="USB Device" Capiversion="2.2.0" exclusive="0">
 712       <description>USB Device Driver API for Cortex-M</description>
 713       <files>
 714         <file category="doc" name="CMSIS/Documentation/Driver/html/group__usbd__interface__gr.html" />
 715         <file category="header" name="CMSIS/Driver/Include/Driver_USBD.h" />
 716       </files>
 717     </api>
 718     <api Cclass="CMSIS Driver" Cgroup="USB Host" Capiversion="2.2.0" exclusive="0">
 719       <description>USB Host Driver API for Cortex-M</description>
 720       <files>
 721         <file category="doc" name="CMSIS/Documentation/Driver/html/group__usbh__interface__gr.html" />
 722         <file category="header" name="CMSIS/Driver/Include/Driver_USBH.h" />
 723       </files>
 724     </api>
 725   </apis>
 726
 727   <!-- conditions are dependency rules that can apply to a component or an individual file -->
 728   <conditions>
 729     <!-- compiler -->
 730     <condition id="ARMCC6">
 731       <accept Tcompiler="ARMCC" Toptions="AC6"/>
 732       <accept Tcompiler="ARMCC" Toptions="AC6LTO"/>
 733     </condition>
 734     <condition id="ARMCC5">
 735       <require Tcompiler="ARMCC" Toptions="AC5"/>
 736     </condition>
 737     <condition id="ARMCC">
 738       <require Tcompiler="ARMCC"/>
 739     </condition>
 740     <condition id="GCC">
 741       <require Tcompiler="GCC"/>
 742     </condition>
 743     <condition id="IAR">
 744       <require Tcompiler="IAR"/>
 745     </condition>
 746     <condition id="ARMCC GCC">
 747       <accept Tcompiler="ARMCC"/>
 748       <accept Tcompiler="GCC"/>
 749     </condition>
 750     <condition id="ARMCC GCC IAR">
 751       <accept Tcompiler="ARMCC"/>
 752       <accept Tcompiler="GCC"/>
 753       <accept Tcompiler="IAR"/>
 754     </condition>
 755
 756     <!-- Arm architecture -->
 757     <condition id="ARMv6-M Device">
 758       <description>Armv6-M architecture based device</description>
 759       <accept Dcore="Cortex-M0"/>
 760       <accept Dcore="Cortex-M0+"/>
 761       <accept Dcore="SC000"/>
 762     </condition>
 763     <condition id="ARMv7-M Device">
 764       <description>Armv7-M architecture based device</description>
 765       <accept Dcore="Cortex-M3"/>
 766       <accept Dcore="Cortex-M4"/>
 767       <accept Dcore="Cortex-M7"/>
 768       <accept Dcore="SC300"/>
 769     </condition>
 770     <condition id="ARMv8-M Device">
 771       <description>Armv8-M architecture based device</description>
 772       <accept Dcore="ARMV8MBL"/>
 773       <accept Dcore="ARMV8MML"/>
 774       <accept Dcore="Cortex-M23"/>
 775       <accept Dcore="Cortex-M33"/>
 776     </condition>
 777     <condition id="ARMv8-M TZ Device">
 778       <description>Armv8-M architecture based device with TrustZone</description>
 779       <require condition="ARMv8-M Device"/>
 780       <require Dtz="TZ"/>
 781     </condition>
 782     <condition id="ARMv6_7-M Device">
 783       <description>Armv6_7-M architecture based device</description>
 784       <accept condition="ARMv6-M Device"/>
 785       <accept condition="ARMv7-M Device"/>
 786     </condition>
 787     <condition id="ARMv6_7_8-M Device">
 788       <description>Armv6_7_8-M architecture based device</description>
 789       <accept condition="ARMv6-M Device"/>
 790       <accept condition="ARMv7-M Device"/>
 791       <accept condition="ARMv8-M Device"/>
 792     </condition>
 793     <condition id="ARMv7-A Device">
 794       <description>Armv7-A architecture based device</description>
 795       <accept Dcore="Cortex-A5"/>
 796       <accept Dcore="Cortex-A7"/>
 797       <accept Dcore="Cortex-A9"/>
 798     </condition>
 799
 800     <!-- ARM core -->
 801     <condition id="CM0">
 802       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device</description>
 803       <accept Dcore="Cortex-M0"/>
 804       <accept Dcore="Cortex-M0+"/>
 805       <accept Dcore="SC000"/>
 806     </condition>
 807     <condition id="CM3">
 808       <description>Cortex-M3 or SC300 processor based device</description>
 809       <accept Dcore="Cortex-M3"/>
 810       <accept Dcore="SC300"/>
 811     </condition>
 812     <condition id="CM4">
 813       <description>Cortex-M4 processor based device</description>
 814       <require Dcore="Cortex-M4" Dfpu="NO_FPU"/>
 815     </condition>
 816     <condition id="CM4_FP">
 817       <description>Cortex-M4 processor based device using Floating Point Unit</description>
 818       <accept Dcore="Cortex-M4" Dfpu="FPU"/>
 819       <accept Dcore="Cortex-M4" Dfpu="SP_FPU"/>
 820       <accept Dcore="Cortex-M4" Dfpu="DP_FPU"/>
 821     </condition>
 822     <condition id="CM7">
 823       <description>Cortex-M7 processor based device</description>
 824       <require Dcore="Cortex-M7" Dfpu="NO_FPU"/>
 825     </condition>
 826     <condition id="CM7_FP">
 827       <description>Cortex-M7 processor based device using Floating Point Unit</description>
 828       <accept Dcore="Cortex-M7" Dfpu="SP_FPU"/>
 829       <accept Dcore="Cortex-M7" Dfpu="DP_FPU"/>
 830     </condition>
 831     <condition id="CM7_SP">
 832       <description>Cortex-M7 processor based device using Floating Point Unit (SP)</description>
 833       <require Dcore="Cortex-M7" Dfpu="SP_FPU"/>
 834     </condition>
 835     <condition id="CM7_DP">
 836       <description>Cortex-M7 processor based device using Floating Point Unit (DP)</description>
 837       <require Dcore="Cortex-M7" Dfpu="DP_FPU"/>
 838     </condition>
 839     <condition id="CM23">
 840       <description>Cortex-M23 processor based device</description>
 841       <require Dcore="Cortex-M23"/>
 842     </condition>
 843     <condition id="CM33">
 844       <description>Cortex-M33 processor based device</description>
 845       <require Dcore="Cortex-M33" Dfpu="NO_FPU"/>
 846     </condition>
 847     <condition id="CM33_FP">
 848       <description>Cortex-M33 processor based device using Floating Point Unit</description>
 849       <require Dcore="Cortex-M33" Dfpu="SP_FPU"/>
 850     </condition>
 851     <condition id="ARMv8MBL">
 852       <description>Armv8-M Baseline processor based device</description>
 853       <require Dcore="ARMV8MBL"/>
 854     </condition>
 855     <condition id="ARMv8MML">
 856       <description>Armv8-M Mainline processor based device</description>
 857       <require Dcore="ARMV8MML" Dfpu="NO_FPU"/>
 858     </condition>
 859     <condition id="ARMv8MML_FP">
 860       <description>Armv8-M Mainline processor based device using Floating Point Unit</description>
 861       <accept Dcore="ARMV8MML" Dfpu="SP_FPU"/>
 862       <accept Dcore="ARMV8MML" Dfpu="DP_FPU"/>
 863     </condition>
 864
 865     <condition id="CM33_NODSP_NOFPU">
 866       <description>CM33, no DSP, no FPU</description>
 867       <require Dcore="Cortex-M33" Ddsp="NO_DSP" Dfpu="NO_FPU"/>
 868     </condition>
 869     <condition id="CM33_DSP_NOFPU">
 870       <description>CM33, DSP, no FPU</description>
 871       <require Dcore="Cortex-M33" Ddsp="DSP" Dfpu="NO_FPU"/>
 872     </condition>
 873     <condition id="CM33_NODSP_SP">
 874       <description>CM33, no DSP, SP FPU</description>
 875       <require Dcore="Cortex-M33" Ddsp="NO_DSP" Dfpu="SP_FPU"/>
 876     </condition>
 877     <condition id="CM33_DSP_SP">
 878       <description>CM33, DSP, SP FPU</description>
 879       <require Dcore="Cortex-M33" Ddsp="DSP" Dfpu="SP_FPU"/>
 880     </condition>
 881
 882     <condition id="ARMv8MML_NODSP_NOFPU">
 883       <description>Armv8-M Mainline, no DSP, no FPU</description>
 884       <require Dcore="ARMV8MML" Ddsp="NO_DSP" Dfpu="NO_FPU"/>
 885     </condition>
 886     <condition id="ARMv8MML_DSP_NOFPU">
 887       <description>Armv8-M Mainline, DSP, no FPU</description>
 888       <require Dcore="ARMV8MML" Ddsp="DSP" Dfpu="NO_FPU"/>
 889     </condition>
 890     <condition id="ARMv8MML_NODSP_SP">
 891       <description>Armv8-M Mainline, no DSP, SP FPU</description>
 892       <require Dcore="ARMV8MML" Ddsp="NO_DSP" Dfpu="SP_FPU"/>
 893     </condition>
 894     <condition id="ARMv8MML_DSP_SP">
 895       <description>Armv8-M Mainline, DSP, SP FPU</description>
 896       <require Dcore="ARMV8MML" Ddsp="DSP" Dfpu="SP_FPU"/>
 897     </condition>
 898
 899     <condition id="CA5_CA9">
 900       <description>Cortex-A5 or Cortex-A9 processor based device</description>
 901       <accept Dcore="Cortex-A5"/>
 902       <accept Dcore="Cortex-A9"/>
 903     </condition>
 904
 905     <condition id="CA7">
 906       <description>Cortex-A7 processor based device</description>
 907       <accept Dcore="Cortex-A7"/>
 908     </condition>
 909
 910     <!-- ARMCC compiler -->
 911     <condition id="CA_ARMCC5">
 912       <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the Arm Compiler 5</description>
 913       <require condition="ARMv7-A Device"/>
 914       <require condition="ARMCC5"/>
 915     </condition>
 916     <condition id="CA_ARMCC6">
 917       <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the Arm Compiler 6</description>
 918       <require condition="ARMv7-A Device"/>
 919       <require condition="ARMCC6"/>
 920     </condition>
 921
 922     <condition id="CM0_ARMCC">
 923       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device for the Arm Compiler</description>
 924       <require condition="CM0"/>
 925       <require Tcompiler="ARMCC"/>
 926     </condition>
 927     <condition id="CM0_LE_ARMCC">
 928       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the Arm Compiler</description>
 929       <require condition="CM0_ARMCC"/>
 930       <require Dendian="Little-endian"/>
 931     </condition>
 932     <condition id="CM0_BE_ARMCC">
 933       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the Arm Compiler</description>
 934       <require condition="CM0_ARMCC"/>
 935       <require Dendian="Big-endian"/>
 936     </condition>
 937
 938     <condition id="CM3_ARMCC">
 939       <description>Cortex-M3 or SC300 processor based device for the Arm Compiler</description>
 940       <require condition="CM3"/>
 941       <require Tcompiler="ARMCC"/>
 942     </condition>
 943     <condition id="CM3_LE_ARMCC">
 944       <description>Cortex-M3 or SC300 processor based device in little endian mode for the Arm Compiler</description>
 945       <require condition="CM3_ARMCC"/>
 946       <require Dendian="Little-endian"/>
 947     </condition>
 948     <condition id="CM3_BE_ARMCC">
 949       <description>Cortex-M3 or SC300 processor based device in big endian mode for the Arm Compiler</description>
 950       <require condition="CM3_ARMCC"/>
 951       <require Dendian="Big-endian"/>
 952     </condition>
 953
 954     <condition id="CM4_ARMCC">
 955       <description>Cortex-M4 processor based device for the Arm Compiler</description>
 956       <require condition="CM4"/>
 957       <require Tcompiler="ARMCC"/>
 958     </condition>
 959     <condition id="CM4_LE_ARMCC">
 960       <description>Cortex-M4 processor based device in little endian mode for the Arm Compiler</description>
 961       <require condition="CM4_ARMCC"/>
 962       <require Dendian="Little-endian"/>
 963     </condition>
 964     <condition id="CM4_BE_ARMCC">
 965       <description>Cortex-M4 processor based device in big endian mode for the Arm Compiler</description>
 966       <require condition="CM4_ARMCC"/>
 967       <require Dendian="Big-endian"/>
 968     </condition>
 969
 970     <condition id="CM4_FP_ARMCC">
 971       <description>Cortex-M4 processor based device using Floating Point Unit for the Arm Compiler</description>
 972       <require condition="CM4_FP"/>
 973       <require Tcompiler="ARMCC"/>
 974     </condition>
 975     <condition id="CM4_FP_LE_ARMCC">
 976       <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
 977       <require condition="CM4_FP_ARMCC"/>
 978       <require Dendian="Little-endian"/>
 979     </condition>
 980     <condition id="CM4_FP_BE_ARMCC">
 981       <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
 982       <require condition="CM4_FP_ARMCC"/>
 983       <require Dendian="Big-endian"/>
 984     </condition>
 985
 986     <condition id="CM7_ARMCC">
 987       <description>Cortex-M7 processor based device for the Arm Compiler</description>
 988       <require condition="CM7"/>
 989       <require Tcompiler="ARMCC"/>
 990     </condition>
 991     <condition id="CM7_LE_ARMCC">
 992       <description>Cortex-M7 processor based device in little endian mode for the Arm Compiler</description>
 993       <require condition="CM7_ARMCC"/>
 994       <require Dendian="Little-endian"/>
 995     </condition>
 996     <condition id="CM7_BE_ARMCC">
 997       <description>Cortex-M7 processor based device in big endian mode for the Arm Compiler</description>
 998       <require condition="CM7_ARMCC"/>
 999       <require Dendian="Big-endian"/>
1000     </condition>
1001
1002     <condition id="CM7_FP_ARMCC">
1003       <description>Cortex-M7 processor based device using Floating Point Unit for the Arm Compiler</description>
1004       <require condition="CM7_FP"/>
1005       <require Tcompiler="ARMCC"/>
1006     </condition>
1007     <condition id="CM7_FP_LE_ARMCC">
1008       <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
1009       <require condition="CM7_FP_ARMCC"/>
1010       <require Dendian="Little-endian"/>
1011     </condition>
1012     <condition id="CM7_FP_BE_ARMCC">
1013       <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
1014       <require condition="CM7_FP_ARMCC"/>
1015       <require Dendian="Big-endian"/>
1016     </condition>
1017
1018     <condition id="CM7_SP_ARMCC">
1019       <description>Cortex-M7 processor based device using Floating Point Unit (SP) for the Arm Compiler</description>
1020       <require condition="CM7_SP"/>
1021       <require Tcompiler="ARMCC"/>
1022     </condition>
1023     <condition id="CM7_SP_LE_ARMCC">
1024       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the Arm Compiler</description>
1025       <require condition="CM7_SP_ARMCC"/>
1026       <require Dendian="Little-endian"/>
1027     </condition>
1028     <condition id="CM7_SP_BE_ARMCC">
1029       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the Arm Compiler</description>
1030       <require condition="CM7_SP_ARMCC"/>
1031       <require Dendian="Big-endian"/>
1032     </condition>
1033
1034     <condition id="CM7_DP_ARMCC">
1035       <description>Cortex-M7 processor based device using Floating Point Unit (DP) for the Arm Compiler</description>
1036       <require condition="CM7_DP"/>
1037       <require Tcompiler="ARMCC"/>
1038     </condition>
1039     <condition id="CM7_DP_LE_ARMCC">
1040       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the Arm Compiler</description>
1041       <require condition="CM7_DP_ARMCC"/>
1042       <require Dendian="Little-endian"/>
1043     </condition>
1044     <condition id="CM7_DP_BE_ARMCC">
1045       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the Arm Compiler</description>
1046       <require condition="CM7_DP_ARMCC"/>
1047       <require Dendian="Big-endian"/>
1048     </condition>
1049
1050     <condition id="CM23_ARMCC">
1051       <description>Cortex-M23 processor based device for the Arm Compiler</description>
1052       <require condition="CM23"/>
1053       <require Tcompiler="ARMCC"/>
1054     </condition>
1055     <condition id="CM23_LE_ARMCC">
1056       <description>Cortex-M23 processor based device in little endian mode for the Arm Compiler</description>
1057       <require condition="CM23_ARMCC"/>
1058       <require Dendian="Little-endian"/>
1059     </condition>
1060     <condition id="CM23_BE_ARMCC">
1061       <description>Cortex-M23 processor based device in big endian mode for the Arm Compiler</description>
1062       <require condition="CM23_ARMCC"/>
1063       <require Dendian="Big-endian"/>
1064     </condition>
1065
1066     <condition id="CM33_ARMCC">
1067       <description>Cortex-M33 processor based device for the Arm Compiler</description>
1068       <require condition="CM33"/>
1069       <require Tcompiler="ARMCC"/>
1070     </condition>
1071     <condition id="CM33_LE_ARMCC">
1072       <description>Cortex-M33 processor based device in little endian mode for the Arm Compiler</description>
1073       <require condition="CM33_ARMCC"/>
1074       <require Dendian="Little-endian"/>
1075     </condition>
1076     <condition id="CM33_BE_ARMCC">
1077       <description>Cortex-M33 processor based device in big endian mode for the Arm Compiler</description>
1078       <require condition="CM33_ARMCC"/>
1079       <require Dendian="Big-endian"/>
1080     </condition>
1081
1082     <condition id="CM33_FP_ARMCC">
1083       <description>Cortex-M33 processor based device using Floating Point Unit for the Arm Compiler</description>
1084       <require condition="CM33_FP"/>
1085       <require Tcompiler="ARMCC"/>
1086     </condition>
1087     <condition id="CM33_FP_LE_ARMCC">
1088       <description>Cortex-M33 processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
1089       <require condition="CM33_FP_ARMCC"/>
1090       <require Dendian="Little-endian"/>
1091     </condition>
1092     <condition id="CM33_FP_BE_ARMCC">
1093       <description>Cortex-M33 processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
1094       <require condition="CM33_FP_ARMCC"/>
1095       <require Dendian="Big-endian"/>
1096     </condition>
1097
1098     <condition id="CM33_NODSP_NOFPU_ARMCC">
1099       <description>Cortex-M33 processor, no DSP, no FPU, Arm Compiler</description>
1100       <require condition="CM33_NODSP_NOFPU"/>
1101       <require Tcompiler="ARMCC"/>
1102     </condition>
1103     <condition id="CM33_DSP_NOFPU_ARMCC">
1104       <description>Cortex-M33 processor, DSP, no FPU, Arm Compiler</description>
1105       <require condition="CM33_DSP_NOFPU"/>
1106       <require Tcompiler="ARMCC"/>
1107     </condition>
1108     <condition id="CM33_NODSP_SP_ARMCC">
1109       <description>Cortex-M33 processor, no DSP, SP FPU, Arm Compiler</description>
1110       <require condition="CM33_NODSP_SP"/>
1111       <require Tcompiler="ARMCC"/>
1112     </condition>
1113     <condition id="CM33_DSP_SP_ARMCC">
1114       <description>Cortex-M33 processor, DSP, SP FPU, Arm Compiler</description>
1115       <require condition="CM33_DSP_SP"/>
1116       <require Tcompiler="ARMCC"/>
1117     </condition>
1118     <condition id="CM33_NODSP_NOFPU_LE_ARMCC">
1119       <description>Cortex-M33 processor, little endian, no DSP, no FPU, Arm Compiler</description>
1120       <require condition="CM33_NODSP_NOFPU_ARMCC"/>
1121       <require Dendian="Little-endian"/>
1122     </condition>
1123     <condition id="CM33_DSP_NOFPU_LE_ARMCC">
1124       <description>Cortex-M33 processor, little endian, DSP, no FPU, Arm Compiler</description>
1125       <require condition="CM33_DSP_NOFPU_ARMCC"/>
1126       <require Dendian="Little-endian"/>
1127     </condition>
1128     <condition id="CM33_NODSP_SP_LE_ARMCC">
1129       <description>Cortex-M33 processor, little endian, no DSP, SP FPU, Arm Compiler</description>
1130       <require condition="CM33_NODSP_SP_ARMCC"/>
1131       <require Dendian="Little-endian"/>
1132     </condition>
1133     <condition id="CM33_DSP_SP_LE_ARMCC">
1134       <description>Cortex-M33 processor, little endian, DSP, SP FPU, Arm Compiler</description>
1135       <require condition="CM33_DSP_SP_ARMCC"/>
1136       <require Dendian="Little-endian"/>
1137     </condition>
1138
1139     <condition id="ARMv8MBL_ARMCC">
1140       <description>Armv8-M Baseline processor based device for the Arm Compiler</description>
1141       <require condition="ARMv8MBL"/>
1142       <require Tcompiler="ARMCC"/>
1143     </condition>
1144     <condition id="ARMv8MBL_LE_ARMCC">
1145       <description>Armv8-M Baseline processor based device in little endian mode for the Arm Compiler</description>
1146       <require condition="ARMv8MBL_ARMCC"/>
1147       <require Dendian="Little-endian"/>
1148     </condition>
1149     <condition id="ARMv8MBL_BE_ARMCC">
1150       <description>Armv8-M Baseline processor based device in big endian mode for the Arm Compiler</description>
1151       <require condition="ARMv8MBL_ARMCC"/>
1152       <require Dendian="Big-endian"/>
1153     </condition>
1154
1155     <condition id="ARMv8MML_ARMCC">
1156       <description>Armv8-M Mainline processor based device for the Arm Compiler</description>
1157       <require condition="ARMv8MML"/>
1158       <require Tcompiler="ARMCC"/>
1159     </condition>
1160     <condition id="ARMv8MML_LE_ARMCC">
1161       <description>Armv8-M Mainline processor based device in little endian mode for the Arm Compiler</description>
1162       <require condition="ARMv8MML_ARMCC"/>
1163       <require Dendian="Little-endian"/>
1164     </condition>
1165     <condition id="ARMv8MML_BE_ARMCC">
1166       <description>Armv8-M Mainline processor based device in big endian mode for the Arm Compiler</description>
1167       <require condition="ARMv8MML_ARMCC"/>
1168       <require Dendian="Big-endian"/>
1169     </condition>
1170
1171     <condition id="ARMv8MML_FP_ARMCC">
1172       <description>Armv8-M Mainline processor based device using Floating Point Unit for the Arm Compiler</description>
1173       <require condition="ARMv8MML_FP"/>
1174       <require Tcompiler="ARMCC"/>
1175     </condition>
1176     <condition id="ARMv8MML_FP_LE_ARMCC">
1177       <description>Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
1178       <require condition="ARMv8MML_FP_ARMCC"/>
1179       <require Dendian="Little-endian"/>
1180     </condition>
1181     <condition id="ARMv8MML_FP_BE_ARMCC">
1182       <description>Armv8-M Mainline processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
1183       <require condition="ARMv8MML_FP_ARMCC"/>
1184       <require Dendian="Big-endian"/>
1185     </condition>
1186
1187     <condition id="ARMv8MML_NODSP_NOFPU_ARMCC">
1188       <description>Armv8-M Mainline, no DSP, no FPU, Arm Compiler</description>
1189       <require condition="ARMv8MML_NODSP_NOFPU"/>
1190       <require Tcompiler="ARMCC"/>
1191     </condition>
1192     <condition id="ARMv8MML_DSP_NOFPU_ARMCC">
1193       <description>Armv8-M Mainline, DSP, no FPU, Arm Compiler</description>
1194       <require condition="ARMv8MML_DSP_NOFPU"/>
1195       <require Tcompiler="ARMCC"/>
1196     </condition>
1197     <condition id="ARMv8MML_NODSP_SP_ARMCC">
1198       <description>Armv8-M Mainline, no DSP, SP FPU, Arm Compiler</description>
1199       <require condition="ARMv8MML_NODSP_SP"/>
1200       <require Tcompiler="ARMCC"/>
1201     </condition>
1202     <condition id="ARMv8MML_DSP_SP_ARMCC">
1203       <description>Armv8-M Mainline, DSP, SP FPU, Arm Compiler</description>
1204       <require condition="ARMv8MML_DSP_SP"/>
1205       <require Tcompiler="ARMCC"/>
1206     </condition>
1207     <condition id="ARMv8MML_NODSP_NOFPU_LE_ARMCC">
1208       <description>Armv8-M Mainline, little endian, no DSP, no FPU, Arm Compiler</description>
1209       <require condition="ARMv8MML_NODSP_NOFPU_ARMCC"/>
1210       <require Dendian="Little-endian"/>
1211     </condition>
1212     <condition id="ARMv8MML_DSP_NOFPU_LE_ARMCC">
1213       <description>Armv8-M Mainline, little endian, DSP, no FPU, Arm Compiler</description>
1214       <require condition="ARMv8MML_DSP_NOFPU_ARMCC"/>
1215       <require Dendian="Little-endian"/>
1216     </condition>
1217     <condition id="ARMv8MML_NODSP_SP_LE_ARMCC">
1218       <description>Armv8-M Mainline, little endian, no DSP, SP FPU, Arm Compiler</description>
1219       <require condition="ARMv8MML_NODSP_SP_ARMCC"/>
1220       <require Dendian="Little-endian"/>
1221     </condition>
1222     <condition id="ARMv8MML_DSP_SP_LE_ARMCC">
1223       <description>Armv8-M Mainline, little endian, DSP, SP FPU, Arm Compiler</description>
1224       <require condition="ARMv8MML_DSP_SP_ARMCC"/>
1225       <require Dendian="Little-endian"/>
1226     </condition>
1227
1228     <!-- GCC compiler -->
1229     <condition id="CA_GCC">
1230       <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the GCC Compiler</description>
1231       <require condition="ARMv7-A Device"/>
1232       <require Tcompiler="GCC"/>
1233     </condition>
1234
1235     <condition id="CM0_GCC">
1236       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device for the GCC Compiler</description>
1237       <require condition="CM0"/>
1238       <require Tcompiler="GCC"/>
1239     </condition>
1240     <condition id="CM0_LE_GCC">
1241       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the GCC Compiler</description>
1242       <require condition="CM0_GCC"/>
1243       <require Dendian="Little-endian"/>
1244     </condition>
1245     <condition id="CM0_BE_GCC">
1246       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the GCC Compiler</description>
1247       <require condition="CM0_GCC"/>
1248       <require Dendian="Big-endian"/>
1249     </condition>
1250
1251     <condition id="CM3_GCC">
1252       <description>Cortex-M3 or SC300 processor based device for the GCC Compiler</description>
1253       <require condition="CM3"/>
1254       <require Tcompiler="GCC"/>
1255     </condition>
1256     <condition id="CM3_LE_GCC">
1257       <description>Cortex-M3 or SC300 processor based device in little endian mode for the GCC Compiler</description>
1258       <require condition="CM3_GCC"/>
1259       <require Dendian="Little-endian"/>
1260     </condition>
1261     <condition id="CM3_BE_GCC">
1262       <description>Cortex-M3 or SC300 processor based device in big endian mode for the GCC Compiler</description>
1263       <require condition="CM3_GCC"/>
1264       <require Dendian="Big-endian"/>
1265     </condition>
1266
1267     <condition id="CM4_GCC">
1268       <description>Cortex-M4 processor based device for the GCC Compiler</description>
1269       <require condition="CM4"/>
1270       <require Tcompiler="GCC"/>
1271     </condition>
1272     <condition id="CM4_LE_GCC">
1273       <description>Cortex-M4 processor based device in little endian mode for the GCC Compiler</description>
1274       <require condition="CM4_GCC"/>
1275       <require Dendian="Little-endian"/>
1276     </condition>
1277     <condition id="CM4_BE_GCC">
1278       <description>Cortex-M4 processor based device in big endian mode for the GCC Compiler</description>
1279       <require condition="CM4_GCC"/>
1280       <require Dendian="Big-endian"/>
1281     </condition>
1282
1283     <condition id="CM4_FP_GCC">
1284       <description>Cortex-M4 processor based device using Floating Point Unit for the GCC Compiler</description>
1285       <require condition="CM4_FP"/>
1286       <require Tcompiler="GCC"/>
1287     </condition>
1288     <condition id="CM4_FP_LE_GCC">
1289       <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
1290       <require condition="CM4_FP_GCC"/>
1291       <require Dendian="Little-endian"/>
1292     </condition>
1293     <condition id="CM4_FP_BE_GCC">
1294       <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
1295       <require condition="CM4_FP_GCC"/>
1296       <require Dendian="Big-endian"/>
1297     </condition>
1298
1299     <condition id="CM7_GCC">
1300       <description>Cortex-M7 processor based device for the GCC Compiler</description>
1301       <require condition="CM7"/>
1302       <require Tcompiler="GCC"/>
1303     </condition>
1304     <condition id="CM7_LE_GCC">
1305       <description>Cortex-M7 processor based device in little endian mode for the GCC Compiler</description>
1306       <require condition="CM7_GCC"/>
1307       <require Dendian="Little-endian"/>
1308     </condition>
1309     <condition id="CM7_BE_GCC">
1310       <description>Cortex-M7 processor based device in big endian mode for the GCC Compiler</description>
1311       <require condition="CM7_GCC"/>
1312       <require Dendian="Big-endian"/>
1313     </condition>
1314
1315     <condition id="CM7_FP_GCC">
1316       <description>Cortex-M7 processor based device using Floating Point Unit for the GCC Compiler</description>
1317       <require condition="CM7_FP"/>
1318       <require Tcompiler="GCC"/>
1319     </condition>
1320     <condition id="CM7_FP_LE_GCC">
1321       <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
1322       <require condition="CM7_FP_GCC"/>
1323       <require Dendian="Little-endian"/>
1324     </condition>
1325     <condition id="CM7_FP_BE_GCC">
1326       <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
1327       <require condition="CM7_FP_GCC"/>
1328       <require Dendian="Big-endian"/>
1329     </condition>
1330
1331     <condition id="CM7_SP_GCC">
1332       <description>Cortex-M7 processor based device using Floating Point Unit (SP) for the GCC Compiler</description>
1333       <require condition="CM7_SP"/>
1334       <require Tcompiler="GCC"/>
1335     </condition>
1336     <condition id="CM7_SP_LE_GCC">
1337       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the GCC Compiler</description>
1338       <require condition="CM7_SP_GCC"/>
1339       <require Dendian="Little-endian"/>
1340     </condition>
1341     <condition id="CM7_SP_BE_GCC">
1342       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the GCC Compiler</description>
1343       <require condition="CM7_SP_GCC"/>
1344       <require Dendian="Big-endian"/>
1345     </condition>
1346
1347     <condition id="CM7_DP_GCC">
1348       <description>Cortex-M7 processor based device using Floating Point Unit (DP) for the GCC Compiler</description>
1349       <require condition="CM7_DP"/>
1350       <require Tcompiler="GCC"/>
1351     </condition>
1352     <condition id="CM7_DP_LE_GCC">
1353       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the GCC Compiler</description>
1354       <require condition="CM7_DP_GCC"/>
1355       <require Dendian="Little-endian"/>
1356     </condition>
1357     <condition id="CM7_DP_BE_GCC">
1358       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the GCC Compiler</description>
1359       <require condition="CM7_DP_GCC"/>
1360       <require Dendian="Big-endian"/>
1361     </condition>
1362
1363     <condition id="CM23_GCC">
1364       <description>Cortex-M23 processor based device for the GCC Compiler</description>
1365       <require condition="CM23"/>
1366       <require Tcompiler="GCC"/>
1367     </condition>
1368     <condition id="CM23_LE_GCC">
1369       <description>Cortex-M23 processor based device in little endian mode for the GCC Compiler</description>
1370       <require condition="CM23_GCC"/>
1371       <require Dendian="Little-endian"/>
1372     </condition>
1373     <condition id="CM23_BE_GCC">
1374       <description>Cortex-M23 processor based device in big endian mode for the GCC Compiler</description>
1375       <require condition="CM23_GCC"/>
1376       <require Dendian="Big-endian"/>
1377     </condition>
1378
1379     <condition id="CM33_GCC">
1380       <description>Cortex-M33 processor based device for the GCC Compiler</description>
1381       <require condition="CM33"/>
1382       <require Tcompiler="GCC"/>
1383     </condition>
1384     <condition id="CM33_LE_GCC">
1385       <description>Cortex-M33 processor based device in little endian mode for the GCC Compiler</description>
1386       <require condition="CM33_GCC"/>
1387       <require Dendian="Little-endian"/>
1388     </condition>
1389     <condition id="CM33_BE_GCC">
1390       <description>Cortex-M33 processor based device in big endian mode for the GCC Compiler</description>
1391       <require condition="CM33_GCC"/>
1392       <require Dendian="Big-endian"/>
1393     </condition>
1394
1395     <condition id="CM33_FP_GCC">
1396       <description>Cortex-M33 processor based device using Floating Point Unit for the GCC Compiler</description>
1397       <require condition="CM33_FP"/>
1398       <require Tcompiler="GCC"/>
1399     </condition>
1400     <condition id="CM33_FP_LE_GCC">
1401       <description>Cortex-M33 processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
1402       <require condition="CM33_FP_GCC"/>
1403       <require Dendian="Little-endian"/>
1404     </condition>
1405     <condition id="CM33_FP_BE_GCC">
1406       <description>Cortex-M33 processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
1407       <require condition="CM33_FP_GCC"/>
1408       <require Dendian="Big-endian"/>
1409     </condition>
1410
1411     <condition id="CM33_NODSP_NOFPU_GCC">
1412       <description>CM33, no DSP, no FPU, GCC Compiler</description>
1413       <require condition="CM33_NODSP_NOFPU"/>
1414       <require Tcompiler="GCC"/>
1415     </condition>
1416     <condition id="CM33_DSP_NOFPU_GCC">
1417       <description>CM33, DSP, no FPU, GCC Compiler</description>
1418       <require condition="CM33_DSP_NOFPU"/>
1419       <require Tcompiler="GCC"/>
1420     </condition>
1421     <condition id="CM33_NODSP_SP_GCC">
1422       <description>CM33, no DSP, SP FPU, GCC Compiler</description>
1423       <require condition="CM33_NODSP_SP"/>
1424       <require Tcompiler="GCC"/>
1425     </condition>
1426     <condition id="CM33_DSP_SP_GCC">
1427       <description>CM33, DSP, SP FPU, GCC Compiler</description>
1428       <require condition="CM33_DSP_SP"/>
1429       <require Tcompiler="GCC"/>
1430     </condition>
1431     <condition id="CM33_NODSP_NOFPU_LE_GCC">
1432       <description>CM33, little endian, no DSP, no FPU, GCC Compiler</description>
1433       <require condition="CM33_NODSP_NOFPU_GCC"/>
1434       <require Dendian="Little-endian"/>
1435     </condition>
1436     <condition id="CM33_DSP_NOFPU_LE_GCC">
1437       <description>CM33, little endian, DSP, no FPU, GCC Compiler</description>
1438       <require condition="CM33_DSP_NOFPU_GCC"/>
1439       <require Dendian="Little-endian"/>
1440     </condition>
1441     <condition id="CM33_NODSP_SP_LE_GCC">
1442       <description>CM33, little endian, no DSP, SP FPU, GCC Compiler</description>
1443       <require condition="CM33_NODSP_SP_GCC"/>
1444       <require Dendian="Little-endian"/>
1445     </condition>
1446     <condition id="CM33_DSP_SP_LE_GCC">
1447       <description>CM33, little endian, DSP, SP FPU, GCC Compiler</description>
1448       <require condition="CM33_DSP_SP_GCC"/>
1449       <require Dendian="Little-endian"/>
1450     </condition>
1451
1452     <condition id="ARMv8MBL_GCC">
1453       <description>Armv8-M Baseline processor based device for the GCC Compiler</description>
1454       <require condition="ARMv8MBL"/>
1455       <require Tcompiler="GCC"/>
1456     </condition>
1457     <condition id="ARMv8MBL_LE_GCC">
1458       <description>Armv8-M Baseline processor based device in little endian mode for the GCC Compiler</description>
1459       <require condition="ARMv8MBL_GCC"/>
1460       <require Dendian="Little-endian"/>
1461     </condition>
1462     <condition id="ARMv8MBL_BE_GCC">
1463       <description>Armv8-M Baseline processor based device in big endian mode for the GCC Compiler</description>
1464       <require condition="ARMv8MBL_GCC"/>
1465       <require Dendian="Big-endian"/>
1466     </condition>
1467
1468     <condition id="ARMv8MML_GCC">
1469       <description>Armv8-M Mainline processor based device for the GCC Compiler</description>
1470       <require condition="ARMv8MML"/>
1471       <require Tcompiler="GCC"/>
1472     </condition>
1473     <condition id="ARMv8MML_LE_GCC">
1474       <description>Armv8-M Mainline processor based device in little endian mode for the GCC Compiler</description>
1475       <require condition="ARMv8MML_GCC"/>
1476       <require Dendian="Little-endian"/>
1477     </condition>
1478     <condition id="ARMv8MML_BE_GCC">
1479       <description>Armv8-M Mainline processor based device in big endian mode for the GCC Compiler</description>
1480       <require condition="ARMv8MML_GCC"/>
1481       <require Dendian="Big-endian"/>
1482     </condition>
1483
1484     <condition id="ARMv8MML_FP_GCC">
1485       <description>Armv8-M Mainline processor based device using Floating Point Unit for the GCC Compiler</description>
1486       <require condition="ARMv8MML_FP"/>
1487       <require Tcompiler="GCC"/>
1488     </condition>
1489     <condition id="ARMv8MML_FP_LE_GCC">
1490       <description>Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
1491       <require condition="ARMv8MML_FP_GCC"/>
1492       <require Dendian="Little-endian"/>
1493     </condition>
1494     <condition id="ARMv8MML_FP_BE_GCC">
1495       <description>Armv8-M Mainline processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
1496       <require condition="ARMv8MML_FP_GCC"/>
1497       <require Dendian="Big-endian"/>
1498     </condition>
1499
1500     <condition id="ARMv8MML_NODSP_NOFPU_GCC">
1501       <description>Armv8-M Mainline, no DSP, no FPU, GCC Compiler</description>
1502       <require condition="ARMv8MML_NODSP_NOFPU"/>
1503       <require Tcompiler="GCC"/>
1504     </condition>
1505     <condition id="ARMv8MML_DSP_NOFPU_GCC">
1506       <description>Armv8-M Mainline, DSP, no FPU, GCC Compiler</description>
1507       <require condition="ARMv8MML_DSP_NOFPU"/>
1508       <require Tcompiler="GCC"/>
1509     </condition>
1510     <condition id="ARMv8MML_NODSP_SP_GCC">
1511       <description>Armv8-M Mainline, no DSP, SP FPU, GCC Compiler</description>
1512       <require condition="ARMv8MML_NODSP_SP"/>
1513       <require Tcompiler="GCC"/>
1514     </condition>
1515     <condition id="ARMv8MML_DSP_SP_GCC">
1516       <description>Armv8-M Mainline, DSP, SP FPU, GCC Compiler</description>
1517       <require condition="ARMv8MML_DSP_SP"/>
1518       <require Tcompiler="GCC"/>
1519     </condition>
1520     <condition id="ARMv8MML_NODSP_NOFPU_LE_GCC">
1521       <description>Armv8-M Mainline, little endian, no DSP, no FPU, GCC Compiler</description>
1522       <require condition="ARMv8MML_NODSP_NOFPU_GCC"/>
1523       <require Dendian="Little-endian"/>
1524     </condition>
1525     <condition id="ARMv8MML_DSP_NOFPU_LE_GCC">
1526       <description>Armv8-M Mainline, little endian, DSP, no FPU, GCC Compiler</description>
1527       <require condition="ARMv8MML_DSP_NOFPU_GCC"/>
1528       <require Dendian="Little-endian"/>
1529     </condition>
1530     <condition id="ARMv8MML_NODSP_SP_LE_GCC">
1531       <description>Armv8-M Mainline, little endian, no DSP, SP FPU, GCC Compiler</description>
1532       <require condition="ARMv8MML_NODSP_SP_GCC"/>
1533       <require Dendian="Little-endian"/>
1534     </condition>
1535     <condition id="ARMv8MML_DSP_SP_LE_GCC">
1536       <description>Armv8-M Mainline, little endian, DSP, SP FPU, GCC Compiler</description>
1537       <require condition="ARMv8MML_DSP_SP_GCC"/>
1538       <require Dendian="Little-endian"/>
1539     </condition>
1540
1541     <!-- IAR compiler -->
1542     <condition id="CA_IAR">
1543       <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the IAR Compiler</description>
1544       <require condition="ARMv7-A Device"/>
1545       <require Tcompiler="IAR"/>
1546     </condition>
1547
1548     <condition id="CM0_IAR">
1549       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device for the IAR Compiler</description>
1550       <require condition="CM0"/>
1551       <require Tcompiler="IAR"/>
1552     </condition>
1553     <condition id="CM0_LE_IAR">
1554       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the IAR Compiler</description>
1555       <require condition="CM0_IAR"/>
1556       <require Dendian="Little-endian"/>
1557     </condition>
1558     <condition id="CM0_BE_IAR">
1559       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the IAR Compiler</description>
1560       <require condition="CM0_IAR"/>
1561       <require Dendian="Big-endian"/>
1562     </condition>
1563
1564     <condition id="CM3_IAR">
1565       <description>Cortex-M3 or SC300 processor based device for the IAR Compiler</description>
1566       <require condition="CM3"/>
1567       <require Tcompiler="IAR"/>
1568     </condition>
1569     <condition id="CM3_LE_IAR">
1570       <description>Cortex-M3 or SC300 processor based device in little endian mode for the IAR Compiler</description>
1571       <require condition="CM3_IAR"/>
1572       <require Dendian="Little-endian"/>
1573     </condition>
1574     <condition id="CM3_BE_IAR">
1575       <description>Cortex-M3 or SC300 processor based device in big endian mode for the IAR Compiler</description>
1576       <require condition="CM3_IAR"/>
1577       <require Dendian="Big-endian"/>
1578     </condition>
1579
1580     <condition id="CM4_IAR">
1581       <description>Cortex-M4 processor based device for the IAR Compiler</description>
1582       <require condition="CM4"/>
1583       <require Tcompiler="IAR"/>
1584     </condition>
1585     <condition id="CM4_LE_IAR">
1586       <description>Cortex-M4 processor based device in little endian mode for the IAR Compiler</description>
1587       <require condition="CM4_IAR"/>
1588       <require Dendian="Little-endian"/>
1589     </condition>
1590     <condition id="CM4_BE_IAR">
1591       <description>Cortex-M4 processor based device in big endian mode for the IAR Compiler</description>
1592       <require condition="CM4_IAR"/>
1593       <require Dendian="Big-endian"/>
1594     </condition>
1595
1596     <condition id="CM4_FP_IAR">
1597       <description>Cortex-M4 processor based device using Floating Point Unit for the IAR Compiler</description>
1598       <require condition="CM4_FP"/>
1599       <require Tcompiler="IAR"/>
1600     </condition>
1601     <condition id="CM4_FP_LE_IAR">
1602       <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
1603       <require condition="CM4_FP_IAR"/>
1604       <require Dendian="Little-endian"/>
1605     </condition>
1606     <condition id="CM4_FP_BE_IAR">
1607       <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
1608       <require condition="CM4_FP_IAR"/>
1609       <require Dendian="Big-endian"/>
1610     </condition>
1611
1612     <condition id="CM7_IAR">
1613       <description>Cortex-M7 processor based device for the IAR Compiler</description>
1614       <require condition="CM7"/>
1615       <require Tcompiler="IAR"/>
1616     </condition>
1617     <condition id="CM7_LE_IAR">
1618       <description>Cortex-M7 processor based device in little endian mode for the IAR Compiler</description>
1619       <require condition="CM7_IAR"/>
1620       <require Dendian="Little-endian"/>
1621     </condition>
1622     <condition id="CM7_BE_IAR">
1623       <description>Cortex-M7 processor based device in big endian mode for the IAR Compiler</description>
1624       <require condition="CM7_IAR"/>
1625       <require Dendian="Big-endian"/>
1626     </condition>
1627
1628     <condition id="CM7_FP_IAR">
1629       <description>Cortex-M7 processor based device using Floating Point Unit for the IAR Compiler</description>
1630       <require condition="CM7_FP"/>
1631       <require Tcompiler="IAR"/>
1632     </condition>
1633     <condition id="CM7_FP_LE_IAR">
1634       <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
1635       <require condition="CM7_FP_IAR"/>
1636       <require Dendian="Little-endian"/>
1637     </condition>
1638     <condition id="CM7_FP_BE_IAR">
1639       <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
1640       <require condition="CM7_FP_IAR"/>
1641       <require Dendian="Big-endian"/>
1642     </condition>
1643
1644     <condition id="CM7_SP_IAR">
1645       <description>Cortex-M7 processor based device using Floating Point Unit (SP) for the IAR Compiler</description>
1646       <require condition="CM7_SP"/>
1647       <require Tcompiler="IAR"/>
1648     </condition>
1649     <condition id="CM7_SP_LE_IAR">
1650       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the IAR Compiler</description>
1651       <require condition="CM7_SP_IAR"/>
1652       <require Dendian="Little-endian"/>
1653     </condition>
1654     <condition id="CM7_SP_BE_IAR">
1655       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the IAR Compiler</description>
1656       <require condition="CM7_SP_IAR"/>
1657       <require Dendian="Big-endian"/>
1658     </condition>
1659
1660     <condition id="CM7_DP_IAR">
1661       <description>Cortex-M7 processor based device using Floating Point Unit (DP) for the IAR Compiler</description>
1662       <require condition="CM7_DP"/>
1663       <require Tcompiler="IAR"/>
1664     </condition>
1665     <condition id="CM7_DP_LE_IAR">
1666       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the IAR Compiler</description>
1667       <require condition="CM7_DP_IAR"/>
1668       <require Dendian="Little-endian"/>
1669     </condition>
1670     <condition id="CM7_DP_BE_IAR">
1671       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the IAR Compiler</description>
1672       <require condition="CM7_DP_IAR"/>
1673       <require Dendian="Big-endian"/>
1674     </condition>
1675
1676     <condition id="CM23_IAR">
1677       <description>Cortex-M23 processor based device for the IAR Compiler</description>
1678       <require condition="CM23"/>
1679       <require Tcompiler="IAR"/>
1680     </condition>
1681     <condition id="CM23_LE_IAR">
1682       <description>Cortex-M23 processor based device in little endian mode for the IAR Compiler</description>
1683       <require condition="CM23_IAR"/>
1684       <require Dendian="Little-endian"/>
1685     </condition>
1686     <condition id="CM23_BE_IAR">
1687       <description>Cortex-M23 processor based device in big endian mode for the IAR Compiler</description>
1688       <require condition="CM23_IAR"/>
1689       <require Dendian="Big-endian"/>
1690     </condition>
1691
1692     <condition id="CM33_IAR">
1693       <description>Cortex-M33 processor based device for the IAR Compiler</description>
1694       <require condition="CM33"/>
1695       <require Tcompiler="IAR"/>
1696     </condition>
1697     <condition id="CM33_LE_IAR">
1698       <description>Cortex-M33 processor based device in little endian mode for the IAR Compiler</description>
1699       <require condition="CM33_IAR"/>
1700       <require Dendian="Little-endian"/>
1701     </condition>
1702     <condition id="CM33_BE_IAR">
1703       <description>Cortex-M33 processor based device in big endian mode for the IAR Compiler</description>
1704       <require condition="CM33_IAR"/>
1705       <require Dendian="Big-endian"/>
1706     </condition>
1707
1708     <condition id="CM33_FP_IAR">
1709       <description>Cortex-M33 processor based device using Floating Point Unit for the IAR Compiler</description>
1710       <require condition="CM33_FP"/>
1711       <require Tcompiler="IAR"/>
1712     </condition>
1713     <condition id="CM33_FP_LE_IAR">
1714       <description>Cortex-M33 processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
1715       <require condition="CM33_FP_IAR"/>
1716       <require Dendian="Little-endian"/>
1717     </condition>
1718     <condition id="CM33_FP_BE_IAR">
1719       <description>Cortex-M33 processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
1720       <require condition="CM33_FP_IAR"/>
1721       <require Dendian="Big-endian"/>
1722     </condition>
1723
1724     <condition id="CM33_NODSP_NOFPU_IAR">
1725       <description>CM33, no DSP, no FPU, IAR Compiler</description>
1726       <require condition="CM33_NODSP_NOFPU"/>
1727       <require Tcompiler="IAR"/>
1728     </condition>
1729     <condition id="CM33_DSP_NOFPU_IAR">
1730       <description>CM33, DSP, no FPU, IAR Compiler</description>
1731       <require condition="CM33_DSP_NOFPU"/>
1732       <require Tcompiler="IAR"/>
1733     </condition>
1734     <condition id="CM33_NODSP_SP_IAR">
1735       <description>CM33, no DSP, SP FPU, IAR Compiler</description>
1736       <require condition="CM33_NODSP_SP"/>
1737       <require Tcompiler="IAR"/>
1738     </condition>
1739     <condition id="CM33_DSP_SP_IAR">
1740       <description>CM33, DSP, SP FPU, IAR Compiler</description>
1741       <require condition="CM33_DSP_SP"/>
1742       <require Tcompiler="IAR"/>
1743     </condition>
1744     <condition id="CM33_NODSP_NOFPU_LE_IAR">
1745       <description>CM33, little endian, no DSP, no FPU, IAR Compiler</description>
1746       <require condition="CM33_NODSP_NOFPU_IAR"/>
1747       <require Dendian="Little-endian"/>
1748     </condition>
1749     <condition id="CM33_DSP_NOFPU_LE_IAR">
1750       <description>CM33, little endian, DSP, no FPU, IAR Compiler</description>
1751       <require condition="CM33_DSP_NOFPU_IAR"/>
1752       <require Dendian="Little-endian"/>
1753     </condition>
1754     <condition id="CM33_NODSP_SP_LE_IAR">
1755       <description>CM33, little endian, no DSP, SP FPU, IAR Compiler</description>
1756       <require condition="CM33_NODSP_SP_IAR"/>
1757       <require Dendian="Little-endian"/>
1758     </condition>
1759     <condition id="CM33_DSP_SP_LE_IAR">
1760       <description>CM33, little endian, DSP, SP FPU, IAR Compiler</description>
1761       <require condition="CM33_DSP_SP_IAR"/>
1762       <require Dendian="Little-endian"/>
1763     </condition>
1764
1765     <condition id="ARMv8MBL_IAR">
1766       <description>Armv8-M Baseline processor based device for the IAR Compiler</description>
1767       <require condition="ARMv8MBL"/>
1768       <require Tcompiler="IAR"/>
1769     </condition>
1770     <condition id="ARMv8MBL_LE_IAR">
1771       <description>Armv8-M Baseline processor based device in little endian mode for the IAR Compiler</description>
1772       <require condition="ARMv8MBL_IAR"/>
1773       <require Dendian="Little-endian"/>
1774     </condition>
1775     <condition id="ARMv8MBL_BE_IAR">
1776       <description>Armv8-M Baseline processor based device in big endian mode for the IAR Compiler</description>
1777       <require condition="ARMv8MBL_IAR"/>
1778       <require Dendian="Big-endian"/>
1779     </condition>
1780
1781     <condition id="ARMv8MML_IAR">
1782       <description>Armv8-M Mainline processor based device for the IAR Compiler</description>
1783       <require condition="ARMv8MML"/>
1784       <require Tcompiler="IAR"/>
1785     </condition>
1786     <condition id="ARMv8MML_LE_IAR">
1787       <description>Armv8-M Mainline processor based device in little endian mode for the IAR Compiler</description>
1788       <require condition="ARMv8MML_IAR"/>
1789       <require Dendian="Little-endian"/>
1790     </condition>
1791     <condition id="ARMv8MML_BE_IAR">
1792       <description>Armv8-M Mainline processor based device in big endian mode for the IAR Compiler</description>
1793       <require condition="ARMv8MML_IAR"/>
1794       <require Dendian="Big-endian"/>
1795     </condition>
1796
1797     <condition id="ARMv8MML_FP_IAR">
1798       <description>Armv8-M Mainline processor based device using Floating Point Unit for the IAR Compiler</description>
1799       <require condition="ARMv8MML_FP"/>
1800       <require Tcompiler="IAR"/>
1801     </condition>
1802     <condition id="ARMv8MML_FP_LE_IAR">
1803       <description>Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
1804       <require condition="ARMv8MML_FP_IAR"/>
1805       <require Dendian="Little-endian"/>
1806     </condition>
1807     <condition id="ARMv8MML_FP_BE_IAR">
1808       <description>Armv8-M Mainline processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
1809       <require condition="ARMv8MML_FP_IAR"/>
1810       <require Dendian="Big-endian"/>
1811     </condition>
1812
1813     <condition id="ARMv8MML_NODSP_NOFPU_IAR">
1814       <description>Armv8-M Mainline, no DSP, no FPU, IAR Compiler</description>
1815       <require condition="ARMv8MML_NODSP_NOFPU"/>
1816       <require Tcompiler="IAR"/>
1817     </condition>
1818     <condition id="ARMv8MML_DSP_NOFPU_IAR">
1819       <description>Armv8-M Mainline, DSP, no FPU, IAR Compiler</description>
1820       <require condition="ARMv8MML_DSP_NOFPU"/>
1821       <require Tcompiler="IAR"/>
1822     </condition>
1823     <condition id="ARMv8MML_NODSP_SP_IAR">
1824       <description>Armv8-M Mainline, no DSP, SP FPU, IAR Compiler</description>
1825       <require condition="ARMv8MML_NODSP_SP"/>
1826       <require Tcompiler="IAR"/>
1827     </condition>
1828     <condition id="ARMv8MML_DSP_SP_IAR">
1829       <description>Armv8-M Mainline, DSP, SP FPU, IAR Compiler</description>
1830       <require condition="ARMv8MML_DSP_SP"/>
1831       <require Tcompiler="IAR"/>
1832     </condition>
1833     <condition id="ARMv8MML_NODSP_NOFPU_LE_IAR">
1834       <description>Armv8-M Mainline, little endian, no DSP, no FPU, IAR Compiler</description>
1835       <require condition="ARMv8MML_NODSP_NOFPU_IAR"/>
1836       <require Dendian="Little-endian"/>
1837     </condition>
1838     <condition id="ARMv8MML_DSP_NOFPU_LE_IAR">
1839       <description>Armv8-M Mainline, little endian, DSP, no FPU, IAR Compiler</description>
1840       <require condition="ARMv8MML_DSP_NOFPU_IAR"/>
1841       <require Dendian="Little-endian"/>
1842     </condition>
1843     <condition id="ARMv8MML_NODSP_SP_LE_IAR">
1844       <description>Armv8-M Mainline, little endian, no DSP, SP FPU, IAR Compiler</description>
1845       <require condition="ARMv8MML_NODSP_SP_IAR"/>
1846       <require Dendian="Little-endian"/>
1847     </condition>
1848     <condition id="ARMv8MML_DSP_SP_LE_IAR">
1849       <description>Armv8-M Mainline, little endian, DSP, SP FPU, IAR Compiler</description>
1850       <require condition="ARMv8MML_DSP_SP_IAR"/>
1851       <require Dendian="Little-endian"/>
1852     </condition>
1853
1854     <!-- conditions selecting single devices and CMSIS Core -->
1855     <!-- used for component startup, GCC version is used for C-Startup -->
1856     <condition id="ARMCM0 CMSIS">
1857       <description>Generic Arm Cortex-M0 device startup and depends on CMSIS Core</description>
1858       <require Dvendor="ARM:82" Dname="ARMCM0"/>
1859       <require Cclass="CMSIS" Cgroup="CORE"/>
1860     </condition>
1861     <condition id="ARMCM0 CMSIS GCC">
1862       <description>Generic ARM Cortex-M0 device startup and depends on CMSIS Core requiring GCC</description>
1863       <require condition="ARMCM0 CMSIS"/>
1864       <require condition="GCC"/>
1865     </condition>
1866
1867     <condition id="ARMCM0+ CMSIS">
1868       <description>Generic Arm Cortex-M0+ device startup and depends on CMSIS Core</description>
1869       <require Dvendor="ARM:82" Dname="ARMCM0P*"/>
1870       <require Cclass="CMSIS" Cgroup="CORE"/>
1871     </condition>
1872     <condition id="ARMCM0+ CMSIS GCC">
1873       <description>Generic Arm Cortex-M0+ device startup and depends CMSIS Core requiring GCC</description>
1874       <require condition="ARMCM0+ CMSIS"/>
1875       <require condition="GCC"/>
1876     </condition>
1877
1878     <condition id="ARMCM3 CMSIS">
1879       <description>Generic Arm Cortex-M3 device startup and depends on CMSIS Core</description>
1880       <require Dvendor="ARM:82" Dname="ARMCM3"/>
1881       <require Cclass="CMSIS" Cgroup="CORE"/>
1882     </condition>
1883     <condition id="ARMCM3 CMSIS GCC">
1884       <description>Generic Arm Cortex-M3 device startup and depends on CMSIS Core requiring GCC</description>
1885       <require condition="ARMCM3 CMSIS"/>
1886       <require condition="GCC"/>
1887     </condition>
1888
1889     <condition id="ARMCM4 CMSIS">
1890       <description>Generic Arm Cortex-M4 device startup and depends on CMSIS Core</description>
1891       <require Dvendor="ARM:82" Dname="ARMCM4*"/>
1892       <require Cclass="CMSIS" Cgroup="CORE"/>
1893     </condition>
1894     <condition id="ARMCM4 CMSIS GCC">
1895       <description>Generic Arm Cortex-M4 device startup and depends on CMSIS Core requiring GCC</description>
1896       <require condition="ARMCM4 CMSIS"/>
1897       <require condition="GCC"/>
1898     </condition>
1899
1900     <condition id="ARMCM7 CMSIS">
1901       <description>Generic Arm Cortex-M7 device startup and depends on CMSIS Core</description>
1902       <require Dvendor="ARM:82" Dname="ARMCM7*"/>
1903       <require Cclass="CMSIS" Cgroup="CORE"/>
1904     </condition>
1905     <condition id="ARMCM7 CMSIS GCC">
1906       <description>Generic Arm Cortex-M7 device startup and depends on CMSIS Core requiring GCC</description>
1907       <require condition="ARMCM7 CMSIS"/>
1908       <require condition="GCC"/>
1909     </condition>
1910
1911     <condition id="ARMCM23 CMSIS">
1912       <description>Generic Arm Cortex-M23 device startup and depends on CMSIS Core</description>
1913       <require Dvendor="ARM:82" Dname="ARMCM23*"/>
1914       <require Cclass="CMSIS" Cgroup="CORE"/>
1915     </condition>
1916     <condition id="ARMCM23 CMSIS GCC">
1917       <description>Generic Arm Cortex-M23 device startup and depends on CMSIS Core requiring GCC</description>
1918       <require condition="ARMCM23 CMSIS"/>
1919       <require condition="GCC"/>
1920     </condition>
1921
1922     <condition id="ARMCM33 CMSIS">
1923       <description>Generic Arm Cortex-M33 device startup and depends on CMSIS Core</description>
1924       <require Dvendor="ARM:82" Dname="ARMCM33*"/>
1925       <require Cclass="CMSIS" Cgroup="CORE"/>
1926     </condition>
1927     <condition id="ARMCM33 CMSIS GCC">
1928       <description>Generic Arm Cortex-M33 device startup and depends on CMSIS Core requiring GCC</description>
1929       <require condition="ARMCM33 CMSIS"/>
1930       <require condition="GCC"/>
1931     </condition>
1932
1933     <condition id="ARMSC000 CMSIS">
1934       <description>Generic Arm SC000 device startup and depends on CMSIS Core</description>
1935       <require Dvendor="ARM:82" Dname="ARMSC000"/>
1936       <require Cclass="CMSIS" Cgroup="CORE"/>
1937     </condition>
1938     <condition id="ARMSC000 CMSIS GCC">
1939       <description>Generic Arm SC000 device startup and depends on CMSIS Core requiring GCC</description>
1940       <require condition="ARMSC000 CMSIS"/>
1941       <require condition="GCC"/>
1942     </condition>
1943
1944     <condition id="ARMSC300 CMSIS">
1945       <description>Generic Arm SC300 device startup and depends on CMSIS Core</description>
1946       <require Dvendor="ARM:82" Dname="ARMSC300"/>
1947       <require Cclass="CMSIS" Cgroup="CORE"/>
1948     </condition>
1949     <condition id="ARMSC300 CMSIS GCC">
1950       <description>Generic Arm SC300 device startup and dependson CMSIS Core requiring GCC</description>
1951       <require condition="ARMSC300 CMSIS"/>
1952       <require condition="GCC"/>
1953     </condition>
1954
1955     <condition id="ARMv8MBL CMSIS">
1956       <description>Generic Armv8-M Baseline device startup and depends on CMSIS Core</description>
1957       <require Dvendor="ARM:82" Dname="ARMv8MBL"/>
1958       <require Cclass="CMSIS" Cgroup="CORE"/>
1959     </condition>
1960     <condition id="ARMv8MBL CMSIS GCC">
1961       <description>Generic Armv8-M Baseline device startup and depends on CMSIS Core requiring GCC</description>
1962       <require condition="ARMv8MBL CMSIS"/>
1963       <require condition="GCC"/>
1964     </condition>
1965
1966     <condition id="ARMv8MML CMSIS">
1967       <description>Generic Armv8-M Mainline device startup and depends on CMSIS Core</description>
1968       <require Dvendor="ARM:82" Dname="ARMv8MML*"/>
1969       <require Cclass="CMSIS" Cgroup="CORE"/>
1970     </condition>
1971     <condition id="ARMv8MML CMSIS GCC">
1972       <description>Generic Armv8-M Mainline device startup and depends on CMSIS Core requiring GCC</description>
1973       <require condition="ARMv8MML CMSIS"/>
1974       <require condition="GCC"/>
1975     </condition>
1976
1977     <condition id="ARMCA5 CMSIS">
1978       <description>Generic Arm Cortex-A5 device startup and depends on CMSIS Core</description>
1979       <require Dvendor="ARM:82" Dname="ARMCA5"/>
1980       <require Cclass="CMSIS" Cgroup="CORE"/>
1981     </condition>
1982
1983     <condition id="ARMCA7 CMSIS">
1984       <description>Generic Arm Cortex-A7 device startup and depends on CMSIS Core</description>
1985       <require Dvendor="ARM:82" Dname="ARMCA7"/>
1986       <require Cclass="CMSIS" Cgroup="CORE"/>
1987     </condition>
1988
1989     <condition id="ARMCA9 CMSIS">
1990       <description>Generic Arm Cortex-A9 device startup and depends on CMSIS Core</description>
1991       <require Dvendor="ARM:82" Dname="ARMCA9"/>
1992       <require Cclass="CMSIS" Cgroup="CORE"/>
1993     </condition>
1994
1995     <!-- CMSIS DSP -->
1996     <condition id="CMSIS DSP">
1997       <description>Components required for DSP</description>
1998       <require condition="ARMv6_7_8-M Device"/>
1999       <require condition="ARMCC GCC IAR"/>
2000       <require Cclass="CMSIS" Cgroup="CORE"/>
2001     </condition>
2002
2003     <!-- CMSIS NN -->
2004     <condition id="CMSIS NN">
2005       <description>Components required for NN</description>
2006       <require condition="CMSIS DSP"/>
2007     </condition>
2008
2009     <!-- RTOS RTX -->
2010     <condition id="RTOS RTX">
2011       <description>Components required for RTOS RTX</description>
2012       <require condition="ARMv6_7-M Device"/>
2013       <require condition="ARMCC GCC IAR"/>
2014       <require Cclass="Device" Cgroup="Startup"/>
2015       <deny    Cclass="CMSIS"  Cgroup="RTOS2" Csub="Keil RTX5"/>
2016     </condition>
2017     <condition id="RTOS RTX IFX">
2018       <description>Components required for RTOS RTX IFX</description>
2019       <require condition="ARMv6_7-M Device"/>
2020       <require condition="ARMCC GCC IAR"/>
2021       <require Dvendor="Infineon:7" Dname="XMC4*"/>
2022       <require Cclass="Device" Cgroup="Startup"/>
2023       <deny    Cclass="CMSIS"  Cgroup="RTOS2" Csub="Keil RTX5"/>
2024     </condition>
2025     <condition id="RTOS RTX5">
2026       <description>Components required for RTOS RTX5</description>
2027       <require condition="ARMv6_7_8-M Device"/>
2028       <require condition="ARMCC GCC IAR"/>
2029       <require Cclass="CMSIS"  Cgroup="RTOS2" Csub="Keil RTX5"/>
2030     </condition>
2031     <condition id="RTOS2 RTX5">
2032       <description>Components required for RTOS2 RTX5</description>
2033       <require condition="ARMv6_7_8-M Device"/>
2034       <require condition="ARMCC GCC IAR"/>
2035       <require Cclass="CMSIS"  Cgroup="CORE"/>
2036       <require Cclass="Device" Cgroup="Startup"/>
2037     </condition>
2038     <condition id="RTOS2 RTX5 v7-A">
2039       <description>Components required for RTOS2 RTX5 on Armv7-A</description>
2040       <require condition="ARMv7-A Device"/>
2041       <require condition="ARMCC GCC IAR"/>
2042       <require Cclass="CMSIS"  Cgroup="CORE"/>
2043       <require Cclass="Device" Cgroup="Startup"/>
2044       <require Cclass="Device" Cgroup="OS Tick"/>
2045       <require Cclass="Device" Cgroup="IRQ Controller"/>
2046     </condition>
2047     <condition id="RTOS2 RTX5 Lib">
2048       <description>Components required for RTOS2 RTX5 Library</description>
2049       <require condition="ARMv6_7_8-M Device"/>
2050       <require condition="ARMCC GCC IAR"/>
2051       <require Cclass="CMSIS"  Cgroup="CORE"/>
2052       <require Cclass="Device" Cgroup="Startup"/>
2053     </condition>
2054     <condition id="RTOS2 RTX5 NS">
2055       <description>Components required for RTOS2 RTX5 in Non-Secure Domain</description>
2056       <require condition="ARMv8-M TZ Device"/>
2057       <require condition="ARMCC GCC IAR"/>
2058       <require Cclass="CMSIS"  Cgroup="CORE"/>
2059       <require Cclass="Device" Cgroup="Startup"/>
2060     </condition>
2061
2062     <!-- OS Tick -->
2063     <condition id="OS Tick PTIM">
2064       <description>Components required for OS Tick Private Timer</description>
2065       <require condition="CA5_CA9"/>
2066       <require Cclass="Device" Cgroup="IRQ Controller"/>
2067     </condition>
2068
2069     <condition id="OS Tick GTIM">
2070       <description>Components required for OS Tick Generic Physical Timer</description>
2071       <require condition="CA7"/>
2072       <require Cclass="Device" Cgroup="IRQ Controller"/>
2073     </condition>
2074
2075   </conditions>
2076
2077   <components>
2078     <!-- CMSIS-Core component -->
2079     <component Cclass="CMSIS" Cgroup="CORE" Cversion="5.1.1"  condition="ARMv6_7_8-M Device" >
2080       <description>CMSIS-CORE for Cortex-M, SC000, SC300, ARMv8-M</description>
2081       <files>
2082         <!-- CPU independent -->
2083         <file category="doc"     name="CMSIS/Documentation/Core/html/index.html"/>
2084         <file category="include" name="CMSIS/Include/"/>
2085         <file category="header"  name="CMSIS/Include/tz_context.h" condition="ARMv8-M TZ Device"/>
2086         <!-- Code template -->
2087         <file category="sourceC" attr="template" condition="ARMv8-M TZ Device" name="CMSIS/Core/Template/ARMv8-M/main_s.c"     version="1.1.0" select="Secure mode 'main' module for ARMv8-M"/>
2088         <file category="sourceC" attr="template" condition="ARMv8-M TZ Device" name="CMSIS/Core/Template/ARMv8-M/tz_context.c" version="1.1.0" select="RTOS Context Management (TrustZone for ARMv8-M)" />
2089       </files>
2090     </component>
2091
2092     <component Cclass="CMSIS" Cgroup="CORE" Cversion="1.1.1"  condition="ARMv7-A Device" >
2093       <description>CMSIS-CORE for Cortex-A</description>
2094       <files>
2095         <!-- CPU independent -->
2096         <file category="doc"     name="CMSIS/Documentation/Core_A/html/index.html"/>
2097         <file category="include" name="CMSIS/Core_A/Include/"/>
2098       </files>
2099     </component>
2100
2101     <!-- CMSIS-Startup components -->
2102     <!-- Cortex-M0 -->
2103     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM0 CMSIS">
2104       <description>System and Startup for Generic Arm Cortex-M0 device</description>
2105       <files>
2106         <!-- include folder / device header file -->
2107         <file category="header"  name="Device/ARM/ARMCM0/Include/ARMCM0.h"/>
2108         <!-- startup / system file -->
2109         <file category="sourceAsm"    name="Device/ARM/ARMCM0/Source/ARM/startup_ARMCM0.s" version="1.0.0" attr="config" condition="ARMCC"/>
2110         <file category="sourceAsm"    name="Device/ARM/ARMCM0/Source/GCC/startup_ARMCM0.S" version="1.0.0" attr="config" condition="GCC"/>
2111         <file category="linkerScript" name="Device/ARM/ARMCM0/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2112         <file category="sourceAsm"    name="Device/ARM/ARMCM0/Source/IAR/startup_ARMCM0.s" version="1.0.0" attr="config" condition="IAR"/>
2113         <file category="sourceC"      name="Device/ARM/ARMCM0/Source/system_ARMCM0.c"      version="1.0.0" attr="config"/>
2114       </files>
2115     </component>
2116     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM0 CMSIS GCC">
2117       <description>System and Startup for Generic Arm Cortex-M0 device</description>
2118       <files>
2119         <!-- include folder / device header file -->
2120         <file category="header"  name="Device/ARM/ARMCM0/Include/ARMCM0.h"/>
2121         <!-- startup / system file -->
2122         <file category="sourceC"      name="Device/ARM/ARMCM0/Source/GCC/startup_ARMCM0.c" version="1.0.0" attr="config" condition="GCC"/>
2123         <file category="linkerScript" name="Device/ARM/ARMCM0/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2124         <file category="sourceC"      name="Device/ARM/ARMCM0/Source/system_ARMCM0.c"      version="1.0.0" attr="config"/>
2125       </files>
2126     </component>
2127
2128     <!-- Cortex-M0+ -->
2129     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM0+ CMSIS">
2130       <description>System and Startup for Generic Arm Cortex-M0+ device</description>
2131       <files>
2132         <!-- include folder / device header file -->
2133         <file category="header"  name="Device/ARM/ARMCM0plus/Include/ARMCM0plus.h"/>
2134         <!-- startup / system file -->
2135         <file category="sourceAsm"    name="Device/ARM/ARMCM0plus/Source/ARM/startup_ARMCM0plus.s" version="1.0.0" attr="config" condition="ARMCC"/>
2136         <file category="sourceAsm"    name="Device/ARM/ARMCM0plus/Source/GCC/startup_ARMCM0plus.S" version="1.0.0" attr="config" condition="GCC"/>
2137         <file category="linkerScript" name="Device/ARM/ARMCM0plus/Source/GCC/gcc_arm.ld"           version="1.0.0" attr="config" condition="GCC"/>
2138         <file category="sourceAsm"    name="Device/ARM/ARMCM0plus/Source/IAR/startup_ARMCM0plus.s" version="1.0.0" attr="config" condition="IAR"/>
2139         <file category="sourceC"      name="Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c"      version="1.0.0" attr="config"/>
2140       </files>
2141     </component>
2142     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM0+ CMSIS GCC">
2143       <description>System and Startup for Generic Arm Cortex-M0+ device</description>
2144       <files>
2145         <!-- include folder / device header file -->
2146         <file category="header"  name="Device/ARM/ARMCM0plus/Include/ARMCM0plus.h"/>
2147         <!-- startup / system file -->
2148         <file category="sourceC"      name="Device/ARM/ARMCM0plus/Source/GCC/startup_ARMCM0plus.c" version="1.0.0" attr="config" condition="GCC"/>
2149         <file category="linkerScript" name="Device/ARM/ARMCM0plus/Source/GCC/gcc_arm.ld"           version="1.0.0" attr="config" condition="GCC"/>
2150         <file category="sourceC"      name="Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c"      version="1.0.0" attr="config"/>
2151       </files>
2152     </component>
2153
2154     <!-- Cortex-M3 -->
2155     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM3 CMSIS">
2156       <description>System and Startup for Generic Arm Cortex-M3 device</description>
2157       <files>
2158         <!-- include folder / device header file -->
2159         <file category="header"  name="Device/ARM/ARMCM3/Include/ARMCM3.h"/>
2160         <!-- startup / system file -->
2161         <file category="sourceAsm"    name="Device/ARM/ARMCM3/Source/ARM/startup_ARMCM3.s" version="1.0.0" attr="config" condition="ARMCC"/>
2162         <file category="sourceAsm"    name="Device/ARM/ARMCM3/Source/GCC/startup_ARMCM3.S" version="1.0.0" attr="config" condition="GCC"/>
2163         <file category="linkerScript" name="Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2164         <file category="sourceAsm"    name="Device/ARM/ARMCM3/Source/IAR/startup_ARMCM3.s" version="1.0.0" attr="config" condition="IAR"/>
2165         <file category="sourceC"      name="Device/ARM/ARMCM3/Source/system_ARMCM3.c"      version="1.0.0" attr="config"/>
2166       </files>
2167     </component>
2168     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM3 CMSIS GCC">
2169       <description>System and Startup for Generic Arm Cortex-M3 device</description>
2170       <files>
2171         <!-- include folder / device header file -->
2172         <file category="header"  name="Device/ARM/ARMCM3/Include/ARMCM3.h"/>
2173         <!-- startup / system file -->
2174         <file category="sourceC"      name="Device/ARM/ARMCM3/Source/GCC/startup_ARMCM3.c" version="1.0.0" attr="config" condition="GCC"/>
2175         <file category="linkerScript" name="Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2176         <file category="sourceC"      name="Device/ARM/ARMCM3/Source/system_ARMCM3.c"      version="1.0.0" attr="config"/>
2177       </files>
2178     </component>
2179
2180     <!-- Cortex-M4 -->
2181     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM4 CMSIS">
2182       <description>System and Startup for Generic Arm Cortex-M4 device</description>
2183       <files>
2184         <!-- include folder / device header file -->
2185         <file category="include" name="Device/ARM/ARMCM4/Include/"/>
2186         <!-- startup / system file -->
2187         <file category="sourceAsm"    name="Device/ARM/ARMCM4/Source/ARM/startup_ARMCM4.s" version="1.0.0" attr="config" condition="ARMCC"/>
2188         <file category="sourceAsm"    name="Device/ARM/ARMCM4/Source/GCC/startup_ARMCM4.S" version="1.0.0" attr="config" condition="GCC"/>
2189         <file category="linkerScript" name="Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2190         <file category="sourceAsm"    name="Device/ARM/ARMCM4/Source/IAR/startup_ARMCM4.s" version="1.0.0" attr="config" condition="IAR"/>
2191         <file category="sourceC"      name="Device/ARM/ARMCM4/Source/system_ARMCM4.c"      version="1.0.0" attr="config"/>
2192       </files>
2193     </component>
2194     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM4 CMSIS GCC">
2195       <description>System and Startup for Generic Arm Cortex-M4 device</description>
2196       <files>
2197         <!-- include folder / device header file -->
2198         <file category="include" name="Device/ARM/ARMCM4/Include/"/>
2199         <!-- startup / system file -->
2200         <file category="sourceC"      name="Device/ARM/ARMCM4/Source/GCC/startup_ARMCM4.c" version="1.0.0" attr="config" condition="GCC"/>
2201         <file category="linkerScript" name="Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2202         <file category="sourceC"      name="Device/ARM/ARMCM4/Source/system_ARMCM4.c"      version="1.0.0" attr="config"/>
2203       </files>
2204     </component>
2205
2206     <!-- Cortex-M7 -->
2207     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM7 CMSIS">
2208       <description>System and Startup for Generic Arm Cortex-M7 device</description>
2209       <files>
2210         <!-- include folder / device header file -->
2211         <file category="include"  name="Device/ARM/ARMCM7/Include/"/>
2212         <!-- startup / system file -->
2213         <file category="sourceAsm"    name="Device/ARM/ARMCM7/Source/ARM/startup_ARMCM7.s" version="1.0.0" attr="config" condition="ARMCC"/>
2214         <file category="sourceAsm"    name="Device/ARM/ARMCM7/Source/GCC/startup_ARMCM7.S" version="1.0.0" attr="config" condition="GCC"/>
2215         <file category="linkerScript" name="Device/ARM/ARMCM7/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2216         <file category="sourceAsm"    name="Device/ARM/ARMCM7/Source/IAR/startup_ARMCM7.s" version="1.0.0" attr="config" condition="IAR"/>
2217         <file category="sourceC"      name="Device/ARM/ARMCM7/Source/system_ARMCM7.c"      version="1.0.0" attr="config"/>
2218       </files>
2219     </component>
2220     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM7 CMSIS GCC">
2221       <description>System and Startup for Generic Arm Cortex-M7 device</description>
2222       <files>
2223         <!-- include folder / device header file -->
2224         <file category="include"  name="Device/ARM/ARMCM7/Include/"/>
2225         <!-- startup / system file -->
2226         <file category="sourceC"      name="Device/ARM/ARMCM7/Source/GCC/startup_ARMCM7.c" version="1.0.0" attr="config" condition="GCC"/>
2227         <file category="linkerScript" name="Device/ARM/ARMCM7/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2228         <file category="sourceC"      name="Device/ARM/ARMCM7/Source/system_ARMCM7.c"      version="1.0.0" attr="config"/>
2229       </files>
2230     </component>
2231
2232     <!-- Cortex-M23 -->
2233     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.0" condition="ARMCM23 CMSIS">
2234       <description>System and Startup for Generic Arm Cortex-M23 device</description>
2235       <files>
2236         <!-- include folder / device header file -->
2237         <file category="include"      name="Device/ARM/ARMCM23/Include/"/>
2238         <!-- startup / system file -->
2239         <file category="sourceAsm"    name="Device/ARM/ARMCM23/Source/ARM/startup_ARMCM23.s" version="1.0.0" attr="config" condition="ARMCC"/>
2240         <file category="sourceAsm"    name="Device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.S" version="1.0.0" attr="config" condition="GCC"/>
2241         <file category="linkerScript" name="Device/ARM/ARMCM23/Source/GCC/gcc_arm.ld"        version="1.0.0" attr="config" condition="GCC"/>
2242         <file category="sourceAsm"    name="Device/ARM/ARMCM23/Source/IAR/startup_ARMCM23.s" version="1.0.0" attr="config" condition="IAR"/>
2243         <file category="sourceC"      name="Device/ARM/ARMCM23/Source/system_ARMCM23.c"      version="1.0.0" attr="config"/>
2244         <!-- SAU configuration -->
2245         <file category="header"       name="Device/ARM/ARMCM23/Include/Template/partition_ARMCM23.h" version="1.0.0" attr="config" condition="ARMv8-M TZ Device"/>
2246       </files>
2247     </component>
2248     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.0" condition="ARMCM23 CMSIS GCC">
2249       <description>System and Startup for Generic Arm Cortex-M23 device</description>
2250       <files>
2251         <!-- include folder / device header file -->
2252         <file category="include"  name="Device/ARM/ARMCM23/Include/"/>
2253         <!-- startup / system file -->
2254         <file category="sourceC"      name="Device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.c" version="1.0.0" attr="config" condition="GCC"/>
2255         <file category="linkerScript" name="Device/ARM/ARMCM23/Source/GCC/gcc_arm.ld"        version="1.0.0" attr="config" condition="GCC"/>
2256         <file category="sourceC"      name="Device/ARM/ARMCM23/Source/system_ARMCM23.c"      version="1.0.0" attr="config"/>
2257         <!-- SAU configuration -->
2258         <file category="header"       name="Device/ARM/ARMCM23/Include/Template/partition_ARMCM23.h" version="1.0.0" attr="config" condition="ARMv8-M TZ Device"/>
2259       </files>
2260     </component>
2261
2262     <!-- Cortex-M33 -->
2263     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.1.0" condition="ARMCM33 CMSIS">
2264       <description>System and Startup for Generic Arm Cortex-M33 device</description>
2265       <files>
2266         <!-- include folder / device header file -->
2267         <file category="include"      name="Device/ARM/ARMCM33/Include/"/>
2268         <!-- startup / system file -->
2269         <file category="sourceAsm"    name="Device/ARM/ARMCM33/Source/ARM/startup_ARMCM33.s"         version="1.0.0" attr="config" condition="ARMCC"/>
2270         <file category="sourceAsm"    name="Device/ARM/ARMCM33/Source/GCC/startup_ARMCM33.S"         version="1.0.0" attr="config" condition="GCC"/>
2271         <file category="linkerScript" name="Device/ARM/ARMCM33/Source/GCC/gcc_arm.ld"                version="1.0.0" attr="config" condition="GCC"/>
2272         <file category="sourceAsm"    name="Device/ARM/ARMCM33/Source/IAR/startup_ARMCM33.s"         version="1.0.0" attr="config" condition="IAR"/>
2273         <file category="sourceC"      name="Device/ARM/ARMCM33/Source/system_ARMCM33.c"              version="1.0.0" attr="config"/>
2274         <!-- SAU configuration -->
2275         <file category="header"       name="Device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2276       </files>
2277     </component>
2278     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.1.0" condition="ARMCM33 CMSIS GCC">
2279       <description>System and Startup for Generic Arm Cortex-M33 device</description>
2280       <files>
2281         <!-- include folder / device header file -->
2282         <file category="include"  name="Device/ARM/ARMCM33/Include/"/>
2283         <!-- startup / system file -->
2284         <file category="sourceC"      name="Device/ARM/ARMCM33/Source/GCC/startup_ARMCM33.c"         version="1.0.0" attr="config" condition="GCC"/>
2285         <file category="linkerScript" name="Device/ARM/ARMCM33/Source/GCC/gcc_arm.ld"                version="1.0.0" attr="config" condition="GCC"/>
2286         <file category="sourceC"      name="Device/ARM/ARMCM33/Source/system_ARMCM33.c"              version="1.0.0" attr="config"/>
2287         <!-- SAU configuration -->
2288         <file category="header"       name="Device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2289       </files>
2290     </component>
2291
2292     <!-- Cortex-SC000 -->
2293     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMSC000 CMSIS">
2294       <description>System and Startup for Generic Arm SC000 device</description>
2295       <files>
2296         <!-- include folder / device header file -->
2297         <file category="header"  name="Device/ARM/ARMSC000/Include/ARMSC000.h"/>
2298         <!-- startup / system file -->
2299         <file category="sourceAsm"    name="Device/ARM/ARMSC000/Source/ARM/startup_ARMSC000.s" version="1.0.0" attr="config" condition="ARMCC"/>
2300         <file category="sourceAsm"    name="Device/ARM/ARMSC000/Source/GCC/startup_ARMSC000.S" version="1.0.0" attr="config" condition="GCC"/>
2301         <file category="linkerScript" name="Device/ARM/ARMSC000/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2302         <file category="sourceAsm"    name="Device/ARM/ARMSC000/Source/IAR/startup_ARMSC000.s" version="1.0.0" attr="config" condition="IAR"/>
2303         <file category="sourceC"      name="Device/ARM/ARMSC000/Source/system_ARMSC000.c"      version="1.0.0" attr="config"/>
2304       </files>
2305     </component>
2306     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMSC000 CMSIS GCC">
2307       <description>System and Startup for Generic Arm SC000 device</description>
2308       <files>
2309         <!-- include folder / device header file -->
2310         <file category="header"  name="Device/ARM/ARMSC000/Include/ARMSC000.h"/>
2311         <!-- startup / system file -->
2312         <file category="sourceC"      name="Device/ARM/ARMSC000/Source/GCC/startup_ARMSC000.c" version="1.0.0" attr="config" condition="GCC"/>
2313         <file category="linkerScript" name="Device/ARM/ARMSC000/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2314         <file category="sourceC"      name="Device/ARM/ARMSC000/Source/system_ARMSC000.c"      version="1.0.0" attr="config"/>
2315       </files>
2316     </component>
2317
2318     <!-- Cortex-SC300 -->
2319     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMSC300 CMSIS">
2320       <description>System and Startup for Generic Arm SC300 device</description>
2321       <files>
2322         <!-- include folder / device header file -->
2323         <file category="header"  name="Device/ARM/ARMSC300/Include/ARMSC300.h"/>
2324         <!-- startup / system file -->
2325         <file category="sourceAsm"    name="Device/ARM/ARMSC300/Source/ARM/startup_ARMSC300.s" version="1.0.0" attr="config" condition="ARMCC"/>
2326         <file category="sourceAsm"    name="Device/ARM/ARMSC300/Source/GCC/startup_ARMSC300.S" version="1.0.0" attr="config" condition="GCC"/>
2327         <file category="linkerScript" name="Device/ARM/ARMSC300/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2328         <file category="sourceAsm"    name="Device/ARM/ARMSC300/Source/IAR/startup_ARMSC300.s" version="1.0.0" attr="config" condition="IAR"/>
2329         <file category="sourceC"      name="Device/ARM/ARMSC300/Source/system_ARMSC300.c"      version="1.0.0" attr="config"/>
2330       </files>
2331     </component>
2332     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMSC300 CMSIS GCC">
2333       <description>System and Startup for Generic Arm SC300 device</description>
2334       <files>
2335         <!-- include folder / device header file -->
2336         <file category="header"  name="Device/ARM/ARMSC300/Include/ARMSC300.h"/>
2337         <!-- startup / system file -->
2338         <file category="sourceC"      name="Device/ARM/ARMSC300/Source/GCC/startup_ARMSC300.c" version="1.0.0" attr="config" condition="GCC"/>
2339         <file category="linkerScript" name="Device/ARM/ARMSC300/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2340         <file category="sourceC"      name="Device/ARM/ARMSC300/Source/system_ARMSC300.c"      version="1.0.0" attr="config"/>
2341       </files>
2342     </component>
2343
2344     <!-- ARMv8MBL -->
2345     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.0" condition="ARMv8MBL CMSIS">
2346       <description>System and Startup for Generic Armv8-M Baseline device</description>
2347       <files>
2348         <!-- include folder / device header file -->
2349         <file category="include"      name="Device/ARM/ARMv8MBL/Include/"/>
2350         <!-- startup / system file -->
2351         <file category="sourceAsm"    name="Device/ARM/ARMv8MBL/Source/ARM/startup_ARMv8MBL.s" version="1.0.0" attr="config" condition="ARMCC"/>
2352         <file category="sourceAsm"    name="Device/ARM/ARMv8MBL/Source/GCC/startup_ARMv8MBL.S" version="1.0.0" attr="config" condition="GCC"/>
2353         <file category="linkerScript" name="Device/ARM/ARMv8MBL/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2354         <file category="sourceC"      name="Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c"      version="1.0.0" attr="config" condition="ARMCC GCC"/>
2355         <!-- SAU configuration -->
2356         <file category="header"       name="Device/ARM/ARMv8MBL/Include/Template/partition_ARMv8MBL.h" version="1.0.0" attr="config"/>
2357       </files>
2358     </component>
2359     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.0" condition="ARMv8MBL CMSIS GCC">
2360       <description>System and Startup for Generic Armv8-M Baseline device</description>
2361       <files>
2362         <!-- include folder / device header file -->
2363         <file category="include"  name="Device/ARM/ARMv8MBL/Include/"/>
2364         <!-- startup / system file -->
2365         <file category="sourceC"      name="Device/ARM/ARMv8MBL/Source/GCC/startup_ARMv8MBL.c" version="1.0.0" attr="config" condition="GCC"/>
2366         <file category="linkerScript" name="Device/ARM/ARMv8MBL/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2367         <file category="sourceC"      name="Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c"      version="1.0.0" attr="config"/>
2368         <!-- SAU configuration -->
2369         <file category="header"       name="Device/ARM/ARMv8MBL/Include/Template/partition_ARMv8MBL.h" version="1.0.0" attr="config" condition="ARMv8-M TZ Device"/>
2370       </files>
2371     </component>
2372
2373     <!-- ARMv8MML -->
2374     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.1.0" condition="ARMv8MML CMSIS">
2375       <description>System and Startup for Generic Armv8-M Mainline device</description>
2376       <files>
2377         <!-- include folder / device header file -->
2378         <file category="include"      name="Device/ARM/ARMv8MML/Include/"/>
2379         <!-- startup / system file -->
2380         <file category="sourceAsm"    name="Device/ARM/ARMv8MML/Source/ARM/startup_ARMv8MML.s"         version="1.0.0" attr="config" condition="ARMCC"/>
2381         <file category="sourceAsm"    name="Device/ARM/ARMv8MML/Source/GCC/startup_ARMv8MML.S"         version="1.0.0" attr="config" condition="GCC"/>
2382         <file category="linkerScript" name="Device/ARM/ARMv8MML/Source/GCC/gcc_arm.ld"                 version="1.0.0" attr="config" condition="GCC"/>
2383         <file category="sourceC"      name="Device/ARM/ARMv8MML/Source/system_ARMv8MML.c"              version="1.0.0" attr="config" condition="ARMCC GCC"/>
2384         <!-- SAU configuration -->
2385         <file category="header"       name="Device/ARM/ARMv8MML/Include/Template/partition_ARMv8MML.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2386       </files>
2387     </component>
2388     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.1.0" condition="ARMv8MML CMSIS GCC">
2389       <description>System and Startup for Generic Armv8-M Mainline device</description>
2390       <files>
2391         <!-- include folder / device header file -->
2392         <file category="include"      name="Device/ARM/ARMv8MML/Include/"/>
2393         <!-- startup / system file -->
2394         <file category="sourceC"      name="Device/ARM/ARMv8MML/Source/GCC/startup_ARMv8MML.c"         version="1.0.0" attr="config" condition="GCC"/>
2395         <file category="linkerScript" name="Device/ARM/ARMv8MML/Source/GCC/gcc_arm.ld"                 version="1.0.0" attr="config" condition="GCC"/>
2396         <file category="sourceC"      name="Device/ARM/ARMv8MML/Source/system_ARMv8MML.c"              version="1.0.0" attr="config"/>
2397         <!-- SAU configuration -->
2398         <file category="header"       name="Device/ARM/ARMv8MML/Include/Template/partition_ARMv8MML.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2399       </files>
2400     </component>
2401
2402     <!-- Cortex-A5 -->
2403     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.0" condition="ARMCA5 CMSIS">
2404       <description>System and Startup for Generic Arm Cortex-A5 device</description>
2405       <files>
2406         <!-- include folder / device header file -->
2407         <file category="include"      name="Device/ARM/ARMCA5/Include/"/>
2408         <!-- startup / system / mmu files -->
2409         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/AC5/startup_ARMCA5.c" version="1.0.0" attr="config" condition="ARMCC5"/>
2410         <file category="linkerScript" name="Device/ARM/ARMCA5/Source/AC5/ARMCA5.sct"       version="1.0.0" attr="config" condition="ARMCC5"/>
2411         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/AC6/startup_ARMCA5.c" version="1.0.0" attr="config" condition="ARMCC6"/>
2412         <file category="linkerScript" name="Device/ARM/ARMCA5/Source/AC6/ARMCA5.sct"       version="1.0.0" attr="config" condition="ARMCC6"/>
2413         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/GCC/startup_ARMCA5.c" version="1.0.0" attr="config" condition="GCC"/>
2414         <file category="other"        name="Device/ARM/ARMCA5/Source/GCC/ARMCA5.ld"        version="1.0.0" attr="config" condition="GCC"/>
2415         <file category="sourceAsm"    name="Device/ARM/ARMCA5/Source/IAR/startup_ARMCA5.s" version="1.0.0" attr="config" condition="IAR"/>
2416         <file category="linkerScript" name="Device/ARM/ARMCA5/Source/IAR/ARMCA5.icf"       version="1.0.0" attr="config" condition="IAR"/>
2417         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/system_ARMCA5.c"      version="1.0.0" attr="config"/>
2418         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/mmu_ARMCA5.c"         version="1.0.0" attr="config"/>
2419         <file category="header"       name="Device/ARM/ARMCA5/Include/system_ARMCA5.h"     version="1.0.0" attr="config"/>
2420         <file category="header"       name="Device/ARM/ARMCA5/Include/mem_ARMCA5.h"        version="1.0.0" attr="config"/>
2421
2422       </files>
2423     </component>
2424
2425     <!-- Cortex-A7 -->
2426     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.0" condition="ARMCA7 CMSIS">
2427       <description>System and Startup for Generic Arm Cortex-A7 device</description>
2428       <files>
2429         <!-- include folder / device header file -->
2430         <file category="include"      name="Device/ARM/ARMCA7/Include/"/>
2431         <!-- startup / system / mmu files -->
2432         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/AC5/startup_ARMCA7.c" version="1.0.0" attr="config" condition="ARMCC5"/>
2433         <file category="linkerScript" name="Device/ARM/ARMCA7/Source/AC5/ARMCA7.sct"       version="1.0.0" attr="config" condition="ARMCC5"/>
2434         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/AC6/startup_ARMCA7.c" version="1.0.0" attr="config" condition="ARMCC6"/>
2435         <file category="linkerScript" name="Device/ARM/ARMCA7/Source/AC6/ARMCA7.sct"       version="1.0.0" attr="config" condition="ARMCC6"/>
2436         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/GCC/startup_ARMCA7.c" version="1.0.0" attr="config" condition="GCC"/>
2437         <file category="other"        name="Device/ARM/ARMCA7/Source/GCC/ARMCA7.ld"        version="1.0.0" attr="config" condition="GCC"/>
2438         <file category="sourceAsm"    name="Device/ARM/ARMCA7/Source/IAR/startup_ARMCA7.s" version="1.0.0" attr="config" condition="IAR"/>
2439         <file category="linkerScript" name="Device/ARM/ARMCA7/Source/IAR/ARMCA7.icf"       version="1.0.0" attr="config" condition="IAR"/>
2440         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/system_ARMCA7.c"      version="1.0.0" attr="config"/>
2441         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/mmu_ARMCA7.c"         version="1.0.0" attr="config"/>
2442         <file category="header"       name="Device/ARM/ARMCA7/Include/system_ARMCA7.h"     version="1.0.0" attr="config"/>
2443         <file category="header"       name="Device/ARM/ARMCA7/Include/mem_ARMCA7.h"        version="1.0.0" attr="config"/>
2444       </files>
2445     </component>
2446
2447     <!-- Cortex-A9 -->
2448     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCA9 CMSIS">
2449       <description>System and Startup for Generic Arm Cortex-A9 device</description>
2450       <files>
2451         <!-- include folder / device header file -->
2452         <file category="include"  name="Device/ARM/ARMCA9/Include/"/>
2453         <!-- startup / system / mmu files -->
2454         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/AC5/startup_ARMCA9.c" version="1.0.0" attr="config" condition="ARMCC5"/>
2455         <file category="linkerScript" name="Device/ARM/ARMCA9/Source/AC5/ARMCA9.sct"       version="1.0.0" attr="config" condition="ARMCC5"/>
2456         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/AC6/startup_ARMCA9.c" version="1.0.0" attr="config" condition="ARMCC6"/>
2457         <file category="linkerScript" name="Device/ARM/ARMCA9/Source/AC6/ARMCA9.sct"       version="1.0.0" attr="config" condition="ARMCC6"/>
2458         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/GCC/startup_ARMCA9.c" version="1.0.0" attr="config" condition="GCC"/>
2459         <file category="other"        name="Device/ARM/ARMCA9/Source/GCC/ARMCA9.ld"        version="1.0.0" attr="config" condition="GCC"/>
2460         <file category="sourceAsm"    name="Device/ARM/ARMCA9/Source/IAR/startup_ARMCA9.s" version="1.0.0" attr="config" condition="IAR"/>
2461         <file category="linkerScript" name="Device/ARM/ARMCA9/Source/IAR/ARMCA9.icf"       version="1.0.0" attr="config" condition="IAR"/>
2462         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/system_ARMCA9.c"      version="1.0.0" attr="config"/>
2463         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/mmu_ARMCA9.c"         version="1.0.0" attr="config"/>
2464         <file category="header"       name="Device/ARM/ARMCA9/Include/system_ARMCA9.h"     version="1.0.0" attr="config"/>
2465         <file category="header"       name="Device/ARM/ARMCA9/Include/mem_ARMCA9.h"        version="1.0.0" attr="config"/>
2466       </files>
2467     </component>
2468
2469     <!-- IRQ Controller -->
2470     <component Cclass="Device" Cgroup="IRQ Controller" Csub="GIC" Capiversion="1.0.0" Cversion="1.0.0" condition="ARMv7-A Device">
2471       <description>IRQ Controller implementation using GIC</description>
2472       <files>
2473         <file category="sourceC" name="CMSIS/Core_A/Source/irq_ctrl_gic.c"/>
2474       </files>
2475     </component>
2476
2477     <!-- OS Tick -->
2478     <component Cclass="Device" Cgroup="OS Tick" Csub="Private Timer" Capiversion="1.0.1" Cversion="1.0.2" condition="OS Tick PTIM">
2479       <description>OS Tick implementation using Private Timer</description>
2480       <files>
2481         <file category="sourceC" name="CMSIS/RTOS2/Source/os_tick_ptim.c"/>
2482       </files>
2483     </component>
2484
2485     <component Cclass="Device" Cgroup="OS Tick" Csub="Generic Physical Timer" Capiversion="1.0.1" Cversion="1.0.1" condition="OS Tick GTIM">
2486       <description>OS Tick implementation using Generic Physical Timer</description>
2487       <files>
2488         <file category="sourceC" name="CMSIS/RTOS2/Source/os_tick_gtim.c"/>
2489       </files>
2490     </component>
2491
2492     <!-- CMSIS-DSP component -->
2493     <component Cclass="CMSIS" Cgroup="DSP" Cversion="1.5.2" condition="CMSIS DSP">
2494       <description>CMSIS-DSP Library for Cortex-M, SC000, and SC300</description>
2495       <files>
2496         <!-- CPU independent -->
2497         <file category="doc" name="CMSIS/Documentation/DSP/html/index.html"/>
2498         <file category="header" name="CMSIS/Include/arm_math.h"/>
2499
2500         <!-- CPU and Compiler dependent -->
2501         <!-- ARMCC -->
2502         <file category="library" condition="CM0_LE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM0l_math.lib"      src="CMSIS/DSP_Lib/Source/ARM"/>
2503         <file category="library" condition="CM0_BE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM0b_math.lib"      src="CMSIS/DSP_Lib/Source/ARM"/>
2504         <file category="library" condition="CM3_LE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM3l_math.lib"      src="CMSIS/DSP_Lib/Source/ARM"/>
2505         <file category="library" condition="CM3_BE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM3b_math.lib"      src="CMSIS/DSP_Lib/Source/ARM"/>
2506         <file category="library" condition="CM4_LE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM4l_math.lib"      src="CMSIS/DSP_Lib/Source/ARM"/>
2507         <file category="library" condition="CM4_BE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM4b_math.lib"      src="CMSIS/DSP_Lib/Source/ARM"/>
2508         <file category="library" condition="CM4_FP_LE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM4lf_math.lib"     src="CMSIS/DSP_Lib/Source/ARM"/>
2509         <file category="library" condition="CM4_FP_BE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM4bf_math.lib"     src="CMSIS/DSP_Lib/Source/ARM"/>
2510         <file category="library" condition="CM7_LE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM7l_math.lib"      src="CMSIS/DSP_Lib/Source/ARM"/>
2511         <file category="library" condition="CM7_BE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM7b_math.lib"      src="CMSIS/DSP_Lib/Source/ARM"/>
2512         <file category="library" condition="CM7_SP_LE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM7lfsp_math.lib"   src="CMSIS/DSP_Lib/Source/ARM"/>
2513         <file category="library" condition="CM7_SP_BE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM7bfsp_math.lib"   src="CMSIS/DSP_Lib/Source/ARM"/>
2514         <file category="library" condition="CM7_DP_LE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM7lfdp_math.lib"   src="CMSIS/DSP_Lib/Source/ARM"/>
2515         <file category="library" condition="CM7_DP_BE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM7bfdp_math.lib"   src="CMSIS/DSP_Lib/Source/ARM"/>
2516
2517         <file category="library" condition="CM23_LE_ARMCC"                  name="CMSIS/Lib/ARM/arm_ARMv8MBLl_math.lib"      src="CMSIS/DSP_Lib/Source/ARM"/>
2518         <file category="library" condition="CM33_NODSP_NOFPU_LE_ARMCC"      name="CMSIS/Lib/ARM/arm_ARMv8MMLl_math.lib"      src="CMSIS/DSP_Lib/Source/ARM"/>
2519         <file category="library" condition="CM33_DSP_NOFPU_LE_ARMCC"        name="CMSIS/Lib/ARM/arm_ARMv8MMLld_math.lib"     src="CMSIS/DSP_Lib/Source/ARM"/>
2520         <file category="library" condition="CM33_NODSP_SP_LE_ARMCC"         name="CMSIS/Lib/ARM/arm_ARMv8MMLlfsp_math.lib"   src="CMSIS/DSP_Lib/Source/ARM"/>
2521         <file category="library" condition="CM33_DSP_SP_LE_ARMCC"           name="CMSIS/Lib/ARM/arm_ARMv8MMLldfsp_math.lib"  src="CMSIS/DSP_Lib/Source/ARM"/>
2522         <file category="library" condition="ARMv8MBL_LE_ARMCC"              name="CMSIS/Lib/ARM/arm_ARMv8MBLl_math.lib"      src="CMSIS/DSP_Lib/Source/ARM"/>
2523         <file category="library" condition="ARMv8MML_NODSP_NOFPU_LE_ARMCC"  name="CMSIS/Lib/ARM/arm_ARMv8MMLl_math.lib"      src="CMSIS/DSP_Lib/Source/ARM"/>
2524         <file category="library" condition="ARMv8MML_DSP_NOFPU_LE_ARMCC"    name="CMSIS/Lib/ARM/arm_ARMv8MMLld_math.lib"     src="CMSIS/DSP_Lib/Source/ARM"/>
2525         <file category="library" condition="ARMv8MML_NODSP_SP_LE_ARMCC"     name="CMSIS/Lib/ARM/arm_ARMv8MMLlfsp_math.lib"   src="CMSIS/DSP_Lib/Source/ARM"/>
2526         <file category="library" condition="ARMv8MML_DSP_SP_LE_ARMCC"       name="CMSIS/Lib/ARM/arm_ARMv8MMLldfsp_math.lib"  src="CMSIS/DSP_Lib/Source/ARM"/>
2527         <!--file category="library" condition="ARMv8MML_DP_NOFPU_LE_ARMCC"     name="CMSIS/Lib/ARM/arm_ARMv8MMLlfdp_math.lib"   src="CMSIS/DSP_Lib/Source/ARM"/-->
2528         <!--file category="library" condition="ARMv8MML_DSP_DP_LE_ARMCC"       name="CMSIS/Lib/ARM/arm_ARMv8MMLldfdp_math.lib"  src="CMSIS/DSP_Lib/Source/ARM"/-->
2529
2530         <!-- GCC -->
2531         <file category="library" condition="CM0_LE_GCC"               name="CMSIS/Lib/GCC/libarm_cortexM0l_math.a"     src="CMSIS/DSP_Lib/Source/GCC"/>
2532         <file category="library" condition="CM3_LE_GCC"               name="CMSIS/Lib/GCC/libarm_cortexM3l_math.a"     src="CMSIS/DSP_Lib/Source/GCC"/>
2533         <file category="library" condition="CM4_LE_GCC"               name="CMSIS/Lib/GCC/libarm_cortexM4l_math.a"     src="CMSIS/DSP_Lib/Source/GCC"/>
2534         <file category="library" condition="CM4_FP_LE_GCC"            name="CMSIS/Lib/GCC/libarm_cortexM4lf_math.a"    src="CMSIS/DSP_Lib/Source/GCC"/>
2535         <file category="library" condition="CM7_LE_GCC"               name="CMSIS/Lib/GCC/libarm_cortexM7l_math.a"     src="CMSIS/DSP_Lib/Source/GCC"/>
2536         <file category="library" condition="CM7_SP_LE_GCC"            name="CMSIS/Lib/GCC/libarm_cortexM7lfsp_math.a"  src="CMSIS/DSP_Lib/Source/GCC"/>
2537         <file category="library" condition="CM7_DP_LE_GCC"            name="CMSIS/Lib/GCC/libarm_cortexM7lfdp_math.a"  src="CMSIS/DSP_Lib/Source/GCC"/>
2538
2539         <file category="library" condition="CM23_LE_GCC"                    name="CMSIS/Lib/GCC/libarm_ARMv8MBLl_math.a"     src="CMSIS/DSP_Lib/Source/GCC"/>
2540         <file category="library" condition="CM33_NODSP_NOFPU_LE_GCC"        name="CMSIS/Lib/GCC/libarm_ARMv8MMLl_math.a"     src="CMSIS/DSP_Lib/Source/GCC"/>
2541         <file category="library" condition="CM33_DSP_NOFPU_LE_GCC"          name="CMSIS/Lib/GCC/libarm_ARMv8MMLld_math.a"    src="CMSIS/DSP_Lib/Source/GCC"/>
2542         <file category="library" condition="CM33_NODSP_SP_LE_GCC"           name="CMSIS/Lib/GCC/libarm_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP_Lib/Source/GCC"/>
2543         <file category="library" condition="CM33_DSP_SP_LE_GCC"             name="CMSIS/Lib/GCC/libarm_ARMv8MMLldfsp_math.a" src="CMSIS/DSP_Lib/Source/GCC"/>
2544         <file category="library" condition="ARMv8MBL_LE_GCC"                name="CMSIS/Lib/GCC/libarm_ARMv8MBLl_math.a"     src="CMSIS/DSP_Lib/Source/GCC"/>
2545         <file category="library" condition="ARMv8MML_NODSP_NOFPU_LE_GCC"    name="CMSIS/Lib/GCC/libarm_ARMv8MMLl_math.a"     src="CMSIS/DSP_Lib/Source/GCC"/>
2546         <file category="library" condition="ARMv8MML_DSP_NOFPU_LE_GCC"      name="CMSIS/Lib/GCC/libarm_ARMv8MMLld_math.a"    src="CMSIS/DSP_Lib/Source/GCC"/>
2547         <file category="library" condition="ARMv8MML_NODSP_SP_LE_GCC"       name="CMSIS/Lib/GCC/libarm_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP_Lib/Source/GCC"/>
2548         <file category="library" condition="ARMv8MML_DSP_SP_LE_GCC"         name="CMSIS/Lib/GCC/libarm_ARMv8MMLldfsp_math.a" src="CMSIS/DSP_Lib/Source/GCC"/>
2549         <!--file category="library" condition="ARMv8MML_DP_NOFPU_LE_GCC"       name="CMSIS/Lib/GCC/libarm_ARMv8MMLlfdp_math.a"  src="CMSIS/DSP_Lib/Source/GCC"/-->
2550         <!--file category="library" condition="ARMv8MML_DSP_DP_LE_GCC"         name="CMSIS/Lib/GCC/libarm_ARMv8MMLldfdp_math.a" src="CMSIS/DSP_Lib/Source/GCC"/-->
2551
2552         <!-- IAR -->
2553         <file category="library" condition="CM0_LE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM0l_math.a"     src="CMSIS/DSP_Lib/Source/IAR"/>
2554         <file category="library" condition="CM0_BE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM0b_math.a"     src="CMSIS/DSP_Lib/Source/IAR"/>
2555         <file category="library" condition="CM3_LE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM3l_math.a"     src="CMSIS/DSP_Lib/Source/IAR"/>
2556         <file category="library" condition="CM3_BE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM3b_math.a"     src="CMSIS/DSP_Lib/Source/IAR"/>
2557         <file category="library" condition="CM4_LE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM4l_math.a"     src="CMSIS/DSP_Lib/Source/IAR"/>
2558         <file category="library" condition="CM4_BE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM4b_math.a"     src="CMSIS/DSP_Lib/Source/IAR"/>
2559         <file category="library" condition="CM4_FP_LE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM4lf_math.a"    src="CMSIS/DSP_Lib/Source/IAR"/>
2560         <file category="library" condition="CM4_FP_BE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM4bf_math.a"    src="CMSIS/DSP_Lib/Source/IAR"/>
2561         <file category="library" condition="CM7_LE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM7l_math.a"     src="CMSIS/DSP_Lib/Source/IAR"/>
2562         <file category="library" condition="CM7_BE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM7b_math.a"     src="CMSIS/DSP_Lib/Source/IAR"/>
2563         <file category="library" condition="CM7_DP_LE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM7lf_math.a"    src="CMSIS/DSP_Lib/Source/IAR"/>
2564         <file category="library" condition="CM7_DP_BE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM7bf_math.a"    src="CMSIS/DSP_Lib/Source/IAR"/>
2565         <file category="library" condition="CM7_SP_LE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM7ls_math.a"    src="CMSIS/DSP_Lib/Source/IAR"/>
2566         <file category="library" condition="CM7_SP_BE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM7bs_math.a"    src="CMSIS/DSP_Lib/Source/IAR"/>
2567
2568         <file category="library" condition="CM23_LE_IAR"              name="CMSIS/Lib/IAR/iar_ARMv8MBLl_math.a"     src="CMSIS/DSP_Lib/Source/IAR"/>
2569         <file category="library" condition="CM33_LE_IAR"              name="CMSIS/Lib/IAR/iar_ARMv8MMLl_math.a"     src="CMSIS/DSP_Lib/Source/IAR"/>
2570         <file category="library" condition="CM33_DSP_SP_LE_IAR"       name="CMSIS/Lib/IAR/iar_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP_Lib/Source/IAR"/>
2571         <file category="library" condition="CM33_FP_LE_IAR"           name="CMSIS/Lib/IAR/iar_ARMv8MMLlfdp_math.a"  src="CMSIS/DSP_Lib/Source/IAR"/>
2572         <file category="library" condition="CM33_DSP_NOFPU_LE_IAR"    name="CMSIS/Lib/IAR/iar_ARMv8MMLld_math.a"    src="CMSIS/DSP_Lib/Source/IAR"/>
2573         <file category="library" condition="CM33_DSP_SP_LE_IAR"       name="CMSIS/Lib/IAR/iar_ARMv8MMLldfsp_math.a" src="CMSIS/DSP_Lib/Source/IAR"/>
2574         <!--file category="library" condition="CM33_DSP_DP_LE_IAR"       name="CMSIS/Lib/IAR/iar_ARMv8MMLldfdp_math.a" src="CMSIS/DSP_Lib/Source/IAR"/-->
2575         <file category="library" condition="ARMv8MBL_LE_IAR"          name="CMSIS/Lib/IAR/iar_ARMv8MBLl_math.a"     src="CMSIS/DSP_Lib/Source/IAR"/>
2576         <file category="library" condition="ARMv8MML_LE_IAR"          name="CMSIS/Lib/IAR/iar_ARMv8MMLl_math.a"     src="CMSIS/DSP_Lib/Source/IAR"/>
2577         <file category="library" condition="ARMv8MML_DSP_SP_LE_IAR"   name="CMSIS/Lib/IAR/iar_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP_Lib/Source/IAR"/>
2578         <file category="library" condition="ARMv8MML_FP_LE_IAR"       name="CMSIS/Lib/IAR/iar_ARMv8MMLlfdp_math.a"  src="CMSIS/DSP_Lib/Source/IAR"/>
2579         <file category="library" condition="ARMv8MML_DSP_NOFPU_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLld_math.a"    src="CMSIS/DSP_Lib/Source/IAR"/>
2580         <file category="library" condition="ARMv8MML_DSP_SP_LE_IAR"   name="CMSIS/Lib/IAR/iar_ARMv8MMLldfsp_math.a" src="CMSIS/DSP_Lib/Source/IAR"/>
2581         <!--file category="library" condition="ARMv8MML_DSP_DP_LE_IAR"   name="CMSIS/Lib/IAR/iar_ARMv8MMLldfdp_math.a" src="CMSIS/DSP_Lib/Source/IAR"/-->
2582
2583       </files>
2584     </component>
2585
2586     <!-- CMSIS-NN component -->
2587     <component Cclass="CMSIS" Cgroup="NN Lib" Cversion="1.0.0" condition="CMSIS NN">
2588       <description>CMSIS-NN Neural Network Library</description>
2589       <files>
2590         <file category="doc" name="CMSIS/Documentation/NN/html/index.html"/>
2591         <file category="header" name="CMSIS/NN/Include/arm_nnfunctions.h"/>
2592
2593         <file category="source" name="CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c"/>
2594         <file category="source" name="CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c"/>
2595         <file category="source" name="CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c"/>
2596         <file category="source" name="CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c"/>
2597
2598         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c"/>
2599         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c"/>
2600         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c"/>
2601         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c"/>
2602         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c"/>
2603         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c"/>
2604         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c"/>
2605         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c"/>
2606         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c"/>
2607         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c"/>
2608         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c"/>
2609
2610         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c"/>
2611         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c"/>
2612         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c"/>
2613         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c"/>
2614         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c"/>
2615         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c"/>
2616
2617         <file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c"/>
2618         <file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c"/>
2619         <file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c"/>
2620
2621         <file category="source" name="CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c"/>
2622
2623         <file category="source" name="CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.c"/>
2624         <file category="source" name="CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.c"/>
2625       </files>
2626     </component>
2627
2628     <!-- CMSIS-RTOS Keil RTX component -->
2629     <component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX" Cversion="4.81.1" Capiversion="1.0.0" isDefaultVariant="1" condition="RTOS RTX">
2630       <description>CMSIS-RTOS RTX implementation for Cortex-M, SC000, and SC300</description>
2631       <RTE_Components_h>
2632         <!-- the following content goes into file 'RTE_Components.h' -->
2633         #define RTE_CMSIS_RTOS                  /* CMSIS-RTOS */
2634         #define RTE_CMSIS_RTOS_RTX              /* CMSIS-RTOS Keil RTX */
2635       </RTE_Components_h>
2636       <files>
2637         <!-- CPU independent -->
2638         <file category="doc" name="CMSIS/Documentation/RTOS/html/rtxImplementation.html"/>
2639         <file category="header" name="CMSIS/RTOS/RTX/INC/cmsis_os.h"/>
2640         <file category="source" attr="config"   name="CMSIS/RTOS/RTX/Templates/RTX_Conf_CM.c" version="4.70.1"/>
2641
2642         <!-- RTX templates -->
2643         <file category="header" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/osObjects.h" select="CMSIS-RTOS 'main' function"/>
2644         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/main.c"      select="CMSIS-RTOS 'main' function"/>
2645         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MailQueue.c" select="CMSIS-RTOS Mail Queue"/>
2646         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MemPool.c"   select="CMSIS-RTOS Memory Pool"/>
2647         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MsgQueue.c"  select="CMSIS-RTOS Message Queue"/>
2648         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Mutex.c"     select="CMSIS-RTOS Mutex"/>
2649         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Semaphore.c" select="CMSIS-RTOS Semaphore"/>
2650         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Thread.c"    select="CMSIS-RTOS Thread"/>
2651         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Timer.c"     select="CMSIS-RTOS Timer"/>
2652         <!-- tool-chain specific template file -->
2653         <file category="source" attr="template" condition="ARMCC" name="CMSIS/RTOS/RTX/SRC/ARM/SVC_Table.s" select="CMSIS-RTOS User SVC"/>
2654         <file category="source" attr="template" condition="GCC"   name="CMSIS/RTOS/RTX/SRC/GCC/SVC_Table.S" select="CMSIS-RTOS User SVC"/>
2655         <file category="source" attr="template" condition="IAR"   name="CMSIS/RTOS/RTX/SRC/IAR/SVC_Table.s" select="CMSIS-RTOS User SVC"/>
2656
2657         <!-- CPU and Compiler dependent -->
2658         <!-- ARMCC -->
2659         <file category="library" condition="CM0_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
2660         <file category="library" condition="CM0_BE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
2661         <file category="library" condition="CM3_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
2662         <file category="library" condition="CM3_BE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
2663         <file category="library" condition="CM4_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
2664         <file category="library" condition="CM4_BE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
2665         <file category="library" condition="CM4_FP_LE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
2666         <file category="library" condition="CM4_FP_BE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
2667         <file category="library" condition="CM7_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
2668         <file category="library" condition="CM7_BE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
2669         <file category="library" condition="CM7_FP_LE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
2670         <file category="library" condition="CM7_FP_BE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
2671         <!-- GCC -->
2672         <file category="library" condition="CM0_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
2673         <file category="library" condition="CM0_BE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
2674         <file category="library" condition="CM3_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
2675         <file category="library" condition="CM3_BE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
2676         <file category="library" condition="CM4_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
2677         <file category="library" condition="CM4_BE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
2678         <file category="library" condition="CM4_FP_LE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
2679         <file category="library" condition="CM4_FP_BE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
2680         <file category="library" condition="CM7_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
2681         <file category="library" condition="CM7_BE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
2682         <file category="library" condition="CM7_FP_LE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
2683         <file category="library" condition="CM7_FP_BE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
2684         <!-- IAR -->
2685         <file category="library" condition="CM0_LE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
2686         <file category="library" condition="CM0_BE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
2687         <file category="library" condition="CM3_LE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
2688         <file category="library" condition="CM3_BE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
2689         <file category="library" condition="CM4_LE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
2690         <file category="library" condition="CM4_BE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
2691         <file category="library" condition="CM4_FP_LE_IAR"   name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
2692         <file category="library" condition="CM4_FP_BE_IAR"   name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
2693         <file category="library" condition="CM7_LE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
2694         <file category="library" condition="CM7_BE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
2695         <file category="library" condition="CM7_FP_LE_IAR"   name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
2696         <file category="library" condition="CM7_FP_BE_IAR"   name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
2697       </files>
2698     </component>
2699     <!-- CMSIS-RTOS Keil RTX component (IFX variant) -->
2700     <component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX" Cvariant="IFX" Cversion="4.81.1" Capiversion="1.0.0" condition="RTOS RTX IFX">
2701       <description>CMSIS-RTOS RTX implementation for Infineon XMC4 series affected by PMU_CM.001 errata</description>
2702       <RTE_Components_h>
2703         <!-- the following content goes into file 'RTE_Components.h' -->
2704         #define RTE_CMSIS_RTOS                  /* CMSIS-RTOS */
2705         #define RTE_CMSIS_RTOS_RTX              /* CMSIS-RTOS Keil RTX */
2706       </RTE_Components_h>
2707       <files>
2708         <!-- CPU independent -->
2709         <file category="doc" name="CMSIS/Documentation/RTOS/html/rtxImplementation.html"/>
2710         <file category="header" name="CMSIS/RTOS/RTX/INC/cmsis_os.h"/>
2711         <file category="source" attr="config"   name="CMSIS/RTOS/RTX/Templates/RTX_Conf_CM.c" version="4.70.1"/>
2712
2713         <!-- RTX templates -->
2714         <file category="header" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/osObjects.h" select="CMSIS-RTOS 'main' function"/>
2715         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/main.c"      select="CMSIS-RTOS 'main' function"/>
2716         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MailQueue.c" select="CMSIS-RTOS Mail Queue"/>
2717         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MemPool.c"   select="CMSIS-RTOS Memory Pool"/>
2718         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MsgQueue.c"  select="CMSIS-RTOS Message Queue"/>
2719         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Mutex.c"     select="CMSIS-RTOS Mutex"/>
2720         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Semaphore.c" select="CMSIS-RTOS Semaphore"/>
2721         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Thread.c"    select="CMSIS-RTOS Thread"/>
2722         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Timer.c"     select="CMSIS-RTOS Timer"/>
2723         <!-- tool-chain specific template file -->
2724         <file category="source" attr="template" condition="ARMCC" name="CMSIS/RTOS/RTX/SRC/ARM/SVC_Table.s" select="CMSIS-RTOS User SVC"/>
2725         <file category="source" attr="template" condition="GCC"   name="CMSIS/RTOS/RTX/SRC/GCC/SVC_Table.S" select="CMSIS-RTOS User SVC"/>
2726         <file category="source" attr="template" condition="IAR"   name="CMSIS/RTOS/RTX/SRC/IAR/SVC_Table.s" select="CMSIS-RTOS User SVC"/>
2727
2728         <!-- CPU and Compiler dependent -->
2729         <!-- ARMCC -->
2730         <file category="library" condition="CM4_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_IFX.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
2731         <file category="library" condition="CM4_FP_LE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_IFX.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
2732         <!-- GCC -->
2733         <file category="library" condition="CM4_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_IFX.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
2734         <file category="library" condition="CM4_FP_LE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_IFX.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
2735         <!-- IAR -->
2736       </files>
2737     </component>
2738
2739     <!-- CMSIS-RTOS Keil RTX5 component -->
2740     <component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX5" Cversion="5.3.1" Capiversion="1.0.0" condition="RTOS RTX5">
2741       <description>CMSIS-RTOS RTX5 implementation for Cortex-M, SC000, and SC300</description>
2742       <RTE_Components_h>
2743         <!-- the following content goes into file 'RTE_Components.h' -->
2744         #define RTE_CMSIS_RTOS                  /* CMSIS-RTOS */
2745         #define RTE_CMSIS_RTOS_RTX5             /* CMSIS-RTOS Keil RTX5 */
2746       </RTE_Components_h>
2747       <files>
2748         <!-- RTX header file -->
2749         <file category="header" name="CMSIS/RTOS2/RTX/Include1/cmsis_os.h"/>
2750         <!-- RTX compatibility module for API V1 -->
2751         <file category="source" name="CMSIS/RTOS2/RTX/Library/cmsis_os1.c"/>
2752       </files>
2753     </component>
2754
2755     <!-- CMSIS-RTOS2 Keil RTX5 component -->
2756     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cversion="5.3.1" Capiversion="2.1.2" condition="RTOS2 RTX5 Lib">
2757       <description>CMSIS-RTOS2 RTX5 for Cortex-M, SC000, C300 and Armv8-M (Library)</description>
2758       <RTE_Components_h>
2759         <!-- the following content goes into file 'RTE_Components.h' -->
2760         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
2761         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
2762       </RTE_Components_h>
2763       <files>
2764         <!-- RTX documentation -->
2765         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
2766
2767         <!-- RTX header files -->
2768         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
2769
2770         <!-- RTX configuration -->
2771         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.3.0"/>
2772         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
2773
2774         <!-- RTX templates -->
2775         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.0.0" select="CMSIS-RTOS2 'main' function"/>
2776         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
2777         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
2778         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
2779         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
2780         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
2781         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
2782         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
2783         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
2784         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
2785
2786         <!-- RTX library configuration -->
2787         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
2788
2789         <!-- RTX libraries (CPU and Compiler dependent) -->
2790         <!-- ARMCC -->
2791         <file category="library" condition="CM0_LE_ARMCC"         name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM0.lib"    src="CMSIS/RTOS2/RTX/Source"/>
2792         <file category="library" condition="CM3_LE_ARMCC"         name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM3.lib"    src="CMSIS/RTOS2/RTX/Source"/>
2793         <file category="library" condition="CM4_LE_ARMCC"         name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM3.lib"    src="CMSIS/RTOS2/RTX/Source"/>
2794         <file category="library" condition="CM4_FP_LE_ARMCC"      name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM4F.lib"   src="CMSIS/RTOS2/RTX/Source"/>
2795         <file category="library" condition="CM7_LE_ARMCC"         name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM3.lib"    src="CMSIS/RTOS2/RTX/Source"/>
2796         <file category="library" condition="CM7_FP_LE_ARMCC"      name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM4F.lib"   src="CMSIS/RTOS2/RTX/Source"/>
2797         <file category="library" condition="CM23_LE_ARMCC"        name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MB.lib"   src="CMSIS/RTOS2/RTX/Source"/>
2798         <file category="library" condition="CM33_LE_ARMCC"        name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib"   src="CMSIS/RTOS2/RTX/Source"/>
2799         <file category="library" condition="CM33_FP_LE_ARMCC"     name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib"  src="CMSIS/RTOS2/RTX/Source"/>
2800         <file category="library" condition="ARMv8MBL_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MB.lib"   src="CMSIS/RTOS2/RTX/Source"/>
2801         <file category="library" condition="ARMv8MML_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib"   src="CMSIS/RTOS2/RTX/Source"/>
2802         <file category="library" condition="ARMv8MML_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib"  src="CMSIS/RTOS2/RTX/Source"/>
2803         <!-- GCC -->
2804         <file category="library" condition="CM0_LE_GCC"           name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM0.a"   src="CMSIS/RTOS2/RTX/Source"/>
2805         <file category="library" condition="CM3_LE_GCC"           name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a"   src="CMSIS/RTOS2/RTX/Source"/>
2806         <file category="library" condition="CM4_LE_GCC"           name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a"   src="CMSIS/RTOS2/RTX/Source"/>
2807         <file category="library" condition="CM4_FP_LE_GCC"        name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM4F.a"  src="CMSIS/RTOS2/RTX/Source"/>
2808         <file category="library" condition="CM7_LE_GCC"           name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a"   src="CMSIS/RTOS2/RTX/Source"/>
2809         <file category="library" condition="CM7_FP_LE_GCC"        name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM4F.a"  src="CMSIS/RTOS2/RTX/Source"/>
2810         <file category="library" condition="CM23_LE_GCC"          name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MB.a"  src="CMSIS/RTOS2/RTX/Source"/>
2811         <file category="library" condition="CM33_LE_GCC"          name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a"  src="CMSIS/RTOS2/RTX/Source"/>
2812         <file category="library" condition="CM33_FP_LE_GCC"       name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
2813         <file category="library" condition="ARMv8MBL_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MB.a"  src="CMSIS/RTOS2/RTX/Source"/>
2814         <file category="library" condition="ARMv8MML_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a"  src="CMSIS/RTOS2/RTX/Source"/>
2815         <file category="library" condition="ARMv8MML_FP_LE_GCC"   name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
2816         <!-- IAR -->
2817         <file category="library" condition="CM0_LE_IAR"           name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM0.a"      src="CMSIS/RTOS2/RTX/Source"/>
2818         <file category="library" condition="CM3_LE_IAR"           name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM3.a"      src="CMSIS/RTOS2/RTX/Source"/>
2819         <file category="library" condition="CM4_LE_IAR"           name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM3.a"      src="CMSIS/RTOS2/RTX/Source"/>
2820         <file category="library" condition="CM4_FP_LE_IAR"        name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM4F.a"     src="CMSIS/RTOS2/RTX/Source"/>
2821         <file category="library" condition="CM7_LE_IAR"           name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM3.a"      src="CMSIS/RTOS2/RTX/Source"/>
2822         <file category="library" condition="CM7_FP_LE_IAR"        name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM4F.a"     src="CMSIS/RTOS2/RTX/Source"/>
2823       </files>
2824     </component>
2825     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library_NS" Cversion="5.3.1" Capiversion="2.1.2" condition="RTOS2 RTX5 NS">
2826       <description>CMSIS-RTOS2 RTX5 for Armv8-M Non-Secure Domain (Library)</description>
2827       <RTE_Components_h>
2828         <!-- the following content goes into file 'RTE_Components.h' -->
2829         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
2830         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
2831         #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS  /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */
2832       </RTE_Components_h>
2833       <files>
2834         <!-- RTX documentation -->
2835         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
2836
2837         <!-- RTX header files -->
2838         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
2839
2840         <!-- RTX configuration -->
2841         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.3.0"/>
2842         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
2843
2844         <!-- RTX templates -->
2845         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.0.0" select="CMSIS-RTOS2 'main' function"/>
2846         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
2847         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
2848         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
2849         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
2850         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
2851         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
2852         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
2853         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
2854         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
2855
2856         <!-- RTX library configuration -->
2857         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
2858
2859         <!-- RTX libraries (CPU and Compiler dependent) -->
2860         <!-- ARMCC -->
2861         <file category="library" condition="CM23_LE_ARMCC"        name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MBN.lib"   src="CMSIS/RTOS2/RTX/Source"/>
2862         <file category="library" condition="CM33_LE_ARMCC"        name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib"   src="CMSIS/RTOS2/RTX/Source"/>
2863         <file category="library" condition="CM33_FP_LE_ARMCC"     name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib"  src="CMSIS/RTOS2/RTX/Source"/>
2864         <file category="library" condition="ARMv8MBL_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MBN.lib"   src="CMSIS/RTOS2/RTX/Source"/>
2865         <file category="library" condition="ARMv8MML_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib"   src="CMSIS/RTOS2/RTX/Source"/>
2866         <file category="library" condition="ARMv8MML_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib"  src="CMSIS/RTOS2/RTX/Source"/>
2867         <!-- GCC -->
2868         <file category="library" condition="CM23_LE_GCC"          name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MBN.a"  src="CMSIS/RTOS2/RTX/Source"/>
2869         <file category="library" condition="CM33_LE_GCC"          name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a"  src="CMSIS/RTOS2/RTX/Source"/>
2870         <file category="library" condition="CM33_FP_LE_GCC"       name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
2871         <file category="library" condition="ARMv8MBL_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MBN.a"  src="CMSIS/RTOS2/RTX/Source"/>
2872         <file category="library" condition="ARMv8MML_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a"  src="CMSIS/RTOS2/RTX/Source"/>
2873         <file category="library" condition="ARMv8MML_FP_LE_GCC"   name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
2874       </files>
2875     </component>
2876     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cversion="5.3.1" Capiversion="2.1.2" condition="RTOS2 RTX5">
2877       <description>CMSIS-RTOS2 RTX5 for Cortex-M, SC000, C300 and Armv8-M (Source)</description>
2878       <RTE_Components_h>
2879         <!-- the following content goes into file 'RTE_Components.h' -->
2880         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
2881         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
2882         #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
2883       </RTE_Components_h>
2884       <files>
2885         <!-- RTX documentation -->
2886         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
2887
2888         <!-- RTX header files -->
2889         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
2890
2891         <!-- RTX configuration -->
2892         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.3.0"/>
2893         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
2894
2895         <!-- RTX templates -->
2896         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.0.0" select="CMSIS-RTOS2 'main' function"/>
2897         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
2898         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
2899         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
2900         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
2901         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
2902         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
2903         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
2904         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
2905         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
2906
2907         <!-- RTX sources (core) -->
2908         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_kernel.c"/>
2909         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_thread.c"/>
2910         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_delay.c"/>
2911         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_timer.c"/>
2912         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evflags.c"/>
2913         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mutex.c"/>
2914         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_semaphore.c"/>
2915         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_memory.c"/>
2916         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mempool.c"/>
2917         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c"/>
2918         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_system.c"/>
2919         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evr.c"/>
2920         <!-- RTX sources (library configuration) -->
2921         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
2922         <!-- RTX sources (handlers ARMCC) -->
2923         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm0.s"         condition="CM0_ARMCC"/>
2924         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm3.s"         condition="CM3_ARMCC"/>
2925         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm3.s"         condition="CM4_ARMCC"/>
2926         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm4f.s"        condition="CM4_FP_ARMCC"/>
2927         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm3.s"         condition="CM7_ARMCC"/>
2928         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm4f.s"        condition="CM7_FP_ARMCC"/>
2929         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl.s"    condition="CM23_ARMCC"/>
2930         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="CM33_ARMCC"/>
2931         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="CM33_FP_ARMCC"/>
2932         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl.s"    condition="ARMv8MBL_ARMCC"/>
2933         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="ARMv8MML_ARMCC"/>
2934         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="ARMv8MML_FP_ARMCC"/>
2935         <!-- RTX sources (handlers GCC) -->
2936         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm0.S"         condition="CM0_GCC"/>
2937         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm3.S"         condition="CM3_GCC"/>
2938         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm3.S"         condition="CM4_GCC"/>
2939         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm4f.S"        condition="CM4_FP_GCC"/>
2940         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm3.S"         condition="CM7_GCC"/>
2941         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm4f.S"        condition="CM7_FP_GCC"/>
2942         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S"    condition="CM23_GCC"/>
2943         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S"    condition="CM33_GCC"/>
2944         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp.S" condition="CM33_FP_GCC"/>
2945         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S"    condition="ARMv8MBL_GCC"/>
2946         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S"    condition="ARMv8MML_GCC"/>
2947         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp.S" condition="ARMv8MML_FP_GCC"/>
2948         <!-- RTX sources (handlers IAR) -->
2949         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm0.s"         condition="CM0_IAR"/>
2950         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm3.s"         condition="CM3_IAR"/>
2951         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm3.s"         condition="CM4_IAR"/>
2952         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm4f.s"        condition="CM4_FP_IAR"/>
2953         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm3.s"         condition="CM7_IAR"/>
2954         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm4f.s"        condition="CM7_FP_IAR"/>
2955         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s"    condition="CM23_IAR"/>
2956         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="CM33_IAR"/>
2957         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="CM33_FP_IAR"/>
2958         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s"    condition="ARMv8MBL_IAR"/>
2959         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="ARMv8MML_IAR"/>
2960         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="ARMv8MML_FP_IAR"/>
2961         <!-- OS Tick (SysTick) -->
2962         <file category="source" name="CMSIS/RTOS2/Source/os_systick.c"/>
2963       </files>
2964     </component>
2965     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cversion="5.3.1" Capiversion="2.1.2" condition="RTOS2 RTX5 v7-A">
2966       <description>CMSIS-RTOS2 RTX5 for Armv7-A (Source)</description>
2967       <RTE_Components_h>
2968         <!-- the following content goes into file 'RTE_Components.h' -->
2969         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
2970         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
2971         #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
2972       </RTE_Components_h>
2973       <files>
2974         <!-- RTX documentation -->
2975         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
2976
2977         <!-- RTX header files -->
2978         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
2979
2980         <!-- RTX configuration -->
2981         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.3.0"/>
2982         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
2983
2984         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/handlers.c"    version="5.1.0"/>
2985
2986         <!-- RTX templates -->
2987         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.0.0" select="CMSIS-RTOS2 'main' function"/>
2988         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
2989         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
2990         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
2991         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
2992         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
2993         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
2994         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
2995         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
2996         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
2997
2998         <!-- RTX sources (core) -->
2999         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_kernel.c"/>
3000         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_thread.c"/>
3001         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_delay.c"/>
3002         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_timer.c"/>
3003         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evflags.c"/>
3004         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mutex.c"/>
3005         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_semaphore.c"/>
3006         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_memory.c"/>
3007         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mempool.c"/>
3008         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c"/>
3009         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_system.c"/>
3010         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evr.c"/>
3011         <!-- RTX sources (library configuration) -->
3012         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
3013         <!-- RTX sources (handlers ARMCC) -->
3014         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_ca.s"          condition="CA_ARMCC5"/>
3015         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_ca.S"          condition="CA_ARMCC6"/>
3016         <!-- RTX sources (handlers GCC) -->
3017         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_ca.S"          condition="CA_GCC"/>
3018         <!-- RTX sources (handlers IAR) -->
3019         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_ca.s"          condition="CA_IAR"/>
3020       </files>
3021     </component>
3022     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source_NS" Cversion="5.3.1" Capiversion="2.1.2" condition="RTOS2 RTX5 NS">
3023       <description>CMSIS-RTOS2 RTX5 for Armv8-M Non-Secure Domain (Source)</description>
3024       <RTE_Components_h>
3025         <!-- the following content goes into file 'RTE_Components.h' -->
3026         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
3027         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
3028         #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
3029         #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS  /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */
3030       </RTE_Components_h>
3031       <files>
3032         <!-- RTX documentation -->
3033         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
3034
3035         <!-- RTX header files -->
3036         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
3037
3038         <!-- RTX configuration -->
3039         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.3.0"/>
3040         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
3041
3042         <!-- RTX templates -->
3043         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.0.0" select="CMSIS-RTOS2 'main' function"/>
3044         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
3045         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
3046         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
3047         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
3048         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
3049         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
3050         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
3051         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
3052         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
3053
3054         <!-- RTX sources (core) -->
3055         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_kernel.c"/>
3056         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_thread.c"/>
3057         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_delay.c"/>
3058         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_timer.c"/>
3059         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evflags.c"/>
3060         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mutex.c"/>
3061         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_semaphore.c"/>
3062         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_memory.c"/>
3063         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mempool.c"/>
3064         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c"/>
3065         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_system.c"/>
3066         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evr.c"/>
3067         <!-- RTX sources (library configuration) -->
3068         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
3069         <!-- RTX sources (ARMCC handlers) -->
3070         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl_ns.s"    condition="CM23_ARMCC"/>
3071         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="CM33_ARMCC"/>
3072         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="CM33_FP_ARMCC"/>
3073         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl_ns.s"    condition="ARMv8MBL_ARMCC"/>
3074         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="ARMv8MML_ARMCC"/>
3075         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="ARMv8MML_FP_ARMCC"/>
3076         <!-- RTX sources (GCC handlers) -->
3077         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl_ns.S"    condition="CM23_GCC"/>
3078         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_ns.S"    condition="CM33_GCC"/>
3079         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp_ns.S" condition="CM33_FP_GCC"/>
3080         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl_ns.S"    condition="ARMv8MBL_GCC"/>
3081         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_ns.S"    condition="ARMv8MML_GCC"/>
3082         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp_ns.S" condition="ARMv8MML_FP_GCC"/>
3083         <!-- RTX sources (IAR handlers) -->
3084         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl_ns.s"    condition="CM23_IAR"/>
3085         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="CM33_IAR"/>
3086         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="CM33_FP_IAR"/>
3087         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl_ns.s"    condition="ARMv8MBL_IAR"/>
3088         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="ARMv8MML_IAR"/>
3089         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="ARMv8MML_FP_IAR"/>
3090         <!-- OS Tick (SysTick) -->
3091         <file category="source" name="CMSIS/RTOS2/Source/os_systick.c"/>
3092       </files>
3093     </component>
3094
3095   </components>
3096
3097   <boards>
3098     <board name="uVision Simulator" vendor="Keil">
3099       <description>uVision Simulator</description>
3100       <mountedDevice    deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0"/>
3101       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0P"/>
3102       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0P_MPU"/>
3103       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM3"/>
3104       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM4"/>
3105       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM4_FP"/>
3106       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7"/>
3107       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7_SP"/>
3108       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7_DP"/>
3109       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MBL"/>
3110       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML"/>
3111       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML_SP"/>
3112       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML_DP"/>
3113       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM23"/>
3114       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM23_TZ"/>
3115       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33"/>
3116       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_TZ"/>
3117       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_DSP_FP"/>
3118       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_DSP_FP_TZ"/>
3119     </board>
3120
3121     <board name="Fixed Virtual Platform" vendor="ARM">
3122       <description>Fixed Virtual Platform</description>
3123       <mountedDevice    deviceIndex="0" Dvendor="ARM:82" Dname="ARMCA5"/>
3124       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCA7"/>
3125       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCA9"/>
3126     </board>
3127   </boards>
3128
3129   <examples>
3130     <example name="DSP_Lib Class Marks example" doc="Abstract.txt" folder="CMSIS/DSP_Lib/Examples/ARM/arm_class_marks_example">
3131       <description>DSP_Lib Class Marks example</description>
3132       <board name="uVision Simulator" vendor="Keil"/>
3133       <project>
3134         <environment name="uv" load="arm_class_marks_example.uvprojx"/>
3135       </project>
3136       <attributes>
3137         <component Cclass="CMSIS" Cgroup="CORE"/>
3138         <component Cclass="CMSIS" Cgroup="DSP"/>
3139         <component Cclass="Device" Cgroup="Startup"/>
3140         <category>Getting Started</category>
3141       </attributes>
3142     </example>
3143
3144     <example name="DSP_Lib Convolution example" doc="Abstract.txt" folder="CMSIS/DSP_Lib/Examples/ARM/arm_convolution_example">
3145       <description>DSP_Lib Convolution example</description>
3146       <board name="uVision Simulator" vendor="Keil"/>
3147       <project>
3148         <environment name="uv" load="arm_convolution_example.uvprojx"/>
3149       </project>
3150       <attributes>
3151         <component Cclass="CMSIS" Cgroup="CORE"/>
3152         <component Cclass="CMSIS" Cgroup="DSP"/>
3153         <component Cclass="Device" Cgroup="Startup"/>
3154         <category>Getting Started</category>
3155       </attributes>
3156     </example>
3157
3158     <example name="DSP_Lib Dotproduct example" doc="Abstract.txt" folder="CMSIS/DSP_Lib/Examples/ARM/arm_dotproduct_example">
3159       <description>DSP_Lib Dotproduct example</description>
3160       <board name="uVision Simulator" vendor="Keil"/>
3161       <project>
3162         <environment name="uv" load="arm_dotproduct_example.uvprojx"/>
3163       </project>
3164       <attributes>
3165         <component Cclass="CMSIS" Cgroup="CORE"/>
3166         <component Cclass="CMSIS" Cgroup="DSP"/>
3167         <component Cclass="Device" Cgroup="Startup"/>
3168         <category>Getting Started</category>
3169       </attributes>
3170     </example>
3171
3172     <example name="DSP_Lib FFT Bin example" doc="Abstract.txt" folder="CMSIS/DSP_Lib/Examples/ARM/arm_fft_bin_example">
3173       <description>DSP_Lib FFT Bin example</description>
3174       <board name="uVision Simulator" vendor="Keil"/>
3175       <project>
3176         <environment name="uv" load="arm_fft_bin_example.uvprojx"/>
3177       </project>
3178       <attributes>
3179         <component Cclass="CMSIS" Cgroup="CORE"/>
3180         <component Cclass="CMSIS" Cgroup="DSP"/>
3181         <component Cclass="Device" Cgroup="Startup"/>
3182         <category>Getting Started</category>
3183       </attributes>
3184     </example>
3185
3186     <example name="DSP_Lib FIR example" doc="Abstract.txt" folder="CMSIS/DSP_Lib/Examples/ARM/arm_fir_example">
3187       <description>DSP_Lib FIR example</description>
3188       <board name="uVision Simulator" vendor="Keil"/>
3189       <project>
3190         <environment name="uv" load="arm_fir_example.uvprojx"/>
3191       </project>
3192       <attributes>
3193         <component Cclass="CMSIS" Cgroup="CORE"/>
3194         <component Cclass="CMSIS" Cgroup="DSP"/>
3195         <component Cclass="Device" Cgroup="Startup"/>
3196         <category>Getting Started</category>
3197       </attributes>
3198     </example>
3199
3200     <example name="DSP_Lib Graphic Equalizer example" doc="Abstract.txt" folder="CMSIS/DSP_Lib/Examples/ARM/arm_graphic_equalizer_example">
3201       <description>DSP_Lib Graphic Equalizer example</description>
3202       <board name="uVision Simulator" vendor="Keil"/>
3203       <project>
3204         <environment name="uv" load="arm_graphic_equalizer_example.uvprojx"/>
3205       </project>
3206       <attributes>
3207         <component Cclass="CMSIS" Cgroup="CORE"/>
3208         <component Cclass="CMSIS" Cgroup="DSP"/>
3209         <component Cclass="Device" Cgroup="Startup"/>
3210         <category>Getting Started</category>
3211       </attributes>
3212     </example>
3213
3214     <example name="DSP_Lib Linear Interpolation example" doc="Abstract.txt" folder="CMSIS/DSP_Lib/Examples/ARM/arm_linear_interp_example">
3215       <description>DSP_Lib Linear Interpolation example</description>
3216       <board name="uVision Simulator" vendor="Keil"/>
3217       <project>
3218         <environment name="uv" load="arm_linear_interp_example.uvprojx"/>
3219       </project>
3220       <attributes>
3221         <component Cclass="CMSIS" Cgroup="CORE"/>
3222         <component Cclass="CMSIS" Cgroup="DSP"/>
3223         <component Cclass="Device" Cgroup="Startup"/>
3224         <category>Getting Started</category>
3225       </attributes>
3226     </example>
3227
3228     <example name="DSP_Lib Matrix example" doc="Abstract.txt" folder="CMSIS/DSP_Lib/Examples/ARM/arm_matrix_example">
3229       <description>DSP_Lib Matrix example</description>
3230       <board name="uVision Simulator" vendor="Keil"/>
3231       <project>
3232         <environment name="uv" load="arm_matrix_example.uvprojx"/>
3233       </project>
3234       <attributes>
3235         <component Cclass="CMSIS" Cgroup="CORE"/>
3236         <component Cclass="CMSIS" Cgroup="DSP"/>
3237         <component Cclass="Device" Cgroup="Startup"/>
3238         <category>Getting Started</category>
3239       </attributes>
3240     </example>
3241
3242     <example name="DSP_Lib Signal Convergence example" doc="Abstract.txt" folder="CMSIS/DSP_Lib/Examples/ARM/arm_signal_converge_example">
3243       <description>DSP_Lib Signal Convergence example</description>
3244       <board name="uVision Simulator" vendor="Keil"/>
3245       <project>
3246         <environment name="uv" load="arm_signal_converge_example.uvprojx"/>
3247       </project>
3248       <attributes>
3249         <component Cclass="CMSIS" Cgroup="CORE"/>
3250         <component Cclass="CMSIS" Cgroup="DSP"/>
3251         <component Cclass="Device" Cgroup="Startup"/>
3252         <category>Getting Started</category>
3253       </attributes>
3254     </example>
3255
3256     <example name="DSP_Lib Sinus/Cosinus example" doc="Abstract.txt" folder="CMSIS/DSP_Lib/Examples/ARM/arm_sin_cos_example">
3257       <description>DSP_Lib Sinus/Cosinus example</description>
3258       <board name="uVision Simulator" vendor="Keil"/>
3259       <project>
3260         <environment name="uv" load="arm_sin_cos_example.uvprojx"/>
3261       </project>
3262       <attributes>
3263         <component Cclass="CMSIS" Cgroup="CORE"/>
3264         <component Cclass="CMSIS" Cgroup="DSP"/>
3265         <component Cclass="Device" Cgroup="Startup"/>
3266         <category>Getting Started</category>
3267       </attributes>
3268     </example>
3269
3270     <example name="DSP_Lib Variance example" doc="Abstract.txt" folder="CMSIS/DSP_Lib/Examples/ARM/arm_variance_example">
3271       <description>DSP_Lib Variance example</description>
3272       <board name="uVision Simulator" vendor="Keil"/>
3273       <project>
3274         <environment name="uv" load="arm_variance_example.uvprojx"/>
3275       </project>
3276       <attributes>
3277         <component Cclass="CMSIS" Cgroup="CORE"/>
3278         <component Cclass="CMSIS" Cgroup="DSP"/>
3279         <component Cclass="Device" Cgroup="Startup"/>
3280         <category>Getting Started</category>
3281       </attributes>
3282     </example>
3283
3284     <example name="NN Library CIFAR10" doc="readme.txt" folder="CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10">
3285       <description>Neural Network CIFAR10 example</description>
3286       <board name="uVision Simulator" vendor="Keil"/>
3287       <project>
3288         <environment name="uv" load="arm_nnexamples_cifar10.uvprojx"/>
3289       </project>
3290       <attributes>
3291         <component Cclass="CMSIS" Cgroup="CORE"/>
3292         <component Cclass="CMSIS" Cgroup="DSP"/>
3293         <component Cclass="CMSIS" Cgroup="NN Lib"/>
3294         <component Cclass="Device" Cgroup="Startup"/>
3295         <category>Getting Started</category>
3296       </attributes>
3297     </example>
3298
3299     <example name="NN Library GRU" doc="readme.txt" folder="CMSIS/NN/Examples/ARM/arm_nn_examples/gru">
3300       <description>Neural Network GRU example</description>
3301       <board name="uVision Simulator" vendor="Keil"/>
3302       <project>
3303         <environment name="uv" load="arm_nnexamples_gru.uvprojx"/>
3304       </project>
3305       <attributes>
3306         <component Cclass="CMSIS" Cgroup="CORE"/>
3307         <component Cclass="CMSIS" Cgroup="DSP"/>
3308         <component Cclass="CMSIS" Cgroup="NN Lib"/>
3309         <component Cclass="Device" Cgroup="Startup"/>
3310         <category>Getting Started</category>
3311       </attributes>
3312     </example>
3313
3314     <example name="CMSIS-RTOS2 Blinky" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/Blinky">
3315       <description>CMSIS-RTOS2 Blinky example</description>
3316       <board name="uVision Simulator" vendor="Keil"/>
3317       <project>
3318         <environment name="uv" load="Blinky.uvprojx"/>
3319       </project>
3320       <attributes>
3321         <component Cclass="CMSIS" Cgroup="CORE"/>
3322         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3323         <component Cclass="Device" Cgroup="Startup"/>
3324         <category>Getting Started</category>
3325       </attributes>
3326     </example>
3327
3328     <example name="CMSIS-RTOS2 RTX5 Migration" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/Migration">
3329       <description>CMSIS-RTOS2 mixed API v1 and v2</description>
3330       <board name="uVision Simulator" vendor="Keil"/>
3331       <project>
3332         <environment name="uv" load="Blinky.uvprojx"/>
3333       </project>
3334       <attributes>
3335         <component Cclass="CMSIS" Cgroup="CORE"/>
3336         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3337         <component Cclass="Device" Cgroup="Startup"/>
3338         <category>Getting Started</category>
3339       </attributes>
3340     </example>
3341
3342     <example name="CMSIS-RTOS2 RTX5 Message Queue" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/MsgQueue">
3343       <description>CMSIS-RTOS2 Message Queue Example</description>
3344       <board name="uVision Simulator" vendor="Keil"/>
3345       <project>
3346         <environment name="uv" load="MsqQueue.uvprojx"/>
3347       </project>
3348       <attributes>
3349         <component Cclass="CMSIS" Cgroup="CORE"/>
3350         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3351         <component Cclass="Compiler" Cgroup="EventRecorder"/>
3352         <component Cclass="Device" Cgroup="Startup"/>
3353         <category>Getting Started</category>
3354       </attributes>
3355     </example>
3356
3357     <example name="CMSIS-RTOS2 RTX5 Memory Pool" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/MemPool">
3358       <description>CMSIS-RTOS2 Memory Pool Example</description>
3359       <board name="Fixed Virtual Platform" vendor="ARM"/>
3360       <project>
3361         <environment name="uv" load="MemPool.uvprojx"/>
3362       </project>
3363       <attributes>
3364         <component Cclass="CMSIS" Cgroup="CORE"/>
3365         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3366         <component Cclass="Compiler" Cgroup="EventRecorder"/>
3367         <component Cclass="Device" Cgroup="Startup"/>
3368         <category>Getting Started</category>
3369       </attributes>
3370     </example>
3371
3372     <example name="TrustZone for ARMv8-M No RTOS" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/NoRTOS">
3373       <description>Bare-metal secure/non-secure example without RTOS</description>
3374       <board name="uVision Simulator" vendor="Keil"/>
3375       <project>
3376         <environment name="uv" load="NoRTOS.uvmpw"/>
3377       </project>
3378       <attributes>
3379         <component Cclass="CMSIS" Cgroup="CORE"/>
3380         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3381         <component Cclass="Device" Cgroup="Startup"/>
3382         <category>Getting Started</category>
3383       </attributes>
3384     </example>
3385
3386     <example name="TrustZone for ARMv8-M RTOS"  doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS">
3387       <description>Secure/non-secure RTOS example with thread context management</description>
3388       <board name="uVision Simulator" vendor="Keil"/>
3389       <project>
3390         <environment name="uv" load="RTOS.uvmpw"/>
3391       </project>
3392       <attributes>
3393         <component Cclass="CMSIS" Cgroup="CORE"/>
3394         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3395         <component Cclass="Device" Cgroup="Startup"/>
3396         <category>Getting Started</category>
3397       </attributes>
3398     </example>
3399
3400     <example name="TrustZone for ARMv8-M RTOS Security Tests"  doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults">
3401       <description>Secure/non-secure RTOS example with security test cases and system recovery</description>
3402       <board name="uVision Simulator" vendor="Keil"/>
3403       <project>
3404         <environment name="uv" load="RTOS_Faults.uvmpw"/>
3405       </project>
3406       <attributes>
3407         <component Cclass="CMSIS" Cgroup="CORE"/>
3408         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3409         <component Cclass="Device" Cgroup="Startup"/>
3410         <category>Getting Started</category>
3411       </attributes>
3412     </example>
3413
3414   </examples>
3415
3416 </package>