begriffs open source - cmsis/blob - ARM.CMSIS.pdsc

   1 <?xml version="1.0" encoding="UTF-8"?>
   2
   3 <package schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="PACK.xsd">
   4   <name>CMSIS</name>
   5   <description>CMSIS (Cortex Microcontroller Software Interface Standard)</description>
   6   <vendor>ARM</vendor>
   7   <!-- <license>license.txt</license> -->
   8   <url>http://www.keil.com/pack/</url>
   9
  10   <releases>
  11     <release version="5.4.1-dev0">
  12       Active development ...
  13       Added Cortex-M35P device support.
  14     </release>
  15     <release version="5.4.0" date="2018-08-01">
  16       Aligned pack structure with repository.
  17       The following folders are deprecated:
  18         - CMSIS/Include/
  19         - CMSIS/DSP_Lib/
  20
  21       CMSIS-Core(M): 5.1.2 (see revision history for details)
  22         - Added Cortex-M1 support (beta).
  23       CMSIS-Core(A): 1.1.2 (see revision history for details)
  24       CMSIS-NN: 1.1.0
  25         - Added new math functions.
  26       CMSIS-RTOS2:
  27         - API 2.1.3 (see revision history for details)
  28         - RTX 5.4.0 (see revision history for details)
  29           * Updated exception handling on Cortex-A
  30       CMSIS-Driver:
  31         - Flash Driver API V2.2.0
  32       Utilities:
  33         - SVDConv 3.3.21
  34         - PackChk 1.3.71
  35     </release>
  36     <release version="5.3.0" date="2018-02-22">
  37       Updated Arm company brand.
  38       CMSIS-Core(M): 5.1.1 (see revision history for details)
  39       CMSIS-Core(A): 1.1.1 (see revision history for details)
  40       CMSIS-DAP: 2.0.0 (see revision history for details)
  41       CMSIS-NN: 1.0.0
  42         - Initial contribution of the bare metal Neural Network Library.
  43       CMSIS-RTOS2:
  44         - RTX 5.3.0 (see revision history for details)
  45         - OS Tick API 1.0.1
  46     </release>
  47     <release version="5.2.0" date="2017-11-16">
  48       CMSIS-Core(M): 5.1.0 (see revision history for details)
  49         - Added MPU Functions for ARMv8-M for Cortex-M23/M33.
  50         - Added compiler_iccarm.h to replace compiler_iar.h shipped with the compiler.
  51       CMSIS-Core(A): 1.1.0 (see revision history for details)
  52         - Added compiler_iccarm.h.
  53         - Added additional access functions for physical timer.
  54       CMSIS-DAP: 1.2.0 (see revision history for details)
  55       CMSIS-DSP: 1.5.2 (see revision history for details)
  56       CMSIS-Driver: 2.6.0 (see revision history for details)
  57         - CAN Driver API V1.2.0
  58         - NAND Driver API V2.3.0
  59       CMSIS-RTOS:
  60         - RTX: added variant for Infineon XMC4 series affected by PMU_CM.001 errata.
  61       CMSIS-RTOS2:
  62         - API 2.1.2 (see revision history for details)
  63         - RTX 5.2.3 (see revision history for details)
  64       Devices:
  65         - Added GCC startup and linker script for Cortex-A9.
  66         - Added device ARMCM0plus_MPU for Cortex-M0+ with MPU.
  67         - Added IAR startup code for Cortex-A9
  68     </release>
  69     <release version="5.1.1" date="2017-09-19">
  70       CMSIS-RTOS2:
  71       - RTX 5.2.1 (see revision history for details)
  72     </release>
  73     <release version="5.1.0" date="2017-08-04">
  74       CMSIS-Core(M): 5.0.2 (see revision history for details)
  75       - Changed Version Control macros to be core agnostic.
  76       - Added MPU Functions for ARMv7-M for Cortex-M0+/M3/M4/M7.
  77       CMSIS-Core(A): 1.0.0 (see revision history for details)
  78       - Initial release
  79       - IRQ Controller API 1.0.0
  80       CMSIS-Driver: 2.05 (see revision history for details)
  81       - All typedefs related to status have been made volatile.
  82       CMSIS-RTOS2:
  83       - API 2.1.1 (see revision history for details)
  84       - RTX 5.2.0 (see revision history for details)
  85       - OS Tick API 1.0.0
  86       CMSIS-DSP: 1.5.2 (see revision history for details)
  87       - Fixed GNU Compiler specific diagnostics.
  88       CMSIS-Pack: 1.5.0 (see revision history for details)
  89       - added System Description File (*.SDF) Format
  90       CMSIS-Zone: 0.0.1 (Preview)
  91       - Initial specification draft
  92     </release>
  93     <release version="5.0.1" date="2017-02-03">
  94       Package Description:
  95       - added taxonomy for Cclass RTOS
  96       CMSIS-RTOS2:
  97       - API 2.1   (see revision history for details)
  98       - RTX 5.1.0 (see revision history for details)
  99       CMSIS-Core: 5.0.1 (see revision history for details)
 100       - Added __PACKED_STRUCT macro
 101       - Added uVisior support
 102       - Updated cmsis_armcc.h: corrected macro __ARM_ARCH_6M__
 103       - Updated template for secure main function (main_s.c)
 104       - Updated template for Context Management for ARMv8-M TrustZone (tz_context.c)
 105       CMSIS-DSP: 1.5.1 (see revision history for details)
 106       - added ARMv8M DSP libraries.
 107       CMSIS-Pack:1.4.9 (see revision history for details)
 108       - added Pack Index File specification and schema file
 109     </release>
 110     <release version="5.0.0" date="2016-11-11">
 111       Changed open source license to Apache 2.0
 112       CMSIS_Core:
 113        - Added support for Cortex-M23 and Cortex-M33.
 114        - Added ARMv8-M device configurations for mainline and baseline.
 115        - Added CMSE support and thread context management for TrustZone for ARMv8-M
 116        - Added cmsis_compiler.h to unify compiler behaviour.
 117        - Updated function SCB_EnableICache (for Cortex-M7).
 118        - Added functions: NVIC_GetEnableIRQ, SCB_GetFPUType
 119       CMSIS-RTOS:
 120         - bug fix in RTX 4.82 (see revision history for details)
 121       CMSIS-RTOS2:
 122         - new API including compatibility layer to CMSIS-RTOS
 123         - reference implementation based on RTX5
 124         - supports all Cortex-M variants including TrustZone for ARMv8-M
 125       CMSIS-SVD:
 126        - reworked SVD format documentation
 127        - removed SVD file database documentation as SVD files are distributed in packs
 128        - updated SVDConv for Win32 and Linux
 129       CMSIS-DSP:
 130        - Moved DSP libraries from CMSIS/DSP/Lib to CMSIS/Lib.
 131        - Added DSP libraries build projects to CMSIS pack.
 132     </release>
 133     <release version="4.5.0" date="2015-10-28">
 134       - CMSIS-Core     4.30.0  (see revision history for details)
 135       - CMSIS-DAP      1.1.0   (unchanged)
 136       - CMSIS-Driver   2.04.0  (see revision history for details)
 137       - CMSIS-DSP      1.4.7   (no source code change [still labeled 1.4.5], see revision history for details)
 138       - CMSIS-Pack     1.4.1   (see revision history for details)
 139       - CMSIS-RTOS     4.80.0  Restored time delay parameter 'millisec' old behavior (prior V4.79) for software compatibility. (see revision history for details)
 140       - CMSIS-SVD      1.3.1   (see revision history for details)
 141     </release>
 142     <release version="4.4.0" date="2015-09-11">
 143       - CMSIS-Core     4.20   (see revision history for details)
 144       - CMSIS-DSP      1.4.6  (no source code change [still labeled 1.4.5], see revision history for details)
 145       - CMSIS-Pack     1.4.0  (adding memory attributes, algorithm style)
 146       - CMSIS-Driver   2.03.0 (adding CAN [Controller Area Network] API)
 147       - CMSIS-RTOS
 148         -- API         1.02   (unchanged)
 149         -- RTX         4.79   (see revision history for details)
 150       - CMSIS-SVD      1.3.0  (see revision history for details)
 151       - CMSIS-DAP      1.1.0  (extended with SWO support)
 152     </release>
 153     <release version="4.3.0" date="2015-03-20">
 154       - CMSIS-Core     4.10   (Cortex-M7 extended Cache Maintenance functions)
 155       - CMSIS-DSP      1.4.5  (see revision history for details)
 156       - CMSIS-Driver   2.02   (adding SAI (Serial Audio Interface) API)
 157       - CMSIS-Pack     1.3.3  (Semantic Versioning, Generator extensions)
 158       - CMSIS-RTOS
 159         -- API         1.02   (unchanged)
 160         -- RTX         4.78   (see revision history for details)
 161       - CMSIS-SVD      1.2    (unchanged)
 162     </release>
 163     <release version="4.2.0" date="2014-09-24">
 164       Adding Cortex-M7 support
 165       - CMSIS-Core     4.00  (Cortex-M7 support, corrected C++ include guards in core header files)
 166       - CMSIS-DSP      1.4.4 (Cortex-M7 support and corrected out of bound issues)
 167       - CMSIS-Pack     1.3.1 (Cortex-M7 updates, clarification, corrected batch files in Tutorial)
 168       - CMSIS-SVD      1.2   (Cortex-M7 extensions)
 169       - CMSIS-RTOS RTX 4.75  (see revision history for details)
 170     </release>
 171     <release version="4.1.1" date="2014-06-30">
 172       - fixed conditions preventing the inclusion of the DSP library in projects for Infineon XMC4000 series devices
 173     </release>
 174     <release version="4.1.0" date="2014-06-12">
 175       - CMSIS-Driver   2.02  (incompatible update)
 176       - CMSIS-Pack     1.3   (see revision history for details)
 177       - CMSIS-DSP      1.4.2 (unchanged)
 178       - CMSIS-Core     3.30  (unchanged)
 179       - CMSIS-RTOS RTX 4.74  (unchanged)
 180       - CMSIS-RTOS API 1.02  (unchanged)
 181       - CMSIS-SVD      1.10  (unchanged)
 182       PACK:
 183       - removed G++ specific files from PACK
 184       - added Component Startup variant "C Startup"
 185       - added Pack Checking Utility
 186       - updated conditions to reflect tool-chain dependency
 187       - added Taxonomy for Graphics
 188       - updated Taxonomy for unified drivers from "Drivers" to "CMSIS Drivers"
 189     </release>
 190     <release version="4.0.0">
 191       - CMSIS-Driver   2.00  Preliminary (incompatible update)
 192       - CMSIS-Pack     1.1   Preliminary
 193       - CMSIS-DSP      1.4.2 (see revision history for details)
 194       - CMSIS-Core     3.30  (see revision history for details)
 195       - CMSIS-RTOS RTX 4.74  (see revision history for details)
 196       - CMSIS-RTOS API 1.02  (unchanged)
 197       - CMSIS-SVD      1.10  (unchanged)
 198     </release>
 199     <release version="3.20.4">
 200       - CMSIS-RTOS 4.74 (see revision history for details)
 201       - PACK Extensions (Boards, Device Features, Flash Programming, Generators, Configuration Wizard). Schema version 1.1.
 202     </release>
 203     <release version="3.20.3">
 204       - CMSIS-Driver API Version 1.10 ARM prefix added (incompatible change)
 205       - CMSIS-RTOS 4.73 (see revision history for details)
 206     </release>
 207     <release version="3.20.2">
 208       - CMSIS-Pack documentation has been added
 209       - CMSIS-Drivers header and documentation have been added to PACK
 210       - CMSIS-CORE, CMSIS-DSP, CMSIS-RTOS API and CMSIS-SVD remain unchanged
 211     </release>
 212     <release version="3.20.1">
 213       - CMSIS-RTOS Keil RTX V4.72 has been added to PACK
 214       - CMSIS-CORE, CMSIS-DSP, CMSIS-RTOS API and CMSIS-SVD remain unchanged
 215     </release>
 216     <release version="3.20.0">
 217       The software portions that are deployed in the application program are now under a BSD license which allows usage
 218       of CMSIS components in any commercial or open source projects.  The Pack Description file Arm.CMSIS.pdsc describes the use cases
 219       The individual components have been update as listed below:
 220       - CMSIS-CORE adds functions for setting breakpoints, supports the latest GCC Compiler, and contains several corrections.
 221       - CMSIS-DSP library is optimized for more performance and contains several bug fixes.
 222       - CMSIS-RTOS API is extended with capabilities for short timeouts, Kernel initialization, and prepared for a C++ interface.
 223       - CMSIS-SVD is unchanged.
 224     </release>
 225   </releases>
 226
 227   <taxonomy>
 228     <description Cclass="Board Support">Generic Interfaces for Evaluation and Development Boards</description>
 229     <description Cclass="CMSIS" doc="CMSIS/Documentation/General/html/index.html">Cortex Microcontroller Software Interface Components</description>
 230     <description Cclass="Device" doc="CMSIS/Documentation/Core/html/index.html">Startup, System Setup</description>
 231     <description Cclass="CMSIS Driver" doc="CMSIS/Documentation/Driver/html/index.html">Unified Device Drivers compliant to CMSIS-Driver Specifications</description>
 232     <description Cclass="File System">File Drive Support and File System</description>
 233     <description Cclass="Graphics">Graphical User Interface</description>
 234     <description Cclass="Network">Network Stack using Internet Protocols</description>
 235     <description Cclass="USB">Universal Serial Bus Stack</description>
 236     <description Cclass="Compiler">Compiler Software Extensions</description>
 237     <description Cclass="RTOS">Real-time Operating System</description>
 238   </taxonomy>
 239
 240   <devices>
 241     <!-- ******************************  Cortex-M0  ****************************** -->
 242     <family Dfamily="ARM Cortex M0" Dvendor="ARM:82">
 243       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/index.html" title="Cortex-M0 Device Generic Users Guide"/>
 244       <description>
 245 The Cortex-M0 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 246 - simple, easy-to-use programmers model
 247 - highly efficient ultra-low power operation
 248 - excellent code density
 249 - deterministic, high-performance interrupt handling
 250 - upward compatibility with the rest of the Cortex-M processor family.
 251       </description>
 252       <!-- debug svd="Device/ARM/SVD/ARMCM0.svd"/ SVD files do not contain any peripheral -->
 253       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 254       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 255       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 256
 257       <device Dname="ARMCM0">
 258         <processor Dcore="Cortex-M0" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
 259         <compile header="Device/ARM/ARMCM0/Include/ARMCM0.h" define="ARMCM0"/>
 260       </device>
 261     </family>
 262
 263     <!-- ******************************  Cortex-M0P  ****************************** -->
 264     <family Dfamily="ARM Cortex M0 plus" Dvendor="ARM:82">
 265       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0662b/index.html" title="Cortex-M0+ Device Generic Users Guide"/>
 266       <description>
 267 The Cortex-M0+ processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 268 - simple, easy-to-use programmers model
 269 - highly efficient ultra-low power operation
 270 - excellent code density
 271 - deterministic, high-performance interrupt handling
 272 - upward compatibility with the rest of the Cortex-M processor family.
 273       </description>
 274       <!-- debug svd="Device/ARM/SVD/ARMCM0P.svd"/ SVD files do not contain any peripheral -->
 275       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 276       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 277       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 278
 279       <device Dname="ARMCM0P">
 280         <processor Dcore="Cortex-M0+" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
 281         <compile header="Device/ARM/ARMCM0plus/Include/ARMCM0plus.h" define="ARMCM0P"/>
 282       </device>
 283
 284       <device Dname="ARMCM0P_MPU">
 285         <processor Dcore="Cortex-M0+" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 286         <compile header="Device/ARM/ARMCM0plus/Include/ARMCM0plus_MPU.h" define="ARMCM0P_MPU"/>
 287       </device>
 288     </family>
 289
 290     <!-- ******************************  Cortex-M1  ****************************** -->
 291     <family Dfamily="ARM Cortex M1" Dvendor="ARM:82">
 292       <!--book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/index.html" title="Cortex-M1 Device Generic Users Guide"/-->
 293       <description>
 294 The ARM Cortex-M1 FPGA processor is intended for deeply embedded applications that require a small processor integrated into an FPGA.
 295 The ARM Cortex-M1 processor implements the ARMv6-M architecture profile.
 296       </description>
 297       <!-- debug svd="Device/ARM/SVD/ARMCM0.svd"/ SVD files do not contain any peripheral -->
 298       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 299       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 300       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 301
 302       <device Dname="ARMCM1">
 303         <processor Dcore="Cortex-M1" DcoreVersion="r1p0" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
 304         <compile header="Device/ARM/ARMCM1/Include/ARMCM1.h" define="ARMCM1"/>
 305       </device>
 306     </family>
 307
 308     <!-- ******************************  Cortex-M3  ****************************** -->
 309     <family Dfamily="ARM Cortex M3" Dvendor="ARM:82">
 310       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/index.html" title="Cortex-M3 Device Generic Users Guide"/>
 311       <description>
 312 The Cortex-M3 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 313 - simple, easy-to-use programmers model
 314 - highly efficient ultra-low power operation
 315 - excellent code density
 316 - deterministic, high-performance interrupt handling
 317 - upward compatibility with the rest of the Cortex-M processor family.
 318       </description>
 319       <!-- debug svd="Device/ARM/SVD/ARMCM3.svd"/ SVD files do not contain any peripheral -->
 320       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 321       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 322       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 323
 324       <device Dname="ARMCM3">
 325         <processor Dcore="Cortex-M3" DcoreVersion="r2p1" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 326         <compile header="Device/ARM/ARMCM3/Include/ARMCM3.h" define="ARMCM3"/>
 327       </device>
 328     </family>
 329
 330     <!-- ******************************  Cortex-M4  ****************************** -->
 331     <family Dfamily="ARM Cortex M4" Dvendor="ARM:82">
 332       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/index.html" title="Cortex-M4 Device Generic Users Guide"/>
 333       <description>
 334 The Cortex-M4 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 335 - simple, easy-to-use programmers model
 336 - highly efficient ultra-low power operation
 337 - excellent code density
 338 - deterministic, high-performance interrupt handling
 339 - upward compatibility with the rest of the Cortex-M processor family.
 340       </description>
 341       <!-- debug svd="Device/ARM/SVD/ARMCM4.svd"/ SVD files do not contain any peripheral -->
 342       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 343       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 344       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 345
 346       <device Dname="ARMCM4">
 347         <processor Dcore="Cortex-M4" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 348         <compile header="Device/ARM/ARMCM4/Include/ARMCM4.h"    define="ARMCM4"/>
 349       </device>
 350
 351       <device Dname="ARMCM4_FP">
 352         <processor Dcore="Cortex-M4" DcoreVersion="r0p1" Dfpu="SP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 353         <compile header="Device/ARM/ARMCM4/Include/ARMCM4_FP.h" define="ARMCM4_FP"/>
 354       </device>
 355     </family>
 356
 357     <!-- ******************************  Cortex-M7  ****************************** -->
 358     <family Dfamily="ARM Cortex M7" Dvendor="ARM:82">
 359       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0646b/index.html" title="Cortex-M7 Device Generic Users Guide"/>
 360       <description>
 361 The Cortex-M7 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 362 - simple, easy-to-use programmers model
 363 - highly efficient ultra-low power operation
 364 - excellent code density
 365 - deterministic, high-performance interrupt handling
 366 - upward compatibility with the rest of the Cortex-M processor family.
 367       </description>
 368       <!-- debug svd="Device/ARM/SVD/ARMCM7.svd"/ SVD files do not contain any peripheral -->
 369       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 370       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 371       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 372
 373       <device Dname="ARMCM7">
 374         <processor Dcore="Cortex-M7" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 375         <compile header="Device/ARM/ARMCM7/Include/ARMCM7.h" define="ARMCM7"/>
 376       </device>
 377
 378       <device Dname="ARMCM7_SP">
 379         <processor Dcore="Cortex-M7" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 380         <compile header="Device/ARM/ARMCM7/Include/ARMCM7_SP.h" define="ARMCM7_SP"/>
 381       </device>
 382
 383       <device Dname="ARMCM7_DP">
 384         <processor Dcore="Cortex-M7" DcoreVersion="r0p0" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 385         <compile header="Device/ARM/ARMCM7/Include/ARMCM7_DP.h" define="ARMCM7_DP"/>
 386       </device>
 387     </family>
 388
 389     <!-- ******************************  Cortex-M23  ********************** -->
 390     <family Dfamily="ARM Cortex M23" Dvendor="ARM:82">
 391       <!--book name="Device/ARM/Documents/??_dgug.pdf"       title="?? Device Generic Users Guide"/-->
 392       <description>
 393 The Arm Cortex-M23 is based on the Armv8-M baseline architecture.
 394 It is the smallest and most energy efficient Arm processor with Arm TrustZone technology.
 395 Cortex-M23 is the ideal processor for constrained embedded applications requiring efficient security.
 396       </description>
 397       <!-- debug svd="Device/ARM/SVD/ARMCM23.svd"/ SVD files do not contain any peripheral -->
 398       <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
 399       <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
 400       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 401       <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
 402       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 403
 404       <device Dname="ARMCM23">
 405         <processor Dcore="Cortex-M23" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
 406         <compile header="Device/ARM/ARMCM23/Include/ARMCM23.h" define="ARMCM23"/>
 407       </device>
 408
 409       <device Dname="ARMCM23_TZ">
 410         <processor Dcore="Cortex-M23" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 411         <compile header="Device/ARM/ARMCM23/Include/ARMCM23_TZ.h" define="ARMCM23_TZ"/>
 412       </device>
 413     </family>
 414
 415     <!-- ******************************  Cortex-M33  ****************************** -->
 416     <family Dfamily="ARM Cortex M33" Dvendor="ARM:82">
 417       <!--book name="Device/ARM/Documents/??_dgug.pdf"       title="?? Device Generic Users Guide"/-->
 418       <description>
 419 The Arm Cortex-M33 is the most configurable of all Cortex-M processors. It is a full featured microcontroller
 420 class processor based on the Armv8-M mainline architecture with Arm TrustZone security.
 421       </description>
 422       <!-- debug svd="Device/ARM/SVD/ARMCM33.svd"/ SVD files do not contain any peripheral -->
 423       <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
 424       <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
 425       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 426       <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
 427       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"          default="1"/-->
 428
 429       <device Dname="ARMCM33">
 430         <processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
 431         <description>
 432           no DSP Instructions, no Floating Point Unit, no TrustZone
 433         </description>
 434         <compile header="Device/ARM/ARMCM33/Include/ARMCM33.h" define="ARMCM33"/>
 435       </device>
 436
 437       <device Dname="ARMCM33_TZ">
 438         <processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 439         <description>
 440           no DSP Instructions, no Floating Point Unit, TrustZone
 441         </description>
 442         <compile header="Device/ARM/ARMCM33/Include/ARMCM33_TZ.h" define="ARMCM33_TZ"/>
 443       </device>
 444
 445       <device Dname="ARMCM33_DSP_FP">
 446         <processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
 447         <description>
 448           DSP Instructions, Single Precision Floating Point Unit, no TrustZone
 449         </description>
 450         <compile header="Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP.h" define="ARMCM33_DSP_FP"/>
 451       </device>
 452
 453       <device Dname="ARMCM33_DSP_FP_TZ">
 454         <processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 455         <description>
 456           DSP Instructions, Single Precision Floating Point Unit, TrustZone
 457         </description>
 458         <compile header="Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h" define="ARMCM33_DSP_FP_TZ"/>
 459       </device>
 460     </family>
 461
 462     <!-- ******************************  Cortex-M35P  ****************************** -->
 463     <family Dfamily="ARM Cortex M35P" Dvendor="ARM:82">
 464       <!--book name="Device/ARM/Documents/??_dgug.pdf"       title="?? Device Generic Users Guide"/-->
 465       <description>
 466 The Arm Cortex-M35P is the most configurable of all Cortex-M processors. It is a full featured microcontroller
 467 class processor based on the Armv8-M mainline architecture with Arm TrustZone security designed for a broad range of secure embedded applications.
 468       </description>
 469
 470       <!-- debug svd="Device/ARM/SVD/ARMCM35P.svd"/ SVD files do not contain any peripheral -->
 471       <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
 472       <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
 473       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 474       <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
 475       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"          default="1"/-->
 476
 477       <device Dname="ARMCM35P">
 478         <processor Dcore="Cortex-M35P" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
 479         <description>
 480           no DSP Instructions, no Floating Point Unit, no TrustZone
 481         </description>
 482         <compile header="Device/ARM/ARMCM35P/Include/ARMCM35P.h" define="ARMCM35P"/>
 483       </device>
 484
 485       <device Dname="ARMCM35P_TZ">
 486         <processor Dcore="Cortex-M35P" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 487         <description>
 488           no DSP Instructions, no Floating Point Unit, TrustZone
 489         </description>
 490         <compile header="Device/ARM/ARMCM35P/Include/ARMCM35P_TZ.h" define="ARMCM35P_TZ"/>
 491       </device>
 492
 493       <device Dname="ARMCM35P_DSP_FP">
 494         <processor Dcore="Cortex-M35P" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
 495         <description>
 496           DSP Instructions, Single Precision Floating Point Unit, no TrustZone
 497         </description>
 498         <compile header="Device/ARM/ARMCM35P/Include/ARMCM35P_DSP_FP.h" define="ARMCM35P_DSP_FP"/>
 499       </device>
 500
 501       <device Dname="ARMCM35P_DSP_FP_TZ">
 502         <processor Dcore="Cortex-M35P" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 503         <description>
 504           DSP Instructions, Single Precision Floating Point Unit, TrustZone
 505         </description>
 506         <compile header="Device/ARM/ARMCM35P/Include/ARMCM35P_DSP_FP_TZ.h" define="ARMCM35P_DSP_FP_TZ"/>
 507       </device>
 508     </family>
 509
 510     <!-- ******************************  ARMSC000  ****************************** -->
 511     <family Dfamily="ARM SC000" Dvendor="ARM:82">
 512       <description>
 513 The Arm SC000 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including:
 514 - simple, easy-to-use programmers model
 515 - highly efficient ultra-low power operation
 516 - excellent code density
 517 - deterministic, high-performance interrupt handling
 518       </description>
 519       <!-- debug svd="Device/ARM/SVD/ARMSC000.svd"/ SVD files do not contain any peripheral -->
 520       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 521       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 522       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 523
 524       <device Dname="ARMSC000">
 525         <processor Dcore="SC000" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
 526         <compile header="Device/ARM/ARMSC000/Include/ARMSC000.h" define="ARMSC000"/>
 527       </device>
 528     </family>
 529
 530     <!-- ******************************  ARMSC300  ****************************** -->
 531     <family Dfamily="ARM SC300" Dvendor="ARM:82">
 532       <description>
 533 The ARM SC300 processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including:
 534 - simple, easy-to-use programmers model
 535 - highly efficient ultra-low power operation
 536 - excellent code density
 537 - deterministic, high-performance interrupt handling
 538       </description>
 539       <!-- debug svd="Device/ARM/SVD/ARMSC300.svd"/ SVD files do not contain any peripheral -->
 540       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 541       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 542       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 543
 544       <device Dname="ARMSC300">
 545         <processor Dcore="SC300" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
 546         <compile header="Device/ARM/ARMSC300/Include/ARMSC300.h" define="ARMSC300"/>
 547       </device>
 548     </family>
 549
 550     <!-- ******************************  ARMv8-M Baseline  ********************** -->
 551     <family Dfamily="ARMv8-M Baseline" Dvendor="ARM:82">
 552       <!--book name="Device/ARM/Documents/ARMv8MBL_dgug.pdf"       title="ARMv8MBL Device Generic Users Guide"/-->
 553       <description>
 554 Armv8-M Baseline based device with TrustZone
 555       </description>
 556       <!-- debug svd="Device/ARM/SVD/ARMv8MBL.svd"/ SVD files do not contain any peripheral -->
 557       <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
 558       <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
 559       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 560       <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
 561       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 562
 563       <device Dname="ARMv8MBL">
 564         <processor Dcore="ARMV8MBL" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 565         <compile header="Device/ARM/ARMv8MBL/Include/ARMv8MBL.h" define="ARMv8MBL"/>
 566       </device>
 567     </family>
 568
 569     <!-- ******************************  ARMv8-M Mainline  ****************************** -->
 570     <family Dfamily="ARMv8-M Mainline" Dvendor="ARM:82">
 571       <!--book name="Device/ARM/Documents/ARMv8MML_dgug.pdf"       title="ARMv8MML Device Generic Users Guide"/-->
 572       <description>
 573 Armv8-M Mainline based device with TrustZone
 574       </description>
 575       <!-- debug svd="Device/ARM/SVD/ARMv8MML.svd"/ SVD files do not contain any peripheral -->
 576       <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
 577       <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
 578       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 579       <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
 580       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 581
 582       <device Dname="ARMv8MML">
 583         <processor Dcore="ARMV8MML" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 584         <description>
 585           no DSP Instructions, no Floating Point Unit, TrustZone
 586         </description>
 587         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML.h" define="ARMv8MML"/>
 588       </device>
 589
 590       <device Dname="ARMv8MML_DSP">
 591         <processor Dcore="ARMV8MML" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 592         <description>
 593           DSP Instructions, no Floating Point Unit, TrustZone
 594         </description>
 595         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DSP.h" define="ARMv8MML_DSP"/>
 596       </device>
 597
 598       <device Dname="ARMv8MML_SP">
 599         <processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 600         <description>
 601           no DSP Instructions, Single Precision Floating Point Unit, TrustZone
 602         </description>
 603         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_SP.h" define="ARMv8MML_SP"/>
 604       </device>
 605
 606       <device Dname="ARMv8MML_DSP_SP">
 607         <processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 608         <description>
 609           DSP Instructions, Single Precision Floating Point Unit, TrustZone
 610         </description>
 611         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_SP.h" define="ARMv8MML_DSP_SP"/>
 612       </device>
 613
 614       <device Dname="ARMv8MML_DP">
 615         <processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="DP_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 616         <description>
 617           no DSP Instructions, Double Precision Floating Point Unit, TrustZone
 618         </description>
 619         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DP.h" define="ARMv8MML_DP"/>
 620       </device>
 621
 622       <device Dname="ARMv8MML_DSP_DP">
 623         <processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="DP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 624         <description>
 625           DSP Instructions, Double Precision Floating Point Unit, TrustZone
 626         </description>
 627         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h" define="ARMv8MML_DSP_DP"/>
 628       </device>
 629     </family>
 630
 631     <!-- ******************************  Cortex-A5  ****************************** -->
 632     <family Dfamily="ARM Cortex A5" Dvendor="ARM:82">
 633       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0433c/index.html" title="Cortex-A5 Technical Reference Manual"/>
 634       <description>
 635 The Arm Cortex-A5 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full
 636 virtual memory capabilities. The Cortex-A5 processor implements the Armv7-A architecture profile and can execute 32-bit
 637 Arm instructions and 16-bit and 32-bit Thumb instructions. The Cortex-A5 is the smallest member of the Cortex-A processor family.
 638       </description>
 639
 640       <memory id="IROM1"                                start="0x80000000" size="0x00200000" startup="1" default="1"/>
 641       <memory id="IRAM1"                                start="0x80200000" size="0x00200000" init   ="0" default="1"/>
 642
 643       <device Dname="ARMCA5">
 644         <processor Dcore="Cortex-A5" DcoreVersion="r0p1" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable"/>
 645         <compile header="Device/ARM/ARMCA5/Include/ARMCA5.h" define="ARMCA5"/>
 646       </device>
 647     </family>
 648
 649     <!-- ******************************  Cortex-A7  ****************************** -->
 650     <family Dfamily="ARM Cortex A7" Dvendor="ARM:82">
 651       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/index.html" title="Cortex-A7 MPCore Technical Reference Manual"/>
 652       <description>
 653 The Cortex-A7 MPCore processor is a high-performance, low-power processor that implements the Armv7-A architecture.
 654 The Cortex-A7 MPCore processor has one to four processors in a single multiprocessor device with a L1 cache subsystem,
 655 an optional integrated GIC, and an optional L2 cache controller.
 656       </description>
 657
 658       <memory id="IROM1"                                start="0x80000000" size="0x00200000" startup="1" default="1"/>
 659       <memory id="IRAM1"                                start="0x80200000" size="0x00200000" init   ="0" default="1"/>
 660
 661       <device Dname="ARMCA7">
 662         <processor Dcore="Cortex-A7" DcoreVersion="r0p5" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable"/>
 663         <compile header="Device/ARM/ARMCA7/Include/ARMCA7.h" define="ARMCA7"/>
 664       </device>
 665     </family>
 666
 667     <!-- ******************************  Cortex-A9  ****************************** -->
 668     <family Dfamily="ARM Cortex A9" Dvendor="ARM:82">
 669       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.100511_0401_10_en/index.html" title="Cortex-A9 Technical Reference Manual"/>
 670       <description>
 671 The Cortex-A9 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full virtual memory capabilities.
 672 The Cortex-A9 processor implements the Armv7-A architecture and runs 32-bit Arm instructions, 16-bit and 32-bit Thumb instructions,
 673 and 8-bit Java bytecodes in Jazelle state.
 674       </description>
 675
 676       <memory id="IROM1"                                start="0x80000000" size="0x00200000" startup="1" default="1"/>
 677       <memory id="IRAM1"                                start="0x80200000" size="0x00200000" init   ="0" default="1"/>
 678
 679       <device Dname="ARMCA9">
 680         <processor Dcore="Cortex-A9" DcoreVersion="r4p1" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable"/>
 681         <compile header="Device/ARM/ARMCA9/Include/ARMCA9.h" define="ARMCA9"/>
 682       </device>
 683     </family>
 684   </devices>
 685
 686
 687   <apis>
 688     <!-- CMSIS Device API -->
 689     <api Cclass="Device" Cgroup="IRQ Controller" Capiversion="1.0.0" exclusive="1">
 690       <description>Device interrupt controller interface</description>
 691       <files>
 692         <file category="header" name="CMSIS/Core_A/Include/irq_ctrl.h"/>
 693       </files>
 694     </api>
 695     <api Cclass="Device" Cgroup="OS Tick" Capiversion="1.0.1" exclusive="1">
 696       <description>RTOS Kernel system tick timer interface</description>
 697       <files>
 698         <file category="header" name="CMSIS/RTOS2/Include/os_tick.h"/>
 699       </files>
 700     </api>
 701     <!-- CMSIS-RTOS API -->
 702     <api Cclass="CMSIS" Cgroup="RTOS" Capiversion="1.0.0" exclusive="1">
 703       <description>CMSIS-RTOS API for Cortex-M, SC000, and SC300</description>
 704       <files>
 705         <file category="doc" name="CMSIS/Documentation/RTOS/html/index.html"/>
 706       </files>
 707     </api>
 708     <api Cclass="CMSIS" Cgroup="RTOS2" Capiversion="2.1.3" exclusive="1">
 709       <description>CMSIS-RTOS API for Cortex-M, SC000, and SC300</description>
 710       <files>
 711         <file category="doc" name="CMSIS/Documentation/RTOS2/html/index.html"/>
 712         <file category="header" name="CMSIS/RTOS2/Include/cmsis_os2.h"/>
 713       </files>
 714     </api>
 715     <!-- CMSIS Driver API -->
 716     <api Cclass="CMSIS Driver" Cgroup="USART" Capiversion="2.3.0" exclusive="0">
 717       <description>USART Driver API for Cortex-M</description>
 718       <files>
 719         <file category="doc" name="CMSIS/Documentation/Driver/html/group__usart__interface__gr.html" />
 720         <file category="header" name="CMSIS/Driver/Include/Driver_USART.h" />
 721       </files>
 722     </api>
 723     <api Cclass="CMSIS Driver" Cgroup="SPI" Capiversion="2.2.0" exclusive="0">
 724       <description>SPI Driver API for Cortex-M</description>
 725       <files>
 726         <file category="doc" name="CMSIS/Documentation/Driver/html/group__spi__interface__gr.html" />
 727         <file category="header" name="CMSIS/Driver/Include/Driver_SPI.h" />
 728       </files>
 729     </api>
 730     <api Cclass="CMSIS Driver" Cgroup="SAI" Capiversion="1.1.0" exclusive="0">
 731       <description>SAI Driver API for Cortex-M</description>
 732       <files>
 733         <file category="doc" name="CMSIS/Documentation/Driver/html/group__sai__interface__gr.html"/>
 734         <file category="header" name="CMSIS/Driver/Include/Driver_SAI.h" />
 735       </files>
 736     </api>
 737     <api Cclass="CMSIS Driver" Cgroup="I2C" Capiversion="2.3.0" exclusive="0">
 738       <description>I2C Driver API for Cortex-M</description>
 739       <files>
 740         <file category="doc" name="CMSIS/Documentation/Driver/html/group__i2c__interface__gr.html"/>
 741         <file category="header" name="CMSIS/Driver/Include/Driver_I2C.h" />
 742       </files>
 743     </api>
 744     <api Cclass="CMSIS Driver" Cgroup="CAN" Capiversion="1.2.0" exclusive="0">
 745       <description>CAN Driver API for Cortex-M</description>
 746       <files>
 747         <file category="doc" name="CMSIS/Documentation/Driver/html/group__can__interface__gr.html"/>
 748         <file category="header" name="CMSIS/Driver/Include/Driver_CAN.h" />
 749       </files>
 750     </api>
 751     <api Cclass="CMSIS Driver" Cgroup="Flash" Capiversion="2.2.0" exclusive="0">
 752       <description>Flash Driver API for Cortex-M</description>
 753       <files>
 754         <file category="doc" name="CMSIS/Documentation/Driver/html/group__flash__interface__gr.html" />
 755         <file category="header" name="CMSIS/Driver/Include/Driver_Flash.h" />
 756       </files>
 757     </api>
 758     <api Cclass="CMSIS Driver" Cgroup="MCI" Capiversion="2.3.0" exclusive="0">
 759       <description>MCI Driver API for Cortex-M</description>
 760       <files>
 761         <file category="doc" name="CMSIS/Documentation/Driver/html/group__mci__interface__gr.html" />
 762         <file category="header" name="CMSIS/Driver/Include/Driver_MCI.h" />
 763       </files>
 764     </api>
 765     <api Cclass="CMSIS Driver" Cgroup="NAND" Capiversion="2.3.0" exclusive="0">
 766       <description>NAND Flash Driver API for Cortex-M</description>
 767       <files>
 768         <file category="doc" name="CMSIS/Documentation/Driver/html/group__nand__interface__gr.html" />
 769         <file category="header" name="CMSIS/Driver/Include/Driver_NAND.h" />
 770       </files>
 771     </api>
 772     <api Cclass="CMSIS Driver" Cgroup="Ethernet" Capiversion="2.1.0" exclusive="0">
 773       <description>Ethernet MAC and PHY Driver API for Cortex-M</description>
 774       <files>
 775         <file category="doc" name="CMSIS/Documentation/Driver/html/group__eth__interface__gr.html" />
 776         <file category="header" name="CMSIS/Driver/Include/Driver_ETH_MAC.h" />
 777         <file category="header" name="CMSIS/Driver/Include/Driver_ETH_PHY.h" />
 778       </files>
 779     </api>
 780     <api Cclass="CMSIS Driver" Cgroup="Ethernet MAC" Capiversion="2.1.0" exclusive="0">
 781       <description>Ethernet MAC Driver API for Cortex-M</description>
 782       <files>
 783         <file category="doc" name="CMSIS/Documentation/Driver/html/group__eth__mac__interface__gr.html" />
 784         <file category="header" name="CMSIS/Driver/Include/Driver_ETH_MAC.h" />
 785       </files>
 786     </api>
 787     <api Cclass="CMSIS Driver" Cgroup="Ethernet PHY" Capiversion="2.1.0" exclusive="0">
 788       <description>Ethernet PHY Driver API for Cortex-M</description>
 789       <files>
 790         <file category="doc" name="CMSIS/Documentation/Driver/html/group__eth__phy__interface__gr.html" />
 791         <file category="header" name="CMSIS/Driver/Include/Driver_ETH_PHY.h" />
 792       </files>
 793     </api>
 794     <api Cclass="CMSIS Driver" Cgroup="USB Device" Capiversion="2.2.0" exclusive="0">
 795       <description>USB Device Driver API for Cortex-M</description>
 796       <files>
 797         <file category="doc" name="CMSIS/Documentation/Driver/html/group__usbd__interface__gr.html" />
 798         <file category="header" name="CMSIS/Driver/Include/Driver_USBD.h" />
 799       </files>
 800     </api>
 801     <api Cclass="CMSIS Driver" Cgroup="USB Host" Capiversion="2.2.0" exclusive="0">
 802       <description>USB Host Driver API for Cortex-M</description>
 803       <files>
 804         <file category="doc" name="CMSIS/Documentation/Driver/html/group__usbh__interface__gr.html" />
 805         <file category="header" name="CMSIS/Driver/Include/Driver_USBH.h" />
 806       </files>
 807     </api>
 808   </apis>
 809
 810   <!-- conditions are dependency rules that can apply to a component or an individual file -->
 811   <conditions>
 812     <!-- compiler -->
 813     <condition id="ARMCC6">
 814       <accept Tcompiler="ARMCC" Toptions="AC6"/>
 815       <accept Tcompiler="ARMCC" Toptions="AC6LTO"/>
 816     </condition>
 817     <condition id="ARMCC5">
 818       <require Tcompiler="ARMCC" Toptions="AC5"/>
 819     </condition>
 820     <condition id="ARMCC">
 821       <require Tcompiler="ARMCC"/>
 822     </condition>
 823     <condition id="GCC">
 824       <require Tcompiler="GCC"/>
 825     </condition>
 826     <condition id="IAR">
 827       <require Tcompiler="IAR"/>
 828     </condition>
 829     <condition id="ARMCC GCC">
 830       <accept Tcompiler="ARMCC"/>
 831       <accept Tcompiler="GCC"/>
 832     </condition>
 833     <condition id="ARMCC GCC IAR">
 834       <accept Tcompiler="ARMCC"/>
 835       <accept Tcompiler="GCC"/>
 836       <accept Tcompiler="IAR"/>
 837     </condition>
 838
 839     <!-- Arm architecture -->
 840     <condition id="ARMv6-M Device">
 841       <description>Armv6-M architecture based device</description>
 842       <accept Dcore="Cortex-M0"/>
 843       <accept Dcore="Cortex-M1"/>
 844       <accept Dcore="Cortex-M0+"/>
 845       <accept Dcore="SC000"/>
 846     </condition>
 847     <condition id="ARMv7-M Device">
 848       <description>Armv7-M architecture based device</description>
 849       <accept Dcore="Cortex-M3"/>
 850       <accept Dcore="Cortex-M4"/>
 851       <accept Dcore="Cortex-M7"/>
 852       <accept Dcore="SC300"/>
 853     </condition>
 854     <condition id="ARMv8-M Device">
 855       <description>Armv8-M architecture based device</description>
 856       <accept Dcore="ARMV8MBL"/>
 857       <accept Dcore="ARMV8MML"/>
 858       <accept Dcore="Cortex-M23"/>
 859       <accept Dcore="Cortex-M33"/>
 860       <accept Dcore="Cortex-M35P"/>
 861     </condition>
 862     <condition id="ARMv8-M TZ Device">
 863       <description>Armv8-M architecture based device with TrustZone</description>
 864       <require condition="ARMv8-M Device"/>
 865       <require Dtz="TZ"/>
 866     </condition>
 867     <condition id="ARMv6_7-M Device">
 868       <description>Armv6_7-M architecture based device</description>
 869       <accept condition="ARMv6-M Device"/>
 870       <accept condition="ARMv7-M Device"/>
 871     </condition>
 872     <condition id="ARMv6_7_8-M Device">
 873       <description>Armv6_7_8-M architecture based device</description>
 874       <accept condition="ARMv6-M Device"/>
 875       <accept condition="ARMv7-M Device"/>
 876       <accept condition="ARMv8-M Device"/>
 877     </condition>
 878     <condition id="ARMv7-A Device">
 879       <description>Armv7-A architecture based device</description>
 880       <accept Dcore="Cortex-A5"/>
 881       <accept Dcore="Cortex-A7"/>
 882       <accept Dcore="Cortex-A9"/>
 883     </condition>
 884
 885     <!-- ARM core -->
 886     <condition id="CM0">
 887       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device</description>
 888       <accept Dcore="Cortex-M0"/>
 889       <accept Dcore="Cortex-M0+"/>
 890       <accept Dcore="SC000"/>
 891     </condition>
 892     <condition id="CM1">
 893       <description>Cortex-M1</description>
 894       <require Dcore="Cortex-M1"/>
 895     </condition>
 896     <condition id="CM3">
 897       <description>Cortex-M3 or SC300 processor based device</description>
 898       <accept Dcore="Cortex-M3"/>
 899       <accept Dcore="SC300"/>
 900     </condition>
 901     <condition id="CM4">
 902       <description>Cortex-M4 processor based device</description>
 903       <require Dcore="Cortex-M4" Dfpu="NO_FPU"/>
 904     </condition>
 905     <condition id="CM4_FP">
 906       <description>Cortex-M4 processor based device using Floating Point Unit</description>
 907       <accept Dcore="Cortex-M4" Dfpu="FPU"/>
 908       <accept Dcore="Cortex-M4" Dfpu="SP_FPU"/>
 909       <accept Dcore="Cortex-M4" Dfpu="DP_FPU"/>
 910     </condition>
 911     <condition id="CM7">
 912       <description>Cortex-M7 processor based device</description>
 913       <require Dcore="Cortex-M7" Dfpu="NO_FPU"/>
 914     </condition>
 915     <condition id="CM7_FP">
 916       <description>Cortex-M7 processor based device using Floating Point Unit</description>
 917       <accept Dcore="Cortex-M7" Dfpu="SP_FPU"/>
 918       <accept Dcore="Cortex-M7" Dfpu="DP_FPU"/>
 919     </condition>
 920     <condition id="CM7_SP">
 921       <description>Cortex-M7 processor based device using Floating Point Unit (SP)</description>
 922       <require Dcore="Cortex-M7" Dfpu="SP_FPU"/>
 923     </condition>
 924     <condition id="CM7_DP">
 925       <description>Cortex-M7 processor based device using Floating Point Unit (DP)</description>
 926       <require Dcore="Cortex-M7" Dfpu="DP_FPU"/>
 927     </condition>
 928     <condition id="CM23">
 929       <description>Cortex-M23 processor based device</description>
 930       <require Dcore="Cortex-M23"/>
 931     </condition>
 932     <condition id="CM33">
 933       <description>Cortex-M33 processor based device</description>
 934       <require Dcore="Cortex-M33" Dfpu="NO_FPU"/>
 935     </condition>
 936     <condition id="CM33_FP">
 937       <description>Cortex-M33 processor based device using Floating Point Unit</description>
 938       <require Dcore="Cortex-M33" Dfpu="SP_FPU"/>
 939     </condition>
 940     <condition id="CM35P">
 941       <description>Cortex-M35P processor based device</description>
 942       <require Dcore="Cortex-M35P" Dfpu="NO_FPU"/>
 943     </condition>
 944     <condition id="CM35P_FP">
 945       <description>Cortex-M35P processor based device using Floating Point Unit</description>
 946       <require Dcore="Cortex-M35P" Dfpu="SP_FPU"/>
 947     </condition>
 948     <condition id="ARMv8MBL">
 949       <description>Armv8-M Baseline processor based device</description>
 950       <require Dcore="ARMV8MBL"/>
 951     </condition>
 952     <condition id="ARMv8MML">
 953       <description>Armv8-M Mainline processor based device</description>
 954       <require Dcore="ARMV8MML" Dfpu="NO_FPU"/>
 955     </condition>
 956     <condition id="ARMv8MML_FP">
 957       <description>Armv8-M Mainline processor based device using Floating Point Unit</description>
 958       <accept Dcore="ARMV8MML" Dfpu="SP_FPU"/>
 959       <accept Dcore="ARMV8MML" Dfpu="DP_FPU"/>
 960     </condition>
 961
 962     <condition id="CM33_NODSP_NOFPU">
 963       <description>CM33, no DSP, no FPU</description>
 964       <require Dcore="Cortex-M33" Ddsp="NO_DSP" Dfpu="NO_FPU"/>
 965     </condition>
 966     <condition id="CM33_DSP_NOFPU">
 967       <description>CM33, DSP, no FPU</description>
 968       <require Dcore="Cortex-M33" Ddsp="DSP" Dfpu="NO_FPU"/>
 969     </condition>
 970     <condition id="CM33_NODSP_SP">
 971       <description>CM33, no DSP, SP FPU</description>
 972       <require Dcore="Cortex-M33" Ddsp="NO_DSP" Dfpu="SP_FPU"/>
 973     </condition>
 974     <condition id="CM33_DSP_SP">
 975       <description>CM33, DSP, SP FPU</description>
 976       <require Dcore="Cortex-M33" Ddsp="DSP" Dfpu="SP_FPU"/>
 977     </condition>
 978
 979     <condition id="CM35P_NODSP_NOFPU">
 980       <description>CM35P, no DSP, no FPU</description>
 981       <require Dcore="Cortex-M35P" Ddsp="NO_DSP" Dfpu="NO_FPU"/>
 982     </condition>
 983     <condition id="CM35P_DSP_NOFPU">
 984       <description>CM35P, DSP, no FPU</description>
 985       <require Dcore="Cortex-M35P" Ddsp="DSP" Dfpu="NO_FPU"/>
 986     </condition>
 987     <condition id="CM35P_NODSP_SP">
 988       <description>CM35P, no DSP, SP FPU</description>
 989       <require Dcore="Cortex-M35P" Ddsp="NO_DSP" Dfpu="SP_FPU"/>
 990     </condition>
 991     <condition id="CM35P_DSP_SP">
 992       <description>CM35P, DSP, SP FPU</description>
 993       <require Dcore="Cortex-M35P" Ddsp="DSP" Dfpu="SP_FPU"/>
 994     </condition>
 995
 996     <condition id="ARMv8MML_NODSP_NOFPU">
 997       <description>Armv8-M Mainline, no DSP, no FPU</description>
 998       <require Dcore="ARMV8MML" Ddsp="NO_DSP" Dfpu="NO_FPU"/>
 999     </condition>
1000     <condition id="ARMv8MML_DSP_NOFPU">
1001       <description>Armv8-M Mainline, DSP, no FPU</description>
1002       <require Dcore="ARMV8MML" Ddsp="DSP" Dfpu="NO_FPU"/>
1003     </condition>
1004     <condition id="ARMv8MML_NODSP_SP">
1005       <description>Armv8-M Mainline, no DSP, SP FPU</description>
1006       <require Dcore="ARMV8MML" Ddsp="NO_DSP" Dfpu="SP_FPU"/>
1007     </condition>
1008     <condition id="ARMv8MML_DSP_SP">
1009       <description>Armv8-M Mainline, DSP, SP FPU</description>
1010       <require Dcore="ARMV8MML" Ddsp="DSP" Dfpu="SP_FPU"/>
1011     </condition>
1012
1013     <condition id="CA5_CA9">
1014       <description>Cortex-A5 or Cortex-A9 processor based device</description>
1015       <accept Dcore="Cortex-A5"/>
1016       <accept Dcore="Cortex-A9"/>
1017     </condition>
1018
1019     <condition id="CA7">
1020       <description>Cortex-A7 processor based device</description>
1021       <accept Dcore="Cortex-A7"/>
1022     </condition>
1023
1024     <!-- ARMCC compiler -->
1025     <condition id="CA_ARMCC5">
1026       <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the Arm Compiler 5</description>
1027       <require condition="ARMv7-A Device"/>
1028       <require condition="ARMCC5"/>
1029     </condition>
1030     <condition id="CA_ARMCC6">
1031       <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the Arm Compiler 6</description>
1032       <require condition="ARMv7-A Device"/>
1033       <require condition="ARMCC6"/>
1034     </condition>
1035
1036     <condition id="CM0_ARMCC">
1037       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device for the Arm Compiler</description>
1038       <require condition="CM0"/>
1039       <require Tcompiler="ARMCC"/>
1040     </condition>
1041     <condition id="CM0_LE_ARMCC">
1042       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the Arm Compiler</description>
1043       <require condition="CM0_ARMCC"/>
1044       <require Dendian="Little-endian"/>
1045     </condition>
1046     <condition id="CM0_BE_ARMCC">
1047       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the Arm Compiler</description>
1048       <require condition="CM0_ARMCC"/>
1049       <require Dendian="Big-endian"/>
1050     </condition>
1051
1052     <condition id="CM1_ARMCC">
1053       <description>Cortex-M1 based device for the Arm Compiler</description>
1054       <require condition="CM1"/>
1055       <require Tcompiler="ARMCC"/>
1056     </condition>
1057     <condition id="CM1_LE_ARMCC">
1058       <description>Cortex-M1 based device in little endian mode for the Arm Compiler</description>
1059       <require condition="CM1_ARMCC"/>
1060       <require Dendian="Little-endian"/>
1061     </condition>
1062     <condition id="CM1_BE_ARMCC">
1063       <description>Cortex-M1 based device in big endian mode for the Arm Compiler</description>
1064       <require condition="CM1_ARMCC"/>
1065       <require Dendian="Big-endian"/>
1066     </condition>
1067
1068     <condition id="CM3_ARMCC">
1069       <description>Cortex-M3 or SC300 processor based device for the Arm Compiler</description>
1070       <require condition="CM3"/>
1071       <require Tcompiler="ARMCC"/>
1072     </condition>
1073     <condition id="CM3_LE_ARMCC">
1074       <description>Cortex-M3 or SC300 processor based device in little endian mode for the Arm Compiler</description>
1075       <require condition="CM3_ARMCC"/>
1076       <require Dendian="Little-endian"/>
1077     </condition>
1078     <condition id="CM3_BE_ARMCC">
1079       <description>Cortex-M3 or SC300 processor based device in big endian mode for the Arm Compiler</description>
1080       <require condition="CM3_ARMCC"/>
1081       <require Dendian="Big-endian"/>
1082     </condition>
1083
1084     <condition id="CM4_ARMCC">
1085       <description>Cortex-M4 processor based device for the Arm Compiler</description>
1086       <require condition="CM4"/>
1087       <require Tcompiler="ARMCC"/>
1088     </condition>
1089     <condition id="CM4_LE_ARMCC">
1090       <description>Cortex-M4 processor based device in little endian mode for the Arm Compiler</description>
1091       <require condition="CM4_ARMCC"/>
1092       <require Dendian="Little-endian"/>
1093     </condition>
1094     <condition id="CM4_BE_ARMCC">
1095       <description>Cortex-M4 processor based device in big endian mode for the Arm Compiler</description>
1096       <require condition="CM4_ARMCC"/>
1097       <require Dendian="Big-endian"/>
1098     </condition>
1099
1100     <condition id="CM4_FP_ARMCC">
1101       <description>Cortex-M4 processor based device using Floating Point Unit for the Arm Compiler</description>
1102       <require condition="CM4_FP"/>
1103       <require Tcompiler="ARMCC"/>
1104     </condition>
1105     <condition id="CM4_FP_LE_ARMCC">
1106       <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
1107       <require condition="CM4_FP_ARMCC"/>
1108       <require Dendian="Little-endian"/>
1109     </condition>
1110     <condition id="CM4_FP_BE_ARMCC">
1111       <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
1112       <require condition="CM4_FP_ARMCC"/>
1113       <require Dendian="Big-endian"/>
1114     </condition>
1115
1116     <condition id="CM7_ARMCC">
1117       <description>Cortex-M7 processor based device for the Arm Compiler</description>
1118       <require condition="CM7"/>
1119       <require Tcompiler="ARMCC"/>
1120     </condition>
1121     <condition id="CM7_LE_ARMCC">
1122       <description>Cortex-M7 processor based device in little endian mode for the Arm Compiler</description>
1123       <require condition="CM7_ARMCC"/>
1124       <require Dendian="Little-endian"/>
1125     </condition>
1126     <condition id="CM7_BE_ARMCC">
1127       <description>Cortex-M7 processor based device in big endian mode for the Arm Compiler</description>
1128       <require condition="CM7_ARMCC"/>
1129       <require Dendian="Big-endian"/>
1130     </condition>
1131
1132     <condition id="CM7_FP_ARMCC">
1133       <description>Cortex-M7 processor based device using Floating Point Unit for the Arm Compiler</description>
1134       <require condition="CM7_FP"/>
1135       <require Tcompiler="ARMCC"/>
1136     </condition>
1137     <condition id="CM7_FP_LE_ARMCC">
1138       <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
1139       <require condition="CM7_FP_ARMCC"/>
1140       <require Dendian="Little-endian"/>
1141     </condition>
1142     <condition id="CM7_FP_BE_ARMCC">
1143       <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
1144       <require condition="CM7_FP_ARMCC"/>
1145       <require Dendian="Big-endian"/>
1146     </condition>
1147
1148     <condition id="CM7_SP_ARMCC">
1149       <description>Cortex-M7 processor based device using Floating Point Unit (SP) for the Arm Compiler</description>
1150       <require condition="CM7_SP"/>
1151       <require Tcompiler="ARMCC"/>
1152     </condition>
1153     <condition id="CM7_SP_LE_ARMCC">
1154       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the Arm Compiler</description>
1155       <require condition="CM7_SP_ARMCC"/>
1156       <require Dendian="Little-endian"/>
1157     </condition>
1158     <condition id="CM7_SP_BE_ARMCC">
1159       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the Arm Compiler</description>
1160       <require condition="CM7_SP_ARMCC"/>
1161       <require Dendian="Big-endian"/>
1162     </condition>
1163
1164     <condition id="CM7_DP_ARMCC">
1165       <description>Cortex-M7 processor based device using Floating Point Unit (DP) for the Arm Compiler</description>
1166       <require condition="CM7_DP"/>
1167       <require Tcompiler="ARMCC"/>
1168     </condition>
1169     <condition id="CM7_DP_LE_ARMCC">
1170       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the Arm Compiler</description>
1171       <require condition="CM7_DP_ARMCC"/>
1172       <require Dendian="Little-endian"/>
1173     </condition>
1174     <condition id="CM7_DP_BE_ARMCC">
1175       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the Arm Compiler</description>
1176       <require condition="CM7_DP_ARMCC"/>
1177       <require Dendian="Big-endian"/>
1178     </condition>
1179
1180     <condition id="CM23_ARMCC">
1181       <description>Cortex-M23 processor based device for the Arm Compiler</description>
1182       <require condition="CM23"/>
1183       <require Tcompiler="ARMCC"/>
1184     </condition>
1185     <condition id="CM23_LE_ARMCC">
1186       <description>Cortex-M23 processor based device in little endian mode for the Arm Compiler</description>
1187       <require condition="CM23_ARMCC"/>
1188       <require Dendian="Little-endian"/>
1189     </condition>
1190     <condition id="CM23_BE_ARMCC">
1191       <description>Cortex-M23 processor based device in big endian mode for the Arm Compiler</description>
1192       <require condition="CM23_ARMCC"/>
1193       <require Dendian="Big-endian"/>
1194     </condition>
1195
1196     <condition id="CM33_ARMCC">
1197       <description>Cortex-M33 processor based device for the Arm Compiler</description>
1198       <require condition="CM33"/>
1199       <require Tcompiler="ARMCC"/>
1200     </condition>
1201     <condition id="CM33_LE_ARMCC">
1202       <description>Cortex-M33 processor based device in little endian mode for the Arm Compiler</description>
1203       <require condition="CM33_ARMCC"/>
1204       <require Dendian="Little-endian"/>
1205     </condition>
1206     <condition id="CM33_BE_ARMCC">
1207       <description>Cortex-M33 processor based device in big endian mode for the Arm Compiler</description>
1208       <require condition="CM33_ARMCC"/>
1209       <require Dendian="Big-endian"/>
1210     </condition>
1211
1212     <condition id="CM33_FP_ARMCC">
1213       <description>Cortex-M33 processor based device using Floating Point Unit for the Arm Compiler</description>
1214       <require condition="CM33_FP"/>
1215       <require Tcompiler="ARMCC"/>
1216     </condition>
1217     <condition id="CM33_FP_LE_ARMCC">
1218       <description>Cortex-M33 processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
1219       <require condition="CM33_FP_ARMCC"/>
1220       <require Dendian="Little-endian"/>
1221     </condition>
1222     <condition id="CM33_FP_BE_ARMCC">
1223       <description>Cortex-M33 processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
1224       <require condition="CM33_FP_ARMCC"/>
1225       <require Dendian="Big-endian"/>
1226     </condition>
1227
1228     <condition id="CM33_NODSP_NOFPU_ARMCC">
1229       <description>Cortex-M33 processor, no DSP, no FPU, Arm Compiler</description>
1230       <require condition="CM33_NODSP_NOFPU"/>
1231       <require Tcompiler="ARMCC"/>
1232     </condition>
1233     <condition id="CM33_DSP_NOFPU_ARMCC">
1234       <description>Cortex-M33 processor, DSP, no FPU, Arm Compiler</description>
1235       <require condition="CM33_DSP_NOFPU"/>
1236       <require Tcompiler="ARMCC"/>
1237     </condition>
1238     <condition id="CM33_NODSP_SP_ARMCC">
1239       <description>Cortex-M33 processor, no DSP, SP FPU, Arm Compiler</description>
1240       <require condition="CM33_NODSP_SP"/>
1241       <require Tcompiler="ARMCC"/>
1242     </condition>
1243     <condition id="CM33_DSP_SP_ARMCC">
1244       <description>Cortex-M33 processor, DSP, SP FPU, Arm Compiler</description>
1245       <require condition="CM33_DSP_SP"/>
1246       <require Tcompiler="ARMCC"/>
1247     </condition>
1248     <condition id="CM33_NODSP_NOFPU_LE_ARMCC">
1249       <description>Cortex-M33 processor, little endian, no DSP, no FPU, Arm Compiler</description>
1250       <require condition="CM33_NODSP_NOFPU_ARMCC"/>
1251       <require Dendian="Little-endian"/>
1252     </condition>
1253     <condition id="CM33_DSP_NOFPU_LE_ARMCC">
1254       <description>Cortex-M33 processor, little endian, DSP, no FPU, Arm Compiler</description>
1255       <require condition="CM33_DSP_NOFPU_ARMCC"/>
1256       <require Dendian="Little-endian"/>
1257     </condition>
1258     <condition id="CM33_NODSP_SP_LE_ARMCC">
1259       <description>Cortex-M33 processor, little endian, no DSP, SP FPU, Arm Compiler</description>
1260       <require condition="CM33_NODSP_SP_ARMCC"/>
1261       <require Dendian="Little-endian"/>
1262     </condition>
1263     <condition id="CM33_DSP_SP_LE_ARMCC">
1264       <description>Cortex-M33 processor, little endian, DSP, SP FPU, Arm Compiler</description>
1265       <require condition="CM33_DSP_SP_ARMCC"/>
1266       <require Dendian="Little-endian"/>
1267     </condition>
1268
1269     <condition id="CM35P_ARMCC">
1270       <description>Cortex-M35P processor based device for the Arm Compiler</description>
1271       <require condition="CM35P"/>
1272       <require Tcompiler="ARMCC"/>
1273     </condition>
1274     <condition id="CM35P_LE_ARMCC">
1275       <description>Cortex-M35P processor based device in little endian mode for the Arm Compiler</description>
1276       <require condition="CM35P_ARMCC"/>
1277       <require Dendian="Little-endian"/>
1278     </condition>
1279     <condition id="CM35P_BE_ARMCC">
1280       <description>Cortex-M35P processor based device in big endian mode for the Arm Compiler</description>
1281       <require condition="CM35P_ARMCC"/>
1282       <require Dendian="Big-endian"/>
1283     </condition>
1284
1285     <condition id="CM35P_FP_ARMCC">
1286       <description>Cortex-M35P processor based device using Floating Point Unit for the Arm Compiler</description>
1287       <require condition="CM35P_FP"/>
1288       <require Tcompiler="ARMCC"/>
1289     </condition>
1290     <condition id="CM35P_FP_LE_ARMCC">
1291       <description>Cortex-M35P processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
1292       <require condition="CM35P_FP_ARMCC"/>
1293       <require Dendian="Little-endian"/>
1294     </condition>
1295     <condition id="CM35P_FP_BE_ARMCC">
1296       <description>Cortex-M35P processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
1297       <require condition="CM35P_FP_ARMCC"/>
1298       <require Dendian="Big-endian"/>
1299     </condition>
1300
1301     <condition id="CM35P_NODSP_NOFPU_ARMCC">
1302       <description>Cortex-M35P processor, no DSP, no FPU, Arm Compiler</description>
1303       <require condition="CM35P_NODSP_NOFPU"/>
1304       <require Tcompiler="ARMCC"/>
1305     </condition>
1306     <condition id="CM35P_DSP_NOFPU_ARMCC">
1307       <description>Cortex-M35P processor, DSP, no FPU, Arm Compiler</description>
1308       <require condition="CM35P_DSP_NOFPU"/>
1309       <require Tcompiler="ARMCC"/>
1310     </condition>
1311     <condition id="CM35P_NODSP_SP_ARMCC">
1312       <description>Cortex-M35P processor, no DSP, SP FPU, Arm Compiler</description>
1313       <require condition="CM35P_NODSP_SP"/>
1314       <require Tcompiler="ARMCC"/>
1315     </condition>
1316     <condition id="CM35P_DSP_SP_ARMCC">
1317       <description>Cortex-M35P processor, DSP, SP FPU, Arm Compiler</description>
1318       <require condition="CM35P_DSP_SP"/>
1319       <require Tcompiler="ARMCC"/>
1320     </condition>
1321     <condition id="CM35P_NODSP_NOFPU_LE_ARMCC">
1322       <description>Cortex-M35P processor, little endian, no DSP, no FPU, Arm Compiler</description>
1323       <require condition="CM35P_NODSP_NOFPU_ARMCC"/>
1324       <require Dendian="Little-endian"/>
1325     </condition>
1326     <condition id="CM35P_DSP_NOFPU_LE_ARMCC">
1327       <description>Cortex-M35P processor, little endian, DSP, no FPU, Arm Compiler</description>
1328       <require condition="CM35P_DSP_NOFPU_ARMCC"/>
1329       <require Dendian="Little-endian"/>
1330     </condition>
1331     <condition id="CM35P_NODSP_SP_LE_ARMCC">
1332       <description>Cortex-M35P processor, little endian, no DSP, SP FPU, Arm Compiler</description>
1333       <require condition="CM35P_NODSP_SP_ARMCC"/>
1334       <require Dendian="Little-endian"/>
1335     </condition>
1336     <condition id="CM35P_DSP_SP_LE_ARMCC">
1337       <description>Cortex-M35P processor, little endian, DSP, SP FPU, Arm Compiler</description>
1338       <require condition="CM35P_DSP_SP_ARMCC"/>
1339       <require Dendian="Little-endian"/>
1340     </condition>
1341
1342     <condition id="ARMv8MBL_ARMCC">
1343       <description>Armv8-M Baseline processor based device for the Arm Compiler</description>
1344       <require condition="ARMv8MBL"/>
1345       <require Tcompiler="ARMCC"/>
1346     </condition>
1347     <condition id="ARMv8MBL_LE_ARMCC">
1348       <description>Armv8-M Baseline processor based device in little endian mode for the Arm Compiler</description>
1349       <require condition="ARMv8MBL_ARMCC"/>
1350       <require Dendian="Little-endian"/>
1351     </condition>
1352     <condition id="ARMv8MBL_BE_ARMCC">
1353       <description>Armv8-M Baseline processor based device in big endian mode for the Arm Compiler</description>
1354       <require condition="ARMv8MBL_ARMCC"/>
1355       <require Dendian="Big-endian"/>
1356     </condition>
1357
1358     <condition id="ARMv8MML_ARMCC">
1359       <description>Armv8-M Mainline processor based device for the Arm Compiler</description>
1360       <require condition="ARMv8MML"/>
1361       <require Tcompiler="ARMCC"/>
1362     </condition>
1363     <condition id="ARMv8MML_LE_ARMCC">
1364       <description>Armv8-M Mainline processor based device in little endian mode for the Arm Compiler</description>
1365       <require condition="ARMv8MML_ARMCC"/>
1366       <require Dendian="Little-endian"/>
1367     </condition>
1368     <condition id="ARMv8MML_BE_ARMCC">
1369       <description>Armv8-M Mainline processor based device in big endian mode for the Arm Compiler</description>
1370       <require condition="ARMv8MML_ARMCC"/>
1371       <require Dendian="Big-endian"/>
1372     </condition>
1373
1374     <condition id="ARMv8MML_FP_ARMCC">
1375       <description>Armv8-M Mainline processor based device using Floating Point Unit for the Arm Compiler</description>
1376       <require condition="ARMv8MML_FP"/>
1377       <require Tcompiler="ARMCC"/>
1378     </condition>
1379     <condition id="ARMv8MML_FP_LE_ARMCC">
1380       <description>Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
1381       <require condition="ARMv8MML_FP_ARMCC"/>
1382       <require Dendian="Little-endian"/>
1383     </condition>
1384     <condition id="ARMv8MML_FP_BE_ARMCC">
1385       <description>Armv8-M Mainline processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
1386       <require condition="ARMv8MML_FP_ARMCC"/>
1387       <require Dendian="Big-endian"/>
1388     </condition>
1389
1390     <condition id="ARMv8MML_NODSP_NOFPU_ARMCC">
1391       <description>Armv8-M Mainline, no DSP, no FPU, Arm Compiler</description>
1392       <require condition="ARMv8MML_NODSP_NOFPU"/>
1393       <require Tcompiler="ARMCC"/>
1394     </condition>
1395     <condition id="ARMv8MML_DSP_NOFPU_ARMCC">
1396       <description>Armv8-M Mainline, DSP, no FPU, Arm Compiler</description>
1397       <require condition="ARMv8MML_DSP_NOFPU"/>
1398       <require Tcompiler="ARMCC"/>
1399     </condition>
1400     <condition id="ARMv8MML_NODSP_SP_ARMCC">
1401       <description>Armv8-M Mainline, no DSP, SP FPU, Arm Compiler</description>
1402       <require condition="ARMv8MML_NODSP_SP"/>
1403       <require Tcompiler="ARMCC"/>
1404     </condition>
1405     <condition id="ARMv8MML_DSP_SP_ARMCC">
1406       <description>Armv8-M Mainline, DSP, SP FPU, Arm Compiler</description>
1407       <require condition="ARMv8MML_DSP_SP"/>
1408       <require Tcompiler="ARMCC"/>
1409     </condition>
1410     <condition id="ARMv8MML_NODSP_NOFPU_LE_ARMCC">
1411       <description>Armv8-M Mainline, little endian, no DSP, no FPU, Arm Compiler</description>
1412       <require condition="ARMv8MML_NODSP_NOFPU_ARMCC"/>
1413       <require Dendian="Little-endian"/>
1414     </condition>
1415     <condition id="ARMv8MML_DSP_NOFPU_LE_ARMCC">
1416       <description>Armv8-M Mainline, little endian, DSP, no FPU, Arm Compiler</description>
1417       <require condition="ARMv8MML_DSP_NOFPU_ARMCC"/>
1418       <require Dendian="Little-endian"/>
1419     </condition>
1420     <condition id="ARMv8MML_NODSP_SP_LE_ARMCC">
1421       <description>Armv8-M Mainline, little endian, no DSP, SP FPU, Arm Compiler</description>
1422       <require condition="ARMv8MML_NODSP_SP_ARMCC"/>
1423       <require Dendian="Little-endian"/>
1424     </condition>
1425     <condition id="ARMv8MML_DSP_SP_LE_ARMCC">
1426       <description>Armv8-M Mainline, little endian, DSP, SP FPU, Arm Compiler</description>
1427       <require condition="ARMv8MML_DSP_SP_ARMCC"/>
1428       <require Dendian="Little-endian"/>
1429     </condition>
1430
1431     <!-- GCC compiler -->
1432     <condition id="CA_GCC">
1433       <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the GCC Compiler</description>
1434       <require condition="ARMv7-A Device"/>
1435       <require Tcompiler="GCC"/>
1436     </condition>
1437
1438     <condition id="CM0_GCC">
1439       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device for the GCC Compiler</description>
1440       <require condition="CM0"/>
1441       <require Tcompiler="GCC"/>
1442     </condition>
1443     <condition id="CM0_LE_GCC">
1444       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the GCC Compiler</description>
1445       <require condition="CM0_GCC"/>
1446       <require Dendian="Little-endian"/>
1447     </condition>
1448     <condition id="CM0_BE_GCC">
1449       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the GCC Compiler</description>
1450       <require condition="CM0_GCC"/>
1451       <require Dendian="Big-endian"/>
1452     </condition>
1453
1454     <condition id="CM1_GCC">
1455       <description>Cortex-M1 based device for the GCC Compiler</description>
1456       <require condition="CM1"/>
1457       <require Tcompiler="GCC"/>
1458     </condition>
1459     <condition id="CM1_LE_GCC">
1460       <description>Cortex-M1 based device in little endian mode for the GCC Compiler</description>
1461       <require condition="CM1_GCC"/>
1462       <require Dendian="Little-endian"/>
1463     </condition>
1464     <condition id="CM1_BE_GCC">
1465       <description>Cortex-M1 based device in big endian mode for the GCC Compiler</description>
1466       <require condition="CM1_GCC"/>
1467       <require Dendian="Big-endian"/>
1468     </condition>
1469
1470     <condition id="CM3_GCC">
1471       <description>Cortex-M3 or SC300 processor based device for the GCC Compiler</description>
1472       <require condition="CM3"/>
1473       <require Tcompiler="GCC"/>
1474     </condition>
1475     <condition id="CM3_LE_GCC">
1476       <description>Cortex-M3 or SC300 processor based device in little endian mode for the GCC Compiler</description>
1477       <require condition="CM3_GCC"/>
1478       <require Dendian="Little-endian"/>
1479     </condition>
1480     <condition id="CM3_BE_GCC">
1481       <description>Cortex-M3 or SC300 processor based device in big endian mode for the GCC Compiler</description>
1482       <require condition="CM3_GCC"/>
1483       <require Dendian="Big-endian"/>
1484     </condition>
1485
1486     <condition id="CM4_GCC">
1487       <description>Cortex-M4 processor based device for the GCC Compiler</description>
1488       <require condition="CM4"/>
1489       <require Tcompiler="GCC"/>
1490     </condition>
1491     <condition id="CM4_LE_GCC">
1492       <description>Cortex-M4 processor based device in little endian mode for the GCC Compiler</description>
1493       <require condition="CM4_GCC"/>
1494       <require Dendian="Little-endian"/>
1495     </condition>
1496     <condition id="CM4_BE_GCC">
1497       <description>Cortex-M4 processor based device in big endian mode for the GCC Compiler</description>
1498       <require condition="CM4_GCC"/>
1499       <require Dendian="Big-endian"/>
1500     </condition>
1501
1502     <condition id="CM4_FP_GCC">
1503       <description>Cortex-M4 processor based device using Floating Point Unit for the GCC Compiler</description>
1504       <require condition="CM4_FP"/>
1505       <require Tcompiler="GCC"/>
1506     </condition>
1507     <condition id="CM4_FP_LE_GCC">
1508       <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
1509       <require condition="CM4_FP_GCC"/>
1510       <require Dendian="Little-endian"/>
1511     </condition>
1512     <condition id="CM4_FP_BE_GCC">
1513       <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
1514       <require condition="CM4_FP_GCC"/>
1515       <require Dendian="Big-endian"/>
1516     </condition>
1517
1518     <condition id="CM7_GCC">
1519       <description>Cortex-M7 processor based device for the GCC Compiler</description>
1520       <require condition="CM7"/>
1521       <require Tcompiler="GCC"/>
1522     </condition>
1523     <condition id="CM7_LE_GCC">
1524       <description>Cortex-M7 processor based device in little endian mode for the GCC Compiler</description>
1525       <require condition="CM7_GCC"/>
1526       <require Dendian="Little-endian"/>
1527     </condition>
1528     <condition id="CM7_BE_GCC">
1529       <description>Cortex-M7 processor based device in big endian mode for the GCC Compiler</description>
1530       <require condition="CM7_GCC"/>
1531       <require Dendian="Big-endian"/>
1532     </condition>
1533
1534     <condition id="CM7_FP_GCC">
1535       <description>Cortex-M7 processor based device using Floating Point Unit for the GCC Compiler</description>
1536       <require condition="CM7_FP"/>
1537       <require Tcompiler="GCC"/>
1538     </condition>
1539     <condition id="CM7_FP_LE_GCC">
1540       <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
1541       <require condition="CM7_FP_GCC"/>
1542       <require Dendian="Little-endian"/>
1543     </condition>
1544     <condition id="CM7_FP_BE_GCC">
1545       <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
1546       <require condition="CM7_FP_GCC"/>
1547       <require Dendian="Big-endian"/>
1548     </condition>
1549
1550     <condition id="CM7_SP_GCC">
1551       <description>Cortex-M7 processor based device using Floating Point Unit (SP) for the GCC Compiler</description>
1552       <require condition="CM7_SP"/>
1553       <require Tcompiler="GCC"/>
1554     </condition>
1555     <condition id="CM7_SP_LE_GCC">
1556       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the GCC Compiler</description>
1557       <require condition="CM7_SP_GCC"/>
1558       <require Dendian="Little-endian"/>
1559     </condition>
1560     <condition id="CM7_SP_BE_GCC">
1561       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the GCC Compiler</description>
1562       <require condition="CM7_SP_GCC"/>
1563       <require Dendian="Big-endian"/>
1564     </condition>
1565
1566     <condition id="CM7_DP_GCC">
1567       <description>Cortex-M7 processor based device using Floating Point Unit (DP) for the GCC Compiler</description>
1568       <require condition="CM7_DP"/>
1569       <require Tcompiler="GCC"/>
1570     </condition>
1571     <condition id="CM7_DP_LE_GCC">
1572       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the GCC Compiler</description>
1573       <require condition="CM7_DP_GCC"/>
1574       <require Dendian="Little-endian"/>
1575     </condition>
1576     <condition id="CM7_DP_BE_GCC">
1577       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the GCC Compiler</description>
1578       <require condition="CM7_DP_GCC"/>
1579       <require Dendian="Big-endian"/>
1580     </condition>
1581
1582     <condition id="CM23_GCC">
1583       <description>Cortex-M23 processor based device for the GCC Compiler</description>
1584       <require condition="CM23"/>
1585       <require Tcompiler="GCC"/>
1586     </condition>
1587     <condition id="CM23_LE_GCC">
1588       <description>Cortex-M23 processor based device in little endian mode for the GCC Compiler</description>
1589       <require condition="CM23_GCC"/>
1590       <require Dendian="Little-endian"/>
1591     </condition>
1592     <condition id="CM23_BE_GCC">
1593       <description>Cortex-M23 processor based device in big endian mode for the GCC Compiler</description>
1594       <require condition="CM23_GCC"/>
1595       <require Dendian="Big-endian"/>
1596     </condition>
1597
1598     <condition id="CM33_GCC">
1599       <description>Cortex-M33 processor based device for the GCC Compiler</description>
1600       <require condition="CM33"/>
1601       <require Tcompiler="GCC"/>
1602     </condition>
1603     <condition id="CM33_LE_GCC">
1604       <description>Cortex-M33 processor based device in little endian mode for the GCC Compiler</description>
1605       <require condition="CM33_GCC"/>
1606       <require Dendian="Little-endian"/>
1607     </condition>
1608     <condition id="CM33_BE_GCC">
1609       <description>Cortex-M33 processor based device in big endian mode for the GCC Compiler</description>
1610       <require condition="CM33_GCC"/>
1611       <require Dendian="Big-endian"/>
1612     </condition>
1613
1614     <condition id="CM33_FP_GCC">
1615       <description>Cortex-M33 processor based device using Floating Point Unit for the GCC Compiler</description>
1616       <require condition="CM33_FP"/>
1617       <require Tcompiler="GCC"/>
1618     </condition>
1619     <condition id="CM33_FP_LE_GCC">
1620       <description>Cortex-M33 processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
1621       <require condition="CM33_FP_GCC"/>
1622       <require Dendian="Little-endian"/>
1623     </condition>
1624     <condition id="CM33_FP_BE_GCC">
1625       <description>Cortex-M33 processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
1626       <require condition="CM33_FP_GCC"/>
1627       <require Dendian="Big-endian"/>
1628     </condition>
1629
1630     <condition id="CM33_NODSP_NOFPU_GCC">
1631       <description>CM33, no DSP, no FPU, GCC Compiler</description>
1632       <require condition="CM33_NODSP_NOFPU"/>
1633       <require Tcompiler="GCC"/>
1634     </condition>
1635     <condition id="CM33_DSP_NOFPU_GCC">
1636       <description>CM33, DSP, no FPU, GCC Compiler</description>
1637       <require condition="CM33_DSP_NOFPU"/>
1638       <require Tcompiler="GCC"/>
1639     </condition>
1640     <condition id="CM33_NODSP_SP_GCC">
1641       <description>CM33, no DSP, SP FPU, GCC Compiler</description>
1642       <require condition="CM33_NODSP_SP"/>
1643       <require Tcompiler="GCC"/>
1644     </condition>
1645     <condition id="CM33_DSP_SP_GCC">
1646       <description>CM33, DSP, SP FPU, GCC Compiler</description>
1647       <require condition="CM33_DSP_SP"/>
1648       <require Tcompiler="GCC"/>
1649     </condition>
1650     <condition id="CM33_NODSP_NOFPU_LE_GCC">
1651       <description>CM33, little endian, no DSP, no FPU, GCC Compiler</description>
1652       <require condition="CM33_NODSP_NOFPU_GCC"/>
1653       <require Dendian="Little-endian"/>
1654     </condition>
1655     <condition id="CM33_DSP_NOFPU_LE_GCC">
1656       <description>CM33, little endian, DSP, no FPU, GCC Compiler</description>
1657       <require condition="CM33_DSP_NOFPU_GCC"/>
1658       <require Dendian="Little-endian"/>
1659     </condition>
1660     <condition id="CM33_NODSP_SP_LE_GCC">
1661       <description>CM33, little endian, no DSP, SP FPU, GCC Compiler</description>
1662       <require condition="CM33_NODSP_SP_GCC"/>
1663       <require Dendian="Little-endian"/>
1664     </condition>
1665     <condition id="CM33_DSP_SP_LE_GCC">
1666       <description>CM33, little endian, DSP, SP FPU, GCC Compiler</description>
1667       <require condition="CM33_DSP_SP_GCC"/>
1668       <require Dendian="Little-endian"/>
1669     </condition>
1670
1671     <condition id="CM35P_GCC">
1672       <description>Cortex-M35P processor based device for the GCC Compiler</description>
1673       <require condition="CM35P"/>
1674       <require Tcompiler="GCC"/>
1675     </condition>
1676     <condition id="CM35P_LE_GCC">
1677       <description>Cortex-M35P processor based device in little endian mode for the GCC Compiler</description>
1678       <require condition="CM35P_GCC"/>
1679       <require Dendian="Little-endian"/>
1680     </condition>
1681     <condition id="CM35P_BE_GCC">
1682       <description>Cortex-M35P processor based device in big endian mode for the GCC Compiler</description>
1683       <require condition="CM35P_GCC"/>
1684       <require Dendian="Big-endian"/>
1685     </condition>
1686
1687     <condition id="CM35P_FP_GCC">
1688       <description>Cortex-M35P processor based device using Floating Point Unit for the GCC Compiler</description>
1689       <require condition="CM35P_FP"/>
1690       <require Tcompiler="GCC"/>
1691     </condition>
1692     <condition id="CM35P_FP_LE_GCC">
1693       <description>Cortex-M35P processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
1694       <require condition="CM35P_FP_GCC"/>
1695       <require Dendian="Little-endian"/>
1696     </condition>
1697     <condition id="CM35P_FP_BE_GCC">
1698       <description>Cortex-M35P processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
1699       <require condition="CM35P_FP_GCC"/>
1700       <require Dendian="Big-endian"/>
1701     </condition>
1702
1703     <condition id="CM35P_NODSP_NOFPU_GCC">
1704       <description>CM35P, no DSP, no FPU, GCC Compiler</description>
1705       <require condition="CM35P_NODSP_NOFPU"/>
1706       <require Tcompiler="GCC"/>
1707     </condition>
1708     <condition id="CM35P_DSP_NOFPU_GCC">
1709       <description>CM35P, DSP, no FPU, GCC Compiler</description>
1710       <require condition="CM35P_DSP_NOFPU"/>
1711       <require Tcompiler="GCC"/>
1712     </condition>
1713     <condition id="CM35P_NODSP_SP_GCC">
1714       <description>CM35P, no DSP, SP FPU, GCC Compiler</description>
1715       <require condition="CM35P_NODSP_SP"/>
1716       <require Tcompiler="GCC"/>
1717     </condition>
1718     <condition id="CM35P_DSP_SP_GCC">
1719       <description>CM35P, DSP, SP FPU, GCC Compiler</description>
1720       <require condition="CM35P_DSP_SP"/>
1721       <require Tcompiler="GCC"/>
1722     </condition>
1723     <condition id="CM35P_NODSP_NOFPU_LE_GCC">
1724       <description>CM35P, little endian, no DSP, no FPU, GCC Compiler</description>
1725       <require condition="CM35P_NODSP_NOFPU_GCC"/>
1726       <require Dendian="Little-endian"/>
1727     </condition>
1728     <condition id="CM35P_DSP_NOFPU_LE_GCC">
1729       <description>CM35P, little endian, DSP, no FPU, GCC Compiler</description>
1730       <require condition="CM35P_DSP_NOFPU_GCC"/>
1731       <require Dendian="Little-endian"/>
1732     </condition>
1733     <condition id="CM35P_NODSP_SP_LE_GCC">
1734       <description>CM35P, little endian, no DSP, SP FPU, GCC Compiler</description>
1735       <require condition="CM35P_NODSP_SP_GCC"/>
1736       <require Dendian="Little-endian"/>
1737     </condition>
1738     <condition id="CM35P_DSP_SP_LE_GCC">
1739       <description>CM35P, little endian, DSP, SP FPU, GCC Compiler</description>
1740       <require condition="CM35P_DSP_SP_GCC"/>
1741       <require Dendian="Little-endian"/>
1742     </condition>
1743
1744     <condition id="ARMv8MBL_GCC">
1745       <description>Armv8-M Baseline processor based device for the GCC Compiler</description>
1746       <require condition="ARMv8MBL"/>
1747       <require Tcompiler="GCC"/>
1748     </condition>
1749     <condition id="ARMv8MBL_LE_GCC">
1750       <description>Armv8-M Baseline processor based device in little endian mode for the GCC Compiler</description>
1751       <require condition="ARMv8MBL_GCC"/>
1752       <require Dendian="Little-endian"/>
1753     </condition>
1754     <condition id="ARMv8MBL_BE_GCC">
1755       <description>Armv8-M Baseline processor based device in big endian mode for the GCC Compiler</description>
1756       <require condition="ARMv8MBL_GCC"/>
1757       <require Dendian="Big-endian"/>
1758     </condition>
1759
1760     <condition id="ARMv8MML_GCC">
1761       <description>Armv8-M Mainline processor based device for the GCC Compiler</description>
1762       <require condition="ARMv8MML"/>
1763       <require Tcompiler="GCC"/>
1764     </condition>
1765     <condition id="ARMv8MML_LE_GCC">
1766       <description>Armv8-M Mainline processor based device in little endian mode for the GCC Compiler</description>
1767       <require condition="ARMv8MML_GCC"/>
1768       <require Dendian="Little-endian"/>
1769     </condition>
1770     <condition id="ARMv8MML_BE_GCC">
1771       <description>Armv8-M Mainline processor based device in big endian mode for the GCC Compiler</description>
1772       <require condition="ARMv8MML_GCC"/>
1773       <require Dendian="Big-endian"/>
1774     </condition>
1775
1776     <condition id="ARMv8MML_FP_GCC">
1777       <description>Armv8-M Mainline processor based device using Floating Point Unit for the GCC Compiler</description>
1778       <require condition="ARMv8MML_FP"/>
1779       <require Tcompiler="GCC"/>
1780     </condition>
1781     <condition id="ARMv8MML_FP_LE_GCC">
1782       <description>Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
1783       <require condition="ARMv8MML_FP_GCC"/>
1784       <require Dendian="Little-endian"/>
1785     </condition>
1786     <condition id="ARMv8MML_FP_BE_GCC">
1787       <description>Armv8-M Mainline processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
1788       <require condition="ARMv8MML_FP_GCC"/>
1789       <require Dendian="Big-endian"/>
1790     </condition>
1791
1792     <condition id="ARMv8MML_NODSP_NOFPU_GCC">
1793       <description>Armv8-M Mainline, no DSP, no FPU, GCC Compiler</description>
1794       <require condition="ARMv8MML_NODSP_NOFPU"/>
1795       <require Tcompiler="GCC"/>
1796     </condition>
1797     <condition id="ARMv8MML_DSP_NOFPU_GCC">
1798       <description>Armv8-M Mainline, DSP, no FPU, GCC Compiler</description>
1799       <require condition="ARMv8MML_DSP_NOFPU"/>
1800       <require Tcompiler="GCC"/>
1801     </condition>
1802     <condition id="ARMv8MML_NODSP_SP_GCC">
1803       <description>Armv8-M Mainline, no DSP, SP FPU, GCC Compiler</description>
1804       <require condition="ARMv8MML_NODSP_SP"/>
1805       <require Tcompiler="GCC"/>
1806     </condition>
1807     <condition id="ARMv8MML_DSP_SP_GCC">
1808       <description>Armv8-M Mainline, DSP, SP FPU, GCC Compiler</description>
1809       <require condition="ARMv8MML_DSP_SP"/>
1810       <require Tcompiler="GCC"/>
1811     </condition>
1812     <condition id="ARMv8MML_NODSP_NOFPU_LE_GCC">
1813       <description>Armv8-M Mainline, little endian, no DSP, no FPU, GCC Compiler</description>
1814       <require condition="ARMv8MML_NODSP_NOFPU_GCC"/>
1815       <require Dendian="Little-endian"/>
1816     </condition>
1817     <condition id="ARMv8MML_DSP_NOFPU_LE_GCC">
1818       <description>Armv8-M Mainline, little endian, DSP, no FPU, GCC Compiler</description>
1819       <require condition="ARMv8MML_DSP_NOFPU_GCC"/>
1820       <require Dendian="Little-endian"/>
1821     </condition>
1822     <condition id="ARMv8MML_NODSP_SP_LE_GCC">
1823       <description>Armv8-M Mainline, little endian, no DSP, SP FPU, GCC Compiler</description>
1824       <require condition="ARMv8MML_NODSP_SP_GCC"/>
1825       <require Dendian="Little-endian"/>
1826     </condition>
1827     <condition id="ARMv8MML_DSP_SP_LE_GCC">
1828       <description>Armv8-M Mainline, little endian, DSP, SP FPU, GCC Compiler</description>
1829       <require condition="ARMv8MML_DSP_SP_GCC"/>
1830       <require Dendian="Little-endian"/>
1831     </condition>
1832
1833     <!-- IAR compiler -->
1834     <condition id="CA_IAR">
1835       <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the IAR Compiler</description>
1836       <require condition="ARMv7-A Device"/>
1837       <require Tcompiler="IAR"/>
1838     </condition>
1839
1840     <condition id="CM0_IAR">
1841       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device for the IAR Compiler</description>
1842       <require condition="CM0"/>
1843       <require Tcompiler="IAR"/>
1844     </condition>
1845     <condition id="CM0_LE_IAR">
1846       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the IAR Compiler</description>
1847       <require condition="CM0_IAR"/>
1848       <require Dendian="Little-endian"/>
1849     </condition>
1850     <condition id="CM0_BE_IAR">
1851       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the IAR Compiler</description>
1852       <require condition="CM0_IAR"/>
1853       <require Dendian="Big-endian"/>
1854     </condition>
1855
1856     <condition id="CM1_IAR">
1857       <description>Cortex-M1 based device for the IAR Compiler</description>
1858       <require condition="CM1"/>
1859       <require Tcompiler="IAR"/>
1860     </condition>
1861     <condition id="CM1_LE_IAR">
1862       <description>Cortex-M1 based device in little endian mode for the IAR Compiler</description>
1863       <require condition="CM1_IAR"/>
1864       <require Dendian="Little-endian"/>
1865     </condition>
1866     <condition id="CM1_BE_IAR">
1867       <description>Cortex-M1 based device in big endian mode for the IAR Compiler</description>
1868       <require condition="CM1_IAR"/>
1869       <require Dendian="Big-endian"/>
1870     </condition>
1871
1872     <condition id="CM3_IAR">
1873       <description>Cortex-M3 or SC300 processor based device for the IAR Compiler</description>
1874       <require condition="CM3"/>
1875       <require Tcompiler="IAR"/>
1876     </condition>
1877     <condition id="CM3_LE_IAR">
1878       <description>Cortex-M3 or SC300 processor based device in little endian mode for the IAR Compiler</description>
1879       <require condition="CM3_IAR"/>
1880       <require Dendian="Little-endian"/>
1881     </condition>
1882     <condition id="CM3_BE_IAR">
1883       <description>Cortex-M3 or SC300 processor based device in big endian mode for the IAR Compiler</description>
1884       <require condition="CM3_IAR"/>
1885       <require Dendian="Big-endian"/>
1886     </condition>
1887
1888     <condition id="CM4_IAR">
1889       <description>Cortex-M4 processor based device for the IAR Compiler</description>
1890       <require condition="CM4"/>
1891       <require Tcompiler="IAR"/>
1892     </condition>
1893     <condition id="CM4_LE_IAR">
1894       <description>Cortex-M4 processor based device in little endian mode for the IAR Compiler</description>
1895       <require condition="CM4_IAR"/>
1896       <require Dendian="Little-endian"/>
1897     </condition>
1898     <condition id="CM4_BE_IAR">
1899       <description>Cortex-M4 processor based device in big endian mode for the IAR Compiler</description>
1900       <require condition="CM4_IAR"/>
1901       <require Dendian="Big-endian"/>
1902     </condition>
1903
1904     <condition id="CM4_FP_IAR">
1905       <description>Cortex-M4 processor based device using Floating Point Unit for the IAR Compiler</description>
1906       <require condition="CM4_FP"/>
1907       <require Tcompiler="IAR"/>
1908     </condition>
1909     <condition id="CM4_FP_LE_IAR">
1910       <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
1911       <require condition="CM4_FP_IAR"/>
1912       <require Dendian="Little-endian"/>
1913     </condition>
1914     <condition id="CM4_FP_BE_IAR">
1915       <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
1916       <require condition="CM4_FP_IAR"/>
1917       <require Dendian="Big-endian"/>
1918     </condition>
1919
1920     <condition id="CM7_IAR">
1921       <description>Cortex-M7 processor based device for the IAR Compiler</description>
1922       <require condition="CM7"/>
1923       <require Tcompiler="IAR"/>
1924     </condition>
1925     <condition id="CM7_LE_IAR">
1926       <description>Cortex-M7 processor based device in little endian mode for the IAR Compiler</description>
1927       <require condition="CM7_IAR"/>
1928       <require Dendian="Little-endian"/>
1929     </condition>
1930     <condition id="CM7_BE_IAR">
1931       <description>Cortex-M7 processor based device in big endian mode for the IAR Compiler</description>
1932       <require condition="CM7_IAR"/>
1933       <require Dendian="Big-endian"/>
1934     </condition>
1935
1936     <condition id="CM7_FP_IAR">
1937       <description>Cortex-M7 processor based device using Floating Point Unit for the IAR Compiler</description>
1938       <require condition="CM7_FP"/>
1939       <require Tcompiler="IAR"/>
1940     </condition>
1941     <condition id="CM7_FP_LE_IAR">
1942       <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
1943       <require condition="CM7_FP_IAR"/>
1944       <require Dendian="Little-endian"/>
1945     </condition>
1946     <condition id="CM7_FP_BE_IAR">
1947       <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
1948       <require condition="CM7_FP_IAR"/>
1949       <require Dendian="Big-endian"/>
1950     </condition>
1951
1952     <condition id="CM7_SP_IAR">
1953       <description>Cortex-M7 processor based device using Floating Point Unit (SP) for the IAR Compiler</description>
1954       <require condition="CM7_SP"/>
1955       <require Tcompiler="IAR"/>
1956     </condition>
1957     <condition id="CM7_SP_LE_IAR">
1958       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the IAR Compiler</description>
1959       <require condition="CM7_SP_IAR"/>
1960       <require Dendian="Little-endian"/>
1961     </condition>
1962     <condition id="CM7_SP_BE_IAR">
1963       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the IAR Compiler</description>
1964       <require condition="CM7_SP_IAR"/>
1965       <require Dendian="Big-endian"/>
1966     </condition>
1967
1968     <condition id="CM7_DP_IAR">
1969       <description>Cortex-M7 processor based device using Floating Point Unit (DP) for the IAR Compiler</description>
1970       <require condition="CM7_DP"/>
1971       <require Tcompiler="IAR"/>
1972     </condition>
1973     <condition id="CM7_DP_LE_IAR">
1974       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the IAR Compiler</description>
1975       <require condition="CM7_DP_IAR"/>
1976       <require Dendian="Little-endian"/>
1977     </condition>
1978     <condition id="CM7_DP_BE_IAR">
1979       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the IAR Compiler</description>
1980       <require condition="CM7_DP_IAR"/>
1981       <require Dendian="Big-endian"/>
1982     </condition>
1983
1984     <condition id="CM23_IAR">
1985       <description>Cortex-M23 processor based device for the IAR Compiler</description>
1986       <require condition="CM23"/>
1987       <require Tcompiler="IAR"/>
1988     </condition>
1989     <condition id="CM23_LE_IAR">
1990       <description>Cortex-M23 processor based device in little endian mode for the IAR Compiler</description>
1991       <require condition="CM23_IAR"/>
1992       <require Dendian="Little-endian"/>
1993     </condition>
1994     <condition id="CM23_BE_IAR">
1995       <description>Cortex-M23 processor based device in big endian mode for the IAR Compiler</description>
1996       <require condition="CM23_IAR"/>
1997       <require Dendian="Big-endian"/>
1998     </condition>
1999
2000     <condition id="CM33_IAR">
2001       <description>Cortex-M33 processor based device for the IAR Compiler</description>
2002       <require condition="CM33"/>
2003       <require Tcompiler="IAR"/>
2004     </condition>
2005     <condition id="CM33_LE_IAR">
2006       <description>Cortex-M33 processor based device in little endian mode for the IAR Compiler</description>
2007       <require condition="CM33_IAR"/>
2008       <require Dendian="Little-endian"/>
2009     </condition>
2010     <condition id="CM33_BE_IAR">
2011       <description>Cortex-M33 processor based device in big endian mode for the IAR Compiler</description>
2012       <require condition="CM33_IAR"/>
2013       <require Dendian="Big-endian"/>
2014     </condition>
2015
2016     <condition id="CM33_FP_IAR">
2017       <description>Cortex-M33 processor based device using Floating Point Unit for the IAR Compiler</description>
2018       <require condition="CM33_FP"/>
2019       <require Tcompiler="IAR"/>
2020     </condition>
2021     <condition id="CM33_FP_LE_IAR">
2022       <description>Cortex-M33 processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
2023       <require condition="CM33_FP_IAR"/>
2024       <require Dendian="Little-endian"/>
2025     </condition>
2026     <condition id="CM33_FP_BE_IAR">
2027       <description>Cortex-M33 processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
2028       <require condition="CM33_FP_IAR"/>
2029       <require Dendian="Big-endian"/>
2030     </condition>
2031
2032     <condition id="CM33_NODSP_NOFPU_IAR">
2033       <description>CM33, no DSP, no FPU, IAR Compiler</description>
2034       <require condition="CM33_NODSP_NOFPU"/>
2035       <require Tcompiler="IAR"/>
2036     </condition>
2037     <condition id="CM33_DSP_NOFPU_IAR">
2038       <description>CM33, DSP, no FPU, IAR Compiler</description>
2039       <require condition="CM33_DSP_NOFPU"/>
2040       <require Tcompiler="IAR"/>
2041     </condition>
2042     <condition id="CM33_NODSP_SP_IAR">
2043       <description>CM33, no DSP, SP FPU, IAR Compiler</description>
2044       <require condition="CM33_NODSP_SP"/>
2045       <require Tcompiler="IAR"/>
2046     </condition>
2047     <condition id="CM33_DSP_SP_IAR">
2048       <description>CM33, DSP, SP FPU, IAR Compiler</description>
2049       <require condition="CM33_DSP_SP"/>
2050       <require Tcompiler="IAR"/>
2051     </condition>
2052     <condition id="CM33_NODSP_NOFPU_LE_IAR">
2053       <description>CM33, little endian, no DSP, no FPU, IAR Compiler</description>
2054       <require condition="CM33_NODSP_NOFPU_IAR"/>
2055       <require Dendian="Little-endian"/>
2056     </condition>
2057     <condition id="CM33_DSP_NOFPU_LE_IAR">
2058       <description>CM33, little endian, DSP, no FPU, IAR Compiler</description>
2059       <require condition="CM33_DSP_NOFPU_IAR"/>
2060       <require Dendian="Little-endian"/>
2061     </condition>
2062     <condition id="CM33_NODSP_SP_LE_IAR">
2063       <description>CM33, little endian, no DSP, SP FPU, IAR Compiler</description>
2064       <require condition="CM33_NODSP_SP_IAR"/>
2065       <require Dendian="Little-endian"/>
2066     </condition>
2067     <condition id="CM33_DSP_SP_LE_IAR">
2068       <description>CM33, little endian, DSP, SP FPU, IAR Compiler</description>
2069       <require condition="CM33_DSP_SP_IAR"/>
2070       <require Dendian="Little-endian"/>
2071     </condition>
2072
2073     <condition id="CM35P_IAR">
2074       <description>Cortex-M35P processor based device for the IAR Compiler</description>
2075       <require condition="CM35P"/>
2076       <require Tcompiler="IAR"/>
2077     </condition>
2078     <condition id="CM35P_LE_IAR">
2079       <description>Cortex-M35P processor based device in little endian mode for the IAR Compiler</description>
2080       <require condition="CM35P_IAR"/>
2081       <require Dendian="Little-endian"/>
2082     </condition>
2083     <condition id="CM35P_BE_IAR">
2084       <description>Cortex-M35P processor based device in big endian mode for the IAR Compiler</description>
2085       <require condition="CM35P_IAR"/>
2086       <require Dendian="Big-endian"/>
2087     </condition>
2088
2089     <condition id="CM35P_FP_IAR">
2090       <description>Cortex-M35P processor based device using Floating Point Unit for the IAR Compiler</description>
2091       <require condition="CM35P_FP"/>
2092       <require Tcompiler="IAR"/>
2093     </condition>
2094     <condition id="CM35P_FP_LE_IAR">
2095       <description>Cortex-M35P processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
2096       <require condition="CM35P_FP_IAR"/>
2097       <require Dendian="Little-endian"/>
2098     </condition>
2099     <condition id="CM35P_FP_BE_IAR">
2100       <description>Cortex-M35P processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
2101       <require condition="CM35P_FP_IAR"/>
2102       <require Dendian="Big-endian"/>
2103     </condition>
2104
2105     <condition id="CM35P_NODSP_NOFPU_IAR">
2106       <description>CM35P, no DSP, no FPU, IAR Compiler</description>
2107       <require condition="CM35P_NODSP_NOFPU"/>
2108       <require Tcompiler="IAR"/>
2109     </condition>
2110     <condition id="CM35P_DSP_NOFPU_IAR">
2111       <description>CM35P, DSP, no FPU, IAR Compiler</description>
2112       <require condition="CM35P_DSP_NOFPU"/>
2113       <require Tcompiler="IAR"/>
2114     </condition>
2115     <condition id="CM35P_NODSP_SP_IAR">
2116       <description>CM35P, no DSP, SP FPU, IAR Compiler</description>
2117       <require condition="CM35P_NODSP_SP"/>
2118       <require Tcompiler="IAR"/>
2119     </condition>
2120     <condition id="CM35P_DSP_SP_IAR">
2121       <description>CM35P, DSP, SP FPU, IAR Compiler</description>
2122       <require condition="CM35P_DSP_SP"/>
2123       <require Tcompiler="IAR"/>
2124     </condition>
2125     <condition id="CM35P_NODSP_NOFPU_LE_IAR">
2126       <description>CM35P, little endian, no DSP, no FPU, IAR Compiler</description>
2127       <require condition="CM35P_NODSP_NOFPU_IAR"/>
2128       <require Dendian="Little-endian"/>
2129     </condition>
2130     <condition id="CM35P_DSP_NOFPU_LE_IAR">
2131       <description>CM35P, little endian, DSP, no FPU, IAR Compiler</description>
2132       <require condition="CM35P_DSP_NOFPU_IAR"/>
2133       <require Dendian="Little-endian"/>
2134     </condition>
2135     <condition id="CM35P_NODSP_SP_LE_IAR">
2136       <description>CM35P, little endian, no DSP, SP FPU, IAR Compiler</description>
2137       <require condition="CM35P_NODSP_SP_IAR"/>
2138       <require Dendian="Little-endian"/>
2139     </condition>
2140     <condition id="CM35P_DSP_SP_LE_IAR">
2141       <description>CM35P, little endian, DSP, SP FPU, IAR Compiler</description>
2142       <require condition="CM35P_DSP_SP_IAR"/>
2143       <require Dendian="Little-endian"/>
2144     </condition>
2145
2146     <condition id="ARMv8MBL_IAR">
2147       <description>Armv8-M Baseline processor based device for the IAR Compiler</description>
2148       <require condition="ARMv8MBL"/>
2149       <require Tcompiler="IAR"/>
2150     </condition>
2151     <condition id="ARMv8MBL_LE_IAR">
2152       <description>Armv8-M Baseline processor based device in little endian mode for the IAR Compiler</description>
2153       <require condition="ARMv8MBL_IAR"/>
2154       <require Dendian="Little-endian"/>
2155     </condition>
2156     <condition id="ARMv8MBL_BE_IAR">
2157       <description>Armv8-M Baseline processor based device in big endian mode for the IAR Compiler</description>
2158       <require condition="ARMv8MBL_IAR"/>
2159       <require Dendian="Big-endian"/>
2160     </condition>
2161
2162     <condition id="ARMv8MML_IAR">
2163       <description>Armv8-M Mainline processor based device for the IAR Compiler</description>
2164       <require condition="ARMv8MML"/>
2165       <require Tcompiler="IAR"/>
2166     </condition>
2167     <condition id="ARMv8MML_LE_IAR">
2168       <description>Armv8-M Mainline processor based device in little endian mode for the IAR Compiler</description>
2169       <require condition="ARMv8MML_IAR"/>
2170       <require Dendian="Little-endian"/>
2171     </condition>
2172     <condition id="ARMv8MML_BE_IAR">
2173       <description>Armv8-M Mainline processor based device in big endian mode for the IAR Compiler</description>
2174       <require condition="ARMv8MML_IAR"/>
2175       <require Dendian="Big-endian"/>
2176     </condition>
2177
2178     <condition id="ARMv8MML_FP_IAR">
2179       <description>Armv8-M Mainline processor based device using Floating Point Unit for the IAR Compiler</description>
2180       <require condition="ARMv8MML_FP"/>
2181       <require Tcompiler="IAR"/>
2182     </condition>
2183     <condition id="ARMv8MML_FP_LE_IAR">
2184       <description>Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
2185       <require condition="ARMv8MML_FP_IAR"/>
2186       <require Dendian="Little-endian"/>
2187     </condition>
2188     <condition id="ARMv8MML_FP_BE_IAR">
2189       <description>Armv8-M Mainline processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
2190       <require condition="ARMv8MML_FP_IAR"/>
2191       <require Dendian="Big-endian"/>
2192     </condition>
2193
2194     <condition id="ARMv8MML_NODSP_NOFPU_IAR">
2195       <description>Armv8-M Mainline, no DSP, no FPU, IAR Compiler</description>
2196       <require condition="ARMv8MML_NODSP_NOFPU"/>
2197       <require Tcompiler="IAR"/>
2198     </condition>
2199     <condition id="ARMv8MML_DSP_NOFPU_IAR">
2200       <description>Armv8-M Mainline, DSP, no FPU, IAR Compiler</description>
2201       <require condition="ARMv8MML_DSP_NOFPU"/>
2202       <require Tcompiler="IAR"/>
2203     </condition>
2204     <condition id="ARMv8MML_NODSP_SP_IAR">
2205       <description>Armv8-M Mainline, no DSP, SP FPU, IAR Compiler</description>
2206       <require condition="ARMv8MML_NODSP_SP"/>
2207       <require Tcompiler="IAR"/>
2208     </condition>
2209     <condition id="ARMv8MML_DSP_SP_IAR">
2210       <description>Armv8-M Mainline, DSP, SP FPU, IAR Compiler</description>
2211       <require condition="ARMv8MML_DSP_SP"/>
2212       <require Tcompiler="IAR"/>
2213     </condition>
2214     <condition id="ARMv8MML_NODSP_NOFPU_LE_IAR">
2215       <description>Armv8-M Mainline, little endian, no DSP, no FPU, IAR Compiler</description>
2216       <require condition="ARMv8MML_NODSP_NOFPU_IAR"/>
2217       <require Dendian="Little-endian"/>
2218     </condition>
2219     <condition id="ARMv8MML_DSP_NOFPU_LE_IAR">
2220       <description>Armv8-M Mainline, little endian, DSP, no FPU, IAR Compiler</description>
2221       <require condition="ARMv8MML_DSP_NOFPU_IAR"/>
2222       <require Dendian="Little-endian"/>
2223     </condition>
2224     <condition id="ARMv8MML_NODSP_SP_LE_IAR">
2225       <description>Armv8-M Mainline, little endian, no DSP, SP FPU, IAR Compiler</description>
2226       <require condition="ARMv8MML_NODSP_SP_IAR"/>
2227       <require Dendian="Little-endian"/>
2228     </condition>
2229     <condition id="ARMv8MML_DSP_SP_LE_IAR">
2230       <description>Armv8-M Mainline, little endian, DSP, SP FPU, IAR Compiler</description>
2231       <require condition="ARMv8MML_DSP_SP_IAR"/>
2232       <require Dendian="Little-endian"/>
2233     </condition>
2234
2235     <!-- conditions selecting single devices and CMSIS Core -->
2236     <!-- used for component startup, GCC version is used for C-Startup -->
2237     <condition id="ARMCM0 CMSIS">
2238       <description>Generic Arm Cortex-M0 device startup and depends on CMSIS Core</description>
2239       <require Dvendor="ARM:82" Dname="ARMCM0"/>
2240       <require Cclass="CMSIS" Cgroup="CORE"/>
2241     </condition>
2242     <condition id="ARMCM0 CMSIS GCC">
2243       <description>Generic ARM Cortex-M0 device startup and depends on CMSIS Core requiring GCC</description>
2244       <require condition="ARMCM0 CMSIS"/>
2245       <require condition="GCC"/>
2246     </condition>
2247
2248     <condition id="ARMCM0+ CMSIS">
2249       <description>Generic Arm Cortex-M0+ device startup and depends on CMSIS Core</description>
2250       <require Dvendor="ARM:82" Dname="ARMCM0P*"/>
2251       <require Cclass="CMSIS" Cgroup="CORE"/>
2252     </condition>
2253     <condition id="ARMCM0+ CMSIS GCC">
2254       <description>Generic Arm Cortex-M0+ device startup and depends CMSIS Core requiring GCC</description>
2255       <require condition="ARMCM0+ CMSIS"/>
2256       <require condition="GCC"/>
2257     </condition>
2258
2259     <condition id="ARMCM1 CMSIS">
2260       <description>Generic Arm Cortex-M1 device startup and depends on CMSIS Core</description>
2261       <require Dvendor="ARM:82" Dname="ARMCM1"/>
2262       <require Cclass="CMSIS" Cgroup="CORE"/>
2263     </condition>
2264     <condition id="ARMCM1 CMSIS GCC">
2265       <description>Generic ARM Cortex-M1 device startup and depends on CMSIS Core requiring GCC</description>
2266       <require condition="ARMCM1 CMSIS"/>
2267       <require condition="GCC"/>
2268     </condition>
2269
2270     <condition id="ARMCM3 CMSIS">
2271       <description>Generic Arm Cortex-M3 device startup and depends on CMSIS Core</description>
2272       <require Dvendor="ARM:82" Dname="ARMCM3"/>
2273       <require Cclass="CMSIS" Cgroup="CORE"/>
2274     </condition>
2275     <condition id="ARMCM3 CMSIS GCC">
2276       <description>Generic Arm Cortex-M3 device startup and depends on CMSIS Core requiring GCC</description>
2277       <require condition="ARMCM3 CMSIS"/>
2278       <require condition="GCC"/>
2279     </condition>
2280
2281     <condition id="ARMCM4 CMSIS">
2282       <description>Generic Arm Cortex-M4 device startup and depends on CMSIS Core</description>
2283       <require Dvendor="ARM:82" Dname="ARMCM4*"/>
2284       <require Cclass="CMSIS" Cgroup="CORE"/>
2285     </condition>
2286     <condition id="ARMCM4 CMSIS GCC">
2287       <description>Generic Arm Cortex-M4 device startup and depends on CMSIS Core requiring GCC</description>
2288       <require condition="ARMCM4 CMSIS"/>
2289       <require condition="GCC"/>
2290     </condition>
2291
2292     <condition id="ARMCM7 CMSIS">
2293       <description>Generic Arm Cortex-M7 device startup and depends on CMSIS Core</description>
2294       <require Dvendor="ARM:82" Dname="ARMCM7*"/>
2295       <require Cclass="CMSIS" Cgroup="CORE"/>
2296     </condition>
2297     <condition id="ARMCM7 CMSIS GCC">
2298       <description>Generic Arm Cortex-M7 device startup and depends on CMSIS Core requiring GCC</description>
2299       <require condition="ARMCM7 CMSIS"/>
2300       <require condition="GCC"/>
2301     </condition>
2302
2303     <condition id="ARMCM23 CMSIS">
2304       <description>Generic Arm Cortex-M23 device startup and depends on CMSIS Core</description>
2305       <require Dvendor="ARM:82" Dname="ARMCM23*"/>
2306       <require Cclass="CMSIS" Cgroup="CORE"/>
2307     </condition>
2308     <condition id="ARMCM23 CMSIS GCC">
2309       <description>Generic Arm Cortex-M23 device startup and depends on CMSIS Core requiring GCC</description>
2310       <require condition="ARMCM23 CMSIS"/>
2311       <require condition="GCC"/>
2312     </condition>
2313
2314     <condition id="ARMCM33 CMSIS">
2315       <description>Generic Arm Cortex-M33 device startup and depends on CMSIS Core</description>
2316       <require Dvendor="ARM:82" Dname="ARMCM33*"/>
2317       <require Cclass="CMSIS" Cgroup="CORE"/>
2318     </condition>
2319     <condition id="ARMCM33 CMSIS GCC">
2320       <description>Generic Arm Cortex-M33 device startup and depends on CMSIS Core requiring GCC</description>
2321       <require condition="ARMCM33 CMSIS"/>
2322       <require condition="GCC"/>
2323     </condition>
2324
2325     <condition id="ARMCM35P CMSIS">
2326       <description>Generic Arm Cortex-M35P device startup and depends on CMSIS Core</description>
2327       <require Dvendor="ARM:82" Dname="ARMCM35P*"/>
2328       <require Cclass="CMSIS" Cgroup="CORE"/>
2329     </condition>
2330     <condition id="ARMCM35P CMSIS GCC">
2331       <description>Generic Arm Cortex-M35P device startup and depends on CMSIS Core requiring GCC</description>
2332       <require condition="ARMCM35P CMSIS"/>
2333       <require condition="GCC"/>
2334     </condition>
2335
2336     <condition id="ARMSC000 CMSIS">
2337       <description>Generic Arm SC000 device startup and depends on CMSIS Core</description>
2338       <require Dvendor="ARM:82" Dname="ARMSC000"/>
2339       <require Cclass="CMSIS" Cgroup="CORE"/>
2340     </condition>
2341     <condition id="ARMSC000 CMSIS GCC">
2342       <description>Generic Arm SC000 device startup and depends on CMSIS Core requiring GCC</description>
2343       <require condition="ARMSC000 CMSIS"/>
2344       <require condition="GCC"/>
2345     </condition>
2346
2347     <condition id="ARMSC300 CMSIS">
2348       <description>Generic Arm SC300 device startup and depends on CMSIS Core</description>
2349       <require Dvendor="ARM:82" Dname="ARMSC300"/>
2350       <require Cclass="CMSIS" Cgroup="CORE"/>
2351     </condition>
2352     <condition id="ARMSC300 CMSIS GCC">
2353       <description>Generic Arm SC300 device startup and dependson CMSIS Core requiring GCC</description>
2354       <require condition="ARMSC300 CMSIS"/>
2355       <require condition="GCC"/>
2356     </condition>
2357
2358     <condition id="ARMv8MBL CMSIS">
2359       <description>Generic Armv8-M Baseline device startup and depends on CMSIS Core</description>
2360       <require Dvendor="ARM:82" Dname="ARMv8MBL"/>
2361       <require Cclass="CMSIS" Cgroup="CORE"/>
2362     </condition>
2363     <condition id="ARMv8MBL CMSIS GCC">
2364       <description>Generic Armv8-M Baseline device startup and depends on CMSIS Core requiring GCC</description>
2365       <require condition="ARMv8MBL CMSIS"/>
2366       <require condition="GCC"/>
2367     </condition>
2368
2369     <condition id="ARMv8MML CMSIS">
2370       <description>Generic Armv8-M Mainline device startup and depends on CMSIS Core</description>
2371       <require Dvendor="ARM:82" Dname="ARMv8MML*"/>
2372       <require Cclass="CMSIS" Cgroup="CORE"/>
2373     </condition>
2374     <condition id="ARMv8MML CMSIS GCC">
2375       <description>Generic Armv8-M Mainline device startup and depends on CMSIS Core requiring GCC</description>
2376       <require condition="ARMv8MML CMSIS"/>
2377       <require condition="GCC"/>
2378     </condition>
2379
2380     <condition id="ARMCA5 CMSIS">
2381       <description>Generic Arm Cortex-A5 device startup and depends on CMSIS Core</description>
2382       <require Dvendor="ARM:82" Dname="ARMCA5"/>
2383       <require Cclass="CMSIS" Cgroup="CORE"/>
2384     </condition>
2385
2386     <condition id="ARMCA7 CMSIS">
2387       <description>Generic Arm Cortex-A7 device startup and depends on CMSIS Core</description>
2388       <require Dvendor="ARM:82" Dname="ARMCA7"/>
2389       <require Cclass="CMSIS" Cgroup="CORE"/>
2390     </condition>
2391
2392     <condition id="ARMCA9 CMSIS">
2393       <description>Generic Arm Cortex-A9 device startup and depends on CMSIS Core</description>
2394       <require Dvendor="ARM:82" Dname="ARMCA9"/>
2395       <require Cclass="CMSIS" Cgroup="CORE"/>
2396     </condition>
2397
2398     <!-- CMSIS DSP -->
2399     <condition id="CMSIS DSP">
2400       <description>Components required for DSP</description>
2401       <require condition="ARMv6_7_8-M Device"/>
2402       <require condition="ARMCC GCC IAR"/>
2403       <require Cclass="CMSIS" Cgroup="CORE"/>
2404     </condition>
2405
2406     <!-- CMSIS NN -->
2407     <condition id="CMSIS NN">
2408       <description>Components required for NN</description>
2409       <require condition="CMSIS DSP"/>
2410     </condition>
2411
2412     <!-- RTOS RTX -->
2413     <condition id="RTOS RTX">
2414       <description>Components required for RTOS RTX</description>
2415       <require condition="ARMv6_7-M Device"/>
2416       <require condition="ARMCC GCC IAR"/>
2417       <require Cclass="Device" Cgroup="Startup"/>
2418       <deny    Cclass="CMSIS"  Cgroup="RTOS2" Csub="Keil RTX5"/>
2419     </condition>
2420     <condition id="RTOS RTX IFX">
2421       <description>Components required for RTOS RTX IFX</description>
2422       <require condition="ARMv6_7-M Device"/>
2423       <require condition="ARMCC GCC IAR"/>
2424       <require Dvendor="Infineon:7" Dname="XMC4*"/>
2425       <require Cclass="Device" Cgroup="Startup"/>
2426       <deny    Cclass="CMSIS"  Cgroup="RTOS2" Csub="Keil RTX5"/>
2427     </condition>
2428     <condition id="RTOS RTX5">
2429       <description>Components required for RTOS RTX5</description>
2430       <require condition="ARMv6_7_8-M Device"/>
2431       <require condition="ARMCC GCC IAR"/>
2432       <require Cclass="CMSIS"  Cgroup="RTOS2" Csub="Keil RTX5"/>
2433     </condition>
2434     <condition id="RTOS2 RTX5">
2435       <description>Components required for RTOS2 RTX5</description>
2436       <require condition="ARMv6_7_8-M Device"/>
2437       <require condition="ARMCC GCC IAR"/>
2438       <require Cclass="CMSIS"  Cgroup="CORE"/>
2439       <require Cclass="Device" Cgroup="Startup"/>
2440     </condition>
2441     <condition id="RTOS2 RTX5 v7-A">
2442       <description>Components required for RTOS2 RTX5 on Armv7-A</description>
2443       <require condition="ARMv7-A Device"/>
2444       <require condition="ARMCC GCC IAR"/>
2445       <require Cclass="CMSIS"  Cgroup="CORE"/>
2446       <require Cclass="Device" Cgroup="Startup"/>
2447       <require Cclass="Device" Cgroup="OS Tick"/>
2448       <require Cclass="Device" Cgroup="IRQ Controller"/>
2449     </condition>
2450     <condition id="RTOS2 RTX5 Lib">
2451       <description>Components required for RTOS2 RTX5 Library</description>
2452       <require condition="ARMv6_7_8-M Device"/>
2453       <require condition="ARMCC GCC IAR"/>
2454       <require Cclass="CMSIS"  Cgroup="CORE"/>
2455       <require Cclass="Device" Cgroup="Startup"/>
2456     </condition>
2457     <condition id="RTOS2 RTX5 NS">
2458       <description>Components required for RTOS2 RTX5 in Non-Secure Domain</description>
2459       <require condition="ARMv8-M TZ Device"/>
2460       <require condition="ARMCC GCC IAR"/>
2461       <require Cclass="CMSIS"  Cgroup="CORE"/>
2462       <require Cclass="Device" Cgroup="Startup"/>
2463     </condition>
2464
2465     <!-- OS Tick -->
2466     <condition id="OS Tick PTIM">
2467       <description>Components required for OS Tick Private Timer</description>
2468       <require condition="CA5_CA9"/>
2469       <require Cclass="Device" Cgroup="IRQ Controller"/>
2470     </condition>
2471
2472     <condition id="OS Tick GTIM">
2473       <description>Components required for OS Tick Generic Physical Timer</description>
2474       <require condition="CA7"/>
2475       <require Cclass="Device" Cgroup="IRQ Controller"/>
2476     </condition>
2477
2478   </conditions>
2479
2480   <components>
2481     <!-- CMSIS-Core component -->
2482     <component Cclass="CMSIS" Cgroup="CORE" Cversion="5.1.2"  condition="ARMv6_7_8-M Device" >
2483       <description>CMSIS-CORE for Cortex-M, SC000, SC300, ARMv8-M</description>
2484       <files>
2485         <!-- CPU independent -->
2486         <file category="doc"     name="CMSIS/Documentation/Core/html/index.html"/>
2487         <file category="include" name="CMSIS/Core/Include/"/>
2488         <file category="header"  name="CMSIS/Core/Include/tz_context.h" condition="ARMv8-M TZ Device"/>
2489         <!-- Code template -->
2490         <file category="sourceC" attr="template" condition="ARMv8-M TZ Device" name="CMSIS/Core/Template/ARMv8-M/main_s.c"     version="1.1.0" select="Secure mode 'main' module for ARMv8-M"/>
2491         <file category="sourceC" attr="template" condition="ARMv8-M TZ Device" name="CMSIS/Core/Template/ARMv8-M/tz_context.c" version="1.1.0" select="RTOS Context Management (TrustZone for ARMv8-M)" />
2492       </files>
2493     </component>
2494
2495     <component Cclass="CMSIS" Cgroup="CORE" Cversion="1.1.2"  condition="ARMv7-A Device" >
2496       <description>CMSIS-CORE for Cortex-A</description>
2497       <files>
2498         <!-- CPU independent -->
2499         <file category="doc"     name="CMSIS/Documentation/Core_A/html/index.html"/>
2500         <file category="include" name="CMSIS/Core_A/Include/"/>
2501       </files>
2502     </component>
2503
2504     <!-- CMSIS-Startup components -->
2505     <!-- Cortex-M0 -->
2506     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM0 CMSIS">
2507       <description>System and Startup for Generic Arm Cortex-M0 device</description>
2508       <files>
2509         <!-- include folder / device header file -->
2510         <file category="header"  name="Device/ARM/ARMCM0/Include/ARMCM0.h"/>
2511         <!-- startup / system file -->
2512         <file category="sourceAsm"    name="Device/ARM/ARMCM0/Source/ARM/startup_ARMCM0.s" version="1.0.0" attr="config" condition="ARMCC"/>
2513         <file category="sourceAsm"    name="Device/ARM/ARMCM0/Source/GCC/startup_ARMCM0.S" version="1.0.0" attr="config" condition="GCC"/>
2514         <file category="linkerScript" name="Device/ARM/ARMCM0/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2515         <file category="sourceAsm"    name="Device/ARM/ARMCM0/Source/IAR/startup_ARMCM0.s" version="1.0.0" attr="config" condition="IAR"/>
2516         <file category="sourceC"      name="Device/ARM/ARMCM0/Source/system_ARMCM0.c"      version="1.0.0" attr="config"/>
2517       </files>
2518     </component>
2519     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM0 CMSIS GCC">
2520       <description>System and Startup for Generic Arm Cortex-M0 device</description>
2521       <files>
2522         <!-- include folder / device header file -->
2523         <file category="header"  name="Device/ARM/ARMCM0/Include/ARMCM0.h"/>
2524         <!-- startup / system file -->
2525         <file category="sourceC"      name="Device/ARM/ARMCM0/Source/GCC/startup_ARMCM0.c" version="1.0.0" attr="config" condition="GCC"/>
2526         <file category="linkerScript" name="Device/ARM/ARMCM0/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2527         <file category="sourceC"      name="Device/ARM/ARMCM0/Source/system_ARMCM0.c"      version="1.0.0" attr="config"/>
2528       </files>
2529     </component>
2530
2531     <!-- Cortex-M0+ -->
2532     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM0+ CMSIS">
2533       <description>System and Startup for Generic Arm Cortex-M0+ device</description>
2534       <files>
2535         <!-- include folder / device header file -->
2536         <file category="header"  name="Device/ARM/ARMCM0plus/Include/ARMCM0plus.h"/>
2537         <!-- startup / system file -->
2538         <file category="sourceAsm"    name="Device/ARM/ARMCM0plus/Source/ARM/startup_ARMCM0plus.s" version="1.0.0" attr="config" condition="ARMCC"/>
2539         <file category="sourceAsm"    name="Device/ARM/ARMCM0plus/Source/GCC/startup_ARMCM0plus.S" version="1.0.0" attr="config" condition="GCC"/>
2540         <file category="linkerScript" name="Device/ARM/ARMCM0plus/Source/GCC/gcc_arm.ld"           version="1.0.0" attr="config" condition="GCC"/>
2541         <file category="sourceAsm"    name="Device/ARM/ARMCM0plus/Source/IAR/startup_ARMCM0plus.s" version="1.0.0" attr="config" condition="IAR"/>
2542         <file category="sourceC"      name="Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c"      version="1.0.0" attr="config"/>
2543       </files>
2544     </component>
2545     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM0+ CMSIS GCC">
2546       <description>System and Startup for Generic Arm Cortex-M0+ device</description>
2547       <files>
2548         <!-- include folder / device header file -->
2549         <file category="header"  name="Device/ARM/ARMCM0plus/Include/ARMCM0plus.h"/>
2550         <!-- startup / system file -->
2551         <file category="sourceC"      name="Device/ARM/ARMCM0plus/Source/GCC/startup_ARMCM0plus.c" version="1.0.0" attr="config" condition="GCC"/>
2552         <file category="linkerScript" name="Device/ARM/ARMCM0plus/Source/GCC/gcc_arm.ld"           version="1.0.0" attr="config" condition="GCC"/>
2553         <file category="sourceC"      name="Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c"      version="1.0.0" attr="config"/>
2554       </files>
2555     </component>
2556
2557     <!-- Cortex-M1 -->
2558     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM1 CMSIS">
2559       <description>System and Startup for Generic Arm Cortex-M1 device</description>
2560       <files>
2561         <!-- include folder / device header file -->
2562         <file category="header"  name="Device/ARM/ARMCM1/Include/ARMCM1.h"/>
2563         <!-- startup / system file -->
2564         <file category="sourceAsm"    name="Device/ARM/ARMCM1/Source/ARM/startup_ARMCM1.s" version="1.0.0" attr="config" condition="ARMCC"/>
2565         <file category="sourceC"      name="Device/ARM/ARMCM1/Source/GCC/startup_ARMCM1.S" version="1.0.0" attr="config" condition="GCC"/>
2566         <file category="linkerScript" name="Device/ARM/ARMCM1/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2567         <file category="sourceAsm"    name="Device/ARM/ARMCM1/Source/IAR/startup_ARMCM1.s" version="1.0.0" attr="config" condition="IAR"/>
2568         <file category="sourceC"      name="Device/ARM/ARMCM1/Source/system_ARMCM1.c"      version="1.0.0" attr="config"/>
2569       </files>
2570     </component>
2571     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM1 CMSIS GCC">
2572       <description>System and Startup for Generic Arm Cortex-M1 device</description>
2573       <files>
2574         <!-- include folder / device header file -->
2575         <file category="header"  name="Device/ARM/ARMCM1/Include/ARMCM1.h"/>
2576         <!-- startup / system file -->
2577         <file category="sourceC"      name="Device/ARM/ARMCM1/Source/GCC/startup_ARMCM1.c" version="1.0.0" attr="config" condition="GCC"/>
2578         <file category="linkerScript" name="Device/ARM/ARMCM1/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2579         <file category="sourceC"      name="Device/ARM/ARMCM1/Source/system_ARMCM1.c"      version="1.0.0" attr="config"/>
2580       </files>
2581     </component>
2582
2583     <!-- Cortex-M3 -->
2584     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM3 CMSIS">
2585       <description>System and Startup for Generic Arm Cortex-M3 device</description>
2586       <files>
2587         <!-- include folder / device header file -->
2588         <file category="header"  name="Device/ARM/ARMCM3/Include/ARMCM3.h"/>
2589         <!-- startup / system file -->
2590         <file category="sourceAsm"    name="Device/ARM/ARMCM3/Source/ARM/startup_ARMCM3.s" version="1.0.0" attr="config" condition="ARMCC"/>
2591         <file category="sourceAsm"    name="Device/ARM/ARMCM3/Source/GCC/startup_ARMCM3.S" version="1.0.0" attr="config" condition="GCC"/>
2592         <file category="linkerScript" name="Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2593         <file category="sourceAsm"    name="Device/ARM/ARMCM3/Source/IAR/startup_ARMCM3.s" version="1.0.0" attr="config" condition="IAR"/>
2594         <file category="sourceC"      name="Device/ARM/ARMCM3/Source/system_ARMCM3.c"      version="1.0.0" attr="config"/>
2595       </files>
2596     </component>
2597     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM3 CMSIS GCC">
2598       <description>System and Startup for Generic Arm Cortex-M3 device</description>
2599       <files>
2600         <!-- include folder / device header file -->
2601         <file category="header"  name="Device/ARM/ARMCM3/Include/ARMCM3.h"/>
2602         <!-- startup / system file -->
2603         <file category="sourceC"      name="Device/ARM/ARMCM3/Source/GCC/startup_ARMCM3.c" version="1.0.0" attr="config" condition="GCC"/>
2604         <file category="linkerScript" name="Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2605         <file category="sourceC"      name="Device/ARM/ARMCM3/Source/system_ARMCM3.c"      version="1.0.0" attr="config"/>
2606       </files>
2607     </component>
2608
2609     <!-- Cortex-M4 -->
2610     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM4 CMSIS">
2611       <description>System and Startup for Generic Arm Cortex-M4 device</description>
2612       <files>
2613         <!-- include folder / device header file -->
2614         <file category="include" name="Device/ARM/ARMCM4/Include/"/>
2615         <!-- startup / system file -->
2616         <file category="sourceAsm"    name="Device/ARM/ARMCM4/Source/ARM/startup_ARMCM4.s" version="1.0.0" attr="config" condition="ARMCC"/>
2617         <file category="sourceAsm"    name="Device/ARM/ARMCM4/Source/GCC/startup_ARMCM4.S" version="1.0.0" attr="config" condition="GCC"/>
2618         <file category="linkerScript" name="Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2619         <file category="sourceAsm"    name="Device/ARM/ARMCM4/Source/IAR/startup_ARMCM4.s" version="1.0.0" attr="config" condition="IAR"/>
2620         <file category="sourceC"      name="Device/ARM/ARMCM4/Source/system_ARMCM4.c"      version="1.0.0" attr="config"/>
2621       </files>
2622     </component>
2623     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM4 CMSIS GCC">
2624       <description>System and Startup for Generic Arm Cortex-M4 device</description>
2625       <files>
2626         <!-- include folder / device header file -->
2627         <file category="include" name="Device/ARM/ARMCM4/Include/"/>
2628         <!-- startup / system file -->
2629         <file category="sourceC"      name="Device/ARM/ARMCM4/Source/GCC/startup_ARMCM4.c" version="1.0.0" attr="config" condition="GCC"/>
2630         <file category="linkerScript" name="Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2631         <file category="sourceC"      name="Device/ARM/ARMCM4/Source/system_ARMCM4.c"      version="1.0.0" attr="config"/>
2632       </files>
2633     </component>
2634
2635     <!-- Cortex-M7 -->
2636     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM7 CMSIS">
2637       <description>System and Startup for Generic Arm Cortex-M7 device</description>
2638       <files>
2639         <!-- include folder / device header file -->
2640         <file category="include"  name="Device/ARM/ARMCM7/Include/"/>
2641         <!-- startup / system file -->
2642         <file category="sourceAsm"    name="Device/ARM/ARMCM7/Source/ARM/startup_ARMCM7.s" version="1.0.0" attr="config" condition="ARMCC"/>
2643         <file category="sourceAsm"    name="Device/ARM/ARMCM7/Source/GCC/startup_ARMCM7.S" version="1.0.0" attr="config" condition="GCC"/>
2644         <file category="linkerScript" name="Device/ARM/ARMCM7/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2645         <file category="sourceAsm"    name="Device/ARM/ARMCM7/Source/IAR/startup_ARMCM7.s" version="1.0.0" attr="config" condition="IAR"/>
2646         <file category="sourceC"      name="Device/ARM/ARMCM7/Source/system_ARMCM7.c"      version="1.0.0" attr="config"/>
2647       </files>
2648     </component>
2649     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM7 CMSIS GCC">
2650       <description>System and Startup for Generic Arm Cortex-M7 device</description>
2651       <files>
2652         <!-- include folder / device header file -->
2653         <file category="include"  name="Device/ARM/ARMCM7/Include/"/>
2654         <!-- startup / system file -->
2655         <file category="sourceC"      name="Device/ARM/ARMCM7/Source/GCC/startup_ARMCM7.c" version="1.0.0" attr="config" condition="GCC"/>
2656         <file category="linkerScript" name="Device/ARM/ARMCM7/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2657         <file category="sourceC"      name="Device/ARM/ARMCM7/Source/system_ARMCM7.c"      version="1.0.0" attr="config"/>
2658       </files>
2659     </component>
2660
2661     <!-- Cortex-M23 -->
2662     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.0" condition="ARMCM23 CMSIS">
2663       <description>System and Startup for Generic Arm Cortex-M23 device</description>
2664       <files>
2665         <!-- include folder / device header file -->
2666         <file category="include"      name="Device/ARM/ARMCM23/Include/"/>
2667         <!-- startup / system file -->
2668         <file category="sourceAsm"    name="Device/ARM/ARMCM23/Source/ARM/startup_ARMCM23.s" version="1.0.0" attr="config" condition="ARMCC"/>
2669         <file category="sourceAsm"    name="Device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.S" version="1.0.0" attr="config" condition="GCC"/>
2670         <file category="linkerScript" name="Device/ARM/ARMCM23/Source/GCC/gcc_arm.ld"        version="1.0.0" attr="config" condition="GCC"/>
2671         <file category="sourceAsm"    name="Device/ARM/ARMCM23/Source/IAR/startup_ARMCM23.s" version="1.0.0" attr="config" condition="IAR"/>
2672         <file category="sourceC"      name="Device/ARM/ARMCM23/Source/system_ARMCM23.c"      version="1.0.0" attr="config"/>
2673         <!-- SAU configuration -->
2674         <file category="header"       name="Device/ARM/ARMCM23/Include/Template/partition_ARMCM23.h" version="1.0.0" attr="config" condition="ARMv8-M TZ Device"/>
2675       </files>
2676     </component>
2677     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.0" condition="ARMCM23 CMSIS GCC">
2678       <description>System and Startup for Generic Arm Cortex-M23 device</description>
2679       <files>
2680         <!-- include folder / device header file -->
2681         <file category="include"  name="Device/ARM/ARMCM23/Include/"/>
2682         <!-- startup / system file -->
2683         <file category="sourceC"      name="Device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.c" version="1.0.0" attr="config" condition="GCC"/>
2684         <file category="linkerScript" name="Device/ARM/ARMCM23/Source/GCC/gcc_arm.ld"        version="1.0.0" attr="config" condition="GCC"/>
2685         <file category="sourceC"      name="Device/ARM/ARMCM23/Source/system_ARMCM23.c"      version="1.0.0" attr="config"/>
2686         <!-- SAU configuration -->
2687         <file category="header"       name="Device/ARM/ARMCM23/Include/Template/partition_ARMCM23.h" version="1.0.0" attr="config" condition="ARMv8-M TZ Device"/>
2688       </files>
2689     </component>
2690
2691     <!-- Cortex-M33 -->
2692     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.1.0" condition="ARMCM33 CMSIS">
2693       <description>System and Startup for Generic Arm Cortex-M33 device</description>
2694       <files>
2695         <!-- include folder / device header file -->
2696         <file category="include"      name="Device/ARM/ARMCM33/Include/"/>
2697         <!-- startup / system file -->
2698         <file category="sourceAsm"    name="Device/ARM/ARMCM33/Source/ARM/startup_ARMCM33.s"         version="1.0.0" attr="config" condition="ARMCC"/>
2699         <file category="sourceAsm"    name="Device/ARM/ARMCM33/Source/GCC/startup_ARMCM33.S"         version="1.0.0" attr="config" condition="GCC"/>
2700         <file category="linkerScript" name="Device/ARM/ARMCM33/Source/GCC/gcc_arm.ld"                version="1.0.0" attr="config" condition="GCC"/>
2701         <file category="sourceAsm"    name="Device/ARM/ARMCM33/Source/IAR/startup_ARMCM33.s"         version="1.0.0" attr="config" condition="IAR"/>
2702         <file category="sourceC"      name="Device/ARM/ARMCM33/Source/system_ARMCM33.c"              version="1.0.0" attr="config"/>
2703         <!-- SAU configuration -->
2704         <file category="header"       name="Device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2705       </files>
2706     </component>
2707     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.1.0" condition="ARMCM33 CMSIS GCC">
2708       <description>System and Startup for Generic Arm Cortex-M33 device</description>
2709       <files>
2710         <!-- include folder / device header file -->
2711         <file category="include"  name="Device/ARM/ARMCM33/Include/"/>
2712         <!-- startup / system file -->
2713         <file category="sourceC"      name="Device/ARM/ARMCM33/Source/GCC/startup_ARMCM33.c"         version="1.0.0" attr="config" condition="GCC"/>
2714         <file category="linkerScript" name="Device/ARM/ARMCM33/Source/GCC/gcc_arm.ld"                version="1.0.0" attr="config" condition="GCC"/>
2715         <file category="sourceC"      name="Device/ARM/ARMCM33/Source/system_ARMCM33.c"              version="1.0.0" attr="config"/>
2716         <!-- SAU configuration -->
2717         <file category="header"       name="Device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2718       </files>
2719     </component>
2720
2721     <!-- Cortex-M35P -->
2722     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.1.0" condition="ARMCM35P CMSIS">
2723       <description>System and Startup for Generic Arm Cortex-M35P device</description>
2724       <files>
2725         <!-- include folder / device header file -->
2726         <file category="include"      name="Device/ARM/ARMCM35P/Include/"/>
2727         <!-- startup / system file -->
2728         <file category="sourceAsm"    name="Device/ARM/ARMCM35P/Source/ARM/startup_ARMCM35P.s"         version="1.0.0" attr="config" condition="ARMCC"/>
2729         <file category="sourceAsm"    name="Device/ARM/ARMCM35P/Source/GCC/startup_ARMCM35P.S"         version="1.0.0" attr="config" condition="GCC"/>
2730         <file category="linkerScript" name="Device/ARM/ARMCM35P/Source/GCC/gcc_arm.ld"                 version="1.0.0" attr="config" condition="GCC"/>
2731         <file category="sourceAsm"    name="Device/ARM/ARMCM35P/Source/IAR/startup_ARMCM35P.s"         version="1.0.0" attr="config" condition="IAR"/>
2732         <file category="sourceC"      name="Device/ARM/ARMCM35P/Source/system_ARMCM35P.c"              version="1.0.0" attr="config"/>
2733         <!-- SAU configuration -->
2734         <file category="header"       name="Device/ARM/ARMCM35P/Include/Template/partition_ARMCM35P.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2735       </files>
2736     </component>
2737     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.1.0" condition="ARMCM35P CMSIS GCC">
2738       <description>System and Startup for Generic Arm Cortex-M35P device</description>
2739       <files>
2740         <!-- include folder / device header file -->
2741         <file category="include"  name="Device/ARM/ARMCM35P/Include/"/>
2742         <!-- startup / system file -->
2743         <file category="sourceC"      name="Device/ARM/ARMCM35P/Source/GCC/startup_ARMCM35P.c"         version="1.0.0" attr="config" condition="GCC"/>
2744         <file category="linkerScript" name="Device/ARM/ARMCM35P/Source/GCC/gcc_arm.ld"                 version="1.0.0" attr="config" condition="GCC"/>
2745         <file category="sourceC"      name="Device/ARM/ARMCM35P/Source/system_ARMCM35P.c"              version="1.0.0" attr="config"/>
2746         <!-- SAU configuration -->
2747         <file category="header"       name="Device/ARM/ARMCM35P/Include/Template/partition_ARMCM35P.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2748       </files>
2749     </component>
2750
2751     <!-- Cortex-SC000 -->
2752     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMSC000 CMSIS">
2753       <description>System and Startup for Generic Arm SC000 device</description>
2754       <files>
2755         <!-- include folder / device header file -->
2756         <file category="header"  name="Device/ARM/ARMSC000/Include/ARMSC000.h"/>
2757         <!-- startup / system file -->
2758         <file category="sourceAsm"    name="Device/ARM/ARMSC000/Source/ARM/startup_ARMSC000.s" version="1.0.0" attr="config" condition="ARMCC"/>
2759         <file category="sourceAsm"    name="Device/ARM/ARMSC000/Source/GCC/startup_ARMSC000.S" version="1.0.0" attr="config" condition="GCC"/>
2760         <file category="linkerScript" name="Device/ARM/ARMSC000/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2761         <file category="sourceAsm"    name="Device/ARM/ARMSC000/Source/IAR/startup_ARMSC000.s" version="1.0.0" attr="config" condition="IAR"/>
2762         <file category="sourceC"      name="Device/ARM/ARMSC000/Source/system_ARMSC000.c"      version="1.0.0" attr="config"/>
2763       </files>
2764     </component>
2765     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMSC000 CMSIS GCC">
2766       <description>System and Startup for Generic Arm SC000 device</description>
2767       <files>
2768         <!-- include folder / device header file -->
2769         <file category="header"  name="Device/ARM/ARMSC000/Include/ARMSC000.h"/>
2770         <!-- startup / system file -->
2771         <file category="sourceC"      name="Device/ARM/ARMSC000/Source/GCC/startup_ARMSC000.c" version="1.0.0" attr="config" condition="GCC"/>
2772         <file category="linkerScript" name="Device/ARM/ARMSC000/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2773         <file category="sourceC"      name="Device/ARM/ARMSC000/Source/system_ARMSC000.c"      version="1.0.0" attr="config"/>
2774       </files>
2775     </component>
2776
2777     <!-- Cortex-SC300 -->
2778     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMSC300 CMSIS">
2779       <description>System and Startup for Generic Arm SC300 device</description>
2780       <files>
2781         <!-- include folder / device header file -->
2782         <file category="header"  name="Device/ARM/ARMSC300/Include/ARMSC300.h"/>
2783         <!-- startup / system file -->
2784         <file category="sourceAsm"    name="Device/ARM/ARMSC300/Source/ARM/startup_ARMSC300.s" version="1.0.0" attr="config" condition="ARMCC"/>
2785         <file category="sourceAsm"    name="Device/ARM/ARMSC300/Source/GCC/startup_ARMSC300.S" version="1.0.0" attr="config" condition="GCC"/>
2786         <file category="linkerScript" name="Device/ARM/ARMSC300/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2787         <file category="sourceAsm"    name="Device/ARM/ARMSC300/Source/IAR/startup_ARMSC300.s" version="1.0.0" attr="config" condition="IAR"/>
2788         <file category="sourceC"      name="Device/ARM/ARMSC300/Source/system_ARMSC300.c"      version="1.0.0" attr="config"/>
2789       </files>
2790     </component>
2791     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMSC300 CMSIS GCC">
2792       <description>System and Startup for Generic Arm SC300 device</description>
2793       <files>
2794         <!-- include folder / device header file -->
2795         <file category="header"  name="Device/ARM/ARMSC300/Include/ARMSC300.h"/>
2796         <!-- startup / system file -->
2797         <file category="sourceC"      name="Device/ARM/ARMSC300/Source/GCC/startup_ARMSC300.c" version="1.0.0" attr="config" condition="GCC"/>
2798         <file category="linkerScript" name="Device/ARM/ARMSC300/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2799         <file category="sourceC"      name="Device/ARM/ARMSC300/Source/system_ARMSC300.c"      version="1.0.0" attr="config"/>
2800       </files>
2801     </component>
2802
2803     <!-- ARMv8MBL -->
2804     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.0" condition="ARMv8MBL CMSIS">
2805       <description>System and Startup for Generic Armv8-M Baseline device</description>
2806       <files>
2807         <!-- include folder / device header file -->
2808         <file category="include"      name="Device/ARM/ARMv8MBL/Include/"/>
2809         <!-- startup / system file -->
2810         <file category="sourceAsm"    name="Device/ARM/ARMv8MBL/Source/ARM/startup_ARMv8MBL.s" version="1.0.0" attr="config" condition="ARMCC"/>
2811         <file category="sourceAsm"    name="Device/ARM/ARMv8MBL/Source/GCC/startup_ARMv8MBL.S" version="1.0.0" attr="config" condition="GCC"/>
2812         <file category="linkerScript" name="Device/ARM/ARMv8MBL/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2813         <file category="sourceC"      name="Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c"      version="1.0.0" attr="config" condition="ARMCC GCC"/>
2814         <!-- SAU configuration -->
2815         <file category="header"       name="Device/ARM/ARMv8MBL/Include/Template/partition_ARMv8MBL.h" version="1.0.0" attr="config"/>
2816       </files>
2817     </component>
2818     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.0" condition="ARMv8MBL CMSIS GCC">
2819       <description>System and Startup for Generic Armv8-M Baseline device</description>
2820       <files>
2821         <!-- include folder / device header file -->
2822         <file category="include"  name="Device/ARM/ARMv8MBL/Include/"/>
2823         <!-- startup / system file -->
2824         <file category="sourceC"      name="Device/ARM/ARMv8MBL/Source/GCC/startup_ARMv8MBL.c" version="1.0.0" attr="config" condition="GCC"/>
2825         <file category="linkerScript" name="Device/ARM/ARMv8MBL/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2826         <file category="sourceC"      name="Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c"      version="1.0.0" attr="config"/>
2827         <!-- SAU configuration -->
2828         <file category="header"       name="Device/ARM/ARMv8MBL/Include/Template/partition_ARMv8MBL.h" version="1.0.0" attr="config" condition="ARMv8-M TZ Device"/>
2829       </files>
2830     </component>
2831
2832     <!-- ARMv8MML -->
2833     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.1.0" condition="ARMv8MML CMSIS">
2834       <description>System and Startup for Generic Armv8-M Mainline device</description>
2835       <files>
2836         <!-- include folder / device header file -->
2837         <file category="include"      name="Device/ARM/ARMv8MML/Include/"/>
2838         <!-- startup / system file -->
2839         <file category="sourceAsm"    name="Device/ARM/ARMv8MML/Source/ARM/startup_ARMv8MML.s"         version="1.0.0" attr="config" condition="ARMCC"/>
2840         <file category="sourceAsm"    name="Device/ARM/ARMv8MML/Source/GCC/startup_ARMv8MML.S"         version="1.0.0" attr="config" condition="GCC"/>
2841         <file category="linkerScript" name="Device/ARM/ARMv8MML/Source/GCC/gcc_arm.ld"                 version="1.0.0" attr="config" condition="GCC"/>
2842         <file category="sourceC"      name="Device/ARM/ARMv8MML/Source/system_ARMv8MML.c"              version="1.0.0" attr="config" condition="ARMCC GCC"/>
2843         <!-- SAU configuration -->
2844         <file category="header"       name="Device/ARM/ARMv8MML/Include/Template/partition_ARMv8MML.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2845       </files>
2846     </component>
2847     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.1.0" condition="ARMv8MML CMSIS GCC">
2848       <description>System and Startup for Generic Armv8-M Mainline device</description>
2849       <files>
2850         <!-- include folder / device header file -->
2851         <file category="include"      name="Device/ARM/ARMv8MML/Include/"/>
2852         <!-- startup / system file -->
2853         <file category="sourceC"      name="Device/ARM/ARMv8MML/Source/GCC/startup_ARMv8MML.c"         version="1.0.0" attr="config" condition="GCC"/>
2854         <file category="linkerScript" name="Device/ARM/ARMv8MML/Source/GCC/gcc_arm.ld"                 version="1.0.0" attr="config" condition="GCC"/>
2855         <file category="sourceC"      name="Device/ARM/ARMv8MML/Source/system_ARMv8MML.c"              version="1.0.0" attr="config"/>
2856         <!-- SAU configuration -->
2857         <file category="header"       name="Device/ARM/ARMv8MML/Include/Template/partition_ARMv8MML.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2858       </files>
2859     </component>
2860
2861     <!-- Cortex-A5 -->
2862     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.0" condition="ARMCA5 CMSIS">
2863       <description>System and Startup for Generic Arm Cortex-A5 device</description>
2864       <files>
2865         <!-- include folder / device header file -->
2866         <file category="include"      name="Device/ARM/ARMCA5/Include/"/>
2867         <!-- startup / system / mmu files -->
2868         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/AC5/startup_ARMCA5.c" version="1.0.0" attr="config" condition="ARMCC5"/>
2869         <file category="linkerScript" name="Device/ARM/ARMCA5/Source/AC5/ARMCA5.sct"       version="1.0.0" attr="config" condition="ARMCC5"/>
2870         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/AC6/startup_ARMCA5.c" version="1.0.0" attr="config" condition="ARMCC6"/>
2871         <file category="linkerScript" name="Device/ARM/ARMCA5/Source/AC6/ARMCA5.sct"       version="1.0.0" attr="config" condition="ARMCC6"/>
2872         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/GCC/startup_ARMCA5.c" version="1.0.0" attr="config" condition="GCC"/>
2873         <file category="other"        name="Device/ARM/ARMCA5/Source/GCC/ARMCA5.ld"        version="1.0.0" attr="config" condition="GCC"/>
2874         <file category="sourceAsm"    name="Device/ARM/ARMCA5/Source/IAR/startup_ARMCA5.s" version="1.0.0" attr="config" condition="IAR"/>
2875         <file category="linkerScript" name="Device/ARM/ARMCA5/Source/IAR/ARMCA5.icf"       version="1.0.0" attr="config" condition="IAR"/>
2876         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/system_ARMCA5.c"      version="1.0.0" attr="config"/>
2877         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/mmu_ARMCA5.c"         version="1.0.0" attr="config"/>
2878         <file category="header"       name="Device/ARM/ARMCA5/Include/system_ARMCA5.h"     version="1.0.0" attr="config"/>
2879         <file category="header"       name="Device/ARM/ARMCA5/Include/mem_ARMCA5.h"        version="1.0.0" attr="config"/>
2880
2881       </files>
2882     </component>
2883
2884     <!-- Cortex-A7 -->
2885     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.0" condition="ARMCA7 CMSIS">
2886       <description>System and Startup for Generic Arm Cortex-A7 device</description>
2887       <files>
2888         <!-- include folder / device header file -->
2889         <file category="include"      name="Device/ARM/ARMCA7/Include/"/>
2890         <!-- startup / system / mmu files -->
2891         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/AC5/startup_ARMCA7.c" version="1.0.0" attr="config" condition="ARMCC5"/>
2892         <file category="linkerScript" name="Device/ARM/ARMCA7/Source/AC5/ARMCA7.sct"       version="1.0.0" attr="config" condition="ARMCC5"/>
2893         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/AC6/startup_ARMCA7.c" version="1.0.0" attr="config" condition="ARMCC6"/>
2894         <file category="linkerScript" name="Device/ARM/ARMCA7/Source/AC6/ARMCA7.sct"       version="1.0.0" attr="config" condition="ARMCC6"/>
2895         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/GCC/startup_ARMCA7.c" version="1.0.0" attr="config" condition="GCC"/>
2896         <file category="other"        name="Device/ARM/ARMCA7/Source/GCC/ARMCA7.ld"        version="1.0.0" attr="config" condition="GCC"/>
2897         <file category="sourceAsm"    name="Device/ARM/ARMCA7/Source/IAR/startup_ARMCA7.s" version="1.0.0" attr="config" condition="IAR"/>
2898         <file category="linkerScript" name="Device/ARM/ARMCA7/Source/IAR/ARMCA7.icf"       version="1.0.0" attr="config" condition="IAR"/>
2899         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/system_ARMCA7.c"      version="1.0.0" attr="config"/>
2900         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/mmu_ARMCA7.c"         version="1.0.0" attr="config"/>
2901         <file category="header"       name="Device/ARM/ARMCA7/Include/system_ARMCA7.h"     version="1.0.0" attr="config"/>
2902         <file category="header"       name="Device/ARM/ARMCA7/Include/mem_ARMCA7.h"        version="1.0.0" attr="config"/>
2903       </files>
2904     </component>
2905
2906     <!-- Cortex-A9 -->
2907     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCA9 CMSIS">
2908       <description>System and Startup for Generic Arm Cortex-A9 device</description>
2909       <files>
2910         <!-- include folder / device header file -->
2911         <file category="include"  name="Device/ARM/ARMCA9/Include/"/>
2912         <!-- startup / system / mmu files -->
2913         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/AC5/startup_ARMCA9.c" version="1.0.0" attr="config" condition="ARMCC5"/>
2914         <file category="linkerScript" name="Device/ARM/ARMCA9/Source/AC5/ARMCA9.sct"       version="1.0.0" attr="config" condition="ARMCC5"/>
2915         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/AC6/startup_ARMCA9.c" version="1.0.0" attr="config" condition="ARMCC6"/>
2916         <file category="linkerScript" name="Device/ARM/ARMCA9/Source/AC6/ARMCA9.sct"       version="1.0.0" attr="config" condition="ARMCC6"/>
2917         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/GCC/startup_ARMCA9.c" version="1.0.0" attr="config" condition="GCC"/>
2918         <file category="other"        name="Device/ARM/ARMCA9/Source/GCC/ARMCA9.ld"        version="1.0.0" attr="config" condition="GCC"/>
2919         <file category="sourceAsm"    name="Device/ARM/ARMCA9/Source/IAR/startup_ARMCA9.s" version="1.0.0" attr="config" condition="IAR"/>
2920         <file category="linkerScript" name="Device/ARM/ARMCA9/Source/IAR/ARMCA9.icf"       version="1.0.0" attr="config" condition="IAR"/>
2921         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/system_ARMCA9.c"      version="1.0.0" attr="config"/>
2922         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/mmu_ARMCA9.c"         version="1.0.0" attr="config"/>
2923         <file category="header"       name="Device/ARM/ARMCA9/Include/system_ARMCA9.h"     version="1.0.0" attr="config"/>
2924         <file category="header"       name="Device/ARM/ARMCA9/Include/mem_ARMCA9.h"        version="1.0.0" attr="config"/>
2925       </files>
2926     </component>
2927
2928     <!-- IRQ Controller -->
2929     <component Cclass="Device" Cgroup="IRQ Controller" Csub="GIC" Capiversion="1.0.0" Cversion="1.0.1" condition="ARMv7-A Device">
2930       <description>IRQ Controller implementation using GIC</description>
2931       <files>
2932         <file category="sourceC" name="CMSIS/Core_A/Source/irq_ctrl_gic.c"/>
2933       </files>
2934     </component>
2935
2936     <!-- OS Tick -->
2937     <component Cclass="Device" Cgroup="OS Tick" Csub="Private Timer" Capiversion="1.0.1" Cversion="1.0.2" condition="OS Tick PTIM">
2938       <description>OS Tick implementation using Private Timer</description>
2939       <files>
2940         <file category="sourceC" name="CMSIS/RTOS2/Source/os_tick_ptim.c"/>
2941       </files>
2942     </component>
2943
2944     <component Cclass="Device" Cgroup="OS Tick" Csub="Generic Physical Timer" Capiversion="1.0.1" Cversion="1.0.1" condition="OS Tick GTIM">
2945       <description>OS Tick implementation using Generic Physical Timer</description>
2946       <files>
2947         <file category="sourceC" name="CMSIS/RTOS2/Source/os_tick_gtim.c"/>
2948       </files>
2949     </component>
2950
2951     <!-- CMSIS-DSP component -->
2952     <component Cclass="CMSIS" Cgroup="DSP" Cversion="1.5.2" condition="CMSIS DSP">
2953       <description>CMSIS-DSP Library for Cortex-M, SC000, and SC300</description>
2954       <files>
2955         <!-- CPU independent -->
2956         <file category="doc" name="CMSIS/Documentation/DSP/html/index.html"/>
2957         <file category="header" name="CMSIS/DSP/Include/arm_math.h"/>
2958
2959         <!-- CPU and Compiler dependent -->
2960         <!-- ARMCC -->
2961         <file category="library" condition="CM0_LE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM0l_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2962         <file category="library" condition="CM0_BE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM0b_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2963         <file category="library" condition="CM1_LE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM0l_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2964         <file category="library" condition="CM1_BE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM0b_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2965         <file category="library" condition="CM3_LE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM3l_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2966         <file category="library" condition="CM3_BE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM3b_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2967         <file category="library" condition="CM4_LE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM4l_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2968         <file category="library" condition="CM4_BE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM4b_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2969         <file category="library" condition="CM4_FP_LE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM4lf_math.lib"     src="CMSIS/DSP/Source/ARM"/>
2970         <file category="library" condition="CM4_FP_BE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM4bf_math.lib"     src="CMSIS/DSP/Source/ARM"/>
2971         <file category="library" condition="CM7_LE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM7l_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2972         <file category="library" condition="CM7_BE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM7b_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2973         <file category="library" condition="CM7_SP_LE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM7lfsp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
2974         <file category="library" condition="CM7_SP_BE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM7bfsp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
2975         <file category="library" condition="CM7_DP_LE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM7lfdp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
2976         <file category="library" condition="CM7_DP_BE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM7bfdp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
2977
2978         <file category="library" condition="CM23_LE_ARMCC"                  name="CMSIS/Lib/ARM/arm_ARMv8MBLl_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2979         <file category="library" condition="CM33_NODSP_NOFPU_LE_ARMCC"      name="CMSIS/Lib/ARM/arm_ARMv8MMLl_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2980         <file category="library" condition="CM33_DSP_NOFPU_LE_ARMCC"        name="CMSIS/Lib/ARM/arm_ARMv8MMLld_math.lib"     src="CMSIS/DSP/Source/ARM"/>
2981         <file category="library" condition="CM33_NODSP_SP_LE_ARMCC"         name="CMSIS/Lib/ARM/arm_ARMv8MMLlfsp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
2982         <file category="library" condition="CM33_DSP_SP_LE_ARMCC"           name="CMSIS/Lib/ARM/arm_ARMv8MMLldfsp_math.lib"  src="CMSIS/DSP/Source/ARM"/>
2983         <file category="library" condition="CM35P_NODSP_NOFPU_LE_ARMCC"     name="CMSIS/Lib/ARM/arm_ARMv8MMLl_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2984         <file category="library" condition="CM35P_DSP_NOFPU_LE_ARMCC"       name="CMSIS/Lib/ARM/arm_ARMv8MMLld_math.lib"     src="CMSIS/DSP/Source/ARM"/>
2985         <file category="library" condition="CM35P_NODSP_SP_LE_ARMCC"        name="CMSIS/Lib/ARM/arm_ARMv8MMLlfsp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
2986         <file category="library" condition="CM35P_DSP_SP_LE_ARMCC"          name="CMSIS/Lib/ARM/arm_ARMv8MMLldfsp_math.lib"  src="CMSIS/DSP/Source/ARM"/>
2987         <file category="library" condition="ARMv8MBL_LE_ARMCC"              name="CMSIS/Lib/ARM/arm_ARMv8MBLl_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2988         <file category="library" condition="ARMv8MML_NODSP_NOFPU_LE_ARMCC"  name="CMSIS/Lib/ARM/arm_ARMv8MMLl_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2989         <file category="library" condition="ARMv8MML_DSP_NOFPU_LE_ARMCC"    name="CMSIS/Lib/ARM/arm_ARMv8MMLld_math.lib"     src="CMSIS/DSP/Source/ARM"/>
2990         <file category="library" condition="ARMv8MML_NODSP_SP_LE_ARMCC"     name="CMSIS/Lib/ARM/arm_ARMv8MMLlfsp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
2991         <file category="library" condition="ARMv8MML_DSP_SP_LE_ARMCC"       name="CMSIS/Lib/ARM/arm_ARMv8MMLldfsp_math.lib"  src="CMSIS/DSP/Source/ARM"/>
2992         <!--file category="library" condition="ARMv8MML_DP_NOFPU_LE_ARMCC"     name="CMSIS/Lib/ARM/arm_ARMv8MMLlfdp_math.lib"   src="CMSIS/DSP/Source/ARM"/-->
2993         <!--file category="library" condition="ARMv8MML_DSP_DP_LE_ARMCC"       name="CMSIS/Lib/ARM/arm_ARMv8MMLldfdp_math.lib"  src="CMSIS/DSP/Source/ARM"/-->
2994
2995         <!-- GCC -->
2996         <file category="library" condition="CM0_LE_GCC"               name="CMSIS/Lib/GCC/libarm_cortexM0l_math.a"     src="CMSIS/DSP/Source/GCC"/>
2997         <file category="library" condition="CM1_LE_GCC"               name="CMSIS/Lib/GCC/libarm_cortexM0l_math.a"     src="CMSIS/DSP/Source/GCC"/>
2998         <file category="library" condition="CM3_LE_GCC"               name="CMSIS/Lib/GCC/libarm_cortexM3l_math.a"     src="CMSIS/DSP/Source/GCC"/>
2999         <file category="library" condition="CM4_LE_GCC"               name="CMSIS/Lib/GCC/libarm_cortexM4l_math.a"     src="CMSIS/DSP/Source/GCC"/>
3000         <file category="library" condition="CM4_FP_LE_GCC"            name="CMSIS/Lib/GCC/libarm_cortexM4lf_math.a"    src="CMSIS/DSP/Source/GCC"/>
3001         <file category="library" condition="CM7_LE_GCC"               name="CMSIS/Lib/GCC/libarm_cortexM7l_math.a"     src="CMSIS/DSP/Source/GCC"/>
3002         <file category="library" condition="CM7_SP_LE_GCC"            name="CMSIS/Lib/GCC/libarm_cortexM7lfsp_math.a"  src="CMSIS/DSP/Source/GCC"/>
3003         <file category="library" condition="CM7_DP_LE_GCC"            name="CMSIS/Lib/GCC/libarm_cortexM7lfdp_math.a"  src="CMSIS/DSP/Source/GCC"/>
3004
3005         <file category="library" condition="CM23_LE_GCC"                    name="CMSIS/Lib/GCC/libarm_ARMv8MBLl_math.a"     src="CMSIS/DSP/Source/GCC"/>
3006         <file category="library" condition="CM33_NODSP_NOFPU_LE_GCC"        name="CMSIS/Lib/GCC/libarm_ARMv8MMLl_math.a"     src="CMSIS/DSP/Source/GCC"/>
3007         <file category="library" condition="CM33_DSP_NOFPU_LE_GCC"          name="CMSIS/Lib/GCC/libarm_ARMv8MMLld_math.a"    src="CMSIS/DSP/Source/GCC"/>
3008         <file category="library" condition="CM33_NODSP_SP_LE_GCC"           name="CMSIS/Lib/GCC/libarm_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP/Source/GCC"/>
3009         <file category="library" condition="CM33_DSP_SP_LE_GCC"             name="CMSIS/Lib/GCC/libarm_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
3010         <file category="library" condition="CM35P_NODSP_NOFPU_LE_GCC"       name="CMSIS/Lib/GCC/libarm_ARMv8MMLl_math.a"     src="CMSIS/DSP/Source/GCC"/>
3011         <file category="library" condition="CM35P_DSP_NOFPU_LE_GCC"         name="CMSIS/Lib/GCC/libarm_ARMv8MMLld_math.a"    src="CMSIS/DSP/Source/GCC"/>
3012         <file category="library" condition="CM35P_NODSP_SP_LE_GCC"          name="CMSIS/Lib/GCC/libarm_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP/Source/GCC"/>
3013         <file category="library" condition="CM35P_DSP_SP_LE_GCC"            name="CMSIS/Lib/GCC/libarm_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
3014         <file category="library" condition="ARMv8MBL_LE_GCC"                name="CMSIS/Lib/GCC/libarm_ARMv8MBLl_math.a"     src="CMSIS/DSP/Source/GCC"/>
3015         <file category="library" condition="ARMv8MML_NODSP_NOFPU_LE_GCC"    name="CMSIS/Lib/GCC/libarm_ARMv8MMLl_math.a"     src="CMSIS/DSP/Source/GCC"/>
3016         <file category="library" condition="ARMv8MML_DSP_NOFPU_LE_GCC"      name="CMSIS/Lib/GCC/libarm_ARMv8MMLld_math.a"    src="CMSIS/DSP/Source/GCC"/>
3017         <file category="library" condition="ARMv8MML_NODSP_SP_LE_GCC"       name="CMSIS/Lib/GCC/libarm_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP/Source/GCC"/>
3018         <file category="library" condition="ARMv8MML_DSP_SP_LE_GCC"         name="CMSIS/Lib/GCC/libarm_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
3019         <!--file category="library" condition="ARMv8MML_DP_NOFPU_LE_GCC"       name="CMSIS/Lib/GCC/libarm_ARMv8MMLlfdp_math.a"  src="CMSIS/DSP/Source/GCC"/-->
3020         <!--file category="library" condition="ARMv8MML_DSP_DP_LE_GCC"         name="CMSIS/Lib/GCC/libarm_ARMv8MMLldfdp_math.a" src="CMSIS/DSP/Source/GCC"/-->
3021
3022         <!-- IAR -->
3023         <file category="library" condition="CM0_LE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM0l_math.a"     src="CMSIS/DSP/Source/IAR"/>
3024         <file category="library" condition="CM0_BE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM0b_math.a"     src="CMSIS/DSP/Source/IAR"/>
3025         <file category="library" condition="CM1_LE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM0l_math.a"     src="CMSIS/DSP/Source/IAR"/>
3026         <file category="library" condition="CM1_BE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM0b_math.a"     src="CMSIS/DSP/Source/IAR"/>
3027         <file category="library" condition="CM3_LE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM3l_math.a"     src="CMSIS/DSP/Source/IAR"/>
3028         <file category="library" condition="CM3_BE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM3b_math.a"     src="CMSIS/DSP/Source/IAR"/>
3029         <file category="library" condition="CM4_LE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM4l_math.a"     src="CMSIS/DSP/Source/IAR"/>
3030         <file category="library" condition="CM4_BE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM4b_math.a"     src="CMSIS/DSP/Source/IAR"/>
3031         <file category="library" condition="CM4_FP_LE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM4lf_math.a"    src="CMSIS/DSP/Source/IAR"/>
3032         <file category="library" condition="CM4_FP_BE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM4bf_math.a"    src="CMSIS/DSP/Source/IAR"/>
3033         <file category="library" condition="CM7_LE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM7l_math.a"     src="CMSIS/DSP/Source/IAR"/>
3034         <file category="library" condition="CM7_BE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM7b_math.a"     src="CMSIS/DSP/Source/IAR"/>
3035         <file category="library" condition="CM7_DP_LE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM7lf_math.a"    src="CMSIS/DSP/Source/IAR"/>
3036         <file category="library" condition="CM7_DP_BE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM7bf_math.a"    src="CMSIS/DSP/Source/IAR"/>
3037         <file category="library" condition="CM7_SP_LE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM7ls_math.a"    src="CMSIS/DSP/Source/IAR"/>
3038         <file category="library" condition="CM7_SP_BE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM7bs_math.a"    src="CMSIS/DSP/Source/IAR"/>
3039
3040         <file category="library" condition="CM23_LE_IAR"              name="CMSIS/Lib/IAR/iar_ARMv8MBLl_math.a"     src="CMSIS/DSP/Source/IAR"/>
3041         <file category="library" condition="CM33_NODSP_NOFPU_LE_IAR"        name="CMSIS/Lib/IAR/iar_ARMv8MMLl_math.a"     src="CMSIS/DSP/Source/IAR"/>
3042         <file category="library" condition="CM33_DSP_NOFPU_LE_IAR"    name="CMSIS/Lib/IAR/iar_ARMv8MMLld_math.a"    src="CMSIS/DSP/Source/IAR"/>
3043         <file category="library" condition="CM33_NODSP_SP_LE_IAR"           name="CMSIS/Lib/IAR/iar_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP/Source/IAR"/>
3044         <file category="library" condition="CM33_DSP_SP_LE_IAR"       name="CMSIS/Lib/IAR/iar_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
3045         <file category="library" condition="CM35P_NODSP_NOFPU_LE_IAR"       name="CMSIS/Lib/IAR/iar_ARMv8MMLl_math.a"     src="CMSIS/DSP/Source/IAR"/>
3046         <file category="library" condition="CM35P_DSP_NOFPU_LE_IAR"         name="CMSIS/Lib/IAR/iar_ARMv8MMLld_math.a"    src="CMSIS/DSP/Source/IAR"/>
3047         <file category="library" condition="CM35P_NODSP_SP_LE_IAR"          name="CMSIS/Lib/IAR/iar_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP/Source/IAR"/>
3048         <file category="library" condition="CM35P_DSP_SP_LE_IAR"            name="CMSIS/Lib/IAR/iar_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
3049         <file category="library" condition="ARMv8MBL_LE_IAR"          name="CMSIS/Lib/IAR/iar_ARMv8MBLl_math.a"     src="CMSIS/DSP/Source/IAR"/>
3050         <file category="library" condition="ARMv8MML_NODSP_NOFPU_LE_IAR"    name="CMSIS/Lib/IAR/iar_ARMv8MMLl_math.a"     src="CMSIS/DSP/Source/IAR"/>
3051         <file category="library" condition="ARMv8MML_DSP_NOFPU_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLld_math.a"    src="CMSIS/DSP/Source/IAR"/>
3052         <file category="library" condition="ARMv8MML_NODSP_SP_LE_IAR"       name="CMSIS/Lib/IAR/iar_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP/Source/IAR"/>
3053         <file category="library" condition="ARMv8MML_DSP_SP_LE_IAR"   name="CMSIS/Lib/IAR/iar_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
3054      <!--file category="library" condition="ARMv8MML_DP_NOFPU_LE_IAR"       name="CMSIS/Lib/IAR/iar_ARMv8MMLlfdp_math.a"  src="CMSIS/DSP/Source/IAR"/-->
3055         <!--file category="library" condition="ARMv8MML_DSP_DP_LE_IAR"   name="CMSIS/Lib/IAR/iar_ARMv8MMLldfdp_math.a" src="CMSIS/DSP/Source/IAR"/-->
3056
3057       </files>
3058     </component>
3059
3060     <!-- CMSIS-NN component -->
3061     <component Cclass="CMSIS" Cgroup="NN Lib" Cversion="1.1.0" condition="CMSIS NN">
3062       <description>CMSIS-NN Neural Network Library</description>
3063       <files>
3064         <file category="doc" name="CMSIS/Documentation/NN/html/index.html"/>
3065         <file category="header" name="CMSIS/NN/Include/arm_nnfunctions.h"/>
3066
3067         <file category="source" name="CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c"/>
3068         <file category="source" name="CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c"/>
3069         <file category="source" name="CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c"/>
3070         <file category="source" name="CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c"/>
3071
3072         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c"/>
3073         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c"/>
3074         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c"/>
3075         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c"/>
3076         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c"/>
3077         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c"/>
3078         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c"/>
3079         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c"/>
3080         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c"/>
3081         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c"/>
3082         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c"/>
3083         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c"/>
3084
3085         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c"/>
3086         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c"/>
3087         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c"/>
3088         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c"/>
3089         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c"/>
3090         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c"/>
3091
3092         <file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c"/>
3093         <file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c"/>
3094         <file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c"/>
3095         <file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.c"/>
3096         <file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.c"/>
3097
3098         <file category="source" name="CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c"/>
3099
3100         <file category="source" name="CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.c"/>
3101         <file category="source" name="CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.c"/>
3102       </files>
3103     </component>
3104
3105     <!-- CMSIS-RTOS Keil RTX component -->
3106     <component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX" Cversion="4.81.1" Capiversion="1.0.0" isDefaultVariant="1" condition="RTOS RTX">
3107       <description>CMSIS-RTOS RTX implementation for Cortex-M, SC000, and SC300</description>
3108       <RTE_Components_h>
3109         <!-- the following content goes into file 'RTE_Components.h' -->
3110         #define RTE_CMSIS_RTOS                  /* CMSIS-RTOS */
3111         #define RTE_CMSIS_RTOS_RTX              /* CMSIS-RTOS Keil RTX */
3112       </RTE_Components_h>
3113       <files>
3114         <!-- CPU independent -->
3115         <file category="doc" name="CMSIS/Documentation/RTOS/html/rtxImplementation.html"/>
3116         <file category="header" name="CMSIS/RTOS/RTX/INC/cmsis_os.h"/>
3117         <file category="source" attr="config"   name="CMSIS/RTOS/RTX/Templates/RTX_Conf_CM.c" version="4.70.1"/>
3118
3119         <!-- RTX templates -->
3120         <file category="header" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/osObjects.h" select="CMSIS-RTOS 'main' function"/>
3121         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/main.c"      select="CMSIS-RTOS 'main' function"/>
3122         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MailQueue.c" select="CMSIS-RTOS Mail Queue"/>
3123         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MemPool.c"   select="CMSIS-RTOS Memory Pool"/>
3124         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MsgQueue.c"  select="CMSIS-RTOS Message Queue"/>
3125         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Mutex.c"     select="CMSIS-RTOS Mutex"/>
3126         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Semaphore.c" select="CMSIS-RTOS Semaphore"/>
3127         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Thread.c"    select="CMSIS-RTOS Thread"/>
3128         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Timer.c"     select="CMSIS-RTOS Timer"/>
3129         <!-- tool-chain specific template file -->
3130         <file category="source" attr="template" condition="ARMCC" name="CMSIS/RTOS/RTX/SRC/ARM/SVC_Table.s" select="CMSIS-RTOS User SVC"/>
3131         <file category="source" attr="template" condition="GCC"   name="CMSIS/RTOS/RTX/SRC/GCC/SVC_Table.S" select="CMSIS-RTOS User SVC"/>
3132         <file category="source" attr="template" condition="IAR"   name="CMSIS/RTOS/RTX/SRC/IAR/SVC_Table.s" select="CMSIS-RTOS User SVC"/>
3133
3134         <!-- CPU and Compiler dependent -->
3135         <!-- ARMCC -->
3136         <file category="library" condition="CM0_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
3137         <file category="library" condition="CM0_BE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3138         <file category="library" condition="CM1_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
3139         <file category="library" condition="CM1_BE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3140         <file category="library" condition="CM3_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
3141         <file category="library" condition="CM3_BE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3142         <file category="library" condition="CM4_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
3143         <file category="library" condition="CM4_BE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3144         <file category="library" condition="CM4_FP_LE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
3145         <file category="library" condition="CM4_FP_BE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3146         <file category="library" condition="CM7_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
3147         <file category="library" condition="CM7_BE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3148         <file category="library" condition="CM7_FP_LE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
3149         <file category="library" condition="CM7_FP_BE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3150         <!-- GCC -->
3151         <file category="library" condition="CM0_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
3152         <file category="library" condition="CM0_BE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3153         <file category="library" condition="CM1_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
3154         <file category="library" condition="CM1_BE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3155         <file category="library" condition="CM3_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
3156         <file category="library" condition="CM3_BE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3157         <file category="library" condition="CM4_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
3158         <file category="library" condition="CM4_BE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3159         <file category="library" condition="CM4_FP_LE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
3160         <file category="library" condition="CM4_FP_BE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3161         <file category="library" condition="CM7_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
3162         <file category="library" condition="CM7_BE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3163         <file category="library" condition="CM7_FP_LE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
3164         <file category="library" condition="CM7_FP_BE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3165         <!-- IAR -->
3166         <file category="library" condition="CM0_LE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
3167         <file category="library" condition="CM0_BE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
3168         <file category="library" condition="CM1_LE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
3169         <file category="library" condition="CM1_BE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
3170         <file category="library" condition="CM3_LE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
3171         <file category="library" condition="CM3_BE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
3172         <file category="library" condition="CM4_LE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
3173         <file category="library" condition="CM4_BE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
3174         <file category="library" condition="CM4_FP_LE_IAR"   name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
3175         <file category="library" condition="CM4_FP_BE_IAR"   name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
3176         <file category="library" condition="CM7_LE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
3177         <file category="library" condition="CM7_BE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
3178         <file category="library" condition="CM7_FP_LE_IAR"   name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
3179         <file category="library" condition="CM7_FP_BE_IAR"   name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
3180       </files>
3181     </component>
3182     <!-- CMSIS-RTOS Keil RTX component (IFX variant) -->
3183     <component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX" Cvariant="IFX" Cversion="4.81.1" Capiversion="1.0.0" condition="RTOS RTX IFX">
3184       <description>CMSIS-RTOS RTX implementation for Infineon XMC4 series affected by PMU_CM.001 errata</description>
3185       <RTE_Components_h>
3186         <!-- the following content goes into file 'RTE_Components.h' -->
3187         #define RTE_CMSIS_RTOS                  /* CMSIS-RTOS */
3188         #define RTE_CMSIS_RTOS_RTX              /* CMSIS-RTOS Keil RTX */
3189       </RTE_Components_h>
3190       <files>
3191         <!-- CPU independent -->
3192         <file category="doc" name="CMSIS/Documentation/RTOS/html/rtxImplementation.html"/>
3193         <file category="header" name="CMSIS/RTOS/RTX/INC/cmsis_os.h"/>
3194         <file category="source" attr="config"   name="CMSIS/RTOS/RTX/Templates/RTX_Conf_CM.c" version="4.70.1"/>
3195
3196         <!-- RTX templates -->
3197         <file category="header" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/osObjects.h" select="CMSIS-RTOS 'main' function"/>
3198         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/main.c"      select="CMSIS-RTOS 'main' function"/>
3199         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MailQueue.c" select="CMSIS-RTOS Mail Queue"/>
3200         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MemPool.c"   select="CMSIS-RTOS Memory Pool"/>
3201         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MsgQueue.c"  select="CMSIS-RTOS Message Queue"/>
3202         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Mutex.c"     select="CMSIS-RTOS Mutex"/>
3203         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Semaphore.c" select="CMSIS-RTOS Semaphore"/>
3204         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Thread.c"    select="CMSIS-RTOS Thread"/>
3205         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Timer.c"     select="CMSIS-RTOS Timer"/>
3206         <!-- tool-chain specific template file -->
3207         <file category="source" attr="template" condition="ARMCC" name="CMSIS/RTOS/RTX/SRC/ARM/SVC_Table.s" select="CMSIS-RTOS User SVC"/>
3208         <file category="source" attr="template" condition="GCC"   name="CMSIS/RTOS/RTX/SRC/GCC/SVC_Table.S" select="CMSIS-RTOS User SVC"/>
3209         <file category="source" attr="template" condition="IAR"   name="CMSIS/RTOS/RTX/SRC/IAR/SVC_Table.s" select="CMSIS-RTOS User SVC"/>
3210
3211         <!-- CPU and Compiler dependent -->
3212         <!-- ARMCC -->
3213         <file category="library" condition="CM4_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_IFX.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3214         <file category="library" condition="CM4_FP_LE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_IFX.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3215         <!-- GCC -->
3216         <file category="library" condition="CM4_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_IFX.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3217         <file category="library" condition="CM4_FP_LE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_IFX.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3218         <!-- IAR -->
3219       </files>
3220     </component>
3221
3222     <!-- CMSIS-RTOS Keil RTX5 component -->
3223     <component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX5" Cversion="5.4.0" Capiversion="1.0.0" condition="RTOS RTX5">
3224       <description>CMSIS-RTOS RTX5 implementation for Cortex-M, SC000, and SC300</description>
3225       <RTE_Components_h>
3226         <!-- the following content goes into file 'RTE_Components.h' -->
3227         #define RTE_CMSIS_RTOS                  /* CMSIS-RTOS */
3228         #define RTE_CMSIS_RTOS_RTX5             /* CMSIS-RTOS Keil RTX5 */
3229       </RTE_Components_h>
3230       <files>
3231         <!-- RTX header file -->
3232         <file category="header" name="CMSIS/RTOS2/RTX/Include1/cmsis_os.h"/>
3233         <!-- RTX compatibility module for API V1 -->
3234         <file category="source" name="CMSIS/RTOS2/RTX/Library/cmsis_os1.c"/>
3235       </files>
3236     </component>
3237
3238     <!-- CMSIS-RTOS2 Keil RTX5 component -->
3239     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cversion="5.4.0" Capiversion="2.1.3" condition="RTOS2 RTX5 Lib">
3240       <description>CMSIS-RTOS2 RTX5 for Cortex-M, SC000, C300 and Armv8-M (Library)</description>
3241       <RTE_Components_h>
3242         <!-- the following content goes into file 'RTE_Components.h' -->
3243         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
3244         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
3245       </RTE_Components_h>
3246       <files>
3247         <!-- RTX documentation -->
3248         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
3249
3250         <!-- RTX header files -->
3251         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
3252
3253         <!-- RTX configuration -->
3254         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.4.0"/>
3255         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
3256
3257         <!-- RTX templates -->
3258         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.0.0" select="CMSIS-RTOS2 'main' function"/>
3259         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
3260         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
3261         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
3262         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
3263         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
3264         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
3265         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
3266         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
3267         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
3268
3269         <!-- RTX library configuration -->
3270         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
3271
3272         <!-- RTX libraries (CPU and Compiler dependent) -->
3273         <!-- ARMCC -->
3274         <file category="library" condition="CM0_LE_ARMCC"         name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM0.lib"    src="CMSIS/RTOS2/RTX/Source"/>
3275         <file category="library" condition="CM1_LE_ARMCC"         name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM0.lib"    src="CMSIS/RTOS2/RTX/Source"/>
3276         <file category="library" condition="CM3_LE_ARMCC"         name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM3.lib"    src="CMSIS/RTOS2/RTX/Source"/>
3277         <file category="library" condition="CM4_LE_ARMCC"         name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM3.lib"    src="CMSIS/RTOS2/RTX/Source"/>
3278         <file category="library" condition="CM4_FP_LE_ARMCC"      name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM4F.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3279         <file category="library" condition="CM7_LE_ARMCC"         name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM3.lib"    src="CMSIS/RTOS2/RTX/Source"/>
3280         <file category="library" condition="CM7_FP_LE_ARMCC"      name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM4F.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3281         <file category="library" condition="CM23_LE_ARMCC"        name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MB.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3282         <file category="library" condition="CM33_LE_ARMCC"        name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3283         <file category="library" condition="CM33_FP_LE_ARMCC"     name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib"  src="CMSIS/RTOS2/RTX/Source"/>
3284         <file category="library" condition="CM35P_LE_ARMCC"       name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3285         <file category="library" condition="CM35P_FP_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib"  src="CMSIS/RTOS2/RTX/Source"/>
3286         <file category="library" condition="ARMv8MBL_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MB.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3287         <file category="library" condition="ARMv8MML_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3288         <file category="library" condition="ARMv8MML_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib"  src="CMSIS/RTOS2/RTX/Source"/>
3289         <!-- GCC -->
3290         <file category="library" condition="CM0_LE_GCC"           name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM0.a"   src="CMSIS/RTOS2/RTX/Source"/>
3291         <file category="library" condition="CM1_LE_GCC"           name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM0.a"   src="CMSIS/RTOS2/RTX/Source"/>
3292         <file category="library" condition="CM3_LE_GCC"           name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a"   src="CMSIS/RTOS2/RTX/Source"/>
3293         <file category="library" condition="CM4_LE_GCC"           name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a"   src="CMSIS/RTOS2/RTX/Source"/>
3294         <file category="library" condition="CM4_FP_LE_GCC"        name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM4F.a"  src="CMSIS/RTOS2/RTX/Source"/>
3295         <file category="library" condition="CM7_LE_GCC"           name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a"   src="CMSIS/RTOS2/RTX/Source"/>
3296         <file category="library" condition="CM7_FP_LE_GCC"        name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM4F.a"  src="CMSIS/RTOS2/RTX/Source"/>
3297         <file category="library" condition="CM23_LE_GCC"          name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MB.a"  src="CMSIS/RTOS2/RTX/Source"/>
3298         <file category="library" condition="CM33_LE_GCC"          name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a"  src="CMSIS/RTOS2/RTX/Source"/>
3299         <file category="library" condition="CM33_FP_LE_GCC"       name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
3300         <file category="library" condition="CM35P_LE_GCC"         name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a"  src="CMSIS/RTOS2/RTX/Source"/>
3301         <file category="library" condition="CM35P_FP_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
3302         <file category="library" condition="ARMv8MBL_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MB.a"  src="CMSIS/RTOS2/RTX/Source"/>
3303         <file category="library" condition="ARMv8MML_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a"  src="CMSIS/RTOS2/RTX/Source"/>
3304         <file category="library" condition="ARMv8MML_FP_LE_GCC"   name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
3305         <!-- IAR -->
3306         <file category="library" condition="CM0_LE_IAR"           name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM0.a"      src="CMSIS/RTOS2/RTX/Source"/>
3307         <file category="library" condition="CM1_LE_IAR"           name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM0.a"      src="CMSIS/RTOS2/RTX/Source"/>
3308         <file category="library" condition="CM3_LE_IAR"           name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM3.a"      src="CMSIS/RTOS2/RTX/Source"/>
3309         <file category="library" condition="CM4_LE_IAR"           name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM3.a"      src="CMSIS/RTOS2/RTX/Source"/>
3310         <file category="library" condition="CM4_FP_LE_IAR"        name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM4F.a"     src="CMSIS/RTOS2/RTX/Source"/>
3311         <file category="library" condition="CM7_LE_IAR"           name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM3.a"      src="CMSIS/RTOS2/RTX/Source"/>
3312         <file category="library" condition="CM7_FP_LE_IAR"        name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM4F.a"     src="CMSIS/RTOS2/RTX/Source"/>
3313       </files>
3314     </component>
3315     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library_NS" Cversion="5.4.0" Capiversion="2.1.3" condition="RTOS2 RTX5 NS">
3316       <description>CMSIS-RTOS2 RTX5 for Armv8-M Non-Secure Domain (Library)</description>
3317       <RTE_Components_h>
3318         <!-- the following content goes into file 'RTE_Components.h' -->
3319         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
3320         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
3321         #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS  /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */
3322       </RTE_Components_h>
3323       <files>
3324         <!-- RTX documentation -->
3325         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
3326
3327         <!-- RTX header files -->
3328         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
3329
3330         <!-- RTX configuration -->
3331         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.4.0"/>
3332         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
3333
3334         <!-- RTX templates -->
3335         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.0.0" select="CMSIS-RTOS2 'main' function"/>
3336         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
3337         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
3338         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
3339         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
3340         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
3341         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
3342         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
3343         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
3344         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
3345
3346         <!-- RTX library configuration -->
3347         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
3348
3349         <!-- RTX libraries (CPU and Compiler dependent) -->
3350         <!-- ARMCC -->
3351         <file category="library" condition="CM23_LE_ARMCC"        name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MBN.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3352         <file category="library" condition="CM33_LE_ARMCC"        name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3353         <file category="library" condition="CM33_FP_LE_ARMCC"     name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib"  src="CMSIS/RTOS2/RTX/Source"/>
3354         <file category="library" condition="CM35P_LE_ARMCC"       name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3355         <file category="library" condition="CM35P_FP_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib"  src="CMSIS/RTOS2/RTX/Source"/>
3356         <file category="library" condition="ARMv8MBL_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MBN.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3357         <file category="library" condition="ARMv8MML_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3358         <file category="library" condition="ARMv8MML_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib"  src="CMSIS/RTOS2/RTX/Source"/>
3359         <!-- GCC -->
3360         <file category="library" condition="CM23_LE_GCC"          name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MBN.a"  src="CMSIS/RTOS2/RTX/Source"/>
3361         <file category="library" condition="CM33_LE_GCC"          name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a"  src="CMSIS/RTOS2/RTX/Source"/>
3362         <file category="library" condition="CM33_FP_LE_GCC"       name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
3363         <file category="library" condition="CM35P_LE_GCC"         name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a"  src="CMSIS/RTOS2/RTX/Source"/>
3364         <file category="library" condition="CM35P_FP_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
3365         <file category="library" condition="ARMv8MBL_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MBN.a"  src="CMSIS/RTOS2/RTX/Source"/>
3366         <file category="library" condition="ARMv8MML_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a"  src="CMSIS/RTOS2/RTX/Source"/>
3367         <file category="library" condition="ARMv8MML_FP_LE_GCC"   name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
3368       </files>
3369     </component>
3370     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cversion="5.4.0" Capiversion="2.1.3" condition="RTOS2 RTX5">
3371       <description>CMSIS-RTOS2 RTX5 for Cortex-M, SC000, C300 and Armv8-M (Source)</description>
3372       <RTE_Components_h>
3373         <!-- the following content goes into file 'RTE_Components.h' -->
3374         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
3375         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
3376         #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
3377       </RTE_Components_h>
3378       <files>
3379         <!-- RTX documentation -->
3380         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
3381
3382         <!-- RTX header files -->
3383         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
3384
3385         <!-- RTX configuration -->
3386         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.4.0"/>
3387         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
3388
3389         <!-- RTX templates -->
3390         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.0.0" select="CMSIS-RTOS2 'main' function"/>
3391         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
3392         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
3393         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
3394         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
3395         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
3396         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
3397         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
3398         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
3399         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
3400
3401         <!-- RTX sources (core) -->
3402         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_kernel.c"/>
3403         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_thread.c"/>
3404         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_delay.c"/>
3405         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_timer.c"/>
3406         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evflags.c"/>
3407         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mutex.c"/>
3408         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_semaphore.c"/>
3409         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_memory.c"/>
3410         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mempool.c"/>
3411         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c"/>
3412         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_system.c"/>
3413         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evr.c"/>
3414         <!-- RTX sources (library configuration) -->
3415         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
3416         <!-- RTX sources (handlers ARMCC) -->
3417         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm0.s"         condition="CM0_ARMCC"/>
3418         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm0.s"         condition="CM1_ARMCC"/>
3419         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm3.s"         condition="CM3_ARMCC"/>
3420         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm3.s"         condition="CM4_ARMCC"/>
3421         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm4f.s"        condition="CM4_FP_ARMCC"/>
3422         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm3.s"         condition="CM7_ARMCC"/>
3423         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm4f.s"        condition="CM7_FP_ARMCC"/>
3424         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl.s"    condition="CM23_ARMCC"/>
3425         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="CM33_ARMCC"/>
3426         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="CM33_FP_ARMCC"/>
3427         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="CM35P_ARMCC"/>
3428         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="CM35P_FP_ARMCC"/>
3429         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl.s"    condition="ARMv8MBL_ARMCC"/>
3430         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="ARMv8MML_ARMCC"/>
3431         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="ARMv8MML_FP_ARMCC"/>
3432         <!-- RTX sources (handlers GCC) -->
3433         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm0.S"         condition="CM0_GCC"/>
3434         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm0.S"         condition="CM1_GCC"/>
3435         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm3.S"         condition="CM3_GCC"/>
3436         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm3.S"         condition="CM4_GCC"/>
3437         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm4f.S"        condition="CM4_FP_GCC"/>
3438         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm3.S"         condition="CM7_GCC"/>
3439         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm4f.S"        condition="CM7_FP_GCC"/>
3440         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S"    condition="CM23_GCC"/>
3441         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S"    condition="CM33_GCC"/>
3442         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp.S" condition="CM33_FP_GCC"/>
3443         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S"    condition="CM35P_GCC"/>
3444         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp.S" condition="CM35P_FP_GCC"/>
3445         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S"    condition="ARMv8MBL_GCC"/>
3446         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S"    condition="ARMv8MML_GCC"/>
3447         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp.S" condition="ARMv8MML_FP_GCC"/>
3448         <!-- RTX sources (handlers IAR) -->
3449         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm0.s"         condition="CM0_IAR"/>
3450         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm0.s"         condition="CM1_IAR"/>
3451         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm3.s"         condition="CM3_IAR"/>
3452         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm3.s"         condition="CM4_IAR"/>
3453         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm4f.s"        condition="CM4_FP_IAR"/>
3454         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm3.s"         condition="CM7_IAR"/>
3455         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm4f.s"        condition="CM7_FP_IAR"/>
3456         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s"    condition="CM23_IAR"/>
3457         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="CM33_IAR"/>
3458         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="CM33_FP_IAR"/>
3459         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="CM35P_IAR"/>
3460         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="CM35P_FP_IAR"/>
3461         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s"    condition="ARMv8MBL_IAR"/>
3462         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="ARMv8MML_IAR"/>
3463         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="ARMv8MML_FP_IAR"/>
3464         <!-- OS Tick (SysTick) -->
3465         <file category="source" name="CMSIS/RTOS2/Source/os_systick.c"/>
3466       </files>
3467     </component>
3468     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cversion="5.4.0" Capiversion="2.1.3" condition="RTOS2 RTX5 v7-A">
3469       <description>CMSIS-RTOS2 RTX5 for Armv7-A (Source)</description>
3470       <RTE_Components_h>
3471         <!-- the following content goes into file 'RTE_Components.h' -->
3472         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
3473         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
3474         #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
3475       </RTE_Components_h>
3476       <files>
3477         <!-- RTX documentation -->
3478         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
3479
3480         <!-- RTX header files -->
3481         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
3482
3483         <!-- RTX configuration -->
3484         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.4.0"/>
3485         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
3486
3487         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/handlers.c"    version="5.1.0"/>
3488
3489         <!-- RTX templates -->
3490         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.0.0" select="CMSIS-RTOS2 'main' function"/>
3491         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
3492         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
3493         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
3494         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
3495         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
3496         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
3497         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
3498         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
3499         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
3500
3501         <!-- RTX sources (core) -->
3502         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_kernel.c"/>
3503         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_thread.c"/>
3504         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_delay.c"/>
3505         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_timer.c"/>
3506         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evflags.c"/>
3507         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mutex.c"/>
3508         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_semaphore.c"/>
3509         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_memory.c"/>
3510         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mempool.c"/>
3511         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c"/>
3512         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_system.c"/>
3513         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evr.c"/>
3514         <!-- RTX sources (library configuration) -->
3515         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
3516         <!-- RTX sources (handlers ARMCC) -->
3517         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_ca.s"          condition="CA_ARMCC5"/>
3518         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_ca.S"          condition="CA_ARMCC6"/>
3519         <!-- RTX sources (handlers GCC) -->
3520         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_ca.S"          condition="CA_GCC"/>
3521         <!-- RTX sources (handlers IAR) -->
3522         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_ca.s"          condition="CA_IAR"/>
3523       </files>
3524     </component>
3525     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source_NS" Cversion="5.4.0" Capiversion="2.1.3" condition="RTOS2 RTX5 NS">
3526       <description>CMSIS-RTOS2 RTX5 for Armv8-M Non-Secure Domain (Source)</description>
3527       <RTE_Components_h>
3528         <!-- the following content goes into file 'RTE_Components.h' -->
3529         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
3530         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
3531         #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
3532         #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS  /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */
3533       </RTE_Components_h>
3534       <files>
3535         <!-- RTX documentation -->
3536         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
3537
3538         <!-- RTX header files -->
3539         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
3540
3541         <!-- RTX configuration -->
3542         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.4.0"/>
3543         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
3544
3545         <!-- RTX templates -->
3546         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.0.0" select="CMSIS-RTOS2 'main' function"/>
3547         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
3548         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
3549         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
3550         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
3551         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
3552         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
3553         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
3554         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
3555         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
3556
3557         <!-- RTX sources (core) -->
3558         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_kernel.c"/>
3559         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_thread.c"/>
3560         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_delay.c"/>
3561         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_timer.c"/>
3562         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evflags.c"/>
3563         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mutex.c"/>
3564         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_semaphore.c"/>
3565         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_memory.c"/>
3566         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mempool.c"/>
3567         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c"/>
3568         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_system.c"/>
3569         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evr.c"/>
3570         <!-- RTX sources (library configuration) -->
3571         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
3572         <!-- RTX sources (ARMCC handlers) -->
3573         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl_ns.s"    condition="CM23_ARMCC"/>
3574         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="CM33_ARMCC"/>
3575         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="CM33_FP_ARMCC"/>
3576         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="CM35P_ARMCC"/>
3577         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="CM35P_FP_ARMCC"/>
3578         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl_ns.s"    condition="ARMv8MBL_ARMCC"/>
3579         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="ARMv8MML_ARMCC"/>
3580         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="ARMv8MML_FP_ARMCC"/>
3581         <!-- RTX sources (GCC handlers) -->
3582         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl_ns.S"    condition="CM23_GCC"/>
3583         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_ns.S"    condition="CM33_GCC"/>
3584         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp_ns.S" condition="CM33_FP_GCC"/>
3585         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_ns.S"    condition="CM35P_GCC"/>
3586         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp_ns.S" condition="CM35P_FP_GCC"/>
3587         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl_ns.S"    condition="ARMv8MBL_GCC"/>
3588         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_ns.S"    condition="ARMv8MML_GCC"/>
3589         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp_ns.S" condition="ARMv8MML_FP_GCC"/>
3590         <!-- RTX sources (IAR handlers) -->
3591         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl_ns.s"    condition="CM23_IAR"/>
3592         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="CM33_IAR"/>
3593         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="CM33_FP_IAR"/>
3594         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="CM35P_IAR"/>
3595         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="CM35P_FP_IAR"/>
3596         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl_ns.s"    condition="ARMv8MBL_IAR"/>
3597         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="ARMv8MML_IAR"/>
3598         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="ARMv8MML_FP_IAR"/>
3599         <!-- OS Tick (SysTick) -->
3600         <file category="source" name="CMSIS/RTOS2/Source/os_systick.c"/>
3601       </files>
3602     </component>
3603
3604   </components>
3605
3606   <boards>
3607     <board name="uVision Simulator" vendor="Keil">
3608       <description>uVision Simulator</description>
3609       <mountedDevice    deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0"/>
3610       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0P"/>
3611       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0P_MPU"/>
3612       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM1"/>
3613       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM3"/>
3614       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM4"/>
3615       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM4_FP"/>
3616       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7"/>
3617       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7_SP"/>
3618       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7_DP"/>
3619       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MBL"/>
3620       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML"/>
3621       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML_SP"/>
3622       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML_DP"/>
3623       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM23"/>
3624       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM23_TZ"/>
3625       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33"/>
3626       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_TZ"/>
3627       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_DSP_FP"/>
3628       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_DSP_FP_TZ"/>
3629       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P"/>
3630       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P_TZ"/>
3631       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P_DSP_FP"/>
3632       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P_DSP_FP_TZ"/>
3633     </board>
3634
3635     <board name="Fixed Virtual Platform" vendor="ARM">
3636       <description>Fixed Virtual Platform</description>
3637       <mountedDevice    deviceIndex="0" Dvendor="ARM:82" Dname="ARMCA5"/>
3638       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCA7"/>
3639       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCA9"/>
3640     </board>
3641   </boards>
3642
3643   <examples>
3644     <example name="DSP_Lib Class Marks example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_class_marks_example">
3645       <description>DSP_Lib Class Marks example</description>
3646       <board name="uVision Simulator" vendor="Keil"/>
3647       <project>
3648         <environment name="uv" load="arm_class_marks_example.uvprojx"/>
3649       </project>
3650       <attributes>
3651         <component Cclass="CMSIS" Cgroup="CORE"/>
3652         <component Cclass="CMSIS" Cgroup="DSP"/>
3653         <component Cclass="Device" Cgroup="Startup"/>
3654         <category>Getting Started</category>
3655       </attributes>
3656     </example>
3657
3658     <example name="DSP_Lib Convolution example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_convolution_example">
3659       <description>DSP_Lib Convolution example</description>
3660       <board name="uVision Simulator" vendor="Keil"/>
3661       <project>
3662         <environment name="uv" load="arm_convolution_example.uvprojx"/>
3663       </project>
3664       <attributes>
3665         <component Cclass="CMSIS" Cgroup="CORE"/>
3666         <component Cclass="CMSIS" Cgroup="DSP"/>
3667         <component Cclass="Device" Cgroup="Startup"/>
3668         <category>Getting Started</category>
3669       </attributes>
3670     </example>
3671
3672     <example name="DSP_Lib Dotproduct example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_dotproduct_example">
3673       <description>DSP_Lib Dotproduct example</description>
3674       <board name="uVision Simulator" vendor="Keil"/>
3675       <project>
3676         <environment name="uv" load="arm_dotproduct_example.uvprojx"/>
3677       </project>
3678       <attributes>
3679         <component Cclass="CMSIS" Cgroup="CORE"/>
3680         <component Cclass="CMSIS" Cgroup="DSP"/>
3681         <component Cclass="Device" Cgroup="Startup"/>
3682         <category>Getting Started</category>
3683       </attributes>
3684     </example>
3685
3686     <example name="DSP_Lib FFT Bin example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_fft_bin_example">
3687       <description>DSP_Lib FFT Bin example</description>
3688       <board name="uVision Simulator" vendor="Keil"/>
3689       <project>
3690         <environment name="uv" load="arm_fft_bin_example.uvprojx"/>
3691       </project>
3692       <attributes>
3693         <component Cclass="CMSIS" Cgroup="CORE"/>
3694         <component Cclass="CMSIS" Cgroup="DSP"/>
3695         <component Cclass="Device" Cgroup="Startup"/>
3696         <category>Getting Started</category>
3697       </attributes>
3698     </example>
3699
3700     <example name="DSP_Lib FIR example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_fir_example">
3701       <description>DSP_Lib FIR example</description>
3702       <board name="uVision Simulator" vendor="Keil"/>
3703       <project>
3704         <environment name="uv" load="arm_fir_example.uvprojx"/>
3705       </project>
3706       <attributes>
3707         <component Cclass="CMSIS" Cgroup="CORE"/>
3708         <component Cclass="CMSIS" Cgroup="DSP"/>
3709         <component Cclass="Device" Cgroup="Startup"/>
3710         <category>Getting Started</category>
3711       </attributes>
3712     </example>
3713
3714     <example name="DSP_Lib Graphic Equalizer example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example">
3715       <description>DSP_Lib Graphic Equalizer example</description>
3716       <board name="uVision Simulator" vendor="Keil"/>
3717       <project>
3718         <environment name="uv" load="arm_graphic_equalizer_example.uvprojx"/>
3719       </project>
3720       <attributes>
3721         <component Cclass="CMSIS" Cgroup="CORE"/>
3722         <component Cclass="CMSIS" Cgroup="DSP"/>
3723         <component Cclass="Device" Cgroup="Startup"/>
3724         <category>Getting Started</category>
3725       </attributes>
3726     </example>
3727
3728     <example name="DSP_Lib Linear Interpolation example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_linear_interp_example">
3729       <description>DSP_Lib Linear Interpolation example</description>
3730       <board name="uVision Simulator" vendor="Keil"/>
3731       <project>
3732         <environment name="uv" load="arm_linear_interp_example.uvprojx"/>
3733       </project>
3734       <attributes>
3735         <component Cclass="CMSIS" Cgroup="CORE"/>
3736         <component Cclass="CMSIS" Cgroup="DSP"/>
3737         <component Cclass="Device" Cgroup="Startup"/>
3738         <category>Getting Started</category>
3739       </attributes>
3740     </example>
3741
3742     <example name="DSP_Lib Matrix example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_matrix_example">
3743       <description>DSP_Lib Matrix example</description>
3744       <board name="uVision Simulator" vendor="Keil"/>
3745       <project>
3746         <environment name="uv" load="arm_matrix_example.uvprojx"/>
3747       </project>
3748       <attributes>
3749         <component Cclass="CMSIS" Cgroup="CORE"/>
3750         <component Cclass="CMSIS" Cgroup="DSP"/>
3751         <component Cclass="Device" Cgroup="Startup"/>
3752         <category>Getting Started</category>
3753       </attributes>
3754     </example>
3755
3756     <example name="DSP_Lib Signal Convergence example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_signal_converge_example">
3757       <description>DSP_Lib Signal Convergence example</description>
3758       <board name="uVision Simulator" vendor="Keil"/>
3759       <project>
3760         <environment name="uv" load="arm_signal_converge_example.uvprojx"/>
3761       </project>
3762       <attributes>
3763         <component Cclass="CMSIS" Cgroup="CORE"/>
3764         <component Cclass="CMSIS" Cgroup="DSP"/>
3765         <component Cclass="Device" Cgroup="Startup"/>
3766         <category>Getting Started</category>
3767       </attributes>
3768     </example>
3769
3770     <example name="DSP_Lib Sinus/Cosinus example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_sin_cos_example">
3771       <description>DSP_Lib Sinus/Cosinus example</description>
3772       <board name="uVision Simulator" vendor="Keil"/>
3773       <project>
3774         <environment name="uv" load="arm_sin_cos_example.uvprojx"/>
3775       </project>
3776       <attributes>
3777         <component Cclass="CMSIS" Cgroup="CORE"/>
3778         <component Cclass="CMSIS" Cgroup="DSP"/>
3779         <component Cclass="Device" Cgroup="Startup"/>
3780         <category>Getting Started</category>
3781       </attributes>
3782     </example>
3783
3784     <example name="DSP_Lib Variance example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_variance_example">
3785       <description>DSP_Lib Variance example</description>
3786       <board name="uVision Simulator" vendor="Keil"/>
3787       <project>
3788         <environment name="uv" load="arm_variance_example.uvprojx"/>
3789       </project>
3790       <attributes>
3791         <component Cclass="CMSIS" Cgroup="CORE"/>
3792         <component Cclass="CMSIS" Cgroup="DSP"/>
3793         <component Cclass="Device" Cgroup="Startup"/>
3794         <category>Getting Started</category>
3795       </attributes>
3796     </example>
3797
3798     <example name="NN Library CIFAR10" doc="readme.txt" folder="CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10">
3799       <description>Neural Network CIFAR10 example</description>
3800       <board name="uVision Simulator" vendor="Keil"/>
3801       <project>
3802         <environment name="uv" load="arm_nnexamples_cifar10.uvprojx"/>
3803       </project>
3804       <attributes>
3805         <component Cclass="CMSIS" Cgroup="CORE"/>
3806         <component Cclass="CMSIS" Cgroup="DSP"/>
3807         <component Cclass="CMSIS" Cgroup="NN Lib"/>
3808         <component Cclass="Device" Cgroup="Startup"/>
3809         <category>Getting Started</category>
3810       </attributes>
3811     </example>
3812
3813     <example name="NN Library GRU" doc="readme.txt" folder="CMSIS/NN/Examples/ARM/arm_nn_examples/gru">
3814       <description>Neural Network GRU example</description>
3815       <board name="uVision Simulator" vendor="Keil"/>
3816       <project>
3817         <environment name="uv" load="arm_nnexamples_gru.uvprojx"/>
3818       </project>
3819       <attributes>
3820         <component Cclass="CMSIS" Cgroup="CORE"/>
3821         <component Cclass="CMSIS" Cgroup="DSP"/>
3822         <component Cclass="CMSIS" Cgroup="NN Lib"/>
3823         <component Cclass="Device" Cgroup="Startup"/>
3824         <category>Getting Started</category>
3825       </attributes>
3826     </example>
3827
3828     <example name="CMSIS-RTOS2 Blinky" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/Blinky">
3829       <description>CMSIS-RTOS2 Blinky example</description>
3830       <board name="uVision Simulator" vendor="Keil"/>
3831       <project>
3832         <environment name="uv" load="Blinky.uvprojx"/>
3833       </project>
3834       <attributes>
3835         <component Cclass="CMSIS" Cgroup="CORE"/>
3836         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3837         <component Cclass="Device" Cgroup="Startup"/>
3838         <category>Getting Started</category>
3839       </attributes>
3840     </example>
3841
3842     <example name="CMSIS-RTOS2 RTX5 Migration" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/Migration">
3843       <description>CMSIS-RTOS2 mixed API v1 and v2</description>
3844       <board name="uVision Simulator" vendor="Keil"/>
3845       <project>
3846         <environment name="uv" load="Blinky.uvprojx"/>
3847       </project>
3848       <attributes>
3849         <component Cclass="CMSIS" Cgroup="CORE"/>
3850         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3851         <component Cclass="Device" Cgroup="Startup"/>
3852         <category>Getting Started</category>
3853       </attributes>
3854     </example>
3855
3856     <example name="CMSIS-RTOS2 RTX5 Message Queue" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/MsgQueue">
3857       <description>CMSIS-RTOS2 Message Queue Example</description>
3858       <board name="uVision Simulator" vendor="Keil"/>
3859       <project>
3860         <environment name="uv" load="MsqQueue.uvprojx"/>
3861       </project>
3862       <attributes>
3863         <component Cclass="CMSIS" Cgroup="CORE"/>
3864         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3865         <component Cclass="Compiler" Cgroup="EventRecorder"/>
3866         <component Cclass="Device" Cgroup="Startup"/>
3867         <category>Getting Started</category>
3868       </attributes>
3869     </example>
3870
3871     <example name="CMSIS-RTOS2 RTX5 Memory Pool" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/MemPool">
3872       <description>CMSIS-RTOS2 Memory Pool Example</description>
3873       <board name="Fixed Virtual Platform" vendor="ARM"/>
3874       <project>
3875         <environment name="uv" load="MemPool.uvprojx"/>
3876       </project>
3877       <attributes>
3878         <component Cclass="CMSIS" Cgroup="CORE"/>
3879         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3880         <component Cclass="Compiler" Cgroup="EventRecorder"/>
3881         <component Cclass="Device" Cgroup="Startup"/>
3882         <category>Getting Started</category>
3883       </attributes>
3884     </example>
3885
3886     <example name="TrustZone for ARMv8-M No RTOS" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/NoRTOS">
3887       <description>Bare-metal secure/non-secure example without RTOS</description>
3888       <board name="uVision Simulator" vendor="Keil"/>
3889       <project>
3890         <environment name="uv" load="NoRTOS.uvmpw"/>
3891       </project>
3892       <attributes>
3893         <component Cclass="CMSIS" Cgroup="CORE"/>
3894         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3895         <component Cclass="Device" Cgroup="Startup"/>
3896         <category>Getting Started</category>
3897       </attributes>
3898     </example>
3899
3900     <example name="TrustZone for ARMv8-M RTOS"  doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS">
3901       <description>Secure/non-secure RTOS example with thread context management</description>
3902       <board name="uVision Simulator" vendor="Keil"/>
3903       <project>
3904         <environment name="uv" load="RTOS.uvmpw"/>
3905       </project>
3906       <attributes>
3907         <component Cclass="CMSIS" Cgroup="CORE"/>
3908         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3909         <component Cclass="Device" Cgroup="Startup"/>
3910         <category>Getting Started</category>
3911       </attributes>
3912     </example>
3913
3914     <example name="TrustZone for ARMv8-M RTOS Security Tests"  doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults">
3915       <description>Secure/non-secure RTOS example with security test cases and system recovery</description>
3916       <board name="uVision Simulator" vendor="Keil"/>
3917       <project>
3918         <environment name="uv" load="RTOS_Faults.uvmpw"/>
3919       </project>
3920       <attributes>
3921         <component Cclass="CMSIS" Cgroup="CORE"/>
3922         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3923         <component Cclass="Device" Cgroup="Startup"/>
3924         <category>Getting Started</category>
3925       </attributes>
3926     </example>
3927
3928   </examples>
3929
3930 </package>