1 /**************************************************************************//**
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2 * @file core_armv8mbl.h
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3 * @brief CMSIS ARMv8MBL Core Peripheral Access Layer Header File
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5 * @date 30. March 2016
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6 ******************************************************************************/
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8 * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
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10 * SPDX-License-Identifier: Apache-2.0
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12 * Licensed under the Apache License, Version 2.0 (the License); you may
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13 * not use this file except in compliance with the License.
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14 * You may obtain a copy of the License at
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16 * http://www.apache.org/licenses/LICENSE-2.0
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18 * Unless required by applicable law or agreed to in writing, software
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19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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21 * See the License for the specific language governing permissions and
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22 * limitations under the License.
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25 #if defined ( __ICCARM__ )
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26 #pragma system_include /* treat file as system include file for MISRA check */
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27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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28 #pragma clang system_header /* treat file as system include file */
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31 #ifndef __CORE_ARMV8MBL_H_GENERIC
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32 #define __CORE_ARMV8MBL_H_GENERIC
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41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
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42 CMSIS violates the following MISRA-C:2004 rules:
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44 \li Required Rule 8.5, object/function definition in header file.<br>
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45 Function definitions in header files are used to allow 'inlining'.
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47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
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48 Unions are used for effective representation of core registers.
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50 \li Advisory Rule 19.7, Function-like macro defined.<br>
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51 Function-like macros are used to allow more efficient code.
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55 /*******************************************************************************
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57 ******************************************************************************/
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59 \ingroup Cortex_ARMv8MBL
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63 /* CMSIS cmGrebe definitions */
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64 #define __ARMv8MBL_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
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65 #define __ARMv8MBL_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
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66 #define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
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67 __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
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69 #define __CORTEX_M ( 2U) /*!< Cortex-M Core */
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71 /* Common defines in core_*.h files
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72 - #define __ASM Compiler keyword for asm
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73 - #define __INLINE Compiler keyword for inline
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74 - #define __STATIC_INLINE Compiler keyword for static inline
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75 - #define __NO_RETURN function that never returns
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76 - #define __USED function or variable that is not optimized away
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77 - #define __WEAK weak function or variable
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78 - #define __UNALIGNED_UINT32 pointer to unaligned uint32_t variable
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80 #if defined ( __CC_ARM ) /* ARM Compiler 4/5 */
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82 #define __INLINE __inline
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83 #define __STATIC_INLINE static __inline
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84 #define __NO_RETURN __declspec(noreturn)
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85 #define __USED __attribute__((used))
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86 #define __WEAK __attribute__((weak))
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87 #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
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89 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler 6 */
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91 #define __INLINE __inline
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92 #define __STATIC_INLINE static __inline
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93 #define __NO_RETURN __attribute__((noreturn))
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94 #define __USED __attribute__((used))
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95 #define __WEAK __attribute__((weak))
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96 #pragma clang diagnostic push
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97 #pragma clang diagnostic ignored "-Wpacked"
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98 struct __attribute__((packed)) T_UINT32 { uint32_t v; };
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99 #pragma clang diagnostic pop
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100 #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
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102 #elif defined ( __GNUC__ ) /* GNU Compiler */
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103 #define __ASM __asm
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104 #define __INLINE inline
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105 #define __STATIC_INLINE static inline
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106 #define __NO_RETURN __attribute__((noreturn))
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107 #define __USED __attribute__((used))
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108 #define __WEAK __attribute__((weak))
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109 struct __attribute__((packed)) T_UINT32 { uint32_t v; };
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110 #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
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112 #elif defined ( __ICCARM__ ) /* IAR Compiler */
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113 #define __ASM __asm
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114 #define __INLINE inline
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115 #define __STATIC_INLINE static inline
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116 #define __NO_RETURN __noreturn
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117 #define __USED __attribute__((used))
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118 #define __WEAK __attribute__((weak))
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119 #define __UNALIGNED_UINT32(x) (x)
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121 #elif defined ( __TI_ARM__ ) /* TI ARM Compiler */
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122 #define __ASM __asm
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123 #define __INLINE inline
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124 #define __STATIC_INLINE static inline
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125 #define __NO_RETURN __attribute__((noreturn))
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126 #define __USED __attribute__((used))
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127 #define __WEAK __attribute__((weak))
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128 #define __UNALIGNED_UINT32(x) (x)
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130 #elif defined ( __TASKING__ ) /* TASKING Compiler */
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131 #define __ASM __asm
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132 #define __INLINE inline
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133 #define __STATIC_INLINE static inline
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134 #define __NO_RETURN __attribute__((noreturn))
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135 #define __USED __attribute__((used))
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136 #define __WEAK __attribute__((weak))
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137 #define __UNALIGNED_UINT32(x) (x)
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139 #elif defined ( __CSMC__ ) /* COSMIC Compiler */
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142 #define __INLINE inline
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143 #define __STATIC_INLINE static inline
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144 #define __NO_RETURN
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147 #define __UNALIGNED_UINT32(x) (x)
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150 #error Unknown compiler
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153 /** __FPU_USED indicates whether an FPU is used or not.
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154 This core does not support an FPU at all
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156 #define __FPU_USED 0U
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158 #if defined ( __CC_ARM )
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159 #if defined __TARGET_FPU_VFP
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160 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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163 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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164 #if defined __ARM_PCS_VFP
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165 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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168 #elif defined ( __GNUC__ )
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169 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
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170 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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173 #elif defined ( __ICCARM__ )
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174 #if defined __ARMVFP__
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175 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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178 #elif defined ( __TI_ARM__ )
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179 #if defined __TI_VFP_SUPPORT__
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180 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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183 #elif defined ( __TASKING__ )
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184 #if defined __FPU_VFP__
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185 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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188 #elif defined ( __CSMC__ )
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189 #if ( __CSMC__ & 0x400U)
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190 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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195 #include "core_cminstr.h" /* Core Instruction Access */
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196 #include "core_cmfunc.h" /* Core Function Access */
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202 #endif /* __CORE_ARMV8MBL_H_GENERIC */
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204 #ifndef __CMSIS_GENERIC
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206 #ifndef __CORE_ARMV8MBL_H_DEPENDANT
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207 #define __CORE_ARMV8MBL_H_DEPENDANT
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213 /* check device defines and use defaults */
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214 #if defined __CHECK_DEVICE_DEFINES
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215 #ifndef __ARMv8MBL_REV
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216 #define __ARMv8MBL_REV 0x0000U
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217 #warning "__ARMv8MBL_REV not defined in device header file; using default!"
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220 #ifndef __FPU_PRESENT
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221 #define __FPU_PRESENT 0U
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222 #warning "__FPU_PRESENT not defined in device header file; using default!"
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225 #ifndef __MPU_PRESENT
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226 #define __MPU_PRESENT 0U
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227 #warning "__MPU_PRESENT not defined in device header file; using default!"
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230 #ifndef __SAU_PRESENT
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231 #define __SAU_PRESENT 0U
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232 #warning "__SAU_PRESENT not defined in device header file; using default!"
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235 #ifndef __VTOR_PRESENT
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236 #define __VTOR_PRESENT 0U
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237 #warning "__VTOR_PRESENT not defined in device header file; using default!"
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240 #ifndef __NVIC_PRIO_BITS
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241 #define __NVIC_PRIO_BITS 2U
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242 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
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245 #ifndef __Vendor_SysTickConfig
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246 #define __Vendor_SysTickConfig 0U
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247 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
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250 #ifndef __ETM_PRESENT
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251 #define __ETM_PRESENT 0U
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252 #warning "__ETM_PRESENT not defined in device header file; using default!"
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255 #ifndef __MTB_PRESENT
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256 #define __MTB_PRESENT 0U
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257 #warning "__MTB_PRESENT not defined in device header file; using default!"
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262 /* IO definitions (access restrictions to peripheral registers) */
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264 \defgroup CMSIS_glob_defs CMSIS Global Defines
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266 <strong>IO Type Qualifiers</strong> are used
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267 \li to specify the access to peripheral variables.
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268 \li for automatic generation of peripheral register debug information.
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271 #define __I volatile /*!< Defines 'read only' permissions */
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273 #define __I volatile const /*!< Defines 'read only' permissions */
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275 #define __O volatile /*!< Defines 'write only' permissions */
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276 #define __IO volatile /*!< Defines 'read / write' permissions */
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278 /* following defines should be used for structure members */
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279 #define __IM volatile const /*! Defines 'read only' structure member permissions */
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280 #define __OM volatile /*! Defines 'write only' structure member permissions */
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281 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
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283 /*@} end of group ARMv8MBL */
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287 /*******************************************************************************
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288 * Register Abstraction
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289 Core Register contain:
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291 - Core NVIC Register
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292 - Core SCB Register
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293 - Core SysTick Register
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294 - Core Debug Register
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295 - Core MPU Register
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296 - Core SAU Register
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297 ******************************************************************************/
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299 \defgroup CMSIS_core_register Defines and Type Definitions
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300 \brief Type definitions and defines for Cortex-M processor based devices.
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304 \ingroup CMSIS_core_register
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305 \defgroup CMSIS_CORE Status and Control Registers
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306 \brief Core Register type definitions.
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311 \brief Union type to access the Application Program Status Register (APSR).
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317 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
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318 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
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319 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
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320 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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321 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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322 } b; /*!< Structure used for bit access */
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323 uint32_t w; /*!< Type used for word access */
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326 /* APSR Register Definitions */
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327 #define APSR_N_Pos 31U /*!< APSR: N Position */
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328 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
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330 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
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331 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
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333 #define APSR_C_Pos 29U /*!< APSR: C Position */
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334 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
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336 #define APSR_V_Pos 28U /*!< APSR: V Position */
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337 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
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341 \brief Union type to access the Interrupt Program Status Register (IPSR).
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347 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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348 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
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349 } b; /*!< Structure used for bit access */
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350 uint32_t w; /*!< Type used for word access */
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353 /* IPSR Register Definitions */
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354 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
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355 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
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359 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
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365 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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366 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
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367 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
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368 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
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369 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
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370 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
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371 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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372 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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373 } b; /*!< Structure used for bit access */
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374 uint32_t w; /*!< Type used for word access */
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377 /* xPSR Register Definitions */
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378 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
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379 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
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381 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
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382 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
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384 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
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385 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
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387 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
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388 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
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390 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
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391 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
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393 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
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394 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
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398 \brief Union type to access the Control Registers (CONTROL).
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404 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
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405 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
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406 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
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407 } b; /*!< Structure used for bit access */
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408 uint32_t w; /*!< Type used for word access */
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411 /* CONTROL Register Definitions */
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412 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
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413 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
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415 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
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416 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
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418 /*@} end of group CMSIS_CORE */
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422 \ingroup CMSIS_core_register
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423 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
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424 \brief Type definitions for the NVIC Registers
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429 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
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433 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
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434 uint32_t RESERVED0[24U];
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435 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
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436 uint32_t RSERVED1[24U];
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437 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
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438 uint32_t RESERVED2[24U];
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439 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
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440 uint32_t RESERVED3[24U];
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441 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register (TODO: Confirm position and count, barely mentioned in v8-M specs) */
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442 uint32_t RESERVED4[24U];
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443 __IOM uint32_t ITNS[8U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
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444 uint32_t RESERVED5[24U];
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445 __IOM uint32_t IP[60U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
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448 /*@} end of group CMSIS_NVIC */
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452 \ingroup CMSIS_core_register
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453 \defgroup CMSIS_SCB System Control Block (SCB)
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454 \brief Type definitions for the System Control Block Registers
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459 \brief Structure type to access the System Control Block (SCB).
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463 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
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464 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
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465 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
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466 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
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468 uint32_t RESERVED0;
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470 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
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471 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
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472 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
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473 uint32_t RESERVED1;
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474 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
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475 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
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478 /* SCB CPUID Register Definitions */
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479 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
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480 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
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482 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
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483 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
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485 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
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486 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
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488 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
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489 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
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491 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
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492 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
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494 /* SCB Interrupt Control State Register Definitions */
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495 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
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496 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
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498 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position (Security Extension) */
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499 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask (Security Extension) */
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501 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
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502 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
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504 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
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505 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
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507 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
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508 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
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510 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
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511 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
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513 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
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514 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
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516 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
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517 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
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519 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
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520 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
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522 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
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523 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
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525 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
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526 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
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528 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
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529 /* SCB Vector Table Offset Register Definitions */
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530 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
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531 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
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534 /* SCB Application Interrupt and Reset Control Register Definitions */
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535 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
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536 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
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538 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
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539 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
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541 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
\r
542 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
\r
544 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
\r
545 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
\r
547 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
\r
548 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
\r
550 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
\r
551 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
\r
553 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
\r
554 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
\r
556 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
\r
557 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
\r
559 /* SCB System Control Register Definitions */
\r
560 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
\r
561 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
\r
563 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
\r
564 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
\r
566 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
\r
567 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
\r
569 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
\r
570 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
\r
572 /* SCB Configuration Control Register Definitions */
\r
573 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
\r
574 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
\r
576 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
\r
577 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
\r
579 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
\r
580 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
\r
582 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
\r
583 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
\r
585 /* SCB System Handler Control and State Register Definitions */
\r
586 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
\r
587 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
\r
589 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
\r
590 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
\r
592 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
\r
593 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
\r
595 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
\r
596 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
\r
598 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
\r
599 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
\r
601 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
\r
602 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
\r
604 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
\r
605 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
\r
607 /*@} end of group CMSIS_SCB */
\r
611 \ingroup CMSIS_core_register
\r
612 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
\r
613 \brief Type definitions for the System Timer Registers.
\r
618 \brief Structure type to access the System Timer (SysTick).
\r
622 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
\r
623 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
\r
624 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
\r
625 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
\r
628 /* SysTick Control / Status Register Definitions */
\r
629 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
\r
630 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
\r
632 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
\r
633 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
\r
635 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
\r
636 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
\r
638 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
\r
639 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
\r
641 /* SysTick Reload Register Definitions */
\r
642 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
\r
643 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
\r
645 /* SysTick Current Register Definitions */
\r
646 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
\r
647 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
\r
649 /* SysTick Calibration Register Definitions */
\r
650 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
\r
651 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
\r
653 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
\r
654 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
\r
656 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
\r
657 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
\r
659 /*@} end of group CMSIS_SysTick */
\r
663 \ingroup CMSIS_core_register
\r
664 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
\r
665 \brief Type definitions for the Data Watchpoint and Trace (DWT)
\r
670 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
\r
674 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
\r
675 uint32_t RESERVED0[6U];
\r
676 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
\r
677 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
\r
678 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
\r
679 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
\r
680 uint32_t RESERVED1[1U];
\r
681 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
\r
682 uint32_t RESERVED2[1U];
\r
683 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
\r
684 uint32_t RESERVED3[1U];
\r
685 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
\r
686 uint32_t RESERVED4[1U];
\r
687 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
\r
688 uint32_t RESERVED5[1U];
\r
689 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
\r
690 uint32_t RESERVED6[1U];
\r
691 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
\r
694 /* DWT Control Register Definitions */
\r
695 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
\r
696 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
\r
698 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
\r
699 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
\r
701 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
\r
702 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
\r
704 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
\r
705 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
\r
707 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
\r
708 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
\r
710 /* DWT Comparator Function Register Definitions */
\r
711 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
\r
712 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
\r
714 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
\r
715 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
\r
717 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
\r
718 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
\r
720 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
\r
721 #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
\r
723 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
\r
724 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
\r
726 /*@}*/ /* end of group CMSIS_DWT */
\r
730 \ingroup CMSIS_core_register
\r
731 \defgroup CMSIS_TPI Trace Port Interface (TPI)
\r
732 \brief Type definitions for the Trace Port Interface (TPI)
\r
737 \brief Structure type to access the Trace Port Interface Register (TPI).
\r
741 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
\r
742 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
\r
743 uint32_t RESERVED0[2U];
\r
744 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
\r
745 uint32_t RESERVED1[55U];
\r
746 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
\r
747 uint32_t RESERVED2[131U];
\r
748 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
\r
749 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
\r
750 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
\r
751 uint32_t RESERVED3[759U];
\r
752 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
\r
753 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
\r
754 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
\r
755 uint32_t RESERVED4[1U];
\r
756 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
\r
757 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
\r
758 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
\r
759 uint32_t RESERVED5[39U];
\r
760 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
\r
761 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
\r
762 uint32_t RESERVED7[8U];
\r
763 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
\r
764 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
\r
767 /* TPI Asynchronous Clock Prescaler Register Definitions */
\r
768 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
\r
769 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
\r
771 /* TPI Selected Pin Protocol Register Definitions */
\r
772 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
\r
773 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
\r
775 /* TPI Formatter and Flush Status Register Definitions */
\r
776 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
\r
777 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
\r
779 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
\r
780 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
\r
782 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
\r
783 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
\r
785 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
\r
786 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
\r
788 /* TPI Formatter and Flush Control Register Definitions */
\r
789 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
\r
790 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
\r
792 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
\r
793 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
\r
795 /* TPI TRIGGER Register Definitions */
\r
796 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
\r
797 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
\r
799 /* TPI Integration ETM Data Register Definitions (FIFO0) */
\r
800 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
\r
801 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
\r
803 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
\r
804 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
\r
806 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
\r
807 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
\r
809 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
\r
810 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
\r
812 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
\r
813 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
\r
815 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
\r
816 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
\r
818 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
\r
819 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
\r
821 /* TPI ITATBCTR2 Register Definitions */
\r
822 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
\r
823 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
\r
825 /* TPI Integration ITM Data Register Definitions (FIFO1) */
\r
826 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
\r
827 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
\r
829 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
\r
830 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
\r
832 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
\r
833 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
\r
835 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
\r
836 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
\r
838 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
\r
839 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
\r
841 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
\r
842 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
\r
844 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
\r
845 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
\r
847 /* TPI ITATBCTR0 Register Definitions */
\r
848 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
\r
849 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
\r
851 /* TPI Integration Mode Control Register Definitions */
\r
852 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
\r
853 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
\r
855 /* TPI DEVID Register Definitions */
\r
856 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
\r
857 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
\r
859 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
\r
860 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
\r
862 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
\r
863 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
\r
865 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
\r
866 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
\r
868 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
\r
869 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
\r
871 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
\r
872 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
\r
874 /* TPI DEVTYPE Register Definitions */
\r
875 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
\r
876 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
\r
878 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
\r
879 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
\r
881 /*@}*/ /* end of group CMSIS_TPI */
\r
884 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
\r
886 \ingroup CMSIS_core_register
\r
887 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
\r
888 \brief Type definitions for the Memory Protection Unit (MPU)
\r
893 \brief Structure type to access the Memory Protection Unit (MPU).
\r
897 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
\r
898 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
\r
899 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
\r
900 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
\r
901 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
\r
902 uint32_t RESERVED0[7U];
\r
903 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
\r
904 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
\r
907 /* MPU Type Register Definitions */
\r
908 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
\r
909 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
\r
911 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
\r
912 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
\r
914 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
\r
915 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
\r
917 /* MPU Control Register Definitions */
\r
918 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
\r
919 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
\r
921 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
\r
922 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
\r
924 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
\r
925 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
\r
927 /* MPU Region Number Register Definitions */
\r
928 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
\r
929 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
\r
931 /* MPU Region Base Address Register Definitions */
\r
932 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
\r
933 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
\r
935 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
\r
936 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
\r
938 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
\r
939 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
\r
941 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
\r
942 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
\r
944 /* MPU Region Limit Address Register Definitions */
\r
945 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
\r
946 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
\r
948 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
\r
949 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
\r
951 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
\r
952 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
\r
954 /* MPU Memory Attribute Indirection Register 0 Definitions */
\r
955 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
\r
956 #define MPU_MAIR0_Attr3_Msk (0xFFUL /*<< MPU_MAIR0_Attr3_Pos*/) /*!< MPU MAIR0: Attr3 Mask */
\r
958 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
\r
959 #define MPU_MAIR0_Attr2_Msk (0xFFUL /*<< MPU_MAIR0_Attr2_Pos*/) /*!< MPU MAIR0: Attr2 Mask */
\r
961 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
\r
962 #define MPU_MAIR0_Attr1_Msk (0xFFUL /*<< MPU_MAIR0_Attr1_Pos*/) /*!< MPU MAIR0: Attr1 Mask */
\r
964 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
\r
965 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
\r
967 /* MPU Memory Attribute Indirection Register 1 Definitions */
\r
968 #define MPU_MAIR1_Attr3_Pos 24U /*!< MPU MAIR1: Attr7 Position */
\r
969 #define MPU_MAIR1_Attr3_Msk (0xFFUL /*<< MPU_MAIR1_Attr7_Pos*/) /*!< MPU MAIR1: Attr7 Mask */
\r
971 #define MPU_MAIR1_Attr2_Pos 16U /*!< MPU MAIR1: Attr6 Position */
\r
972 #define MPU_MAIR1_Attr2_Msk (0xFFUL /*<< MPU_MAIR1_Attr6_Pos*/) /*!< MPU MAIR1: Attr6 Mask */
\r
974 #define MPU_MAIR1_Attr1_Pos 8U /*!< MPU MAIR1: Attr5 Position */
\r
975 #define MPU_MAIR1_Attr1_Msk (0xFFUL /*<< MPU_MAIR1_Attr5_Pos*/) /*!< MPU MAIR1: Attr5 Mask */
\r
977 #define MPU_MAIR1_Attr0_Pos 0U /*!< MPU MAIR1: Attr4 Position */
\r
978 #define MPU_MAIR1_Attr0_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
\r
980 /*@} end of group CMSIS_MPU */
\r
984 #if defined (__SAU_PRESENT) && (__SAU_PRESENT == 1U)
\r
986 \ingroup CMSIS_core_register
\r
987 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
\r
988 \brief Type definitions for the Security Attribution Unit (SAU)
\r
993 \brief Structure type to access the Security Attribution Unit (SAU).
\r
997 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
\r
998 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
\r
999 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
\r
1000 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
\r
1001 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
\r
1004 /* SAU Control Register Definitions */
\r
1005 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
\r
1006 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
\r
1008 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
\r
1009 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
\r
1011 /* SAU Type Register Definitions */
\r
1012 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
\r
1013 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
\r
1015 /* SAU Region Number Register Definitions */
\r
1016 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
\r
1017 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
\r
1019 /* SAU Region Base Address Register Definitions */
\r
1020 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
\r
1021 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
\r
1023 /* SAU Region Limit Address Register Definitions */
\r
1024 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
\r
1025 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
\r
1027 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
\r
1028 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
\r
1030 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
\r
1031 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
\r
1033 /*@} end of group CMSIS_SAU */
\r
1038 \ingroup CMSIS_core_register
\r
1039 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\r
1040 \brief Type definitions for the Core Debug Registers
\r
1045 \brief Structure type to access the Core Debug Register (CoreDebug).
\r
1049 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
\r
1050 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
\r
1051 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
\r
1052 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
\r
1055 /* Debug Halting Control and Status Register Definitions */
\r
1056 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
\r
1057 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
\r
1059 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
\r
1060 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
\r
1062 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
\r
1063 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
\r
1065 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
\r
1066 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
\r
1068 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
\r
1069 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
\r
1071 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
\r
1072 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
\r
1074 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
\r
1075 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
\r
1077 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
\r
1078 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
\r
1080 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
\r
1081 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
\r
1083 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
\r
1084 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
\r
1086 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
\r
1087 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
\r
1089 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
\r
1090 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
\r
1092 /* Debug Core Register Selector Register Definitions */
\r
1093 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
\r
1094 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
\r
1096 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
\r
1097 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
\r
1099 /* Debug Exception and Monitor Control Register */
\r
1100 #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
\r
1101 #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
\r
1103 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
\r
1104 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
\r
1106 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
\r
1107 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
\r
1109 /*@} end of group CMSIS_CoreDebug */
\r
1113 \ingroup CMSIS_core_register
\r
1114 \defgroup CMSIS_core_bitfield Core register bit field macros
\r
1115 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
\r
1120 \brief Mask and shift a bit field value for use in a register bit range.
\r
1121 \param[in] field Name of the register bit field.
\r
1122 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\r
1123 \return Masked and shifted value.
\r
1125 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
\r
1128 \brief Mask and shift a register value to extract a bit filed value.
\r
1129 \param[in] field Name of the register bit field.
\r
1130 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\r
1131 \return Masked and shifted bit field value.
\r
1133 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
\r
1135 /*@} end of group CMSIS_core_bitfield */
\r
1139 \ingroup CMSIS_core_register
\r
1140 \defgroup CMSIS_core_base Core Definitions
\r
1141 \brief Definitions for base addresses, unions, and structures.
\r
1145 /* Memory mapping of ARMv8MBL Hardware */
\r
1146 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
\r
1147 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
\r
1148 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
\r
1149 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
\r
1150 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
\r
1151 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
\r
1152 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
\r
1155 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
\r
1156 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
\r
1157 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
\r
1158 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
\r
1159 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
\r
1160 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
\r
1162 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
\r
1163 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
\r
1164 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
\r
1167 #if defined (__SAU_PRESENT) && (__SAU_PRESENT == 1U)
\r
1168 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
\r
1169 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
\r
1172 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
\r
1173 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secuer address space) */
\r
1174 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secuer address space) */
\r
1175 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secuer address space) */
\r
1176 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secuer address space) */
\r
1177 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secuer address space) */
\r
1179 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secuer address space) */
\r
1180 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secuer address space) */
\r
1181 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secuer address space) */
\r
1182 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secuer address space) */
\r
1184 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
\r
1185 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secuer address space) */
\r
1186 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secuer address space) */
\r
1189 #if defined (__SAU_PRESENT) && (__SAU_PRESENT == 1U)
\r
1190 #define SAU_BASE_NS (SCS_BASE_NS + 0x0DD0UL) /*!< Security Attribution Unit (non-secuer address space) */
\r
1191 #define SAU_NS ((SAU_Type *) SAU_BASE_NS ) /*!< Security Attribution Unit (non-secuer address space) */
\r
1194 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
\r
1199 /*******************************************************************************
\r
1200 * Hardware Abstraction Layer
\r
1201 Core Function Interface contains:
\r
1202 - Core NVIC Functions
\r
1203 - Core SysTick Functions
\r
1204 - Core Register Access Functions
\r
1205 ******************************************************************************/
\r
1207 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
\r
1212 /* ########################## NVIC functions #################################### */
\r
1214 \ingroup CMSIS_Core_FunctionInterface
\r
1215 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
\r
1216 \brief Functions that manage interrupts and exceptions via the NVIC.
\r
1220 /* Interrupt Priorities are WORD accessible only under ARMv6M */
\r
1221 /* The following MACROS handle generation of the register offset and byte masks */
\r
1222 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
\r
1223 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
\r
1224 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
\r
1228 \brief Enable External Interrupt
\r
1229 \details Enables a device-specific interrupt in the NVIC interrupt controller.
\r
1230 \param [in] IRQn External interrupt number. Value cannot be negative.
\r
1232 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
\r
1234 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
\r
1239 \brief Disable External Interrupt
\r
1240 \details Disables a device-specific interrupt in the NVIC interrupt controller.
\r
1241 \param [in] IRQn External interrupt number. Value cannot be negative.
\r
1243 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
\r
1245 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
\r
1250 \brief Get Pending Interrupt
\r
1251 \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
\r
1252 \param [in] IRQn Interrupt number.
\r
1253 \return 0 Interrupt status is not pending.
\r
1254 \return 1 Interrupt status is pending.
\r
1256 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
\r
1258 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
1263 \brief Set Pending Interrupt
\r
1264 \details Sets the pending bit of an external interrupt.
\r
1265 \param [in] IRQn Interrupt number. Value cannot be negative.
\r
1267 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
\r
1269 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
\r
1274 \brief Clear Pending Interrupt
\r
1275 \details Clears the pending bit of an external interrupt.
\r
1276 \param [in] IRQn External interrupt number. Value cannot be negative.
\r
1278 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
\r
1280 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
\r
1285 \brief Get Active Interrupt
\r
1286 \details Reads the active register in NVIC and returns the active bit.
\r
1287 \param [in] IRQn Interrupt number.
\r
1288 \return 0 Interrupt status is not active.
\r
1289 \return 1 Interrupt status is active.
\r
1291 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
\r
1293 return ((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
1298 \brief Get Interrupt Target State
\r
1299 \details Reads the interrupt target field from the NVIC Interrupt Controller.
\r
1300 \param [in] IRQn External interrupt number. Value cannot be negative.
\r
1301 \return 0 if interrupt is assigned to Secure
\r
1302 \return 1 if interrupt is assigned to Non Secure
\r
1304 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
\r
1306 return ((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
1311 \brief Set Interrupt Target State
\r
1312 \details Sets the interrupt target field in the NVIC.
\r
1313 \param [in] IRQn External interrupt number. Value cannot be negative.
\r
1314 \return 0 if interrupt is assigned to Secure
\r
1315 1 if interrupt is assigned to Non Secure
\r
1317 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
\r
1319 NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
\r
1320 return ((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
1325 \brief Clear Interrupt Target State
\r
1326 \details Clears the interrupt target field in the NVIC.
\r
1327 \param [in] IRQn External interrupt number. Value cannot be negative.
\r
1328 \return 0 if interrupt is assigned to Secure
\r
1329 1 if interrupt is assigned to Non Secure
\r
1331 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
\r
1333 NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
\r
1334 return ((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
1339 \brief Set Interrupt Priority
\r
1340 \details Sets the priority of an interrupt.
\r
1341 \note The priority cannot be set for every core interrupt.
\r
1342 \param [in] IRQn Interrupt number.
\r
1343 \param [in] priority Priority to set.
\r
1345 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
\r
1347 if ((int32_t)(IRQn) < 0)
\r
1349 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
\r
1350 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
\r
1354 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
\r
1355 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
\r
1361 \brief Get Interrupt Priority
\r
1362 \details Reads the priority of an interrupt.
\r
1363 The interrupt number can be positive to specify an external (device specific) interrupt,
\r
1364 or negative to specify an internal (core) interrupt.
\r
1365 \param [in] IRQn Interrupt number.
\r
1366 \return Interrupt Priority.
\r
1367 Value is aligned automatically to the implemented priority bits of the microcontroller.
\r
1369 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
\r
1372 if ((int32_t)(IRQn) < 0)
\r
1374 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
\r
1378 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
\r
1384 \brief System Reset
\r
1385 \details Initiates a system reset request to reset the MCU.
\r
1387 __STATIC_INLINE void NVIC_SystemReset(void)
\r
1389 __DSB(); /* Ensure all outstanding memory accesses included
\r
1390 buffered write are completed before reset */
\r
1391 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
\r
1392 SCB_AIRCR_SYSRESETREQ_Msk);
\r
1393 __DSB(); /* Ensure completion of memory access */
\r
1395 for(;;) /* wait until reset */
\r
1401 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
\r
1403 \brief Enable External Interrupt (non-secure)
\r
1404 \details Enables a device-specific interrupt in the non-secure NVIC when in secure state.
\r
1405 \param [in] IRQn External interrupt number. Value cannot be negative.
\r
1407 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
\r
1409 NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
\r
1414 \brief Disable External Interrupt (non-secure)
\r
1415 \details Disables a device-specific interrupt in the non-secure NVIC when in secure state.
\r
1416 \param [in] IRQn External interrupt number. Value cannot be negative.
\r
1418 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
\r
1420 NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
\r
1425 \brief Get Pending Interrupt (non-secure)
\r
1426 \details Reads the pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified interrupt.
\r
1427 \param [in] IRQn Interrupt number.
\r
1428 \return 0 Interrupt status is not pending.
\r
1429 \return 1 Interrupt status is pending.
\r
1431 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
\r
1433 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
1438 \brief Set Pending Interrupt (non-secure)
\r
1439 \details Sets the pending bit of an non-secure external interrupt when in secure state.
\r
1440 \param [in] IRQn Interrupt number. Value cannot be negative.
\r
1442 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
\r
1444 NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
\r
1449 \brief Clear Pending Interrupt (non-secure)
\r
1450 \details Clears the pending bit of an non-secure external interrupt when in secure state.
\r
1451 \param [in] IRQn External interrupt number. Value cannot be negative.
\r
1453 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
\r
1455 NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
\r
1460 \brief Get Active Interrupt (non-secure)
\r
1461 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit.
\r
1462 \param [in] IRQn Interrupt number.
\r
1463 \return 0 Interrupt status is not active.
\r
1464 \return 1 Interrupt status is active.
\r
1466 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
\r
1468 return ((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
1473 \brief Get Interrupt Target State (non-secure)
\r
1474 \details Reads the interrupt target field from the non-secure NVIC when in secure state.
\r
1475 \param [in] IRQn External interrupt number. Value cannot be negative.
\r
1476 \return 0 if interrupt is assigned to Secure
\r
1477 \return 1 if interrupt is assigned to Non Secure
\r
1479 __STATIC_INLINE uint32_t TZ_NVIC_GetTargetState_NS(IRQn_Type IRQn)
\r
1481 return ((uint32_t)(((NVIC_NS->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
1486 \brief Set Interrupt Target State (non-secure)
\r
1487 \details Sets the interrupt target field in the non-secure NVIC when in secure state.
\r
1488 \param [in] IRQn External interrupt number. Value cannot be negative.
\r
1489 \return 0 if interrupt is assigned to Secure
\r
1490 \return 1 if interrupt is assigned to Non Secure
\r
1492 __STATIC_INLINE uint32_t TZ_NVIC_SetTargetState_NS(IRQn_Type IRQn)
\r
1494 NVIC_NS->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
\r
1495 return ((uint32_t)(((NVIC_NS->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
1500 \brief Clear Interrupt Target State (non-secure)
\r
1501 \details Clears the interrupt target field in the non-secure NVIC when in secure state.
\r
1502 \param [in] IRQn External interrupt number. Value cannot be negative.
\r
1503 \return 0 if interrupt is assigned to Secure
\r
1504 \return 1 if interrupt is assigned to Non Secure
\r
1506 __STATIC_INLINE uint32_t TZ_NVIC_ClearTargetState_NS(IRQn_Type IRQn)
\r
1508 NVIC_NS->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
\r
1509 return ((uint32_t)(((NVIC_NS->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
\r
1514 \brief Set Interrupt Priority (non-secure)
\r
1515 \details Sets the priority of an non-secure interrupt when in secure state.
\r
1516 \note The priority cannot be set for every core interrupt.
\r
1517 \param [in] IRQn Interrupt number.
\r
1518 \param [in] priority Priority to set.
\r
1520 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
\r
1522 if ((int32_t)(IRQn) < 0)
\r
1524 SCB_NS->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
\r
1525 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
\r
1529 NVIC_NS->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
\r
1530 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
\r
1536 \brief Get Interrupt Priority (non-secure)
\r
1537 \details Reads the priority of an non-secure interrupt when in secure state.
\r
1538 The interrupt number can be positive to specify an external (device specific) interrupt,
\r
1539 or negative to specify an internal (core) interrupt.
\r
1540 \param [in] IRQn Interrupt number.
\r
1541 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
\r
1543 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
\r
1546 if ((int32_t)(IRQn) < 0)
\r
1548 return((uint32_t)(((SCB_NS->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
\r
1552 return((uint32_t)(((NVIC_NS->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
\r
1555 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
\r
1557 /*@} end of CMSIS_Core_NVICFunctions */
\r
1560 /* ########################## FPU functions #################################### */
\r
1562 \ingroup CMSIS_Core_FunctionInterface
\r
1563 \defgroup CMSIS_Core_FpuFunctions FPU Functions
\r
1564 \brief Function that provides FPU type.
\r
1569 \brief get FPU type
\r
1570 \details returns the FPU type
\r
1573 - \b 1: Single precision FPU
\r
1574 - \b 2: Double + Single precision FPU
\r
1576 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
\r
1578 return 0U; /* No FPU */
\r
1582 /*@} end of CMSIS_Core_FpuFunctions */
\r
1586 /* ########################## SAU functions #################################### */
\r
1588 \ingroup CMSIS_Core_FunctionInterface
\r
1589 \defgroup CMSIS_Core_SAUFunctions SAU Functions
\r
1590 \brief Functions that configure the SAU.
\r
1594 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
\r
1598 \details Enables the Security Attribution Unit (SAU).
\r
1600 __STATIC_INLINE void TZ_SAU_Enable(void)
\r
1602 #if defined (__SAU_PRESENT) && (__SAU_PRESENT == 1U)
\r
1603 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
\r
1610 \brief Disable SAU
\r
1611 \details Disables the Security Attribution Unit (SAU).
\r
1613 __STATIC_INLINE void TZ_SAU_Disable(void)
\r
1615 #if defined (__SAU_PRESENT) && (__SAU_PRESENT == 1U)
\r
1616 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
\r
1620 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
\r
1622 /*@} end of CMSIS_Core_SAUFunctions */
\r
1627 /* ################################## SysTick function ############################################ */
\r
1629 \ingroup CMSIS_Core_FunctionInterface
\r
1630 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\r
1631 \brief Functions that configure the System.
\r
1635 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
\r
1638 \brief System Tick Configuration
\r
1639 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
\r
1640 Counter is in free running mode to generate periodic interrupts.
\r
1641 \param [in] ticks Number of ticks between two interrupts.
\r
1642 \return 0 Function succeeded.
\r
1643 \return 1 Function failed.
\r
1644 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
\r
1645 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
\r
1646 must contain a vendor-specific implementation of this function.
\r
1648 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
\r
1650 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
\r
1652 return (1UL); /* Reload value impossible */
\r
1655 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
\r
1656 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
\r
1657 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
\r
1658 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
\r
1659 SysTick_CTRL_TICKINT_Msk |
\r
1660 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
\r
1661 return (0UL); /* Function successful */
\r
1664 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
\r
1666 \brief System Tick Configuration (non-secure)
\r
1667 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
\r
1668 Counter is in free running mode to generate periodic interrupts.
\r
1669 \param [in] ticks Number of ticks between two interrupts.
\r
1670 \return 0 Function succeeded.
\r
1671 \return 1 Function failed.
\r
1672 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
\r
1673 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
\r
1674 must contain a vendor-specific implementation of this function.
\r
1677 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
\r
1679 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
\r
1681 return (1UL); /* Reload value impossible */
\r
1684 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
\r
1685 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
\r
1686 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
\r
1687 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
\r
1688 SysTick_CTRL_TICKINT_Msk |
\r
1689 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
\r
1690 return (0UL); /* Function successful */
\r
1692 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
\r
1696 /*@} end of CMSIS_Core_SysTickFunctions */
\r
1701 #ifdef __cplusplus
\r
1705 #endif /* __CORE_ARMV8MBL_H_DEPENDANT */
\r
1707 #endif /* __CMSIS_GENERIC */
\r
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