2 # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
3 #----------------------------------------------------------------------------------------------
4 cluster.CLUSTER_ID=0x0 # (int , init-time) default = '0x0' : Processor cluster ID value : [0x0..0xF]
5 cluster.dic-spi_count=0x40 # (int , init-time) default = '0x40' : Number of shared peripheral interrupts implemented : [0x0..0x1E0]
6 cluster.CFGSDISABLE=0 # (bool , init-time) default = '0' : Disable some accesses to GIC registers
7 cluster.l1_icache-state_modelled=0 # (bool , run-time ) default = '0' : Set whether L1 I-cache has stateful implementation
8 cluster.l1_dcache-state_modelled=0 # (bool , run-time ) default = '0' : Set whether L1 D-cache has stateful implementation
9 cluster.l2_cache-state_modelled=0 # (bool , run-time ) default = '0' : Set whether L2 cache has stateful implementation
10 cluster.disable_periph_decoder=0 # (bool , init-time) default = '0' :
11 cluster.l2_cache-size=0x80000 # (int , init-time) default = '0x80000' : Set L2 cache size in bytes : [0x0..0x100000]
12 cluster.internal_vgic=1 # (bool , init-time) default = '1' : Configures whether the model of the processor contains a VGIC
13 cluster.cpi_mul=0x1 # (int , run-time ) default = '0x1' : Multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
14 cluster.cpi_div=0x1 # (int , run-time ) default = '0x1' : Divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
15 cluster.l1_icache-hit_latency=0x0 # (int , run-time ) default = '0x0' : L1 I-Cache timing annotation latency for hit. Intended to model the tag-lookup time. This is only used when l1_icache-state_modelled=true.
16 cluster.l1_icache-miss_latency=0x0 # (int , run-time ) default = '0x0' : L1 I-Cache timing annotation latency for miss. Intended to model the time for failed tag-lookup and allocation of intermediate buffers. This is only used when l1_icache-state_modelled=true.
17 cluster.l1_icache-read_latency=0x0 # (int , run-time ) default = '0x0' : L1 I-Cache timing annotation latency for read accesses given in ticks per byte accessed.l1_icache-read_access_latency must be set to 0 for per-byte latencies to be applied. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus. This is only used when l1_icache-state_modelled=true.
18 cluster.l1_icache-read_access_latency=0x0 # (int , run-time ) default = '0x0' : L1 I-Cache timing annotation latency for read accesses given in ticks per access. If this parameter is non-zero, per-access latencies will be used instead of per-byte even if l1_icache-read_latency is set. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus, This is only used when l1_icache-state_modelled=true.
19 cluster.l1_icache-maintenance_latency=0x0 # (int , run-time ) default = '0x0' : L1 I-Cache timing annotation latency for cache maintenance operations given in total ticks. This is only used when l1_icache-state_modelled=true.
20 cluster.l1_dcache-hit_latency=0x0 # (int , run-time ) default = '0x0' : L1 D-Cache timing annotation latency for hit. Intended to model the tag-lookup time. This is only used when l1_dcache-state_modelled=true.
21 cluster.l1_dcache-miss_latency=0x0 # (int , run-time ) default = '0x0' : L1 D-Cache timing annotation latency for miss. Intended to model the time for failed tag-lookup and allocation of intermediate buffers. This is only used when l1_dcache-state_modelled=true.
22 cluster.l1_dcache-read_latency=0x0 # (int , run-time ) default = '0x0' : L1 D-Cache timing annotation latency for read accesses given in ticks per byte accessed.l1_dcache-read_access_latency must be set to 0 for per-byte latencies to be applied. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus. This is only used when l1_dcache-state_modelled=true.
23 cluster.l1_dcache-read_access_latency=0x0 # (int , run-time ) default = '0x0' : L1 D-Cache timing annotation latency for read accesses given in ticks per access. If this parameter is non-zero, per-access latencies will be used instead of per-byte even if l1_dcache-read_latency is set. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus, This is only used when l1_dcache-state_modelled=true.
24 cluster.l1_dcache-write_latency=0x0 # (int , run-time ) default = '0x0' : L1 D-Cache timing annotation latency for write accesses given in ticks per byte accessed. l1_dcache-write_access_latency must be set to 0 for per-byte latencies to be applied. This is only used when l1_dcache-state_modelled=true.
25 cluster.l1_dcache-write_access_latency=0x0 # (int , run-time ) default = '0x0' : L1 D-Cache timing annotation latency for write accesses given in ticks per access. If this parameter is non-zero, per-access latencies will be used instead of per-byte even if l1_dcache-write_latency is set. This is only used when l1_dcache-state_modelled=true.
26 cluster.l1_dcache-maintenance_latency=0x0 # (int , run-time ) default = '0x0' : L1 D-Cache timing annotation latency for cache maintenance operations given in total ticks. This is only used when l1_dcache-state_modelled=true.
27 cluster.l1_dcache-snoop_data_transfer_latency=0x0 # (int , run-time ) default = '0x0' : L1 D-Cache timing annotation latency for received snoop accesses that perfom a data transfer given in ticks per byte accessed. This is only used when l1_dcache-state_modelled=true.
28 cluster.l2_cache-hit_latency=0x0 # (int , run-time ) default = '0x0' : L2 Cache timing annotation latency for hit. Intended to model the tag-lookup time. This is only used when l2_cache-state_modelled=true.
29 cluster.l2_cache-miss_latency=0x0 # (int , run-time ) default = '0x0' : L2 Cache timing annotation latency for miss. Intended to model the time for failed tag-lookup and allocation of intermediate buffers. This is only used when l2_cache-state_modelled=true.
30 cluster.l2_cache-read_latency=0x0 # (int , run-time ) default = '0x0' : L2 Cache timing annotation latency for read accesses given in ticks per byte accessed.l2_cache-read_access_latency must be set to 0 for per-byte latencies to be applied. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus. This is only used when l2_cache-state_modelled=true.
31 cluster.l2_cache-read_access_latency=0x0 # (int , run-time ) default = '0x0' : L2 Cache timing annotation latency for read accesses given in ticks per access. If this parameter is non-zero, per-access latencies will be used instead of per-byte even if l2_cache-read_latency is set. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus, This is only used when l2_cache-state_modelled=true.
32 cluster.l2_cache-write_latency=0x0 # (int , run-time ) default = '0x0' : L2 Cache timing annotation latency for write accesses given in ticks per byte accessed. l2_cache-write_access_latency must be set to 0 for per-byte latencies to be applied. This is only used when l2_cache-state_modelled=true.
33 cluster.l2_cache-write_access_latency=0x0 # (int , run-time ) default = '0x0' : L2 Cache timing annotation latency for write accesses given in ticks per access. If this parameter is non-zero, per-access latencies will be used instead of per-byte even if l2_cache-write_latency is set. This is only used when l2_cache-state_modelled=true.
34 cluster.l2_cache-maintenance_latency=0x0 # (int , run-time ) default = '0x0' : L2 Cache timing annotation latency for cache maintenance operations given in total ticks. This is only used when l2_cache-state_modelled=true.
35 cluster.l2_cache-snoop_data_transfer_latency=0x0 # (int , run-time ) default = '0x0' : L2 Cache timing annotation latency for received snoop accesses that perfom a data transfer given in ticks per byte accessed. This is only used when l2_cache-state_modelled=true.
36 cluster.l2_cache-snoop_issue_latency=0x0 # (int , run-time ) default = '0x0' : L2 Cache timing annotation latency for snoop accesses issued by this cache in total ticks. This is only used when l2_cache-state_modelled=true.
37 cluster.cpu0.vfp-present=1 # (bool , init-time) default = '1' : Set whether CT model has been built with VFP support
38 cluster.cpu0.ase-present=1 # (bool , init-time) default = '1' : Set whether CT model has been built with NEON support
39 cluster.cpu0.CFGEND=0 # (bool , init-time) default = '0' : Initialize to BE8 endianness
40 cluster.cpu0.CP15SDISABLE=0 # (bool , init-time) default = '0' : Initialize to disable access to some CP15 registers
41 cluster.cpu0.TEINIT=0 # (bool , init-time) default = '0' : T32 exception enable. The default has exceptions including reset handled in A32 state
42 cluster.cpu0.VINITHI=0 # (bool , init-time) default = '0' : Initialize with high vectors enabled
43 cluster.cpu0.vfp-enable_at_reset=0 # (bool , init-time) default = '0' : Enable coprocessor access and VFP at reset
44 cluster.cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false
45 cluster.cpu0.semihosting-hlt-enable=0 # (bool , init-time) default = '0' : Enable semihosting HLT traps. Applications that use HLT semihosting must set this parameter to true and the semihosting-enable parameter to true
46 cluster.cpu0.semihosting-ARM_SVC=0x123456 # (int , init-time) default = '0x123456' : ARM SVC number for semihosting : [0x0..0xFFFFFF]
47 cluster.cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : Thumb SVC number for semihosting : [0x0..0xFF]
48 cluster.cpu0.semihosting-ARM_HLT=0xF000 # (int , init-time) default = '0xF000' : ARM HLT number for semihosting : [0x0..0xFFFF]
49 cluster.cpu0.semihosting-Thumb_HLT=0x3C # (int , init-time) default = '0x3C' : Thumb HLT number for semihosting : [0x0..0x3F]
50 cluster.cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls
51 cluster.cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF]
52 cluster.cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0xFF000000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]
53 cluster.cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0xFFFF0000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]
54 cluster.cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0xFF000000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]
55 cluster.cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access.
56 cluster.cpu0.DBGROMADDRV=1 # (bool , init-time) default = '1' : If true this sets bits[1:0] of the CP15 DBGDRAR to indicate that the address is valid
57 cluster.cpu0.DBGROMADDR=0x12000003 # (int , init-time) default = '0x12000003' : This value is used to initialize the CP15 DBGDRAR register. Bits[39:12] of this register specify the ROM table physical address : [0x0..0xFFFFFFFF]
58 cluster.cpu0.DBGSELFADDRV=1 # (bool , init-time) default = '1' : If true this sets bits[1:0] of the CP15 DBGDSAR to indicate that the address is valid
59 cluster.cpu0.DBGSELFADDR=0x10003 # (int , init-time) default = '0x10003' : This value is used to initialize the CP15 DBGDSAR register. Bits[39:17] of this register specify the ROM table physical address : [0x0..0xFFFFFFFF]
60 cluster.cpu0.min_sync_level=0x0 # (int , run-time ) default = '0x0' : Force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
61 cluster.cpu0.l1_dcache-size=0x8000 # (int , init-time) default = '0x8000' : Size of L1 D-cache : [0x2000..0x10000]
62 cluster.cpu0.l1_icache-size=0x8000 # (int , init-time) default = '0x8000' : Size of L1 I-cache : [0x2000..0x10000]
63 globalcounter.non_arch_start_at_default=1 # (bool , init-time) default = '1' : Firmware is expected to enable the timer at boot time. However, turning this parameter on is a model-specific way of enabling the counter module out of reset.
64 globalcounter.base_frequency=0x5F5E100 # (int , init-time) default = '0x5F5E100' : Reset value for CNTFID0, base frequency in Hz
65 globalcounter.use_real_time=0 # (bool , init-time) default = '0' : Update the Generic Timer counter at a real-time base frequency instead of simulator time
66 globalcounter.non_arch_fixed_frequency=0x0 # (int , init-time) default = '0x0' : If set, ignore CNTFID0 and instead use this frequency in Hz
67 globalcounter.cntcidr0123_C=0x0 # (int , init-time) default = '0x0' : Values to be returned for control-frame CIDR registers
68 globalcounter.cntpidr0123_C=0x0 # (int , init-time) default = '0x0' : Values to be returned for control-frame PIDR registers 0-3
69 globalcounter.cntpidr4567_C=0x0 # (int , init-time) default = '0x0' : Values to be returned for control-frame PIDR registers 4-7
70 globalcounter.cntcidr0123_R=0x0 # (int , init-time) default = '0x0' : Values to be returned for read-frame CIDR registers
71 globalcounter.cntpidr0123_R=0x0 # (int , init-time) default = '0x0' : Values to be returned for read-frame PIDR registers 0-3
72 globalcounter.cntpidr4567_R=0x0 # (int , init-time) default = '0x0' : Values to be returned for read-frame PIDR registers 4-7
73 globalcounter.readonly_is_WI=0 # (bool , init-time) default = '0' : Ignore (rather than failing) on writes to read-frame
74 globalcounter.diagnostics=0x0 # (int , init-time) default = '0x0' : Diagnostics : [0x0..0x4]
75 motherboard.proc_id0=0x14000000 # (int , init-time) default = '0x14000000' : Processor ID at CoreTile Express Site 1
76 motherboard.proc_id1=0xFF000000 # (int , init-time) default = '0xFF000000' : Processor ID at CoreTile Express Site 2
77 motherboard.daughter_led_count=0x0 # (int , init-time) default = '0x0' : Number of LEDs that the daughter board has : [0x0..0x20]
78 motherboard.daughter_user_switch_count=0x0 # (int , init-time) default = '0x0' : Number of switches that the daughter board has : [0x0..0x20]
79 motherboard.disable_snooping_dma=0 # (bool , init-time) default = '0' : Disable DMA snooping
80 motherboard.sp805_wdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
81 motherboard.sp810_sysctrl.sysid=0x0 # (int , init-time) default = '0x0' : System Identification Register.
82 motherboard.sp810_sysctrl.use_s8=0 # (bool , init-time) default = '0' : Use Switch 8 (S1-S4)
83 motherboard.pl111_clcd.pixel_double_limit=0x12C # (int , init-time) default = '0x12C' : Minimum LCD pixel width before display will be zoomed
84 motherboard.pl031_rtc.RTCDR_reset_value=0x0 # (int , init-time) default = '0x0' : Reset value for RTCDR
85 motherboard.pl031_rtc.RTCDR_use_current_time=1 # (bool , init-time) default = '1' : Use current Unix/POSIX time for reset value for RTCDR. If true RTCDR_reset_value is ignored
86 motherboard.pl011_uart3.clock_rate=0xE10000 # (int , init-time) default = '0xE10000' : Clock rate for PL011.
87 motherboard.pl011_uart3.baud_rate=0x9600 # (int , init-time) default = '0x9600' : Baud rate.
88 motherboard.pl011_uart3.uart_enable=0 # (bool , init-time) default = '0' : Enable uart when the system starts up. (clock_rate and baud_rate are only valid when this option is enabled.)
89 motherboard.pl011_uart3.untimed_fifos=1 # (bool , init-time) default = '1' : Ignore the clock rate and transmit/receive serial data immediately
90 motherboard.pl011_uart3.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
91 motherboard.pl011_uart3.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
92 motherboard.pl011_uart3.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
93 motherboard.pl011_uart3.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
94 motherboard.pl011_uart3.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
95 motherboard.pl011_uart3.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
96 motherboard.pl011_uart3.enable_dc4=1 # (bool , run-time ) default = '1' : Enable DC4 commands (try echo -e "help:\024" in a Linux shell)
97 motherboard.pl011_uart3.revision="r1p4" # (string, init-time) default = 'r1p4' : Revision to simulate
98 motherboard.pl011_uart2.clock_rate=0xE10000 # (int , init-time) default = '0xE10000' : Clock rate for PL011.
99 motherboard.pl011_uart2.baud_rate=0x9600 # (int , init-time) default = '0x9600' : Baud rate.
100 motherboard.pl011_uart2.uart_enable=0 # (bool , init-time) default = '0' : Enable uart when the system starts up. (clock_rate and baud_rate are only valid when this option is enabled.)
101 motherboard.pl011_uart2.untimed_fifos=1 # (bool , init-time) default = '1' : Ignore the clock rate and transmit/receive serial data immediately
102 motherboard.pl011_uart2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
103 motherboard.pl011_uart2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
104 motherboard.pl011_uart2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
105 motherboard.pl011_uart2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
106 motherboard.pl011_uart2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
107 motherboard.pl011_uart2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
108 motherboard.pl011_uart2.enable_dc4=1 # (bool , run-time ) default = '1' : Enable DC4 commands (try echo -e "help:\024" in a Linux shell)
109 motherboard.pl011_uart2.revision="r1p4" # (string, init-time) default = 'r1p4' : Revision to simulate
110 motherboard.pl011_uart1.clock_rate=0xE10000 # (int , init-time) default = '0xE10000' : Clock rate for PL011.
111 motherboard.pl011_uart1.baud_rate=0x9600 # (int , init-time) default = '0x9600' : Baud rate.
112 motherboard.pl011_uart1.uart_enable=0 # (bool , init-time) default = '0' : Enable uart when the system starts up. (clock_rate and baud_rate are only valid when this option is enabled.)
113 motherboard.pl011_uart1.untimed_fifos=1 # (bool , init-time) default = '1' : Ignore the clock rate and transmit/receive serial data immediately
114 motherboard.pl011_uart1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
115 motherboard.pl011_uart1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
116 motherboard.pl011_uart1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
117 motherboard.pl011_uart1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
118 motherboard.pl011_uart1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
119 motherboard.pl011_uart1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
120 motherboard.pl011_uart1.enable_dc4=1 # (bool , run-time ) default = '1' : Enable DC4 commands (try echo -e "help:\024" in a Linux shell)
121 motherboard.pl011_uart1.revision="r1p4" # (string, init-time) default = 'r1p4' : Revision to simulate
122 motherboard.pl011_uart0.clock_rate=0xE10000 # (int , init-time) default = '0xE10000' : Clock rate for PL011.
123 motherboard.pl011_uart0.baud_rate=0x9600 # (int , init-time) default = '0x9600' : Baud rate.
124 motherboard.pl011_uart0.uart_enable=0 # (bool , init-time) default = '0' : Enable uart when the system starts up. (clock_rate and baud_rate are only valid when this option is enabled.)
125 motherboard.pl011_uart0.untimed_fifos=1 # (bool , init-time) default = '1' : Ignore the clock rate and transmit/receive serial data immediately
126 motherboard.pl011_uart0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
127 motherboard.pl011_uart0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
128 motherboard.pl011_uart0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
129 motherboard.pl011_uart0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
130 motherboard.pl011_uart0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
131 motherboard.pl011_uart0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
132 motherboard.pl011_uart0.enable_dc4=1 # (bool , run-time ) default = '1' : Enable DC4 commands (try echo -e "help:\024" in a Linux shell)
133 motherboard.pl011_uart0.revision="r1p4" # (string, init-time) default = 'r1p4' : Revision to simulate
134 motherboard.pl180_mci.pl180_fifo_depth=0x10 # (int , init-time) default = '0x10' : PL180 FIFO Depth : [0x10..0x200]
135 motherboard.ve_sysregs.user_switches_value=0x0 # (int , init-time) default = '0x0' : User switches
136 motherboard.ve_sysregs.exit_on_shutdown=0 # (bool , init-time) default = '0' : SYS_CFG_SHUTDOWN exits simulation
137 motherboard.ve_sysregs.tilePresent=1 # (bool , init-time) default = '1' : Tile fitted
138 motherboard.ve_sysregs.mmbSiteDefault=0x1 # (int , init-time) default = '0x1' : Default MMB source (0=MB, 1=DB1, 2=DB2) : [0x0..0x2]
139 motherboard.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled
140 motherboard.smsc_91c111.mac_address="00:02:f7:ef:4e:b4" # (string, init-time) default = '00:02:f7:ef:4e:b4' : Host/model MAC address
141 motherboard.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode
142 motherboard.mmc.diagnostics=0x0 # (int , init-time) default = '0x0' : Diagnostics level : [0x0..0x4]
143 motherboard.mmc.p_mmc_file="mmc.dat" # (string, init-time) default = 'mmc.dat' : MMCard filename
144 motherboard.mmc.p_prodName="ARMmmc" # (string, init-time) default = 'ARMmmc' : Card ID Product Name (6 chars)
145 motherboard.mmc.p_prodRev=0x1 # (int , init-time) default = '0x1' : Card ID Product Revision
146 motherboard.mmc.p_manid=0x2 # (int , init-time) default = '0x2' : Card ID Manufacturer ID
147 motherboard.mmc.p_OEMid=0x0 # (int , init-time) default = '0x0' : Card ID OEM ID
148 motherboard.mmc.p_sernum=0xCA4D0001 # (int , init-time) default = '0xCA4D0001' : Card Serial Number
149 motherboard.mmc.p_fast_access=1 # (bool , init-time) default = '1' : Don't simulate MMC block access delays
150 motherboard.mmc.force_sector_addressing=0 # (bool , init-time) default = '0' : Use sector addressing even on small cards
151 motherboard.mmc.card_type="SD" # (string, init-time) default = 'SD' : Card type ('SD' or 'SDHC')
152 motherboard.dummy_usb.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
153 motherboard.dummy_usb.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
154 motherboard.dummy_ram.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
155 motherboard.dummy_ram.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
156 motherboard.dummy_local_dap_rom.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
157 motherboard.dummy_local_dap_rom.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
158 motherboard.psram.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
159 motherboard.psram.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
160 motherboard.vram.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
161 motherboard.vram.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
162 motherboard.flash1.diagnostics=0x0 # (int , init-time) default = '0x0' : Diagnostic level : [0x0..0x4]
163 motherboard.flash1.trapwrite=0 # (bool , init-time) default = '0' : Generate abort on write
164 motherboard.flash1.model_blocklock=0 # (bool , init-time) default = '0' : Model per-block locking
165 motherboard.flash1.unphysical_writes=1 # (bool , init-time) default = '1' : Writes to flash are overwrite not AND
166 motherboard.flash0.diagnostics=0x0 # (int , init-time) default = '0x0' : Diagnostic level : [0x0..0x4]
167 motherboard.flash0.trapwrite=0 # (bool , init-time) default = '0' : Generate abort on write
168 motherboard.flash0.model_blocklock=0 # (bool , init-time) default = '0' : Model per-block locking
169 motherboard.flash0.unphysical_writes=1 # (bool , init-time) default = '1' : Writes to flash are overwrite not AND
170 motherboard.flashloader1.fname="(none)" # (string, init-time) default = '(none)' : Filename (Default '(none)' means: Do not load any file. An empty string will cause a warning.)
171 motherboard.flashloader1.fnameWrite="(none)" # (string, init-time) default = '(none)' : FilenameWrite (Default '(none)' means: Do not save any file. An empty string will cause a warning.)
172 motherboard.flashloader0.fname="(none)" # (string, init-time) default = '(none)' : Filename (Default '(none)' means: Do not load any file. An empty string will cause a warning.)
173 motherboard.flashloader0.fnameWrite="(none)" # (string, init-time) default = '(none)' : FilenameWrite (Default '(none)' means: Do not save any file. An empty string will cause a warning.)
174 motherboard.terminal_0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
175 motherboard.terminal_0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
176 motherboard.terminal_0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
177 motherboard.terminal_0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
178 motherboard.terminal_0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
179 motherboard.terminal_1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
180 motherboard.terminal_1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
181 motherboard.terminal_1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
182 motherboard.terminal_1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
183 motherboard.terminal_1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
184 motherboard.terminal_2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
185 motherboard.terminal_2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
186 motherboard.terminal_2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
187 motherboard.terminal_2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
188 motherboard.terminal_2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
189 motherboard.terminal_3.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
190 motherboard.terminal_3.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
191 motherboard.terminal_3.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
192 motherboard.terminal_3.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
193 motherboard.terminal_3.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
194 motherboard.vis.trap_key=0x4A # (int , init-time) default = '0x4A' : Trap key that works with left Ctrl to toggle mouse display.
195 motherboard.vis.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation.
196 motherboard.vis.disable_visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation
197 motherboard.vis.window_title="Fast Models - CLCD %cpu%" # (string, init-time) default = 'Fast Models - CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name)
198 motherboard.vis.cluster0_name="Cluster0" # (string, init-time) default = 'Cluster0' : Cluster0 name
199 motherboard.vis.cluster1_name="Cluster1" # (string, init-time) default = 'Cluster1' : Cluster1 name
200 motherboard.vis.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls.
201 motherboard.vis.recorder.recordingFileName="" # (string, init-time) default = '' : recording filename (empty string disables recording)
202 motherboard.vis.recorder.playbackFileName="" # (string, init-time) default = '' : playback filename (empty string disables playback)
203 motherboard.vis.recorder.recordingTimeBase=0x5F5E100 # (int , init-time) default = '0x5F5E100' : timebase in 1/s (relative to the master clock (e.g. 100000000 means 10 nanoseconds resolution simulated time for a 1Hz master clock)) to be used for recording (higher values -> higher time resolution, playback time base is always taken from the playback file)
204 motherboard.vis.recorder.verbose=0x0 # (int , run-time ) default = '0x0' : enable verbose messages (1=normal, 2=even more)
205 motherboard.vis.recorder.checkInstructionCount=1 # (bool , run-time ) default = '1' : check instruction count in recording file against actual instruction count during playback
206 motherboard.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface
207 motherboard.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking
208 motherboard.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking
209 motherboard.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking
210 motherboard.vfs2.mount="" # (string, init-time) default = '' : Path to host system folder to make accessible to target OS
211 motherboard.virtioblockdevice.image_path="" # (string, init-time) default = '' : image file path
212 motherboard.virtioblockdevice.read_only=0 # (bool , init-time) default = '0' : Only allow device to be read
213 motherboard.virtioblockdevice.secure_accesses=0 # (bool , init-time) default = '0' : Make device generate transactions with NS=0
214 motherboard.virtioblockdevice.quiet=0 # (bool , init-time) default = '0' : Don't print warnings on malformed commands/descriptors
215 motherboard.virtiop9device.root_path="" # (string, init-time) default = '' : root directory path
216 motherboard.virtiop9device.mount_tag="FM" # (string, init-time) default = 'FM' : mount tag
217 motherboard.virtiop9device.secure_accesses=0 # (bool , init-time) default = '0' : Make device generate transactions with NS=0
218 motherboard.virtiop9device.quiet=0 # (bool , init-time) default = '0' : Don't print warnings on malformed commands/descriptors
219 daughterboard.dram_size=0x4 # (int , init-time) default = '0x4' : Size of main memory in gigabytes (2, 4 or 8) : [0x2..0x8]
220 daughterboard.dram_alias=1 # (bool , init-time) default = '1' : Alias the bottom 2GB region in upper memory
221 daughterboard.secure_memory=0 # (bool , init-time) default = '0' : Support a region of secure memory
222 daughterboard.sram.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
223 daughterboard.sram.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
224 daughterboard.dram.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
225 daughterboard.dram.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
226 daughterboard.dram_aliased.secure=0x1 # (int , run-time ) default = '0x1' : Secure Port
227 daughterboard.dram_aliased.normal=0x2 # (int , run-time ) default = '0x2' : Normal Port
228 daughterboard.dram_limit_4.secure=0x1 # (int , run-time ) default = '0x1' : Secure Port
229 daughterboard.dram_limit_4.normal=0x2 # (int , run-time ) default = '0x2' : Normal Port
230 daughterboard.dram_limit_8.secure=0x1 # (int , run-time ) default = '0x1' : Secure Port
231 daughterboard.dram_limit_8.normal=0x2 # (int , run-time ) default = '0x2' : Normal Port
232 daughterboard.secure_region.secure=0x1 # (int , run-time ) default = '0x1' : Secure Port
233 daughterboard.secure_region.normal=0x2 # (int , run-time ) default = '0x2' : Normal Port
234 daughterboard.nonsecure_region.secure=0x1 # (int , run-time ) default = '0x1' : Secure Port
235 daughterboard.nonsecure_region.normal=0x2 # (int , run-time ) default = '0x2' : Normal Port
236 daughterboard.secureRO.diagnostics=0x0 # (int , init-time) default = '0x0' : Diagnostic level : [0x0..0x4]
237 daughterboard.secureRO.trapwrite=0 # (bool , init-time) default = '0' : Generate abort on write
238 daughterboard.secureRO.model_blocklock=0 # (bool , init-time) default = '0' : Model per-block locking
239 daughterboard.secureRO.unphysical_writes=1 # (bool , init-time) default = '1' : Writes to flash are overwrite not AND
240 daughterboard.secureROloader.fname="(none)" # (string, init-time) default = '(none)' : Filename (Default '(none)' means: Do not load any file. An empty string will cause a warning.)
241 daughterboard.secureROloader.fnameWrite="(none)" # (string, init-time) default = '(none)' : FilenameWrite (Default '(none)' means: Do not save any file. An empty string will cause a warning.)
242 daughterboard.secureSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
243 daughterboard.secureSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
244 daughterboard.secureDRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
245 daughterboard.secureDRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
246 daughterboard.hdlcd.diagnostics=0x0 # (int , init-time) default = '0x0' : Diagnostics level : [0x0..0x4]
247 daughterboard.hdlcd.disable_snooping_dma=0 # (bool , init-time) default = '0' : Disable DMA snooping
248 daughterboard.hdlcd.force_frame_rate=0x32 # (int , init-time) default = '0x32' : Force frame rate to the value of the parameter in frames per simulated second, regardless of the input clock. When 0, use the input clock as a pixel clock : [0x0..0x78]
249 daughterboard.dmc.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
250 daughterboard.dmc.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
251 daughterboard.dmc_phy.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
252 daughterboard.dmc_phy.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
253 daughterboard.exclusive_monitor.enable_component=1 # (bool , init-time) default = '1' : Enable component
254 daughterboard.exclusive_monitor.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
255 daughterboard.exclusive_monitor.match_access_width=0 # (bool , init-time) default = '0' : Fail STREX if not the same access width as LDREX
256 daughterboard.exclusive_monitor.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
257 daughterboard.exclusive_monitor.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
258 daughterboard.exclusive_monitor.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
259 daughterboard.exclusive_monitor.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
260 #----------------------------------------------------------------------------------------------
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