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 127   <div class="headertitle"><div class="title">Device Header File &lt;Device.h&gt; </div></div>
 128 </div><!--header-->
 129 <div class="contents">
 130 <div class="textblock"><p><a class="anchor" id="md_src_core_device_h"></a> The Device Header File contains the following functionalities that are device-specific:</p><ul>
 131 <li><a class="el" href="device_h_pg.html#interrupt_number_sec">Interrupt Number Definition</a> provides interrupt numbers (IRQn) for all exceptions and interrupts of the device.</li>
 132 <li><a class="el" href="device_h_pg.html#core_config_sect">Configuration of the Processor and Core Peripherals</a> reflect the features of the device.</li>
 133 <li><a class="el" href="device_h_pg.html#device_access">Device Peripheral Access Layer</a> provides definitions for the <a class="el" href="group__peripheral__gr.html">Peripheral Access</a> to all device peripherals. It contains all data structures and the address mapping for device-specific peripherals.</li>
 134 <li><b>Access Functions for Peripherals (optional)</b> provide additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device-specific library provided by the silicon vendor.</li>
 135 </ul>
 136 <p><a href="modules.html">API Reference</a> describes the standard features and functions of the <a class="el" href="device_h_pg.html">Device Header File &lt;Device.h&gt;</a> in details.</p>
 137 <h1><a class="anchor" id="interrupt_number_sec"></a>
 138 Interrupt Number Definition</h1>
 139 <p><a class="el" href="device_h_pg.html">Device Header File &lt;Device.h&gt;</a> contains the enumeration <a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> that defines all exceptions and interrupts of the device.</p><ul>
 140 <li>Negative IRQn values represent processor core exceptions (internal interrupts).</li>
 141 <li>Positive IRQn values represent device-specific exceptions (external interrupts). The first device-specific interrupt has the IRQn value 0. The IRQn values needs extension to reflect the device-specific interrupt vector table in the <a class="el" href="startup_c_pg.html">Startup File startup_&lt;Device&gt;.c</a>.</li>
 142 </ul>
 143 <p><b>Example:</b></p>
 144 <p>The following example shows the extension of the interrupt vector table for the LPC1100 device family.</p>
 145 <div class="fragment"><div class="line"><span class="keyword">typedef</span> <span class="keyword">enum</span> IRQn</div>
 146 <div class="line">{</div>
 147 <div class="line"><span class="comment">/******  Cortex-M0 Processor Exceptions Numbers ***************************************************/</span></div>
 148 <div class="line">  <a class="code hl_enumvalue" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ade177d9c70c89e084093024b932a4e30">NonMaskableInt_IRQn</a>           = -14,      </div>
 149 <div class="line">  <a class="code hl_enumvalue" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab1a222a34a32f0ef5ac65e714efc1f85">HardFault_IRQn</a>                = -13,      </div>
 150 <div class="line">  <a class="code hl_enumvalue" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4ce820b3cc6cf3a796b41aadc0cf1237">SVCall_IRQn</a>                   = -5,       </div>
 151 <div class="line">  <a class="code hl_enumvalue" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a03c3cc89984928816d81793fc7bce4a2">PendSV_IRQn</a>                   = -2,       </div>
 152 <div class="line">  <a class="code hl_enumvalue" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7">SysTick_IRQn</a>                  = -1,       </div>
 153 <div class="line"><span class="comment">/******  LPC11xx/LPC11Cxx Specific Interrupt Numbers **********************************************/</span></div>
 154 <div class="line">  WAKEUP0_IRQn                  = 0,        </div>
 155 <div class="line">  WAKEUP1_IRQn                  = 1,        </div>
 156 <div class="line">  WAKEUP2_IRQn                  = 2,</div>
 157 <div class="line">                 :       :</div>
 158 <div class="line">                 :       :</div>
 159 <div class="line">  EINT1_IRQn                    = 30,       </div>
 160 <div class="line">  EINT0_IRQn                    = 31,       </div>
 161 <div class="line">} <a class="code hl_enumeration" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>;</div>
 162 <div class="ttc" id="agroup__NVIC__gr_html_ga7e1129cd8a196f4284d41db3e82ad5c8"><div class="ttname"><a href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a></div><div class="ttdeci">IRQn_Type</div><div class="ttdoc">Definition of IRQn numbers.</div><div class="ttdef"><b>Definition:</b> ref_nvic.txt:385</div></div>
 163 <div class="ttc" id="agroup__NVIC__gr_html_gga7e1129cd8a196f4284d41db3e82ad5c8a03c3cc89984928816d81793fc7bce4a2"><div class="ttname"><a href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a03c3cc89984928816d81793fc7bce4a2">PendSV_IRQn</a></div><div class="ttdeci">@ PendSV_IRQn</div><div class="ttdoc">Exception 14: Pend SV Interrupt [not on Cortex-M0 variants].</div><div class="ttdef"><b>Definition:</b> ref_nvic.txt:397</div></div>
 164 <div class="ttc" id="agroup__NVIC__gr_html_gga7e1129cd8a196f4284d41db3e82ad5c8a4ce820b3cc6cf3a796b41aadc0cf1237"><div class="ttname"><a href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4ce820b3cc6cf3a796b41aadc0cf1237">SVCall_IRQn</a></div><div class="ttdeci">@ SVCall_IRQn</div><div class="ttdoc">Exception 11: SVC Interrupt.</div><div class="ttdef"><b>Definition:</b> ref_nvic.txt:395</div></div>
 165 <div class="ttc" id="agroup__NVIC__gr_html_gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7"><div class="ttname"><a href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7">SysTick_IRQn</a></div><div class="ttdeci">@ SysTick_IRQn</div><div class="ttdoc">Exception 15: System Tick Interrupt.</div><div class="ttdef"><b>Definition:</b> ref_nvic.txt:398</div></div>
 166 <div class="ttc" id="agroup__NVIC__gr_html_gga7e1129cd8a196f4284d41db3e82ad5c8ab1a222a34a32f0ef5ac65e714efc1f85"><div class="ttname"><a href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab1a222a34a32f0ef5ac65e714efc1f85">HardFault_IRQn</a></div><div class="ttdeci">@ HardFault_IRQn</div><div class="ttdoc">Exception 3: Hard Fault Interrupt.</div><div class="ttdef"><b>Definition:</b> ref_nvic.txt:388</div></div>
 167 <div class="ttc" id="agroup__NVIC__gr_html_gga7e1129cd8a196f4284d41db3e82ad5c8ade177d9c70c89e084093024b932a4e30"><div class="ttname"><a href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ade177d9c70c89e084093024b932a4e30">NonMaskableInt_IRQn</a></div><div class="ttdeci">@ NonMaskableInt_IRQn</div><div class="ttdoc">Exception 2: Non Maskable Interrupt.</div><div class="ttdef"><b>Definition:</b> ref_nvic.txt:387</div></div>
 168 </div><!-- fragment --><h1><a class="anchor" id="core_config_sect"></a>
 169 Configuration of the Processor and Core Peripherals</h1>
 170 <p>The <a class="el" href="device_h_pg.html">Device Header File &lt;Device.h&gt;</a> configures the Cortex-M or SecurCore processors and the core peripherals with <code>#define</code> directives that are set prior to including the file <code>core_&lt;cpu&gt;.h</code>.</p>
 171 <p>The following tables list the <em>#defines</em> along with the possible values for each processor core. If these <em>#defines</em> are missing default values are used.</p>
 172 <p><b>Cortex-M0 core</b> (core_cm0.h) </p><table class="cmtable">
 173 <tr>
 174 <th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
 175 <tr>
 176 <td><a class="el" href="group__device__config.html#ga905517438930a3f13cbc632e52990534">__CM0_REV</a> </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number)  </td></tr>
 177 <tr>
 178 <td><a class="el" href="group__device__config.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a> </td><td>2 </td><td>2 </td><td>Number of priority bits implemented in the NVIC (device specific)  </td></tr>
 179 <tr>
 180 <td><a class="el" href="group__device__config.html#gab58771b4ec03f9bdddc84770f7c95c68">__Vendor_SysTickConfig</a> </td><td>0 .. 1 </td><td>0 </td><td>Vendor defined <b>SysTick_Config</b> function.  </td></tr>
 181 </table>
 182 <p><b>Cortex-M0+ core</b> (core_cm0plus.h) </p><table class="cmtable">
 183 <tr>
 184 <th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
 185 <tr>
 186 <td><a class="el" href="group__device__config.html#ga2b7180ed347a0e902c5765deb46e650e">__CM0PLUS_REV</a> </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number)  </td></tr>
 187 <tr>
 188 <td><a class="el" href="group__device__config.html#gaddbae1a1b57539f398eb5546a17de8f6">__VTOR_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if a VTOR register is present or not  </td></tr>
 189 <tr>
 190 <td><a class="el" href="group__device__config.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a> </td><td>2 </td><td>2 </td><td>Number of priority bits implemented in the NVIC (device specific)  </td></tr>
 191 <tr>
 192 <td><a class="el" href="group__device__config.html#gab58771b4ec03f9bdddc84770f7c95c68">__Vendor_SysTickConfig</a> </td><td>0 .. 1 </td><td>0 </td><td>Vendor defined <b>SysTick_Config</b> function.  </td></tr>
 193 </table>
 194 <p><b>Cortex-M3 core</b> (core_cm3.h) </p><table class="cmtable">
 195 <tr>
 196 <th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
 197 <tr>
 198 <td><a class="el" href="group__device__config.html#gac6a3f185c4640e06443c18b3c8d93f53">__CM3_REV</a> </td><td>0x0101 | 0x0200 </td><td>0x0200 </td><td>Core revision number ([15:8] revision number, [7:0] patch number)  </td></tr>
 199 <tr>
 200 <td><a class="el" href="group__device__config.html#gaddbae1a1b57539f398eb5546a17de8f6">__VTOR_PRESENT</a> </td><td>0 .. 1 </td><td>1 </td><td>Defines if a VTOR register is present or not  </td></tr>
 201 <tr>
 202 <td><a class="el" href="group__device__config.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a> </td><td>2 .. 8 </td><td>4 </td><td>Number of priority bits implemented in the NVIC (device specific)  </td></tr>
 203 <tr>
 204 <td><a class="el" href="group__device__config.html#ga4127d1b31aaf336fab3d7329d117f448">__MPU_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not  </td></tr>
 205 <tr>
 206 <td><a class="el" href="group__device__config.html#gab58771b4ec03f9bdddc84770f7c95c68">__Vendor_SysTickConfig</a> </td><td>0 .. 1 </td><td>0 </td><td>Vendor defined <b>SysTick_Config</b> function.  </td></tr>
 207 </table>
 208 <p><b>Cortex-M4 core</b> (core_cm4.h) </p><table class="cmtable">
 209 <tr>
 210 <th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
 211 <tr>
 212 <td><a class="el" href="group__device__config.html#ga45a97e4bb8b6ce7c334acc5f45ace3ba">__CM4_REV</a> </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number)  </td></tr>
 213 <tr>
 214 <td><a class="el" href="group__device__config.html#gaddbae1a1b57539f398eb5546a17de8f6">__VTOR_PRESENT</a> </td><td>0 .. 1 </td><td>1 </td><td>Defines if a VTOR register is present or not  </td></tr>
 215 <tr>
 216 <td><a class="el" href="group__device__config.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a> </td><td>2 .. 8 </td><td>4 </td><td>Number of priority bits implemented in the NVIC (device specific)  </td></tr>
 217 <tr>
 218 <td><a class="el" href="group__device__config.html#ga4127d1b31aaf336fab3d7329d117f448">__MPU_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not  </td></tr>
 219 <tr>
 220 <td><a class="el" href="group__device__config.html#gac1ba8a48ca926bddc88be9bfd7d42641">__FPU_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if a FPU is present or not  </td></tr>
 221 <tr>
 222 <td><a class="el" href="group__device__config.html#gab58771b4ec03f9bdddc84770f7c95c68">__Vendor_SysTickConfig</a> </td><td>0 .. 1 </td><td>0 </td><td>Vendor defined <b>SysTick_Config</b> function.  </td></tr>
 223 </table>
 224 <p><b>Cortex-M7 core</b> (core_cm7.h) </p><table class="cmtable">
 225 <tr>
 226 <th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
 227 <tr>
 228 <td><a class="el" href="group__device__config.html#ga8eb40c0d30a09a0ae388e56b21d8f22c">__CM7_REV</a> </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number)  </td></tr>
 229 <tr>
 230 <td><a class="el" href="group__device__config.html#ga4127d1b31aaf336fab3d7329d117f448">__MPU_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not  </td></tr>
 231 <tr>
 232 <td><a class="el" href="group__device__config.html#gaddbae1a1b57539f398eb5546a17de8f6">__VTOR_PRESENT</a> </td><td>0 .. 1 </td><td>1 </td><td>Defines if a VTOR register is present or not  </td></tr>
 233 <tr>
 234 <td><a class="el" href="group__device__config.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a> </td><td>2 .. 8 </td><td>4 </td><td>Number of priority bits implemented in the NVIC (device specific)  </td></tr>
 235 <tr>
 236 <td><a class="el" href="group__device__config.html#gab58771b4ec03f9bdddc84770f7c95c68">__Vendor_SysTickConfig</a> </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function.   </td></tr>
 237 <tr>
 238 <td><a class="el" href="group__device__config.html#gac1ba8a48ca926bddc88be9bfd7d42641">__FPU_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if a FPU is present or not.  </td></tr>
 239 <tr>
 240 <td><a class="el" href="group__device__config.html#ga2a528de57b6217f9fc9d4487d0db6328">__FPU_DP</a> </td><td>0 .. 1 </td><td>0 </td><td>The combination of the defines <a class="el" href="group__device__config.html#gac1ba8a48ca926bddc88be9bfd7d42641">__FPU_PRESENT</a> and <a class="el" href="group__device__config.html#ga2a528de57b6217f9fc9d4487d0db6328">__FPU_DP</a> determine whether the FPU is with single or double precision.   </td></tr>
 241 <tr>
 242 <td><a class="el" href="group__device__config.html#ga3580fa1aeb7c2ed580904f8f70f8a919">__ICACHE_PRESENT</a> </td><td>0 .. 1 </td><td>1 </td><td>Instruction Chache present or not  </td></tr>
 243 <tr>
 244 <td><a class="el" href="group__device__config.html#ga11d3ac679daeb58d0cec0a4e6ca59010">__DCACHE_PRESENT</a> </td><td>0 .. 1 </td><td>1 </td><td>Data Chache present or not  </td></tr>
 245 <tr>
 246 <td><a class="el" href="group__device__config.html#gacbb998663708df6626abb09378303019">__DTCM_PRESENT</a> </td><td>0 .. 1 </td><td>1 </td><td>Data Tightly Coupled Memory is present or not  </td></tr>
 247 </table>
 248 <p><b>SecurCore SC000 core</b> (core_sc000.h) </p><table class="cmtable">
 249 <tr>
 250 <th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
 251 <tr>
 252 <td><a class="el" href="group__device__config.html#gaf293b060f9c15592d18e6b0b977194bf">__SC000_REV</a> </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number)  </td></tr>
 253 <tr>
 254 <td><a class="el" href="group__device__config.html#gaddbae1a1b57539f398eb5546a17de8f6">__VTOR_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if a VTOR register is present or not  </td></tr>
 255 <tr>
 256 <td><a class="el" href="group__device__config.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a> </td><td>2 </td><td>2 </td><td>Number of priority bits implemented in the NVIC (device specific)  </td></tr>
 257 <tr>
 258 <td><a class="el" href="group__device__config.html#ga4127d1b31aaf336fab3d7329d117f448">__MPU_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not  </td></tr>
 259 <tr>
 260 <td><a class="el" href="group__device__config.html#gab58771b4ec03f9bdddc84770f7c95c68">__Vendor_SysTickConfig</a> </td><td>0 .. 1 </td><td>0 </td><td>Vendor defined <b>SysTick_Config</b> function.  </td></tr>
 261 </table>
 262 <p><b>SecurCore SC300 core</b> (core_sc300.h) </p><table class="cmtable">
 263 <tr>
 264 <th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
 265 <tr>
 266 <td><a class="el" href="group__device__config.html#ga3029728b4fc64727b43bcfd853a7180b">__SC300_REV</a> </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number)  </td></tr>
 267 <tr>
 268 <td><a class="el" href="group__device__config.html#gaddbae1a1b57539f398eb5546a17de8f6">__VTOR_PRESENT</a> </td><td>0 .. 1 </td><td>1 </td><td>Defines if a VTOR register is present or not  </td></tr>
 269 <tr>
 270 <td><a class="el" href="group__device__config.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a> </td><td>2 .. 8 </td><td>4 </td><td>Number of priority bits implemented in the NVIC (device specific)  </td></tr>
 271 <tr>
 272 <td><a class="el" href="group__device__config.html#ga4127d1b31aaf336fab3d7329d117f448">__MPU_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not  </td></tr>
 273 <tr>
 274 <td><a class="el" href="group__device__config.html#gab58771b4ec03f9bdddc84770f7c95c68">__Vendor_SysTickConfig</a> </td><td>0 .. 1 </td><td>0 </td><td>Vendor defined <b>SysTick_Config</b> function.  </td></tr>
 275 </table>
 276 <p><b>Cortex-M23 core, Armv8-M Baseline core</b> (core_cm23.h , core_armv8mbl.h) </p><table class="cmtable">
 277 <tr>
 278 <th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
 279 <tr>
 280 <td><a class="el" href="group__device__config.html#ga645c9be694a2d5b5a5b772a0102c727a">__ARMv8MBL_REV</a> or <a class="el" href="group__device__config.html#ga0f6c2b504ee424a7895fd7a420acdd0e">__CM23_REV</a> </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number)  </td></tr>
 281 <tr>
 282 <td><a class="el" href="group__device__config.html#ga4127d1b31aaf336fab3d7329d117f448">__MPU_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not  </td></tr>
 283 <tr>
 284 <td><a class="el" href="group__device__config.html#gadae9d54c744e525135b097c618bae3c4">__SAUREGION_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if SAU regions are present or not  </td></tr>
 285 <tr>
 286 <td><a class="el" href="group__device__config.html#gaddbae1a1b57539f398eb5546a17de8f6">__VTOR_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if a VTOR register is present or not  </td></tr>
 287 <tr>
 288 <td><a class="el" href="group__device__config.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a> </td><td>2 </td><td>2 </td><td>Number of priority bits implemented in the NVIC (device specific)  </td></tr>
 289 <tr>
 290 <td><a class="el" href="group__device__config.html#gab58771b4ec03f9bdddc84770f7c95c68">__Vendor_SysTickConfig</a> </td><td>0 .. 1 </td><td>0 </td><td>Vendor defined <b>SysTick_Config</b> function.  </td></tr>
 291 </table>
 292 <p><b>Cortex-M33, Cortex-M35P, Armv8-M Mainline core</b> (core_cm33.h, core_cm35p.h, core_armv8mml.h) </p><table class="cmtable">
 293 <tr>
 294 <th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
 295 <tr>
 296 <td><a class="el" href="group__device__config.html#gadb7d425f5ad0389b0eb1c6a69f8eb214">__ARMv8MML_REV</a> or <a class="el" href="group__device__config.html#ga178e7a57b608f3e20d1c0cf18a2c2ac3">__CM33_REV</a> or <a class="el" href="group__device__config.html#gadd339c07b13a763dda6e83f4c05122f6">__CM35P_REV</a> </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number)  </td></tr>
 297 <tr>
 298 <td><a class="el" href="group__device__config.html#ga4127d1b31aaf336fab3d7329d117f448">__MPU_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not  </td></tr>
 299 <tr>
 300 <td><a class="el" href="group__device__config.html#gadae9d54c744e525135b097c618bae3c4">__SAUREGION_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if SAU regions are present or not  </td></tr>
 301 <tr>
 302 <td><a class="el" href="group__device__config.html#gac1ba8a48ca926bddc88be9bfd7d42641">__FPU_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if a FPU is present or not  </td></tr>
 303 <tr>
 304 <td><a class="el" href="group__device__config.html#gaddbae1a1b57539f398eb5546a17de8f6">__VTOR_PRESENT</a> </td><td>0 .. 1 </td><td>1 </td><td>Defines if a VTOR register is present or not  </td></tr>
 305 <tr>
 306 <td><a class="el" href="group__device__config.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a> </td><td>2 .. 8 </td><td>3 </td><td>Number of priority bits implemented in the NVIC (device specific)  </td></tr>
 307 <tr>
 308 <td><a class="el" href="group__device__config.html#gab58771b4ec03f9bdddc84770f7c95c68">__Vendor_SysTickConfig</a> </td><td>0 .. 1 </td><td>0 </td><td>Vendor defined <b>SysTick_Config</b> function.  </td></tr>
 309 </table>
 310 <p><b>Cortex-M55 core, Armv8.1-M Mainline core</b> (core_cm55.h, core_armv81mml.h) </p><table class="cmtable">
 311 <tr>
 312 <th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
 313 <tr>
 314 <td><a class="el" href="group__device__config.html#ga4dd7b69d473733e59cd99fc786174cd3">__ARMv81MML_REV</a> or <a class="el" href="group__device__config.html#gaea2d16e963063038cde86cee33c4ef37">__CM55_REV</a> </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number)  </td></tr>
 315 <tr>
 316 <td><a class="el" href="group__device__config.html#ga4127d1b31aaf336fab3d7329d117f448">__MPU_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not  </td></tr>
 317 <tr>
 318 <td><a class="el" href="group__device__config.html#gadae9d54c744e525135b097c618bae3c4">__SAUREGION_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if SAU regions are present or not  </td></tr>
 319 <tr>
 320 <td><a class="el" href="group__device__config.html#gac1ba8a48ca926bddc88be9bfd7d42641">__FPU_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if a FPU is present or not  </td></tr>
 321 <tr>
 322 <td><a class="el" href="group__device__config.html#ga2a528de57b6217f9fc9d4487d0db6328">__FPU_DP</a> </td><td>0 .. 1 </td><td>0 </td><td>The combination of the defines <a class="el" href="group__device__config.html#gac1ba8a48ca926bddc88be9bfd7d42641">__FPU_PRESENT</a> and <a class="el" href="group__device__config.html#ga2a528de57b6217f9fc9d4487d0db6328">__FPU_DP</a> determine whether the FPU is with single or double precision.   </td></tr>
 323 <tr>
 324 <td><a class="el" href="group__device__config.html#ga3580fa1aeb7c2ed580904f8f70f8a919">__ICACHE_PRESENT</a> </td><td>0 .. 1 </td><td>1 </td><td>Instruction Chache present or not  </td></tr>
 325 <tr>
 326 <td><a class="el" href="group__device__config.html#ga11d3ac679daeb58d0cec0a4e6ca59010">__DCACHE_PRESENT</a> </td><td>0 .. 1 </td><td>1 </td><td>Data Chache present or not  </td></tr>
 327 <tr>
 328 <td><a class="el" href="group__device__config.html#gaddbae1a1b57539f398eb5546a17de8f6">__VTOR_PRESENT</a> </td><td>0 .. 1 </td><td>1 </td><td>Defines if a VTOR register is present or not  </td></tr>
 329 <tr>
 330 <td><a class="el" href="group__device__config.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a> </td><td>2 .. 8 </td><td>3 </td><td>Number of priority bits implemented in the NVIC (device specific)  </td></tr>
 331 <tr>
 332 <td><a class="el" href="group__device__config.html#gab58771b4ec03f9bdddc84770f7c95c68">__Vendor_SysTickConfig</a> </td><td>0 .. 1 </td><td>0 </td><td>Vendor defined <b>SysTick_Config</b> function.  </td></tr>
 333 </table>
 334 <p><b>Cortex-M85 core</b> (core_cm85.h) </p><table class="cmtable">
 335 <tr>
 336 <th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
 337 <tr>
 338 <td><a class="el" href="group__device__config.html#gab1efd620a97f291faa1092e10e693bd3">__CM85_REV</a> </td><td>0x0001 </td><td>0x0001 </td><td>Core revision number ([15:8] revision number, [7:0] patch number)  </td></tr>
 339 <tr>
 340 <td><a class="el" href="group__device__config.html#ga4127d1b31aaf336fab3d7329d117f448">__MPU_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not  </td></tr>
 341 <tr>
 342 <td><a class="el" href="group__device__config.html#gadae9d54c744e525135b097c618bae3c4">__SAUREGION_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if SAU regions are present or not  </td></tr>
 343 <tr>
 344 <td><a class="el" href="group__device__config.html#gac1ba8a48ca926bddc88be9bfd7d42641">__FPU_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if a FPU is present or not  </td></tr>
 345 <tr>
 346 <td><a class="el" href="group__device__config.html#ga2a528de57b6217f9fc9d4487d0db6328">__FPU_DP</a> </td><td>0 .. 1 </td><td>0 </td><td>The combination of the defines <a class="el" href="group__device__config.html#gac1ba8a48ca926bddc88be9bfd7d42641">__FPU_PRESENT</a> and <a class="el" href="group__device__config.html#ga2a528de57b6217f9fc9d4487d0db6328">__FPU_DP</a> determine whether the FPU is with single or double precision.   </td></tr>
 347 <tr>
 348 <td><a class="el" href="group__device__config.html#ga3580fa1aeb7c2ed580904f8f70f8a919">__ICACHE_PRESENT</a> </td><td>0 .. 1 </td><td>1 </td><td>Instruction Chache present or not  </td></tr>
 349 <tr>
 350 <td><a class="el" href="group__device__config.html#ga11d3ac679daeb58d0cec0a4e6ca59010">__DCACHE_PRESENT</a> </td><td>0 .. 1 </td><td>1 </td><td>Data Chache present or not  </td></tr>
 351 <tr>
 352 <td><a class="el" href="group__device__config.html#gaddbae1a1b57539f398eb5546a17de8f6">__VTOR_PRESENT</a> </td><td>0 .. 1 </td><td>1 </td><td>Defines if a VTOR register is present or not  </td></tr>
 353 <tr>
 354 <td><a class="el" href="group__device__config.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a> </td><td>2 .. 8 </td><td>3 </td><td>Number of priority bits implemented in the NVIC (device specific)  </td></tr>
 355 <tr>
 356 <td><a class="el" href="group__device__config.html#gab58771b4ec03f9bdddc84770f7c95c68">__Vendor_SysTickConfig</a> </td><td>0 .. 1 </td><td>0 </td><td>Vendor defined <b>SysTick_Config</b> function.  </td></tr>
 357 </table>
 358 <p><b>Example</b></p>
 359 <p>The following code exemplifies the configuration of the Cortex-M4 Processor and Core Peripherals.</p>
 360 <div class="fragment"><div class="line"><span class="preprocessor">#define __CM4_REV                 0x0001U   </span><span class="comment">/* Core revision r0p1                                 */</span><span class="preprocessor"></span></div>
 361 <div class="line"><span class="preprocessor">#define __MPU_PRESENT             1U        </span><span class="comment">/* MPU present or not                                 */</span><span class="preprocessor"></span></div>
 362 <div class="line"><span class="preprocessor">#define __VTOR_PRESENT            1U        </span><span class="comment">/* VTOR present */</span><span class="preprocessor"></span></div>
 363 <div class="line"><span class="preprocessor">#define __NVIC_PRIO_BITS          3U        </span><span class="comment">/* Number of Bits used for Priority Levels            */</span><span class="preprocessor"></span></div>
 364 <div class="line"><span class="preprocessor">#define __Vendor_SysTickConfig    0U        </span><span class="comment">/* Set to 1 if different SysTick Config is used       */</span><span class="preprocessor"></span></div>
 365 <div class="line"><span class="preprocessor">#define __FPU_PRESENT             1U        </span><span class="comment">/* FPU present or not                                 */</span><span class="preprocessor"></span></div>
 366 <div class="line">.</div>
 367 <div class="line">.</div>
 368 <div class="line"><span class="preprocessor">#include &lt;core_cm4.h&gt;</span>                       <span class="comment">/* Cortex-M4 processor and core peripherals           */</span></div>
 369 <div class="line"><span class="preprocessor">#include &quot;system_&lt;Device&gt;</span>.h<span class="stringliteral">&quot;                /* Device System Header                               */</span></div>
 370 </div><!-- fragment --><h1><a class="anchor" id="device_access"></a>
 371 Device Peripheral Access Layer</h1>
 372 <p>The <a class="el" href="device_h_pg.html">Device Header File &lt;Device.h&gt;</a> contains for each peripheral:</p><ul>
 373 <li>Register Layout Typedef</li>
 374 <li>Base Address</li>
 375 <li>Access Definitions</li>
 376 </ul>
 377 <p>The section <a class="el" href="group__peripheral__gr.html">Peripheral Access</a> shows examples for peripheral definitions.</p>
 378 <h1><a class="anchor" id="device_h_sec"></a>
 379 Device.h Template File</h1>
 380 <p>CMSIS-Core <a class="el" href="cmsis_device_files.html#cmsis_template_files">Device Template Files</a> include <code>Device.h</code> file that can be used as a starting point for chip vendors to implement the device-specific features required in a Device header file as described above. But the may also contain other functions to access device-specific peripherals. </p>
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