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 127   <div class="summary">
 128 <a href="#define-members">Macros</a>  </div>
 129   <div class="headertitle"><div class="title">Peripheral Access</div></div>
 130 </div><!--header-->
 131 <div class="contents">
 132
 133 <p>Naming conventions and optional features for accessing peripherals.
 134 <a href="#details">More...</a></p>
 135 <table class="memberdecls">
 136 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a>
 137 Macros</h2></td></tr>
 138 <tr class="memitem:ga286e3b913dbd236c7f48ea70c8821f4e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a>(field,  value)</td></tr>
 139 <tr class="memdesc:ga286e3b913dbd236c7f48ea70c8821f4e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mask and shift a bit field value for assigning the result to a peripheral register.  <br /></td></tr>
 140 <tr class="separator:ga286e3b913dbd236c7f48ea70c8821f4e"><td class="memSeparator" colspan="2">&#160;</td></tr>
 141 <tr class="memitem:ga139b6e261c981f014f386927ca4a8444"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444">_FLD2VAL</a>(field,  value)</td></tr>
 142 <tr class="memdesc:ga139b6e261c981f014f386927ca4a8444"><td class="mdescLeft">&#160;</td><td class="mdescRight">Extract from a peripheral register value the a bit field value.  <br /></td></tr>
 143 <tr class="separator:ga139b6e261c981f014f386927ca4a8444"><td class="memSeparator" colspan="2">&#160;</td></tr>
 144 </table>
 145 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
 146 <p>Naming conventions and optional features for accessing peripherals. </p>
 147 <p>The section below describes the naming conventions, requirements, and optional features for accessing device specific peripherals. Most of the rules also apply to the core peripherals. The <a class="el" href="device_h_pg.html">Device Header File &lt;Device.h&gt;</a> contains typically these definition and also includes the core specific header files.</p>
 148 <p>The definitions for <a class="el" href="group__peripheral__gr.html">Peripheral Access</a> can be generated using the <a href="https://open-cmsis-pack.github.io/svd-spec/latest/index.html"><b>CMSIS-SVD</b></a> System View Description for Peripherals. Refer to <a href="https://open-cmsis-pack.github.io/svd-spec/latest/svd_SVDConv_pg.html"><b>SVDConv.exe</b></a> for more information. </p>
 149 <p>Each peripheral provides a data type definition with a name that is composed of:</p><ul>
 150 <li>an optional prefix <b>&lt;<em>device abbreviation&gt;</em>_</b></li>
 151 <li><b>&lt;<em>peripheral name</em>&gt;</b></li>
 152 <li>postfix <b>_Type</b> or <b>_TypeDef</b> to identify a type definition.</li>
 153 </ul>
 154 <p>Examples:</p><ul>
 155 <li><b>UART_TypeDef</b> for the peripheral <b>UART</b>.</li>
 156 <li><b>LPC_UART_TypeDef</b> for the device family <b>LPC</b> and the peripheral <b>UART</b>.</li>
 157 </ul>
 158 <p>The data type definition uses standard C data types defined by the ANSI C header file &lt;stdint.h&gt;.</p>
 159 <ul>
 160 <li>IO Type Qualifiers are used to specify the access to peripheral variables. <table class="markdownTable">
 161 <tr class="markdownTableHead">
 162 <th class="markdownTableHeadLeft">IO Type Qualifier   </th><th class="markdownTableHeadLeft">Type   </th><th class="markdownTableHeadLeft">Description    </th></tr>
 163 <tr class="markdownTableRowOdd">
 164 <td class="markdownTableBodyLeft"><b>__IM</b>   </td><td class="markdownTableBodyLeft">Struct member   </td><td class="markdownTableBodyLeft">Defines 'read only' permissions    </td></tr>
 165 <tr class="markdownTableRowEven">
 166 <td class="markdownTableBodyLeft"><b>__OM</b>   </td><td class="markdownTableBodyLeft">Struct member   </td><td class="markdownTableBodyLeft">Defines 'write only' permissions    </td></tr>
 167 <tr class="markdownTableRowOdd">
 168 <td class="markdownTableBodyLeft"><b>__IOM</b>   </td><td class="markdownTableBodyLeft">Struct member   </td><td class="markdownTableBodyLeft">Defines 'read / write' permissions    </td></tr>
 169 <tr class="markdownTableRowEven">
 170 <td class="markdownTableBodyLeft"><b>__I</b>   </td><td class="markdownTableBodyLeft">Scalar variable   </td><td class="markdownTableBodyLeft">Defines 'read only' permissions    </td></tr>
 171 <tr class="markdownTableRowOdd">
 172 <td class="markdownTableBodyLeft"><b>__O</b>   </td><td class="markdownTableBodyLeft">Scalar variable   </td><td class="markdownTableBodyLeft">Defines 'write only' permissions    </td></tr>
 173 <tr class="markdownTableRowEven">
 174 <td class="markdownTableBodyLeft"><b>__IO</b>   </td><td class="markdownTableBodyLeft">Scalar variable   </td><td class="markdownTableBodyLeft">Defines 'read / write' permissions   </td></tr>
 175 </table>
 176 </li>
 177 </ul>
 178 <dl class="section note"><dt>Note</dt><dd><b>__IM</b>, <b>__OM</b>, <b>__IOM</b> are added in CMSIS-Core V4.20 to enhance support for C++. Prior version used <b>__I</b>, <b>__O</b>, <b>__IO</b> also for struct member definitions.</dd></dl>
 179 <p>The typedef <b>&lt;<em>device abbreviation</em>&gt;_UART_TypeDef</b> shown below defines the generic register layout for all UART channels in a device.</p>
 180 <div class="fragment"><div class="line"><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
 181 <div class="line">{</div>
 182 <div class="line">  <span class="keyword">union </span>{</div>
 183 <div class="line">  __IM  uint8_t  RBR;                 <span class="comment">/* Offset: 0x000 (R/ )  Receiver Buffer Register            */</span></div>
 184 <div class="line">  __OM  uint8_t  THR;                 <span class="comment">/* Offset: 0x000 ( /W)  Transmit Holding Register           */</span></div>
 185 <div class="line">  __IOM uint8_t  DLL;                 <span class="comment">/* Offset: 0x000 (R/W)  Divisor Latch LSB                   */</span></div>
 186 <div class="line">        uint32_t RESERVED0;</div>
 187 <div class="line">  };</div>
 188 <div class="line">  <span class="keyword">union </span>{</div>
 189 <div class="line">  __IOM uint8_t  DLM;                 <span class="comment">/* Offset: 0x004 (R/W)  Divisor Latch MSB                   */</span></div>
 190 <div class="line">  __IOM uint32_t IER;                 <span class="comment">/* Offset: 0x004 (R/W)  Interrupt Enable Register           */</span></div>
 191 <div class="line">  };</div>
 192 <div class="line">  <span class="keyword">union </span>{</div>
 193 <div class="line">  __IM  uint32_t IIR;                 <span class="comment">/* Offset: 0x008 (R/ )  Interrupt ID Register               */</span></div>
 194 <div class="line">  __OM  uint8_t  FCR;                 <span class="comment">/* Offset: 0x008 ( /W)  FIFO Control Register               */</span></div>
 195 <div class="line">  };</div>
 196 <div class="line">  __IOM uint8_t  LCR;                 <span class="comment">/* Offset: 0x00C (R/W)  Line Control Register               */</span></div>
 197 <div class="line">        uint8_t  RESERVED1[7];</div>
 198 <div class="line">  __IM  uint8_t  LSR;                 <span class="comment">/* Offset: 0x014 (R/ )  Line Status Register                */</span></div>
 199 <div class="line">        uint8_t  RESERVED2[7];</div>
 200 <div class="line">  __IOM uint8_t  SCR;                 <span class="comment">/* Offset: 0x01C (R/W)  Scratch Pad Register                */</span></div>
 201 <div class="line">        uint8_t  RESERVED3[3];</div>
 202 <div class="line">  __IOM uint32_t ACR;                 <span class="comment">/* Offset: 0x020 (R/W)  Autobaud Control Register           */</span></div>
 203 <div class="line">  __IOM uint8_t  ICR;                 <span class="comment">/* Offset: 0x024 (R/W)  IrDA Control Register               */</span></div>
 204 <div class="line">        uint8_t  RESERVED4[3];</div>
 205 <div class="line">  __IOM uint8_t  FDR;                 <span class="comment">/* Offset: 0x028 (R/W)  Fractional Divider Register         */</span></div>
 206 <div class="line">        uint8_t  RESERVED5[7];</div>
 207 <div class="line">  __IOM uint8_t  TER;                 <span class="comment">/* Offset: 0x030 (R/W)  Transmit Enable Register            */</span></div>
 208 <div class="line">        uint8_t  RESERVED6[39];</div>
 209 <div class="line">  __IM  uint8_t  FIFOLVL;             <span class="comment">/* Offset: 0x058 (R/ )  FIFO Level Register                 */</span></div>
 210 <div class="line">} LPC_UART_TypeDef;</div>
 211 </div><!-- fragment --><p>To access the registers of the UART defined above, pointers to this register structure are defined. If more instances of a peripheral exist, the variables have a postfix (digit or letter) that identifies the peripheral.</p>
 212 <p><b>Example:</b> In this example <b>LPC_UART2</b> and <b>LPC_UART3</b> are two pointers to UARTs defined with above register structure. <br  />
 213 </p><div class="fragment"><div class="line"><span class="preprocessor">#define LPC_UART2             ((LPC_UART_TypeDef      *) LPC_UART2_BASE    )</span></div>
 214 <div class="line"><span class="preprocessor">#define LPC_UART3             ((LPC_UART_TypeDef      *) LPC_UART3_BASE    )</span></div>
 215 </div><!-- fragment --><dl class="section note"><dt>Note</dt><dd><ul>
 216 <li>The prefix <b>LPC</b> is optional.</li>
 217 </ul>
 218 </dd></dl>
 219 <p>The registers in the various UARTs can now be referred in the user code as shown below:<br  />
 220 </p><div class="fragment"><div class="line">val = LPC_UART2-&gt;DR   <span class="comment">// is the data register of UART1.</span></div>
 221 </div><!-- fragment --><hr  />
 222 <h1><a class="anchor" id="core_cmsis_pal_min_reqs"></a>
 223 Minimal Requirements</h1>
 224 <p>To access the peripheral registers and related function in a device, the files <b><em>device.h</em></b> and <b>core_cm<em>#</em>.h</b> define as a minimum: <br  />
 225 <br  />
 226 </p><ul>
 227 <li>The <b>Register Layout Typedef</b> for each peripheral that defines all register names. RESERVED is used to introduce space into the structure for adjusting the addresses of the peripheral registers. <br  />
 228 <br  />
 229 <b>Example:</b> <div class="fragment"><div class="line"><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
 230 <div class="line">{</div>
 231 <div class="line">  __IOM uint32_t CTRL;                <span class="comment">/* Offset: 0x000 (R/W)  SysTick Control and Status Register */</span></div>
 232 <div class="line">  __IOM uint32_t LOAD;                <span class="comment">/* Offset: 0x004 (R/W)  SysTick Reload Value Register       */</span></div>
 233 <div class="line">  __IOM uint32_t VAL;                 <span class="comment">/* Offset: 0x008 (R/W)  SysTick Current Value Register      */</span></div>
 234 <div class="line">  __IM  uint32_t CALIB;               <span class="comment">/* Offset: 0x00C (R/ )  SysTick Calibration Register        */</span></div>
 235 <div class="line">} <a class="code hl_struct" href="structSysTick__Type.html">SysTick_Type</a>;</div>
 236 <div class="ttc" id="astructSysTick__Type_html"><div class="ttname"><a href="structSysTick__Type.html">SysTick_Type</a></div><div class="ttdoc">Structure type to access the System Timer (SysTick).</div><div class="ttdef"><b>Definition:</b> ref_data_structs.txt:164</div></div>
 237 </div><!-- fragment --></li>
 238 <li><b>Base Address</b> for each peripheral (in case of multiple peripherals that use the same <b>register layout typedef</b> multiple base addresses are defined). <br  />
 239 <br  />
 240 <b>Example:</b> <div class="fragment"><div class="line"><span class="preprocessor">#define SysTick_BASE (SCS_BASE + 0x0010)            </span><span class="comment">/* SysTick Base Address     */</span><span class="preprocessor"></span></div>
 241 </div><!-- fragment --></li>
 242 <li><b>Access Definitions</b> for each peripheral. In case of multiple peripherals that are using the same <b>register layout typdef</b>, multiple access definitions exist (LPC_UART0, LPC_UART2). <br  />
 243 <br  />
 244 <b>Example:</b> <div class="fragment"><div class="line"><span class="preprocessor">#define SysTick ((SysTick_Type *) Systick_BASE)    </span><span class="comment">/* SysTick access definition */</span><span class="preprocessor"></span></div>
 245 </div><!-- fragment --></li>
 246 </ul>
 247 <p>These definitions allow accessing peripheral registers with simple assignments.</p>
 248 <ul>
 249 <li><b>Example:</b> <br  />
 250 <div class="fragment"><div class="line">SysTick-&gt;CTRL = 0;</div>
 251 </div><!-- fragment --></li>
 252 </ul>
 253 <hr  />
 254 <h1><a class="anchor" id="core_cmsis_pal_opts"></a>
 255 Optional Features</h1>
 256 <p>Optionally, the file <b><em>device</em>.h</b> may define:</p>
 257 <ul>
 258 <li><a class="el" href="group__peripheral__gr.html#core_cmsis_pal_bitfields">Register Bit Fields</a> and #define constants that simplify access to peripheral registers. These constants may define bit-positions or other specific patterns that are required for programming peripheral registers. The identifiers should start with <b>&lt;<em>device abbreviation</em>&gt;_</b> and <b>&lt;<em>peripheral name</em>&gt;_</b>. It is recommended to use CAPITAL letters for #define constants.</li>
 259 <li>More complex functions (i.e. status query before a sending register is accessed). Again, these functions start with <b>&lt;<em>device abbreviation</em>&gt;_</b> and <b>&lt;<em>peripheral name</em>&gt;_</b>.</li>
 260 </ul>
 261 <hr  />
 262 <h1><a class="anchor" id="core_cmsis_pal_bitfields"></a>
 263 Register Bit Fields</h1>
 264 <p>For Core Register, macros define the position and the mask value for a bit field. It is recommended to create such definitions also for other peripheral registers.</p>
 265 <p><b>Example:</b></p>
 266 <p>Bit field definitions for register CPUID in SCB (System Control Block).</p>
 267 <div class="fragment"><div class="line"><span class="comment">/* SCB CPUID Register Definitions */</span></div>
 268 <div class="line"><span class="preprocessor">#define SCB_CPUID_IMPLEMENTER_Pos      24U                                       </span></div>
 269 <div class="line"><span class="preprocessor">#define SCB_CPUID_IMPLEMENTER_Msk      (0xFFUL &lt;&lt; SCB_CPUID_IMPLEMENTER_Pos)     </span></div>
 270 <div class="line"><span class="preprocessor">#define SCB_CPUID_VARIANT_Pos          20U                                       </span></div>
 271 <div class="line"><span class="preprocessor">#define SCB_CPUID_VARIANT_Msk          (0xFUL &lt;&lt; SCB_CPUID_VARIANT_Pos)          </span></div>
 272 <div class="line"><span class="preprocessor">#define SCB_CPUID_ARCHITECTURE_Pos     16U                                       </span></div>
 273 <div class="line"><span class="preprocessor">#define SCB_CPUID_ARCHITECTURE_Msk     (0xFUL &lt;&lt; SCB_CPUID_ARCHITECTURE_Pos)     </span></div>
 274 <div class="line"><span class="preprocessor">#define SCB_CPUID_PARTNO_Pos            4U                                       </span></div>
 275 <div class="line"><span class="preprocessor">#define SCB_CPUID_PARTNO_Msk           (0xFFFUL &lt;&lt; SCB_CPUID_PARTNO_Pos)         </span></div>
 276 <div class="line"><span class="preprocessor">#define SCB_CPUID_REVISION_Pos          0U                                       </span></div>
 277 <div class="line"><span class="preprocessor">#define SCB_CPUID_REVISION_Msk         (0xFUL </span><span class="comment">/*&lt;&lt; SCB_CPUID_REVISION_Pos*/</span><span class="preprocessor">)     </span></div>
 278 </div><!-- fragment --><p>The macros <b><a class="el" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e" title="Mask and shift a bit field value for assigning the result to a peripheral register.">_VAL2FLD(field, value)</a></b> and <b><a class="el" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444" title="Extract from a peripheral register value the a bit field value.">_FLD2VAL(field, value)</a></b> enable access to bit fields. </p>
 279 <h2 class="groupheader">Macro Definition Documentation</h2>
 280 <a id="ga139b6e261c981f014f386927ca4a8444" name="ga139b6e261c981f014f386927ca4a8444"></a>
 281 <h2 class="memtitle"><span class="permalink"><a href="#ga139b6e261c981f014f386927ca4a8444">&#9670;&#160;</a></span>_FLD2VAL</h2>
 282
 283 <div class="memitem">
 284 <div class="memproto">
 285       <table class="memname">
 286         <tr>
 287           <td class="memname">#define _FLD2VAL</td>
 288           <td>(</td>
 289           <td class="paramtype">&#160;</td>
 290           <td class="paramname">field, </td>
 291         </tr>
 292         <tr>
 293           <td class="paramkey"></td>
 294           <td></td>
 295           <td class="paramtype">&#160;</td>
 296           <td class="paramname">value&#160;</td>
 297         </tr>
 298         <tr>
 299           <td></td>
 300           <td>)</td>
 301           <td></td><td></td>
 302         </tr>
 303       </table>
 304 </div><div class="memdoc">
 305
 306 <p>Extract from a peripheral register value the a bit field value. </p>
 307 <dl class="params"><dt>Parameters</dt><dd>
 308   <table class="params">
 309     <tr><td class="paramname">field</td><td>name of bit field. </td></tr>
 310     <tr><td class="paramname">value</td><td>value of the register. This parameter is interpreted as an uint32_t type.</td></tr>
 311   </table>
 312   </dd>
 313 </dl>
 314 <p>The macro <a class="el" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444">_FLD2VAL</a> uses the #define's <em>_Pos</em> and <em>_Msk</em> of the related bit field to extract the value of a bit field from a register.</p>
 315 <p><b>Example:</b> </p><div class="fragment"><div class="line"><span class="keywordtype">id</span> = <a class="code hl_define" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444">_FLD2VAL</a>(SCB_CPUID_REVISION, SCB-&gt;CPUID);</div>
 316 <div class="ttc" id="agroup__peripheral__gr_html_ga139b6e261c981f014f386927ca4a8444"><div class="ttname"><a href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444">_FLD2VAL</a></div><div class="ttdeci">#define _FLD2VAL(field, value)</div><div class="ttdoc">Extract from a peripheral register value the a bit field value.</div><div class="ttdef"><b>Definition:</b> ref_peripheral.txt:226</div></div>
 317 </div><!-- fragment -->
 318 </div>
 319 </div>
 320 <a id="ga286e3b913dbd236c7f48ea70c8821f4e" name="ga286e3b913dbd236c7f48ea70c8821f4e"></a>
 321 <h2 class="memtitle"><span class="permalink"><a href="#ga286e3b913dbd236c7f48ea70c8821f4e">&#9670;&#160;</a></span>_VAL2FLD</h2>
 322
 323 <div class="memitem">
 324 <div class="memproto">
 325       <table class="memname">
 326         <tr>
 327           <td class="memname">#define _VAL2FLD</td>
 328           <td>(</td>
 329           <td class="paramtype">&#160;</td>
 330           <td class="paramname">field, </td>
 331         </tr>
 332         <tr>
 333           <td class="paramkey"></td>
 334           <td></td>
 335           <td class="paramtype">&#160;</td>
 336           <td class="paramname">value&#160;</td>
 337         </tr>
 338         <tr>
 339           <td></td>
 340           <td>)</td>
 341           <td></td><td></td>
 342         </tr>
 343       </table>
 344 </div><div class="memdoc">
 345
 346 <p>Mask and shift a bit field value for assigning the result to a peripheral register. </p>
 347 <dl class="params"><dt>Parameters</dt><dd>
 348   <table class="params">
 349     <tr><td class="paramname">field</td><td>name of bit field. </td></tr>
 350     <tr><td class="paramname">value</td><td>value for the bit field. This parameter is interpreted as an uint32_t type.</td></tr>
 351   </table>
 352   </dd>
 353 </dl>
 354 <p>The macro <a class="el" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a> uses the #define's <em>_Pos</em> and <em>_Msk</em> of the related bit field to shift bit-field values for assigning to a register.</p>
 355 <p><b>Example:</b> </p><div class="fragment"><div class="line">SCB-&gt;CPUID = <a class="code hl_define" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a>(SCB_CPUID_REVISION, 0x3) | <a class="code hl_define" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a>(SCB_CPUID_VARIANT, 0x3);</div>
 356 <div class="ttc" id="agroup__peripheral__gr_html_ga286e3b913dbd236c7f48ea70c8821f4e"><div class="ttname"><a href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a></div><div class="ttdeci">#define _VAL2FLD(field, value)</div><div class="ttdoc">Mask and shift a bit field value for assigning the result to a peripheral register.</div><div class="ttdef"><b>Definition:</b> ref_peripheral.txt:209</div></div>
 357 </div><!-- fragment -->
 358 </div>
 359 </div>
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