begriffs open source - cmsis/blob - main/Core_A/html/group__CMSIS__CPSR__M.html

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  46    <div id="projectname">CMSIS-Core (Cortex-A)
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  55    <div id="projectbrief">CMSIS-Core support for Cortex-A processor-based devices</div>
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 129 <div class="header">
 130   <div class="summary">
 131 <a href="#define-members">Macros</a>  </div>
 132   <div class="headertitle"><div class="title">CPSR M field values<div class="ingroups"><a class="el" href="group__CMSIS__core__register.html">Core Register Access</a> &raquo; <a class="el" href="group__CMSIS__CPSR.html">Current Program Status Register (CPSR)</a></div></div></div>
 133 </div><!--header-->
 134 <div class="contents">
 135
 136 <p>Valid values for CPSR M field.
 137 <a href="#details">More...</a></p>
 138 <table class="memberdecls">
 139 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a>
 140 Macros</h2></td></tr>
 141 <tr class="memitem:gad716a0ee4dc815f0f01e1339d6511a4e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#gad716a0ee4dc815f0f01e1339d6511a4e">CPSR_M_USR</a>&#160;&#160;&#160;0x10U</td></tr>
 142 <tr class="memdesc:gad716a0ee4dc815f0f01e1339d6511a4e"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPSR: M User mode (PL0)  <br /></td></tr>
 143 <tr class="separator:gad716a0ee4dc815f0f01e1339d6511a4e"><td class="memSeparator" colspan="2">&#160;</td></tr>
 144 <tr class="memitem:ga868ef12e003f541f90a613ca7f6ada74"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#ga868ef12e003f541f90a613ca7f6ada74">CPSR_M_FIQ</a>&#160;&#160;&#160;0x11U</td></tr>
 145 <tr class="memdesc:ga868ef12e003f541f90a613ca7f6ada74"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPSR: M Fast Interrupt mode (PL1)  <br /></td></tr>
 146 <tr class="separator:ga868ef12e003f541f90a613ca7f6ada74"><td class="memSeparator" colspan="2">&#160;</td></tr>
 147 <tr class="memitem:gada3f31a773f7fc7bf6567d598cf3a1db"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#gada3f31a773f7fc7bf6567d598cf3a1db">CPSR_M_IRQ</a>&#160;&#160;&#160;0x12U</td></tr>
 148 <tr class="memdesc:gada3f31a773f7fc7bf6567d598cf3a1db"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPSR: M Interrupt mode (PL1)  <br /></td></tr>
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 151 <tr class="memdesc:ga5afcb85bd2968acc2b09cb9d99c531ad"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPSR: M Supervisor mode (PL1)  <br /></td></tr>
 152 <tr class="separator:ga5afcb85bd2968acc2b09cb9d99c531ad"><td class="memSeparator" colspan="2">&#160;</td></tr>
 153 <tr class="memitem:ga69d734db93f67899b4bffcf62f80f098"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#ga69d734db93f67899b4bffcf62f80f098">CPSR_M_MON</a>&#160;&#160;&#160;0x16U</td></tr>
 154 <tr class="memdesc:ga69d734db93f67899b4bffcf62f80f098"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPSR: M Monitor mode (PL1)  <br /></td></tr>
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 156 <tr class="memitem:gac8c0a99a21ef256f5d3115595a845bfa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#gac8c0a99a21ef256f5d3115595a845bfa">CPSR_M_ABT</a>&#160;&#160;&#160;0x17U</td></tr>
 157 <tr class="memdesc:gac8c0a99a21ef256f5d3115595a845bfa"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPSR: M Abort mode (PL1)  <br /></td></tr>
 158 <tr class="separator:gac8c0a99a21ef256f5d3115595a845bfa"><td class="memSeparator" colspan="2">&#160;</td></tr>
 159 <tr class="memitem:ga002c78f542ca5c5fdd02d2aeee9f6988"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#ga002c78f542ca5c5fdd02d2aeee9f6988">CPSR_M_HYP</a>&#160;&#160;&#160;0x1AU</td></tr>
 160 <tr class="memdesc:ga002c78f542ca5c5fdd02d2aeee9f6988"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPSR: M Hypervisor mode (PL2)  <br /></td></tr>
 161 <tr class="separator:ga002c78f542ca5c5fdd02d2aeee9f6988"><td class="memSeparator" colspan="2">&#160;</td></tr>
 162 <tr class="memitem:ga07d4f42d6971c2f0cc25872008ddf5ef"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#ga07d4f42d6971c2f0cc25872008ddf5ef">CPSR_M_UND</a>&#160;&#160;&#160;0x1BU</td></tr>
 163 <tr class="memdesc:ga07d4f42d6971c2f0cc25872008ddf5ef"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPSR: M Undefined mode (PL1)  <br /></td></tr>
 164 <tr class="separator:ga07d4f42d6971c2f0cc25872008ddf5ef"><td class="memSeparator" colspan="2">&#160;</td></tr>
 165 <tr class="memitem:gaa0a3996ce096cd205bce34f90b10912c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#gaa0a3996ce096cd205bce34f90b10912c">CPSR_M_SYS</a>&#160;&#160;&#160;0x1FU</td></tr>
 166 <tr class="memdesc:gaa0a3996ce096cd205bce34f90b10912c"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPSR: M System mode (PL1)  <br /></td></tr>
 167 <tr class="separator:gaa0a3996ce096cd205bce34f90b10912c"><td class="memSeparator" colspan="2">&#160;</td></tr>
 168 </table>
 169 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
 170 <p>The M field can contain one of these values which indicates the current processor mode. </p>
 171 <h2 class="groupheader">Macro Definition Documentation</h2>
 172 <a id="gac8c0a99a21ef256f5d3115595a845bfa" name="gac8c0a99a21ef256f5d3115595a845bfa"></a>
 173 <h2 class="memtitle"><span class="permalink"><a href="#gac8c0a99a21ef256f5d3115595a845bfa">&#9670;&#160;</a></span>CPSR_M_ABT</h2>
 174
 175 <div class="memitem">
 176 <div class="memproto">
 177       <table class="memname">
 178         <tr>
 179           <td class="memname">#define CPSR_M_ABT&#160;&#160;&#160;0x17U</td>
 180         </tr>
 181       </table>
 182 </div><div class="memdoc">
 183 <p>Abort mode is the default mode to which a Data Abort exception or Prefetch Abort exception is taken. </p>
 184
 185 </div>
 186 </div>
 187 <a id="ga868ef12e003f541f90a613ca7f6ada74" name="ga868ef12e003f541f90a613ca7f6ada74"></a>
 188 <h2 class="memtitle"><span class="permalink"><a href="#ga868ef12e003f541f90a613ca7f6ada74">&#9670;&#160;</a></span>CPSR_M_FIQ</h2>
 189
 190 <div class="memitem">
 191 <div class="memproto">
 192       <table class="memname">
 193         <tr>
 194           <td class="memname">#define CPSR_M_FIQ&#160;&#160;&#160;0x11U</td>
 195         </tr>
 196       </table>
 197 </div><div class="memdoc">
 198 <p>FIQ mode is the default mode to which an FIQ interrupt is taken. </p>
 199
 200 </div>
 201 </div>
 202 <a id="ga002c78f542ca5c5fdd02d2aeee9f6988" name="ga002c78f542ca5c5fdd02d2aeee9f6988"></a>
 203 <h2 class="memtitle"><span class="permalink"><a href="#ga002c78f542ca5c5fdd02d2aeee9f6988">&#9670;&#160;</a></span>CPSR_M_HYP</h2>
 204
 205 <div class="memitem">
 206 <div class="memproto">
 207       <table class="memname">
 208         <tr>
 209           <td class="memname">#define CPSR_M_HYP&#160;&#160;&#160;0x1AU</td>
 210         </tr>
 211       </table>
 212 </div><div class="memdoc">
 213 <p>Hyp mode is the Non-secure PL2 mode, implemented as part of the Virtualization Extensions. Hyp mode is entered on taking an exception from Non-secure state that must be taken to PL2. </p>
 214
 215 </div>
 216 </div>
 217 <a id="gada3f31a773f7fc7bf6567d598cf3a1db" name="gada3f31a773f7fc7bf6567d598cf3a1db"></a>
 218 <h2 class="memtitle"><span class="permalink"><a href="#gada3f31a773f7fc7bf6567d598cf3a1db">&#9670;&#160;</a></span>CPSR_M_IRQ</h2>
 219
 220 <div class="memitem">
 221 <div class="memproto">
 222       <table class="memname">
 223         <tr>
 224           <td class="memname">#define CPSR_M_IRQ&#160;&#160;&#160;0x12U</td>
 225         </tr>
 226       </table>
 227 </div><div class="memdoc">
 228 <p>IRQ mode is the default mode to which an IRQ interrupt is taken. </p>
 229
 230 </div>
 231 </div>
 232 <a id="ga69d734db93f67899b4bffcf62f80f098" name="ga69d734db93f67899b4bffcf62f80f098"></a>
 233 <h2 class="memtitle"><span class="permalink"><a href="#ga69d734db93f67899b4bffcf62f80f098">&#9670;&#160;</a></span>CPSR_M_MON</h2>
 234
 235 <div class="memitem">
 236 <div class="memproto">
 237       <table class="memname">
 238         <tr>
 239           <td class="memname">#define CPSR_M_MON&#160;&#160;&#160;0x16U</td>
 240         </tr>
 241       </table>
 242 </div><div class="memdoc">
 243 <p>Monitor mode is the mode to which a Secure Monitor Call exception is taken. </p>
 244
 245 </div>
 246 </div>
 247 <a id="ga5afcb85bd2968acc2b09cb9d99c531ad" name="ga5afcb85bd2968acc2b09cb9d99c531ad"></a>
 248 <h2 class="memtitle"><span class="permalink"><a href="#ga5afcb85bd2968acc2b09cb9d99c531ad">&#9670;&#160;</a></span>CPSR_M_SVC</h2>
 249
 250 <div class="memitem">
 251 <div class="memproto">
 252       <table class="memname">
 253         <tr>
 254           <td class="memname">#define CPSR_M_SVC&#160;&#160;&#160;0x13U</td>
 255         </tr>
 256       </table>
 257 </div><div class="memdoc">
 258 <p>Supervisor mode is the default mode to which a Supervisor Call exception is taken. </p>
 259
 260 </div>
 261 </div>
 262 <a id="gaa0a3996ce096cd205bce34f90b10912c" name="gaa0a3996ce096cd205bce34f90b10912c"></a>
 263 <h2 class="memtitle"><span class="permalink"><a href="#gaa0a3996ce096cd205bce34f90b10912c">&#9670;&#160;</a></span>CPSR_M_SYS</h2>
 264
 265 <div class="memitem">
 266 <div class="memproto">
 267       <table class="memname">
 268         <tr>
 269           <td class="memname">#define CPSR_M_SYS&#160;&#160;&#160;0x1FU</td>
 270         </tr>
 271       </table>
 272 </div><div class="memdoc">
 273 <p>Software executing in System mode executes at PL1. System mode has the same registers available as User mode, and is not entered by any exception. </p>
 274
 275 </div>
 276 </div>
 277 <a id="ga07d4f42d6971c2f0cc25872008ddf5ef" name="ga07d4f42d6971c2f0cc25872008ddf5ef"></a>
 278 <h2 class="memtitle"><span class="permalink"><a href="#ga07d4f42d6971c2f0cc25872008ddf5ef">&#9670;&#160;</a></span>CPSR_M_UND</h2>
 279
 280 <div class="memitem">
 281 <div class="memproto">
 282       <table class="memname">
 283         <tr>
 284           <td class="memname">#define CPSR_M_UND&#160;&#160;&#160;0x1BU</td>
 285         </tr>
 286       </table>
 287 </div><div class="memdoc">
 288 <p>Undefined mode is the default mode to which an instruction-related exception, including any attempt to execute an UNDEFINED instruction, is taken. </p>
 289
 290 </div>
 291 </div>
 292 <a id="gad716a0ee4dc815f0f01e1339d6511a4e" name="gad716a0ee4dc815f0f01e1339d6511a4e"></a>
 293 <h2 class="memtitle"><span class="permalink"><a href="#gad716a0ee4dc815f0f01e1339d6511a4e">&#9670;&#160;</a></span>CPSR_M_USR</h2>
 294
 295 <div class="memitem">
 296 <div class="memproto">
 297       <table class="memname">
 298         <tr>
 299           <td class="memname">#define CPSR_M_USR&#160;&#160;&#160;0x10U</td>
 300         </tr>
 301       </table>
 302 </div><div class="memdoc">
 303 <p>An operating system runs applications in User mode to restrict the use of system resources. Software executing in User mode executes at PL0. Execution in User mode is sometimes described as unprivileged execution. </p>
 304
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