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46 <div id="projectname">CMSIS-Core (Cortex-A)
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55 <div id="projectbrief">CMSIS-Core support for Cortex-A processor-based devices</div>
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130 <div class="summary">
131 <a href="#define-members">Macros</a> </div>
132 <div class="headertitle"><div class="title">SCTLR Bits<div class="ingroups"><a class="el" href="group__CMSIS__core__register.html">Core Register Access</a> » <a class="el" href="group__CMSIS__SCTLR.html">System Control Register (SCTLR)</a></div></div></div>
134 <div class="contents">
136 <p>Bit position and mask macros.
137 <a href="#details">More...</a></p>
138 <table class="memberdecls">
139 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a>
140 Macros</h2></td></tr>
141 <tr class="memitem:gab0a611e2359e04624379e1ddd4dc64b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gab0a611e2359e04624379e1ddd4dc64b1">SCTLR_TE_Pos</a>   30U</td></tr>
142 <tr class="memdesc:gab0a611e2359e04624379e1ddd4dc64b1"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: TE Position. <br /></td></tr>
143 <tr class="separator:gab0a611e2359e04624379e1ddd4dc64b1"><td class="memSeparator" colspan="2"> </td></tr>
144 <tr class="memitem:ga4a68d6660c76951ada2541ceaf040b3b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga4a68d6660c76951ada2541ceaf040b3b">SCTLR_TE_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gab0a611e2359e04624379e1ddd4dc64b1">SCTLR_TE_Pos</a>)</td></tr>
145 <tr class="memdesc:ga4a68d6660c76951ada2541ceaf040b3b"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: TE Mask. <br /></td></tr>
146 <tr class="separator:ga4a68d6660c76951ada2541ceaf040b3b"><td class="memSeparator" colspan="2"> </td></tr>
147 <tr class="memitem:ga4ac80ef4db2641dc9e6e8df0825a151e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga4ac80ef4db2641dc9e6e8df0825a151e">SCTLR_AFE_Pos</a>   29U</td></tr>
148 <tr class="memdesc:ga4ac80ef4db2641dc9e6e8df0825a151e"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: AFE Position. <br /></td></tr>
149 <tr class="separator:ga4ac80ef4db2641dc9e6e8df0825a151e"><td class="memSeparator" colspan="2"> </td></tr>
150 <tr class="memitem:ga9016d6e50562d2584c1f1a95bde1e957"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga9016d6e50562d2584c1f1a95bde1e957">SCTLR_AFE_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga4ac80ef4db2641dc9e6e8df0825a151e">SCTLR_AFE_Pos</a>)</td></tr>
151 <tr class="memdesc:ga9016d6e50562d2584c1f1a95bde1e957"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: AFE Mask. <br /></td></tr>
152 <tr class="separator:ga9016d6e50562d2584c1f1a95bde1e957"><td class="memSeparator" colspan="2"> </td></tr>
153 <tr class="memitem:gaf76fa48119363f9b88c2c8f5b74e0a04"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gaf76fa48119363f9b88c2c8f5b74e0a04">SCTLR_TRE_Pos</a>   28U</td></tr>
154 <tr class="memdesc:gaf76fa48119363f9b88c2c8f5b74e0a04"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: TRE Position. <br /></td></tr>
155 <tr class="separator:gaf76fa48119363f9b88c2c8f5b74e0a04"><td class="memSeparator" colspan="2"> </td></tr>
156 <tr class="memitem:gab0481eb9812a4908601cb20c8ae84918"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gab0481eb9812a4908601cb20c8ae84918">SCTLR_TRE_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gaf76fa48119363f9b88c2c8f5b74e0a04">SCTLR_TRE_Pos</a>)</td></tr>
157 <tr class="memdesc:gab0481eb9812a4908601cb20c8ae84918"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: TRE Mask. <br /></td></tr>
158 <tr class="separator:gab0481eb9812a4908601cb20c8ae84918"><td class="memSeparator" colspan="2"> </td></tr>
159 <tr class="memitem:gac1cf872c51ed0baa6ed23e26c1ed35a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gac1cf872c51ed0baa6ed23e26c1ed35a9">SCTLR_NMFI_Pos</a>   27U</td></tr>
160 <tr class="memdesc:gac1cf872c51ed0baa6ed23e26c1ed35a9"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: NMFI Position. <br /></td></tr>
161 <tr class="separator:gac1cf872c51ed0baa6ed23e26c1ed35a9"><td class="memSeparator" colspan="2"> </td></tr>
162 <tr class="memitem:gab92a3bd63ad9ac3d408e1b615bedc279"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gab92a3bd63ad9ac3d408e1b615bedc279">SCTLR_NMFI_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gac1cf872c51ed0baa6ed23e26c1ed35a9">SCTLR_NMFI_Pos</a>)</td></tr>
163 <tr class="memdesc:gab92a3bd63ad9ac3d408e1b615bedc279"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: NMFI Mask. <br /></td></tr>
164 <tr class="separator:gab92a3bd63ad9ac3d408e1b615bedc279"><td class="memSeparator" colspan="2"> </td></tr>
165 <tr class="memitem:ga0baec19421bd41277c5d8783c59942fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga0baec19421bd41277c5d8783c59942fa">SCTLR_EE_Pos</a>   25U</td></tr>
166 <tr class="memdesc:ga0baec19421bd41277c5d8783c59942fa"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: EE Position. <br /></td></tr>
167 <tr class="separator:ga0baec19421bd41277c5d8783c59942fa"><td class="memSeparator" colspan="2"> </td></tr>
168 <tr class="memitem:ga8d95cd61bc40dc77f8855f40c797d044"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga8d95cd61bc40dc77f8855f40c797d044">SCTLR_EE_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga0baec19421bd41277c5d8783c59942fa">SCTLR_EE_Pos</a>)</td></tr>
169 <tr class="memdesc:ga8d95cd61bc40dc77f8855f40c797d044"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: EE Mask. <br /></td></tr>
170 <tr class="separator:ga8d95cd61bc40dc77f8855f40c797d044"><td class="memSeparator" colspan="2"> </td></tr>
171 <tr class="memitem:ga1372b569553a0740d881e24c0be7334f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga1372b569553a0740d881e24c0be7334f">SCTLR_VE_Pos</a>   24U</td></tr>
172 <tr class="memdesc:ga1372b569553a0740d881e24c0be7334f"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: VE Position. <br /></td></tr>
173 <tr class="separator:ga1372b569553a0740d881e24c0be7334f"><td class="memSeparator" colspan="2"> </td></tr>
174 <tr class="memitem:gad94a7feadba850299a68c56e39c0b274"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gad94a7feadba850299a68c56e39c0b274">SCTLR_VE_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga1372b569553a0740d881e24c0be7334f">SCTLR_VE_Pos</a>)</td></tr>
175 <tr class="memdesc:gad94a7feadba850299a68c56e39c0b274"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: VE Mask. <br /></td></tr>
176 <tr class="separator:gad94a7feadba850299a68c56e39c0b274"><td class="memSeparator" colspan="2"> </td></tr>
177 <tr class="memitem:gaa0431730d7ce929db03d8accee558e17"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gaa0431730d7ce929db03d8accee558e17">SCTLR_U_Pos</a>   22U</td></tr>
178 <tr class="memdesc:gaa0431730d7ce929db03d8accee558e17"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: U Position. <br /></td></tr>
179 <tr class="separator:gaa0431730d7ce929db03d8accee558e17"><td class="memSeparator" colspan="2"> </td></tr>
180 <tr class="memitem:gaa047daa7ab35b5ad5dd238c7377a232f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gaa047daa7ab35b5ad5dd238c7377a232f">SCTLR_U_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gaa0431730d7ce929db03d8accee558e17">SCTLR_U_Pos</a>)</td></tr>
181 <tr class="memdesc:gaa047daa7ab35b5ad5dd238c7377a232f"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: U Mask. <br /></td></tr>
182 <tr class="separator:gaa047daa7ab35b5ad5dd238c7377a232f"><td class="memSeparator" colspan="2"> </td></tr>
183 <tr class="memitem:gad88d563fa9a8b09fe36702a5329b0360"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gad88d563fa9a8b09fe36702a5329b0360">SCTLR_FI_Pos</a>   21U</td></tr>
184 <tr class="memdesc:gad88d563fa9a8b09fe36702a5329b0360"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: FI Position. <br /></td></tr>
185 <tr class="separator:gad88d563fa9a8b09fe36702a5329b0360"><td class="memSeparator" colspan="2"> </td></tr>
186 <tr class="memitem:ga316b80925b88fe3b88ec46a55655b0bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga316b80925b88fe3b88ec46a55655b0bc">SCTLR_FI_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gad88d563fa9a8b09fe36702a5329b0360">SCTLR_FI_Pos</a>)</td></tr>
187 <tr class="memdesc:ga316b80925b88fe3b88ec46a55655b0bc"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: FI Mask. <br /></td></tr>
188 <tr class="separator:ga316b80925b88fe3b88ec46a55655b0bc"><td class="memSeparator" colspan="2"> </td></tr>
189 <tr class="memitem:ga7c7d88f3db4de438ddd069cf3fbc88b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga7c7d88f3db4de438ddd069cf3fbc88b3">SCTLR_UWXN_Pos</a>   20U</td></tr>
190 <tr class="memdesc:ga7c7d88f3db4de438ddd069cf3fbc88b3"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: UWXN Position. <br /></td></tr>
191 <tr class="separator:ga7c7d88f3db4de438ddd069cf3fbc88b3"><td class="memSeparator" colspan="2"> </td></tr>
192 <tr class="memitem:gab834e64e0da7c2a98d747ce73252c199"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gab834e64e0da7c2a98d747ce73252c199">SCTLR_UWXN_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga7c7d88f3db4de438ddd069cf3fbc88b3">SCTLR_UWXN_Pos</a>)</td></tr>
193 <tr class="memdesc:gab834e64e0da7c2a98d747ce73252c199"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: UWXN Mask. <br /></td></tr>
194 <tr class="separator:gab834e64e0da7c2a98d747ce73252c199"><td class="memSeparator" colspan="2"> </td></tr>
195 <tr class="memitem:gaf145654986fd6d014136580ad279d256"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gaf145654986fd6d014136580ad279d256">SCTLR_WXN_Pos</a>   19U</td></tr>
196 <tr class="memdesc:gaf145654986fd6d014136580ad279d256"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: WXN Position. <br /></td></tr>
197 <tr class="separator:gaf145654986fd6d014136580ad279d256"><td class="memSeparator" colspan="2"> </td></tr>
198 <tr class="memitem:ga510b03214d135f15ad3c5d41ec20a291"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga510b03214d135f15ad3c5d41ec20a291">SCTLR_WXN_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gaf145654986fd6d014136580ad279d256">SCTLR_WXN_Pos</a>)</td></tr>
199 <tr class="memdesc:ga510b03214d135f15ad3c5d41ec20a291"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: WXN Mask. <br /></td></tr>
200 <tr class="separator:ga510b03214d135f15ad3c5d41ec20a291"><td class="memSeparator" colspan="2"> </td></tr>
201 <tr class="memitem:ga316882abba6c9cdd31dbbd7ba46c9f52"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga316882abba6c9cdd31dbbd7ba46c9f52">SCTLR_HA_Pos</a>   17U</td></tr>
202 <tr class="memdesc:ga316882abba6c9cdd31dbbd7ba46c9f52"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: HA Position. <br /></td></tr>
203 <tr class="separator:ga316882abba6c9cdd31dbbd7ba46c9f52"><td class="memSeparator" colspan="2"> </td></tr>
204 <tr class="memitem:ga6830e9bf54a6b548f329ac047f59c179"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga6830e9bf54a6b548f329ac047f59c179">SCTLR_HA_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga316882abba6c9cdd31dbbd7ba46c9f52">SCTLR_HA_Pos</a>)</td></tr>
205 <tr class="memdesc:ga6830e9bf54a6b548f329ac047f59c179"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: HA Mask. <br /></td></tr>
206 <tr class="separator:ga6830e9bf54a6b548f329ac047f59c179"><td class="memSeparator" colspan="2"> </td></tr>
207 <tr class="memitem:ga86e5b78ba8f818061644688db75ddc64"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga86e5b78ba8f818061644688db75ddc64">SCTLR_RR_Pos</a>   14U</td></tr>
208 <tr class="memdesc:ga86e5b78ba8f818061644688db75ddc64"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: RR Position. <br /></td></tr>
209 <tr class="separator:ga86e5b78ba8f818061644688db75ddc64"><td class="memSeparator" colspan="2"> </td></tr>
210 <tr class="memitem:ga1ff9e6766c7e1ca312b025bf34d384bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga1ff9e6766c7e1ca312b025bf34d384bc">SCTLR_RR_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga86e5b78ba8f818061644688db75ddc64">SCTLR_RR_Pos</a>)</td></tr>
211 <tr class="memdesc:ga1ff9e6766c7e1ca312b025bf34d384bc"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: RR Mask. <br /></td></tr>
212 <tr class="separator:ga1ff9e6766c7e1ca312b025bf34d384bc"><td class="memSeparator" colspan="2"> </td></tr>
213 <tr class="memitem:ga57778fd6afbe5b4fe8d8ea828acf833d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga57778fd6afbe5b4fe8d8ea828acf833d">SCTLR_V_Pos</a>   13U</td></tr>
214 <tr class="memdesc:ga57778fd6afbe5b4fe8d8ea828acf833d"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: V Position. <br /></td></tr>
215 <tr class="separator:ga57778fd6afbe5b4fe8d8ea828acf833d"><td class="memSeparator" colspan="2"> </td></tr>
216 <tr class="memitem:gaf84f3f15bf6917acdc5b5a4ad661ac11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gaf84f3f15bf6917acdc5b5a4ad661ac11">SCTLR_V_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga57778fd6afbe5b4fe8d8ea828acf833d">SCTLR_V_Pos</a>)</td></tr>
217 <tr class="memdesc:gaf84f3f15bf6917acdc5b5a4ad661ac11"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: V Mask. <br /></td></tr>
218 <tr class="separator:gaf84f3f15bf6917acdc5b5a4ad661ac11"><td class="memSeparator" colspan="2"> </td></tr>
219 <tr class="memitem:gaaaa818a1da51059bd979f0e768ebcc7c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gaaaa818a1da51059bd979f0e768ebcc7c">SCTLR_I_Pos</a>   12U</td></tr>
220 <tr class="memdesc:gaaaa818a1da51059bd979f0e768ebcc7c"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: I Position. <br /></td></tr>
221 <tr class="separator:gaaaa818a1da51059bd979f0e768ebcc7c"><td class="memSeparator" colspan="2"> </td></tr>
222 <tr class="memitem:gab3cc0744fb07127e3c0f18cba9d51666"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gab3cc0744fb07127e3c0f18cba9d51666">SCTLR_I_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gaaaa818a1da51059bd979f0e768ebcc7c">SCTLR_I_Pos</a>)</td></tr>
223 <tr class="memdesc:gab3cc0744fb07127e3c0f18cba9d51666"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: I Mask. <br /></td></tr>
224 <tr class="separator:gab3cc0744fb07127e3c0f18cba9d51666"><td class="memSeparator" colspan="2"> </td></tr>
225 <tr class="memitem:gaa0eade648c9a34de891af0e6f47857dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gaa0eade648c9a34de891af0e6f47857dd">SCTLR_Z_Pos</a>   11U</td></tr>
226 <tr class="memdesc:gaa0eade648c9a34de891af0e6f47857dd"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: Z Position. <br /></td></tr>
227 <tr class="separator:gaa0eade648c9a34de891af0e6f47857dd"><td class="memSeparator" colspan="2"> </td></tr>
228 <tr class="memitem:ga12a05acdcb8db6e99970f26206d3067c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga12a05acdcb8db6e99970f26206d3067c">SCTLR_Z_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gaa0eade648c9a34de891af0e6f47857dd">SCTLR_Z_Pos</a>)</td></tr>
229 <tr class="memdesc:ga12a05acdcb8db6e99970f26206d3067c"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: Z Mask. <br /></td></tr>
230 <tr class="separator:ga12a05acdcb8db6e99970f26206d3067c"><td class="memSeparator" colspan="2"> </td></tr>
231 <tr class="memitem:ga3290be0882c1493bca9a0db6b4d0bff8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga3290be0882c1493bca9a0db6b4d0bff8">SCTLR_SW_Pos</a>   10U</td></tr>
232 <tr class="memdesc:ga3290be0882c1493bca9a0db6b4d0bff8"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: SW Position. <br /></td></tr>
233 <tr class="separator:ga3290be0882c1493bca9a0db6b4d0bff8"><td class="memSeparator" colspan="2"> </td></tr>
234 <tr class="memitem:gae4074aefcf01786fe199c82e273271b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gae4074aefcf01786fe199c82e273271b8">SCTLR_SW_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga3290be0882c1493bca9a0db6b4d0bff8">SCTLR_SW_Pos</a>)</td></tr>
235 <tr class="memdesc:gae4074aefcf01786fe199c82e273271b8"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: SW Mask. <br /></td></tr>
236 <tr class="separator:gae4074aefcf01786fe199c82e273271b8"><td class="memSeparator" colspan="2"> </td></tr>
237 <tr class="memitem:ga5f185efbe1a9eb5738b2573f076a0859"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga5f185efbe1a9eb5738b2573f076a0859">SCTLR_B_Pos</a>   7U</td></tr>
238 <tr class="memdesc:ga5f185efbe1a9eb5738b2573f076a0859"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: B Position. <br /></td></tr>
239 <tr class="separator:ga5f185efbe1a9eb5738b2573f076a0859"><td class="memSeparator" colspan="2"> </td></tr>
240 <tr class="memitem:ga4853d6f9ccbf919fcdadb0b2a5913cc6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga4853d6f9ccbf919fcdadb0b2a5913cc6">SCTLR_B_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga5f185efbe1a9eb5738b2573f076a0859">SCTLR_B_Pos</a>)</td></tr>
241 <tr class="memdesc:ga4853d6f9ccbf919fcdadb0b2a5913cc6"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: B Mask. <br /></td></tr>
242 <tr class="separator:ga4853d6f9ccbf919fcdadb0b2a5913cc6"><td class="memSeparator" colspan="2"> </td></tr>
243 <tr class="memitem:gace284f69e1a810957665adf0cb2e4b2b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gace284f69e1a810957665adf0cb2e4b2b">SCTLR_CP15BEN_Pos</a>   5U</td></tr>
244 <tr class="memdesc:gace284f69e1a810957665adf0cb2e4b2b"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: CP15BEN Position. <br /></td></tr>
245 <tr class="separator:gace284f69e1a810957665adf0cb2e4b2b"><td class="memSeparator" colspan="2"> </td></tr>
246 <tr class="memitem:ga5541a6a63db4d4d233b8f57b1d46fbac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga5541a6a63db4d4d233b8f57b1d46fbac">SCTLR_CP15BEN_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gace284f69e1a810957665adf0cb2e4b2b">SCTLR_CP15BEN_Pos</a>)</td></tr>
247 <tr class="memdesc:ga5541a6a63db4d4d233b8f57b1d46fbac"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: CP15BEN Mask. <br /></td></tr>
248 <tr class="separator:ga5541a6a63db4d4d233b8f57b1d46fbac"><td class="memSeparator" colspan="2"> </td></tr>
249 <tr class="memitem:ga8a0394c5147b8212767087e3421deffa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga8a0394c5147b8212767087e3421deffa">SCTLR_C_Pos</a>   2U</td></tr>
250 <tr class="memdesc:ga8a0394c5147b8212767087e3421deffa"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: C Position. <br /></td></tr>
251 <tr class="separator:ga8a0394c5147b8212767087e3421deffa"><td class="memSeparator" colspan="2"> </td></tr>
252 <tr class="memitem:ga2be72788d984153ded81711e20fd2d33"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga2be72788d984153ded81711e20fd2d33">SCTLR_C_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga8a0394c5147b8212767087e3421deffa">SCTLR_C_Pos</a>)</td></tr>
253 <tr class="memdesc:ga2be72788d984153ded81711e20fd2d33"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: C Mask. <br /></td></tr>
254 <tr class="separator:ga2be72788d984153ded81711e20fd2d33"><td class="memSeparator" colspan="2"> </td></tr>
255 <tr class="memitem:ga0d667a307e974515ebc15b5249f34146"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga0d667a307e974515ebc15b5249f34146">SCTLR_A_Pos</a>   1U</td></tr>
256 <tr class="memdesc:ga0d667a307e974515ebc15b5249f34146"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: A Position. <br /></td></tr>
257 <tr class="separator:ga0d667a307e974515ebc15b5249f34146"><td class="memSeparator" colspan="2"> </td></tr>
258 <tr class="memitem:ga678c919832272745678213e55211e741"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga678c919832272745678213e55211e741">SCTLR_A_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga0d667a307e974515ebc15b5249f34146">SCTLR_A_Pos</a>)</td></tr>
259 <tr class="memdesc:ga678c919832272745678213e55211e741"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: A Mask. <br /></td></tr>
260 <tr class="separator:ga678c919832272745678213e55211e741"><td class="memSeparator" colspan="2"> </td></tr>
261 <tr class="memitem:ga88e34078fa8cf719aab6f53f138c9810"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga88e34078fa8cf719aab6f53f138c9810">SCTLR_M_Pos</a>   0U</td></tr>
262 <tr class="memdesc:ga88e34078fa8cf719aab6f53f138c9810"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: M Position. <br /></td></tr>
263 <tr class="separator:ga88e34078fa8cf719aab6f53f138c9810"><td class="memSeparator" colspan="2"> </td></tr>
264 <tr class="memitem:gaf460824cdbf549bd914aa79762572e8e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gaf460824cdbf549bd914aa79762572e8e">SCTLR_M_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga88e34078fa8cf719aab6f53f138c9810">SCTLR_M_Pos</a>)</td></tr>
265 <tr class="memdesc:gaf460824cdbf549bd914aa79762572e8e"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: M Mask. <br /></td></tr>
266 <tr class="separator:gaf460824cdbf549bd914aa79762572e8e"><td class="memSeparator" colspan="2"> </td></tr>
268 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
269 <p>Bit position and mask macros. </p>
270 <h2 class="groupheader">Macro Definition Documentation</h2>
271 <a id="ga678c919832272745678213e55211e741" name="ga678c919832272745678213e55211e741"></a>
272 <h2 class="memtitle"><span class="permalink"><a href="#ga678c919832272745678213e55211e741">◆ </a></span>SCTLR_A_Msk</h2>
274 <div class="memitem">
275 <div class="memproto">
276 <table class="memname">
278 <td class="memname">#define SCTLR_A_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga0d667a307e974515ebc15b5249f34146">SCTLR_A_Pos</a>)</td>
281 </div><div class="memdoc">
283 <p>SCTLR: A Mask. </p>
287 <a id="ga0d667a307e974515ebc15b5249f34146" name="ga0d667a307e974515ebc15b5249f34146"></a>
288 <h2 class="memtitle"><span class="permalink"><a href="#ga0d667a307e974515ebc15b5249f34146">◆ </a></span>SCTLR_A_Pos</h2>
290 <div class="memitem">
291 <div class="memproto">
292 <table class="memname">
294 <td class="memname">#define SCTLR_A_Pos   1U</td>
297 </div><div class="memdoc">
299 <p>SCTLR: A Position. </p>
303 <a id="ga9016d6e50562d2584c1f1a95bde1e957" name="ga9016d6e50562d2584c1f1a95bde1e957"></a>
304 <h2 class="memtitle"><span class="permalink"><a href="#ga9016d6e50562d2584c1f1a95bde1e957">◆ </a></span>SCTLR_AFE_Msk</h2>
306 <div class="memitem">
307 <div class="memproto">
308 <table class="memname">
310 <td class="memname">#define SCTLR_AFE_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga4ac80ef4db2641dc9e6e8df0825a151e">SCTLR_AFE_Pos</a>)</td>
313 </div><div class="memdoc">
315 <p>SCTLR: AFE Mask. </p>
319 <a id="ga4ac80ef4db2641dc9e6e8df0825a151e" name="ga4ac80ef4db2641dc9e6e8df0825a151e"></a>
320 <h2 class="memtitle"><span class="permalink"><a href="#ga4ac80ef4db2641dc9e6e8df0825a151e">◆ </a></span>SCTLR_AFE_Pos</h2>
322 <div class="memitem">
323 <div class="memproto">
324 <table class="memname">
326 <td class="memname">#define SCTLR_AFE_Pos   29U</td>
329 </div><div class="memdoc">
331 <p>SCTLR: AFE Position. </p>
335 <a id="ga4853d6f9ccbf919fcdadb0b2a5913cc6" name="ga4853d6f9ccbf919fcdadb0b2a5913cc6"></a>
336 <h2 class="memtitle"><span class="permalink"><a href="#ga4853d6f9ccbf919fcdadb0b2a5913cc6">◆ </a></span>SCTLR_B_Msk</h2>
338 <div class="memitem">
339 <div class="memproto">
340 <table class="memname">
342 <td class="memname">#define SCTLR_B_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga5f185efbe1a9eb5738b2573f076a0859">SCTLR_B_Pos</a>)</td>
345 </div><div class="memdoc">
347 <p>SCTLR: B Mask. </p>
351 <a id="ga5f185efbe1a9eb5738b2573f076a0859" name="ga5f185efbe1a9eb5738b2573f076a0859"></a>
352 <h2 class="memtitle"><span class="permalink"><a href="#ga5f185efbe1a9eb5738b2573f076a0859">◆ </a></span>SCTLR_B_Pos</h2>
354 <div class="memitem">
355 <div class="memproto">
356 <table class="memname">
358 <td class="memname">#define SCTLR_B_Pos   7U</td>
361 </div><div class="memdoc">
363 <p>SCTLR: B Position. </p>
367 <a id="ga2be72788d984153ded81711e20fd2d33" name="ga2be72788d984153ded81711e20fd2d33"></a>
368 <h2 class="memtitle"><span class="permalink"><a href="#ga2be72788d984153ded81711e20fd2d33">◆ </a></span>SCTLR_C_Msk</h2>
370 <div class="memitem">
371 <div class="memproto">
372 <table class="memname">
374 <td class="memname">#define SCTLR_C_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga8a0394c5147b8212767087e3421deffa">SCTLR_C_Pos</a>)</td>
377 </div><div class="memdoc">
379 <p>SCTLR: C Mask. </p>
383 <a id="ga8a0394c5147b8212767087e3421deffa" name="ga8a0394c5147b8212767087e3421deffa"></a>
384 <h2 class="memtitle"><span class="permalink"><a href="#ga8a0394c5147b8212767087e3421deffa">◆ </a></span>SCTLR_C_Pos</h2>
386 <div class="memitem">
387 <div class="memproto">
388 <table class="memname">
390 <td class="memname">#define SCTLR_C_Pos   2U</td>
393 </div><div class="memdoc">
395 <p>SCTLR: C Position. </p>
399 <a id="ga5541a6a63db4d4d233b8f57b1d46fbac" name="ga5541a6a63db4d4d233b8f57b1d46fbac"></a>
400 <h2 class="memtitle"><span class="permalink"><a href="#ga5541a6a63db4d4d233b8f57b1d46fbac">◆ </a></span>SCTLR_CP15BEN_Msk</h2>
402 <div class="memitem">
403 <div class="memproto">
404 <table class="memname">
406 <td class="memname">#define SCTLR_CP15BEN_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gace284f69e1a810957665adf0cb2e4b2b">SCTLR_CP15BEN_Pos</a>)</td>
409 </div><div class="memdoc">
411 <p>SCTLR: CP15BEN Mask. </p>
415 <a id="gace284f69e1a810957665adf0cb2e4b2b" name="gace284f69e1a810957665adf0cb2e4b2b"></a>
416 <h2 class="memtitle"><span class="permalink"><a href="#gace284f69e1a810957665adf0cb2e4b2b">◆ </a></span>SCTLR_CP15BEN_Pos</h2>
418 <div class="memitem">
419 <div class="memproto">
420 <table class="memname">
422 <td class="memname">#define SCTLR_CP15BEN_Pos   5U</td>
425 </div><div class="memdoc">
427 <p>SCTLR: CP15BEN Position. </p>
431 <a id="ga8d95cd61bc40dc77f8855f40c797d044" name="ga8d95cd61bc40dc77f8855f40c797d044"></a>
432 <h2 class="memtitle"><span class="permalink"><a href="#ga8d95cd61bc40dc77f8855f40c797d044">◆ </a></span>SCTLR_EE_Msk</h2>
434 <div class="memitem">
435 <div class="memproto">
436 <table class="memname">
438 <td class="memname">#define SCTLR_EE_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga0baec19421bd41277c5d8783c59942fa">SCTLR_EE_Pos</a>)</td>
441 </div><div class="memdoc">
443 <p>SCTLR: EE Mask. </p>
447 <a id="ga0baec19421bd41277c5d8783c59942fa" name="ga0baec19421bd41277c5d8783c59942fa"></a>
448 <h2 class="memtitle"><span class="permalink"><a href="#ga0baec19421bd41277c5d8783c59942fa">◆ </a></span>SCTLR_EE_Pos</h2>
450 <div class="memitem">
451 <div class="memproto">
452 <table class="memname">
454 <td class="memname">#define SCTLR_EE_Pos   25U</td>
457 </div><div class="memdoc">
459 <p>SCTLR: EE Position. </p>
463 <a id="ga316b80925b88fe3b88ec46a55655b0bc" name="ga316b80925b88fe3b88ec46a55655b0bc"></a>
464 <h2 class="memtitle"><span class="permalink"><a href="#ga316b80925b88fe3b88ec46a55655b0bc">◆ </a></span>SCTLR_FI_Msk</h2>
466 <div class="memitem">
467 <div class="memproto">
468 <table class="memname">
470 <td class="memname">#define SCTLR_FI_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gad88d563fa9a8b09fe36702a5329b0360">SCTLR_FI_Pos</a>)</td>
473 </div><div class="memdoc">
475 <p>SCTLR: FI Mask. </p>
479 <a id="gad88d563fa9a8b09fe36702a5329b0360" name="gad88d563fa9a8b09fe36702a5329b0360"></a>
480 <h2 class="memtitle"><span class="permalink"><a href="#gad88d563fa9a8b09fe36702a5329b0360">◆ </a></span>SCTLR_FI_Pos</h2>
482 <div class="memitem">
483 <div class="memproto">
484 <table class="memname">
486 <td class="memname">#define SCTLR_FI_Pos   21U</td>
489 </div><div class="memdoc">
491 <p>SCTLR: FI Position. </p>
495 <a id="ga6830e9bf54a6b548f329ac047f59c179" name="ga6830e9bf54a6b548f329ac047f59c179"></a>
496 <h2 class="memtitle"><span class="permalink"><a href="#ga6830e9bf54a6b548f329ac047f59c179">◆ </a></span>SCTLR_HA_Msk</h2>
498 <div class="memitem">
499 <div class="memproto">
500 <table class="memname">
502 <td class="memname">#define SCTLR_HA_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga316882abba6c9cdd31dbbd7ba46c9f52">SCTLR_HA_Pos</a>)</td>
505 </div><div class="memdoc">
507 <p>SCTLR: HA Mask. </p>
511 <a id="ga316882abba6c9cdd31dbbd7ba46c9f52" name="ga316882abba6c9cdd31dbbd7ba46c9f52"></a>
512 <h2 class="memtitle"><span class="permalink"><a href="#ga316882abba6c9cdd31dbbd7ba46c9f52">◆ </a></span>SCTLR_HA_Pos</h2>
514 <div class="memitem">
515 <div class="memproto">
516 <table class="memname">
518 <td class="memname">#define SCTLR_HA_Pos   17U</td>
521 </div><div class="memdoc">
523 <p>SCTLR: HA Position. </p>
527 <a id="gab3cc0744fb07127e3c0f18cba9d51666" name="gab3cc0744fb07127e3c0f18cba9d51666"></a>
528 <h2 class="memtitle"><span class="permalink"><a href="#gab3cc0744fb07127e3c0f18cba9d51666">◆ </a></span>SCTLR_I_Msk</h2>
530 <div class="memitem">
531 <div class="memproto">
532 <table class="memname">
534 <td class="memname">#define SCTLR_I_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gaaaa818a1da51059bd979f0e768ebcc7c">SCTLR_I_Pos</a>)</td>
537 </div><div class="memdoc">
539 <p>SCTLR: I Mask. </p>
543 <a id="gaaaa818a1da51059bd979f0e768ebcc7c" name="gaaaa818a1da51059bd979f0e768ebcc7c"></a>
544 <h2 class="memtitle"><span class="permalink"><a href="#gaaaa818a1da51059bd979f0e768ebcc7c">◆ </a></span>SCTLR_I_Pos</h2>
546 <div class="memitem">
547 <div class="memproto">
548 <table class="memname">
550 <td class="memname">#define SCTLR_I_Pos   12U</td>
553 </div><div class="memdoc">
555 <p>SCTLR: I Position. </p>
559 <a id="gaf460824cdbf549bd914aa79762572e8e" name="gaf460824cdbf549bd914aa79762572e8e"></a>
560 <h2 class="memtitle"><span class="permalink"><a href="#gaf460824cdbf549bd914aa79762572e8e">◆ </a></span>SCTLR_M_Msk</h2>
562 <div class="memitem">
563 <div class="memproto">
564 <table class="memname">
566 <td class="memname">#define SCTLR_M_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga88e34078fa8cf719aab6f53f138c9810">SCTLR_M_Pos</a>)</td>
569 </div><div class="memdoc">
571 <p>SCTLR: M Mask. </p>
575 <a id="ga88e34078fa8cf719aab6f53f138c9810" name="ga88e34078fa8cf719aab6f53f138c9810"></a>
576 <h2 class="memtitle"><span class="permalink"><a href="#ga88e34078fa8cf719aab6f53f138c9810">◆ </a></span>SCTLR_M_Pos</h2>
578 <div class="memitem">
579 <div class="memproto">
580 <table class="memname">
582 <td class="memname">#define SCTLR_M_Pos   0U</td>
585 </div><div class="memdoc">
587 <p>SCTLR: M Position. </p>
591 <a id="gab92a3bd63ad9ac3d408e1b615bedc279" name="gab92a3bd63ad9ac3d408e1b615bedc279"></a>
592 <h2 class="memtitle"><span class="permalink"><a href="#gab92a3bd63ad9ac3d408e1b615bedc279">◆ </a></span>SCTLR_NMFI_Msk</h2>
594 <div class="memitem">
595 <div class="memproto">
596 <table class="memname">
598 <td class="memname">#define SCTLR_NMFI_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gac1cf872c51ed0baa6ed23e26c1ed35a9">SCTLR_NMFI_Pos</a>)</td>
601 </div><div class="memdoc">
603 <p>SCTLR: NMFI Mask. </p>
607 <a id="gac1cf872c51ed0baa6ed23e26c1ed35a9" name="gac1cf872c51ed0baa6ed23e26c1ed35a9"></a>
608 <h2 class="memtitle"><span class="permalink"><a href="#gac1cf872c51ed0baa6ed23e26c1ed35a9">◆ </a></span>SCTLR_NMFI_Pos</h2>
610 <div class="memitem">
611 <div class="memproto">
612 <table class="memname">
614 <td class="memname">#define SCTLR_NMFI_Pos   27U</td>
617 </div><div class="memdoc">
619 <p>SCTLR: NMFI Position. </p>
623 <a id="ga1ff9e6766c7e1ca312b025bf34d384bc" name="ga1ff9e6766c7e1ca312b025bf34d384bc"></a>
624 <h2 class="memtitle"><span class="permalink"><a href="#ga1ff9e6766c7e1ca312b025bf34d384bc">◆ </a></span>SCTLR_RR_Msk</h2>
626 <div class="memitem">
627 <div class="memproto">
628 <table class="memname">
630 <td class="memname">#define SCTLR_RR_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga86e5b78ba8f818061644688db75ddc64">SCTLR_RR_Pos</a>)</td>
633 </div><div class="memdoc">
635 <p>SCTLR: RR Mask. </p>
639 <a id="ga86e5b78ba8f818061644688db75ddc64" name="ga86e5b78ba8f818061644688db75ddc64"></a>
640 <h2 class="memtitle"><span class="permalink"><a href="#ga86e5b78ba8f818061644688db75ddc64">◆ </a></span>SCTLR_RR_Pos</h2>
642 <div class="memitem">
643 <div class="memproto">
644 <table class="memname">
646 <td class="memname">#define SCTLR_RR_Pos   14U</td>
649 </div><div class="memdoc">
651 <p>SCTLR: RR Position. </p>
655 <a id="gae4074aefcf01786fe199c82e273271b8" name="gae4074aefcf01786fe199c82e273271b8"></a>
656 <h2 class="memtitle"><span class="permalink"><a href="#gae4074aefcf01786fe199c82e273271b8">◆ </a></span>SCTLR_SW_Msk</h2>
658 <div class="memitem">
659 <div class="memproto">
660 <table class="memname">
662 <td class="memname">#define SCTLR_SW_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga3290be0882c1493bca9a0db6b4d0bff8">SCTLR_SW_Pos</a>)</td>
665 </div><div class="memdoc">
667 <p>SCTLR: SW Mask. </p>
671 <a id="ga3290be0882c1493bca9a0db6b4d0bff8" name="ga3290be0882c1493bca9a0db6b4d0bff8"></a>
672 <h2 class="memtitle"><span class="permalink"><a href="#ga3290be0882c1493bca9a0db6b4d0bff8">◆ </a></span>SCTLR_SW_Pos</h2>
674 <div class="memitem">
675 <div class="memproto">
676 <table class="memname">
678 <td class="memname">#define SCTLR_SW_Pos   10U</td>
681 </div><div class="memdoc">
683 <p>SCTLR: SW Position. </p>
687 <a id="ga4a68d6660c76951ada2541ceaf040b3b" name="ga4a68d6660c76951ada2541ceaf040b3b"></a>
688 <h2 class="memtitle"><span class="permalink"><a href="#ga4a68d6660c76951ada2541ceaf040b3b">◆ </a></span>SCTLR_TE_Msk</h2>
690 <div class="memitem">
691 <div class="memproto">
692 <table class="memname">
694 <td class="memname">#define SCTLR_TE_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gab0a611e2359e04624379e1ddd4dc64b1">SCTLR_TE_Pos</a>)</td>
697 </div><div class="memdoc">
699 <p>SCTLR: TE Mask. </p>
703 <a id="gab0a611e2359e04624379e1ddd4dc64b1" name="gab0a611e2359e04624379e1ddd4dc64b1"></a>
704 <h2 class="memtitle"><span class="permalink"><a href="#gab0a611e2359e04624379e1ddd4dc64b1">◆ </a></span>SCTLR_TE_Pos</h2>
706 <div class="memitem">
707 <div class="memproto">
708 <table class="memname">
710 <td class="memname">#define SCTLR_TE_Pos   30U</td>
713 </div><div class="memdoc">
715 <p>SCTLR: TE Position. </p>
719 <a id="gab0481eb9812a4908601cb20c8ae84918" name="gab0481eb9812a4908601cb20c8ae84918"></a>
720 <h2 class="memtitle"><span class="permalink"><a href="#gab0481eb9812a4908601cb20c8ae84918">◆ </a></span>SCTLR_TRE_Msk</h2>
722 <div class="memitem">
723 <div class="memproto">
724 <table class="memname">
726 <td class="memname">#define SCTLR_TRE_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gaf76fa48119363f9b88c2c8f5b74e0a04">SCTLR_TRE_Pos</a>)</td>
729 </div><div class="memdoc">
731 <p>SCTLR: TRE Mask. </p>
735 <a id="gaf76fa48119363f9b88c2c8f5b74e0a04" name="gaf76fa48119363f9b88c2c8f5b74e0a04"></a>
736 <h2 class="memtitle"><span class="permalink"><a href="#gaf76fa48119363f9b88c2c8f5b74e0a04">◆ </a></span>SCTLR_TRE_Pos</h2>
738 <div class="memitem">
739 <div class="memproto">
740 <table class="memname">
742 <td class="memname">#define SCTLR_TRE_Pos   28U</td>
745 </div><div class="memdoc">
747 <p>SCTLR: TRE Position. </p>
751 <a id="gaa047daa7ab35b5ad5dd238c7377a232f" name="gaa047daa7ab35b5ad5dd238c7377a232f"></a>
752 <h2 class="memtitle"><span class="permalink"><a href="#gaa047daa7ab35b5ad5dd238c7377a232f">◆ </a></span>SCTLR_U_Msk</h2>
754 <div class="memitem">
755 <div class="memproto">
756 <table class="memname">
758 <td class="memname">#define SCTLR_U_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gaa0431730d7ce929db03d8accee558e17">SCTLR_U_Pos</a>)</td>
761 </div><div class="memdoc">
763 <p>SCTLR: U Mask. </p>
767 <a id="gaa0431730d7ce929db03d8accee558e17" name="gaa0431730d7ce929db03d8accee558e17"></a>
768 <h2 class="memtitle"><span class="permalink"><a href="#gaa0431730d7ce929db03d8accee558e17">◆ </a></span>SCTLR_U_Pos</h2>
770 <div class="memitem">
771 <div class="memproto">
772 <table class="memname">
774 <td class="memname">#define SCTLR_U_Pos   22U</td>
777 </div><div class="memdoc">
779 <p>SCTLR: U Position. </p>
783 <a id="gab834e64e0da7c2a98d747ce73252c199" name="gab834e64e0da7c2a98d747ce73252c199"></a>
784 <h2 class="memtitle"><span class="permalink"><a href="#gab834e64e0da7c2a98d747ce73252c199">◆ </a></span>SCTLR_UWXN_Msk</h2>
786 <div class="memitem">
787 <div class="memproto">
788 <table class="memname">
790 <td class="memname">#define SCTLR_UWXN_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga7c7d88f3db4de438ddd069cf3fbc88b3">SCTLR_UWXN_Pos</a>)</td>
793 </div><div class="memdoc">
795 <p>SCTLR: UWXN Mask. </p>
799 <a id="ga7c7d88f3db4de438ddd069cf3fbc88b3" name="ga7c7d88f3db4de438ddd069cf3fbc88b3"></a>
800 <h2 class="memtitle"><span class="permalink"><a href="#ga7c7d88f3db4de438ddd069cf3fbc88b3">◆ </a></span>SCTLR_UWXN_Pos</h2>
802 <div class="memitem">
803 <div class="memproto">
804 <table class="memname">
806 <td class="memname">#define SCTLR_UWXN_Pos   20U</td>
809 </div><div class="memdoc">
811 <p>SCTLR: UWXN Position. </p>
815 <a id="gaf84f3f15bf6917acdc5b5a4ad661ac11" name="gaf84f3f15bf6917acdc5b5a4ad661ac11"></a>
816 <h2 class="memtitle"><span class="permalink"><a href="#gaf84f3f15bf6917acdc5b5a4ad661ac11">◆ </a></span>SCTLR_V_Msk</h2>
818 <div class="memitem">
819 <div class="memproto">
820 <table class="memname">
822 <td class="memname">#define SCTLR_V_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga57778fd6afbe5b4fe8d8ea828acf833d">SCTLR_V_Pos</a>)</td>
825 </div><div class="memdoc">
827 <p>SCTLR: V Mask. </p>
831 <a id="ga57778fd6afbe5b4fe8d8ea828acf833d" name="ga57778fd6afbe5b4fe8d8ea828acf833d"></a>
832 <h2 class="memtitle"><span class="permalink"><a href="#ga57778fd6afbe5b4fe8d8ea828acf833d">◆ </a></span>SCTLR_V_Pos</h2>
834 <div class="memitem">
835 <div class="memproto">
836 <table class="memname">
838 <td class="memname">#define SCTLR_V_Pos   13U</td>
841 </div><div class="memdoc">
843 <p>SCTLR: V Position. </p>
847 <a id="gad94a7feadba850299a68c56e39c0b274" name="gad94a7feadba850299a68c56e39c0b274"></a>
848 <h2 class="memtitle"><span class="permalink"><a href="#gad94a7feadba850299a68c56e39c0b274">◆ </a></span>SCTLR_VE_Msk</h2>
850 <div class="memitem">
851 <div class="memproto">
852 <table class="memname">
854 <td class="memname">#define SCTLR_VE_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga1372b569553a0740d881e24c0be7334f">SCTLR_VE_Pos</a>)</td>
857 </div><div class="memdoc">
859 <p>SCTLR: VE Mask. </p>
863 <a id="ga1372b569553a0740d881e24c0be7334f" name="ga1372b569553a0740d881e24c0be7334f"></a>
864 <h2 class="memtitle"><span class="permalink"><a href="#ga1372b569553a0740d881e24c0be7334f">◆ </a></span>SCTLR_VE_Pos</h2>
866 <div class="memitem">
867 <div class="memproto">
868 <table class="memname">
870 <td class="memname">#define SCTLR_VE_Pos   24U</td>
873 </div><div class="memdoc">
875 <p>SCTLR: VE Position. </p>
879 <a id="ga510b03214d135f15ad3c5d41ec20a291" name="ga510b03214d135f15ad3c5d41ec20a291"></a>
880 <h2 class="memtitle"><span class="permalink"><a href="#ga510b03214d135f15ad3c5d41ec20a291">◆ </a></span>SCTLR_WXN_Msk</h2>
882 <div class="memitem">
883 <div class="memproto">
884 <table class="memname">
886 <td class="memname">#define SCTLR_WXN_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gaf145654986fd6d014136580ad279d256">SCTLR_WXN_Pos</a>)</td>
889 </div><div class="memdoc">
891 <p>SCTLR: WXN Mask. </p>
895 <a id="gaf145654986fd6d014136580ad279d256" name="gaf145654986fd6d014136580ad279d256"></a>
896 <h2 class="memtitle"><span class="permalink"><a href="#gaf145654986fd6d014136580ad279d256">◆ </a></span>SCTLR_WXN_Pos</h2>
898 <div class="memitem">
899 <div class="memproto">
900 <table class="memname">
902 <td class="memname">#define SCTLR_WXN_Pos   19U</td>
905 </div><div class="memdoc">
907 <p>SCTLR: WXN Position. </p>
911 <a id="ga12a05acdcb8db6e99970f26206d3067c" name="ga12a05acdcb8db6e99970f26206d3067c"></a>
912 <h2 class="memtitle"><span class="permalink"><a href="#ga12a05acdcb8db6e99970f26206d3067c">◆ </a></span>SCTLR_Z_Msk</h2>
914 <div class="memitem">
915 <div class="memproto">
916 <table class="memname">
918 <td class="memname">#define SCTLR_Z_Msk   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gaa0eade648c9a34de891af0e6f47857dd">SCTLR_Z_Pos</a>)</td>
921 </div><div class="memdoc">
923 <p>SCTLR: Z Mask. </p>
927 <a id="gaa0eade648c9a34de891af0e6f47857dd" name="gaa0eade648c9a34de891af0e6f47857dd"></a>
928 <h2 class="memtitle"><span class="permalink"><a href="#gaa0eade648c9a34de891af0e6f47857dd">◆ </a></span>SCTLR_Z_Pos</h2>
930 <div class="memitem">
931 <div class="memproto">
932 <table class="memname">
934 <td class="memname">#define SCTLR_Z_Pos   11U</td>
937 </div><div class="memdoc">
939 <p>SCTLR: Z Position. </p>
943 </div><!-- contents -->
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