begriffs open source - cmsis/blob - main/Core_A/rev_histCoreA.html

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  46    <div id="projectname">CMSIS-Core (Cortex-A)
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  55    <div id="projectbrief">CMSIS-Core support for Cortex-A processor-based devices</div>
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 130   <div class="headertitle"><div class="title">Revision History of CMSIS-Core (Cortex-A) </div></div>
 131 </div><!--header-->
 132 <div class="contents">
 133 <div class="textblock"><p><a class="anchor" id="md_src_history"></a> CMSIS-Core (A) component is maintaned with own versioning that gets incremented together with the <a href="../General/cmsis_pack.html">CMSIS Software Pack</a> releases.</p>
 134 <p>The table below provides information about the changes delivered with specific versions of CMSIS-Core (A) updates.</p>
 135 <table class="cmtable" summary="Revision History">
 136 <tr>
 137 <th>Version </th><th>Description  </th></tr>
 138 <tr>
 139 <td>V1.2.1 </td><td><ul>
 140 <li>
 141 Bugfixes for Cortex-A32 </li>
 142 </ul>
 143 </td></tr>
 144 <tr>
 145 <td>V1.2.0 </td><td><ul>
 146 <li>
 147 Fixed GIC_SetPendingIRQ to use GICD_SGIR instead of GICD_SPENDSGIR for compliance with all GIC specification versions. </li>
 148 <li>
 149 Added missing DSP intrinsics. </li>
 150 <li>
 151 Reworked assembly intrinsics: volatile, barriers and clobbers. </li>
 152 </ul>
 153 </td></tr>
 154 <tr>
 155 <td>V1.1.4 </td><td><ul>
 156 <li>
 157 Fixed <a class="el" href="group__FPU__functions.html#ga1e4728985ee8b4fa89cc01c032f69565" title="Enable Floating Point Unit.">__FPU_Enable()</a>. </li>
 158 </ul>
 159 </td></tr>
 160 <tr>
 161 <td>V1.1.3 </td><td><ul>
 162 <li>
 163 Fixed <a class="el" href="cmsis__armclang__a_8h.html#a7009688fca7a35b5e3ba6cf11cc74869" title="Get USR/SYS Stack Pointer.">__get_SP_usr()</a>/__set_SP_usr() for ArmClang. </li>
 164 <li>
 165 Fixed zero argument handling in <a class="el" href="group__CMSIS__Core__InstructionInterface.html#ga90884c591ac5d73d6069334eba9d6c02" title="Count leading zeros.">__CLZ()</a> . </li>
 166 </ul>
 167 </td></tr>
 168 <tr>
 169 <td>V1.1.2 </td><td><ul>
 170 <li>
 171 Removed using get/set built-ins FPSCR in GCC &gt;= 7.2 due to shortcomings. </li>
 172 <li>
 173 Fixed co-processor register access macros for Arm Compiler 5. </li>
 174 </ul>
 175 </td></tr>
 176 <tr>
 177 <td>V1.1.1 </td><td><ul>
 178 <li>
 179 Refactored L1 cache maintenance to be compiler agnostic. </li>
 180 </ul>
 181 </td></tr>
 182 <tr>
 183 <td>V1.1.0 </td><td><ul>
 184 <li>
 185 Added compiler_iccarm.h for IAR compiler. </li>
 186 <li>
 187 Added missing core access functions for Arm Compiler 5. </li>
 188 <li>
 189 Aligned access function to coprocessor 15. </li>
 190 <li>
 191 Additional generic Timer functions. </li>
 192 <li>
 193 Bug fixes and minor enhancements. </li>
 194 </ul>
 195 </td></tr>
 196 <tr>
 197 <td>V1.0.0 </td><td>Initial Release for Cortex-A5/A7/A9 processors.  </td></tr>
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