1 /*-----------------------------------------------------------------------------
3 * Purpose: CV Config header
4 *----------------------------------------------------------------------------
5 * Copyright (c) 2017 - 2018 Arm Limited. All rights reserved.
6 *----------------------------------------------------------------------------*/
10 #include "RTE_Components.h"
11 #include CMSIS_device_header
13 //-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
15 // <h> Common Test Settings
16 // <o> Print Output Format <0=> Plain Text <1=> XML
17 // <i> Set the test results output format to plain text or XML
18 #ifndef PRINT_XML_REPORT
19 #define PRINT_XML_REPORT 1
21 // <o> Buffer size for assertions results
22 // <i> Set the buffer size for assertions results buffer
23 #define BUFFER_ASSERTIONS 128U
26 // <h> Disable Test Cases
27 // <i> Uncheck to disable an individual test case
28 // <q0> TC_CoreInstr_NOP
29 #define TC_COREINSTR_NOP_EN 1
30 // <q0> TC_CoreInstr_SEV
31 #define TC_COREINSTR_SEV_EN 1
32 // <q0> TC_CoreInstr_BKPT
33 #define TC_COREINSTR_BKPT_EN 1
34 // <q0> TC_CoreInstr_ISB
35 #define TC_COREINSTR_ISB_EN 1
36 // <q0> TC_CoreInstr_DSB
37 #define TC_COREINSTR_DSB_EN 1
38 // <q0> TC_CoreInstr_DMB
39 #define TC_COREINSTR_DMB_EN 1
40 // <q0> TC_CoreInstr_WFI
41 #define TC_COREINSTR_WFI_EN 0
42 // <q0> TC_CoreInstr_WFE
43 #define TC_COREINSTR_WFE_EN 0
45 // <q0> TC_CoreInstr_REV
46 #define TC_COREINSTR_REV_EN 1
47 // <q0> TC_CoreInstr_REV16
48 #define TC_COREINSTR_REV16_EN 1
49 // <q0> TC_CoreInstr_REVSH
50 #define TC_COREINSTR_REVSH_EN 1
51 // <q0> TC_CoreInstr_ROR
52 #define TC_COREINSTR_ROR_EN 1
53 // <q0> TC_CoreInstr_RBIT
54 #define TC_COREINSTR_RBIT_EN 1
55 // <q0> TC_CoreInstr_CLZ
56 #define TC_COREINSTR_CLZ_EN 1
57 // <q0> TC_CoreInstr_SSAT
58 #define TC_COREINSTR_SSAT_EN 1
59 // <q0> TC_CoreInstr_USAT
60 #define TC_COREINSTR_USAT_EN 1
61 // <q0> TC_CoreInstr_RRX
62 #define TC_COREINSTR_RRX_EN 1
63 // <q0> TC_CoreInstr_LoadStoreExlusive
64 #define TC_COREINSTR_LOADSTOREEXCLUSIVE_EN 1
65 // <q0> TC_CoreInstr_LoadStoreUnpriv
66 #define TC_COREINSTR_LOADSTOREUNPRIV_EN 1
67 // <q0> TC_CoreInstr_LoadStoreAcquire
68 #define TC_COREINSTR_LOADSTOREACQUIRE_EN 1
69 // <q0> TC_CoreInstr_LoadStoreAcquireExclusive
70 #define TC_COREINSTR_LOADSTOREACQUIREEXCLUSIVE_EN 1
72 // <q0> TC_CoreSimd_SatAddSub
73 #define TC_CORESIMD_SATADDSUB_EN 1
74 // <q0> TC_CoreSimd_ParSat16
75 #define TC_CORESIMD_PARSAT16_EN 1
76 // <q0> TC_CoreSimd_PackUnpack
77 #define TC_CORESIMD_PACKUNPACK_EN 1
78 // <q0> TC_CoreSimd_ParSel
79 #define TC_CORESIMD_PARSEL_EN 1
80 // <q0> TC_CoreSimd_ParAddSub8
81 #define TC_CORESIMD_PARADDSUB8_EN 1
82 // <q0> TC_CoreSimd_AbsDif8
83 #define TC_CORESIMD_ABSDIF8_EN 1
84 // <q0> TC_CoreSimd_ParAddSub16
85 #define TC_CORESIMD_PARADDSUB16_EN 1
86 // <q0> TC_CoreSimd_ParMul16
87 #define TC_CORESIMD_PARMUL16_EN 1
88 // <q0> TC_CoreSimd_Pack16
89 #define TC_CORESIMD_PACK16_EN 1
90 // <q0> TC_CoreSimd_MulAcc32
91 #define TC_CORESIMD_MULACC32_EN 1
93 // <q0> TC_CoreFunc_EnDisIRQ
94 #define TC_COREFUNC_ENDISIRQ_EN 1
95 // <q0> TC_CoreFunc_IRQPrio
96 #define TC_COREFUNC_IRQPRIO_EN 1
97 // <q0> TC_CoreFunc_EncDecIRQPrio
98 #define TC_COREFUNC_ENCDECIRQPRIO_EN 1
99 // <q0> TC_CoreFunc_IRQVect
100 #define TC_COREFUNC_IRQVECT_EN 1
101 // <q0> TC_CoreFunc_Control
102 #define TC_COREFUNC_CONTROL_EN 1
103 // <q0> TC_CoreFunc_IPSR
104 #define TC_COREFUNC_IPSR_EN 1
105 // <q0> TC_CoreFunc_APSR
106 #define TC_COREFUNC_APSR_EN 1
107 // <q0> TC_CoreFunc_PSP
108 #define TC_COREFUNC_PSP_EN 1
109 // <q0> TC_CoreFunc_MSP
110 #define TC_COREFUNC_MSP_EN 1
112 // <q0> TC_CoreFunc_PSPLIM
113 #define TC_COREFUNC_PSPLIM_EN 1
114 // <q0> TC_CoreFunc_PSPLIM_NS
115 #define TC_COREFUNC_PSPLIM_NS_EN 1
116 // <q0> TC_CoreFunc_MSPLIM
117 #define TC_COREFUNC_MSPLIM_EN 1
118 // <q0> TC_CoreFunc_MSPLIM_NS
119 #define TC_COREFUNC_MSPLIM_NS_EN 1
120 // <q0> TC_CoreFunc_PRIMASK
121 #define TC_COREFUNC_PRIMASK_EN 1
122 // <q0> TC_CoreFunc_FAULTMASK
123 #define TC_COREFUNC_FAULTMASK_EN 1
124 // <q0> TC_CoreFunc_BASEPRI
125 #define TC_COREFUNC_BASEPRI_EN 1
126 // <q0> TC_CoreFunc_FPUType
127 #define TC_COREFUNC_FPUTYPE_EN 1
128 // <q0> TC_CoreFunc_FPSCR
129 #define TC_COREFUNC_FPSCR_EN 1
131 // <q0> TC_MPU_SetClear
132 #define TC_MPU_SETCLEAR_EN 1
134 #define TC_MPU_LOAD_EN 1
136 // <q0> TC_CML1Cache_EnDisableICache
137 #define TC_CML1CACHE_ENDISABLE_ICACHE 1
138 // <q0> TC_CML1Cache_EnDisableDCache
139 #define TC_CML1CACHE_ENDISABLE_DCACHE 1
140 // <q0> TC_CML1Cache_CleanDCacheByAddrWhileDisabled
141 #define TC_CML1CACHE_CLEANDCACHEBYADDRWHILEDISABLED 1
145 #endif /* __CV_CONFIG_H */