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 127   <div class="headertitle"><div class="title">Memory Management Unit Files mmu_&lt;device&gt;.c </div></div>
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 129 <div class="contents">
 130 <div class="textblock"><pre class="fragment">/**************************************************************************//**
 131  * @file     system_Device.c
 132  * @brief    MMU Configuration
 133  *           Device &lt;DeviceAbbreviation&gt;
 134  * @version  V1.1.0
 135  * @date     23. November 2018
 136  ******************************************************************************/
 137 /*
 138  * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 139  *
 140  * SPDX-License-Identifier: Apache-2.0
 141  *
 142  * Licensed under the Apache License, Version 2.0 (the License); you may
 143  * not use this file except in compliance with the License.
 144  * You may obtain a copy of the License at
 145  *
 146  * www.apache.org/licenses/LICENSE-2.0
 147  *
 148  * Unless required by applicable law or agreed to in writing, software
 149  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 150  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 151  * See the License for the specific language governing permissions and
 152  * limitations under the License.
 153  */
 154
 155 /* Memory map description
 156
 157    ToDo: add in this file your device memory map description
 158          following is an example of a Cortex-A9 Arm FVP device
 159
 160                                                      Memory Type
 161 0xFFFFFFFF |--------------------------|             ------------
 162            |       FLAG SYNC          |             Device Memory
 163 0xFFFFF000 |--------------------------|             ------------
 164            |         Fault            |                Fault
 165 0xFFF00000 |--------------------------|             ------------
 166            |                          |                Normal
 167            |                          |
 168            |      Daughterboard       |
 169            |         memory           |
 170            |                          |
 171 0x80505000 |--------------------------|             ------------
 172            |TTB (L2 Sync Flags   ) 4k |                Normal
 173 0x80504C00 |--------------------------|             ------------
 174            |TTB (L2 Peripherals-B) 16k|                Normal
 175 0x80504800 |--------------------------|             ------------
 176            |TTB (L2 Peripherals-A) 16k|                Normal
 177 0x80504400 |--------------------------|             ------------
 178            |TTB (L2 Priv Periphs)  4k |                Normal
 179 0x80504000 |--------------------------|             ------------
 180            |    TTB (L1 Descriptors)  |                Normal
 181 0x80500000 |--------------------------|             ------------
 182            |           Heap           |                Normal
 183            |--------------------------|             ------------
 184            |          Stack           |                Normal
 185 0x80400000 |--------------------------|             ------------
 186            |         ZI Data          |                Normal
 187 0x80300000 |--------------------------|             ------------
 188            |         RW Data          |                Normal
 189 0x80200000 |--------------------------|             ------------
 190            |         RO Data          |                Normal
 191            |--------------------------|             ------------
 192            |         RO Code          |              USH Normal
 193 0x80000000 |--------------------------|             ------------
 194            |      Daughterboard       |                Fault
 195            |      HSB AXI buses       |
 196 0x40000000 |--------------------------|             ------------
 197            |      Daughterboard       |                Fault
 198            |  test chips peripherals  |
 199 0x2C002000 |--------------------------|             ------------
 200            |     Private Address      |            Device Memory
 201 0x2C000000 |--------------------------|             ------------
 202            |      Daughterboard       |                Fault
 203            |  test chips peripherals  |
 204 0x20000000 |--------------------------|             ------------
 205            |       Peripherals        |           Device Memory RW/RO
 206            |                          |              &amp; Fault
 207 0x00000000 |--------------------------|
 208 */
 209
 210 // L1 Cache info and restrictions about architecture of the caches (CCSIR register):
 211 // Write-Through support *not* available
 212 // Write-Back support available.
 213 // Read allocation support available.
 214 // Write allocation support available.
 215
 216 // Note: You should use the Shareable attribute carefully.
 217 // For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
 218 // Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
 219 // Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
 220
 221 // Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
 222 // When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
 223 // When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
 224
 225 // Following MMU configuration is expected
 226 // SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
 227 // SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
 228 // Domain 0 is always the Client domain
 229 // Descriptors should place all memory in domain 0
 230
 231 #include "&lt;Device&gt;.h" /* ToDo: replace '&lt;Device&gt;' with your device name */
 232
 233 // L2 table pointers
 234 //-----------------------------------------------------
 235 #define PRIVATE_TABLE_L2_BASE_4k       (0x80504000) //Map 4k Private Address space
 236 #define SYNC_FLAGS_TABLE_L2_BASE_4k    (0x80504C00) //Map 4k Flag synchronization
 237 #define PERIPHERAL_A_TABLE_L2_BASE_64k (0x80504400) //Map 64k Peripheral #1
 238 #define PERIPHERAL_B_TABLE_L2_BASE_64k (0x80504800) //Map 64k Peripheral #2
 239
 240 //--------------------- PERIPHERALS -------------------
 241 #define PERIPHERAL_A_FAULT             (0x00000000 + 0x1C000000)
 242 #define PERIPHERAL_B_FAULT             (0x00100000 + 0x1C000000)
 243
 244 //--------------------- SYNC FLAGS --------------------
 245 #define FLAG_SYNC                       0xFFFFF000
 246 #define F_SYNC_BASE                     0xFFF00000  //1M aligned
 247
 248 //Import symbols from linker
 249 extern uint32_t Image$$VECTORS$$Base;
 250 extern uint32_t Image$$RW_DATA$$Base;
 251 extern uint32_t Image$$ZI_DATA$$Base;
 252 extern uint32_t Image$$TTB$$ZI$$Base;
 253
 254 static uint32_t Sect_Normal;        // outer &amp; inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
 255 static uint32_t Sect_Normal_Cod;    // outer &amp; inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
 256 static uint32_t Sect_Normal_RO;     // as Sect_Normal_Cod, but not executable
 257 static uint32_t Sect_Normal_RW;     // as Sect_Normal_Cod, but writeable and not executable
 258 static uint32_t Sect_Device_RO;     // device, non-shareable, non-executable, ro, domain 0, base addr 0
 259 static uint32_t Sect_Device_RW;     // as Sect_Device_RO, but writeable
 260
 261 /* Define global descriptors */
 262 static uint32_t Page_L1_4k  = 0x0;  // generic
 263 static uint32_t Page_L1_64k = 0x0;  // generic
 264 static uint32_t Page_4k_Device_RW;  // shared device, not executable, rw, domain 0
 265 static uint32_t Page_64k_Device_RW; // shared device, not executable, rw, domain 0
 266
 267 void MMU_CreateTranslationTable(void)
 268 {
 269   mmu_region_attributes_Type region;
 270
 271   // Create 4GB of faulting entries
 272   MMU_TTSection (&amp;Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
 273
 274   /*
 275    * Generate descriptors. Refer to core_ca.h to get information about attributes
 276    *
 277    */
 278   // Create descriptors for Vectors, RO, RW, ZI sections
 279   section_normal(Sect_Normal, region);
 280   section_normal_cod(Sect_Normal_Cod, region);
 281   section_normal_ro(Sect_Normal_RO, region);
 282   section_normal_rw(Sect_Normal_RW, region);
 283   // Create descriptors for peripherals
 284   section_Device_ro(Sect_Device_RO, region);
 285   section_Device_rw(Sect_Device_RW, region);
 286   // Create descriptors for 64k pages
 287   page64k_Device_rw(Page_L1_64k, Page_64k_Device_RW, region);
 288   // Create descriptors for 4k pages
 289   page4k_Device_rw(Page_L1_4k, Page_4k_Device_RW, region);
 290
 291   /*
 292    *  Define MMU flat-map regions and attributes
 293    *
 294    */
 295   // Define Image
 296   MMU_TTSection (&amp;Image$$TTB$$ZI$$Base, (uint32_t)&amp;Image$$VECTORS$$Base     ,    1U, Sect_Normal_Cod);
 297   MMU_TTSection (&amp;Image$$TTB$$ZI$$Base, (uint32_t)&amp;Image$$RW_DATA$$Base     ,    1U, Sect_Normal_RW);
 298   MMU_TTSection (&amp;Image$$TTB$$ZI$$Base, (uint32_t)&amp;Image$$ZI_DATA$$Base     ,    1U, Sect_Normal_RW);
 299
 300   // All DRAM executable, RW, cacheable - applications may choose to divide memory into RO executable
 301   MMU_TTSection (&amp;Image$$TTB$$ZI$$Base, (uint32_t)&amp;Image$$TTB$$ZI$$Base     , 2043U, Sect_Normal);
 302
 303   //--------------------- PERIPHERALS -------------------
 304   MMU_TTSection (&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_FLASH_BASE0    ,   64U, Sect_Device_RO);
 305   MMU_TTSection (&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_FLASH_BASE1    ,   64U, Sect_Device_RO);
 306   MMU_TTSection (&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_SRAM_BASE      ,   64U, Sect_Device_RW);
 307   MMU_TTSection (&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_VRAM_BASE      ,   32U, Sect_Device_RW);
 308   MMU_TTSection (&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_ETHERNET_BASE  ,   16U, Sect_Device_RW);
 309   MMU_TTSection (&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_USB_BASE       ,   16U, Sect_Device_RW);
 310
 311   // Create (16 * 64k)=1MB faulting entries to cover peripheral range
 312   MMU_TTPage64k(&amp;Image$$TTB$$ZI$$Base, PERIPHERAL_A_FAULT                   ,   16U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
 313   // Define peripheral range
 314   MMU_TTPage64k(&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_DAP_BASE        ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
 315   MMU_TTPage64k(&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_SYSTEM_REG_BASE ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
 316   MMU_TTPage64k(&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_SERIAL_BASE     ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
 317   MMU_TTPage64k(&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_AACI_BASE       ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
 318   MMU_TTPage64k(&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_MMCI_BASE       ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
 319   MMU_TTPage64k(&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_KMI0_BASE       ,    2U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
 320   MMU_TTPage64k(&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_UART_BASE       ,    4U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
 321   MMU_TTPage64k(&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_WDT_BASE        ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
 322
 323   // Create (16 * 64k)=1MB faulting entries to cover peripheral range
 324   MMU_TTPage64k(&amp;Image$$TTB$$ZI$$Base, PERIPHERAL_B_FAULT                   ,   16U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
 325   // Define peripheral range
 326   MMU_TTPage64k(&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_TIMER_BASE      ,    2U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
 327   MMU_TTPage64k(&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_DVI_BASE        ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
 328   MMU_TTPage64k(&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_RTC_BASE        ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
 329   MMU_TTPage64k(&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_UART4_BASE      ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
 330   MMU_TTPage64k(&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_CLCD_BASE       ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
 331
 332   // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory
 333   MMU_TTPage4k (&amp;Image$$TTB$$ZI$$Base, __get_CBAR()                         ,  256U,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
 334   // Define private address space entry
 335   MMU_TTPage4k (&amp;Image$$TTB$$ZI$$Base, __get_CBAR()                         ,    2U,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
 336   // Define L2CC entry
 337   MMU_TTPage4k (&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_L2C_BASE        ,    1U,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
 338
 339   // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)
 340   MMU_TTPage4k (&amp;Image$$TTB$$ZI$$Base, F_SYNC_BASE                          ,  256U, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
 341   // Define synchronization space entry.
 342   MMU_TTPage4k (&amp;Image$$TTB$$ZI$$Base, FLAG_SYNC                            ,    1U, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);
 343
 344   /* Set location of level 1 page table
 345   ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
 346   ; 13:7  - 0x0
 347   ; 6     - IRGN[0] 0x1  (Inner WB WA)
 348   ; 5     - NOS     0x0  (Non-shared)
 349   ; 4:3   - RGN     0x01 (Outer WB WA)
 350   ; 2     - IMP     0x0  (Implementation Defined)
 351   ; 1     - S       0x0  (Non-shared)
 352   ; 0     - IRGN[1] 0x0  (Inner WB WA) */
 353   __set_TTBR0(((uint32_t)&amp;Image$$TTB$$ZI$$Base) | 0x48);
 354   __ISB();
 355
 356   /* Set up domain access control register
 357   ; We set domain 0 to Client and all other domains to No Access.
 358   ; All translation table entries specify domain 0 */
 359   __set_DACR(1);
 360   __ISB();
 361 }
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