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55 <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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130 <div class="summary">
131 <a href="#define-members">Macros</a> </div>
132 <div class="headertitle"><div class="title">PMU Events for Armv8.1-M<div class="ingroups"><a class="el" href="group__pmu8__functions.html">PMU Functions for Armv8.1-M</a></div></div></div>
134 <div class="contents">
136 <p>IDs for Armv8.1-M architecture defined events.
137 <a href="#details">More...</a></p>
138 <table class="memberdecls">
139 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a>
140 Macros</h2></td></tr>
141 <tr class="memitem:ga6e02b08550d7e9b273ff7913f1b57bea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga6e02b08550d7e9b273ff7913f1b57bea">ARM_PMU_SW_INCR</a>   0x0000</td></tr>
142 <tr class="memdesc:ga6e02b08550d7e9b273ff7913f1b57bea"><td class="mdescLeft"> </td><td class="mdescRight">Software update to the PMU_SWINC register, architecturally executed and condition code check pass. <br /></td></tr>
143 <tr class="separator:ga6e02b08550d7e9b273ff7913f1b57bea"><td class="memSeparator" colspan="2"> </td></tr>
144 <tr class="memitem:gac43e0e0f9e385ea66402bdeebf3fea3e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gac43e0e0f9e385ea66402bdeebf3fea3e">ARM_PMU_L1I_CACHE_REFILL</a>   0x0001</td></tr>
145 <tr class="memdesc:gac43e0e0f9e385ea66402bdeebf3fea3e"><td class="mdescLeft"> </td><td class="mdescRight">L1 I-Cache refill. <br /></td></tr>
146 <tr class="separator:gac43e0e0f9e385ea66402bdeebf3fea3e"><td class="memSeparator" colspan="2"> </td></tr>
147 <tr class="memitem:ga64a3d7bfb7ec9d7bdeb073a4fe1bbc38"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga64a3d7bfb7ec9d7bdeb073a4fe1bbc38">ARM_PMU_L1D_CACHE_REFILL</a>   0x0003</td></tr>
148 <tr class="memdesc:ga64a3d7bfb7ec9d7bdeb073a4fe1bbc38"><td class="mdescLeft"> </td><td class="mdescRight">L1 D-Cache refill. <br /></td></tr>
149 <tr class="separator:ga64a3d7bfb7ec9d7bdeb073a4fe1bbc38"><td class="memSeparator" colspan="2"> </td></tr>
150 <tr class="memitem:ga7505ae74c1d905f01b05dd5466c1efc0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga7505ae74c1d905f01b05dd5466c1efc0">ARM_PMU_L1D_CACHE</a>   0x0004</td></tr>
151 <tr class="memdesc:ga7505ae74c1d905f01b05dd5466c1efc0"><td class="mdescLeft"> </td><td class="mdescRight">L1 D-Cache access. <br /></td></tr>
152 <tr class="separator:ga7505ae74c1d905f01b05dd5466c1efc0"><td class="memSeparator" colspan="2"> </td></tr>
153 <tr class="memitem:ga2e8725ee07c2b2c75a1b54261bc26cc8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga2e8725ee07c2b2c75a1b54261bc26cc8">ARM_PMU_LD_RETIRED</a>   0x0006</td></tr>
154 <tr class="memdesc:ga2e8725ee07c2b2c75a1b54261bc26cc8"><td class="mdescLeft"> </td><td class="mdescRight">Memory-reading instruction architecturally executed and condition code check pass. <br /></td></tr>
155 <tr class="separator:ga2e8725ee07c2b2c75a1b54261bc26cc8"><td class="memSeparator" colspan="2"> </td></tr>
156 <tr class="memitem:ga8179d1144f8ec993bd1343e276d7b49b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8179d1144f8ec993bd1343e276d7b49b">ARM_PMU_ST_RETIRED</a>   0x0007</td></tr>
157 <tr class="memdesc:ga8179d1144f8ec993bd1343e276d7b49b"><td class="mdescLeft"> </td><td class="mdescRight">Memory-writing instruction architecturally executed and condition code check pass. <br /></td></tr>
158 <tr class="separator:ga8179d1144f8ec993bd1343e276d7b49b"><td class="memSeparator" colspan="2"> </td></tr>
159 <tr class="memitem:ga8a5e60eee460addfc66e275a2c4c4800"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8a5e60eee460addfc66e275a2c4c4800">ARM_PMU_INST_RETIRED</a>   0x0008</td></tr>
160 <tr class="memdesc:ga8a5e60eee460addfc66e275a2c4c4800"><td class="mdescLeft"> </td><td class="mdescRight">Instruction architecturally executed. <br /></td></tr>
161 <tr class="separator:ga8a5e60eee460addfc66e275a2c4c4800"><td class="memSeparator" colspan="2"> </td></tr>
162 <tr class="memitem:gac97858bd621eab4592569444f0a5c37f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gac97858bd621eab4592569444f0a5c37f">ARM_PMU_EXC_TAKEN</a>   0x0009</td></tr>
163 <tr class="memdesc:gac97858bd621eab4592569444f0a5c37f"><td class="mdescLeft"> </td><td class="mdescRight">Exception entry. <br /></td></tr>
164 <tr class="separator:gac97858bd621eab4592569444f0a5c37f"><td class="memSeparator" colspan="2"> </td></tr>
165 <tr class="memitem:gaf9424157e9c5dca3a3689d181005c4f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf9424157e9c5dca3a3689d181005c4f8">ARM_PMU_EXC_RETURN</a>   0x000A</td></tr>
166 <tr class="memdesc:gaf9424157e9c5dca3a3689d181005c4f8"><td class="mdescLeft"> </td><td class="mdescRight">Exception return instruction architecturally executed and the condition code check pass. <br /></td></tr>
167 <tr class="separator:gaf9424157e9c5dca3a3689d181005c4f8"><td class="memSeparator" colspan="2"> </td></tr>
168 <tr class="memitem:ga54fd2c392399221077c67866a395e587"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga54fd2c392399221077c67866a395e587">ARM_PMU_PC_WRITE_RETIRED</a>   0x000C</td></tr>
169 <tr class="memdesc:ga54fd2c392399221077c67866a395e587"><td class="mdescLeft"> </td><td class="mdescRight">Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass. <br /></td></tr>
170 <tr class="separator:ga54fd2c392399221077c67866a395e587"><td class="memSeparator" colspan="2"> </td></tr>
171 <tr class="memitem:ga22bfb189fff7c1ea9f81097a543ed756"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga22bfb189fff7c1ea9f81097a543ed756">ARM_PMU_BR_IMMED_RETIRED</a>   0x000D</td></tr>
172 <tr class="memdesc:ga22bfb189fff7c1ea9f81097a543ed756"><td class="mdescLeft"> </td><td class="mdescRight">Immediate branch architecturally executed. <br /></td></tr>
173 <tr class="separator:ga22bfb189fff7c1ea9f81097a543ed756"><td class="memSeparator" colspan="2"> </td></tr>
174 <tr class="memitem:gab717347b1c3601cffb9c99b43b2a45c5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab717347b1c3601cffb9c99b43b2a45c5">ARM_PMU_BR_RETURN_RETIRED</a>   0x000E</td></tr>
175 <tr class="memdesc:gab717347b1c3601cffb9c99b43b2a45c5"><td class="mdescLeft"> </td><td class="mdescRight">Function return instruction architecturally executed and the condition code check pass. <br /></td></tr>
176 <tr class="separator:gab717347b1c3601cffb9c99b43b2a45c5"><td class="memSeparator" colspan="2"> </td></tr>
177 <tr class="memitem:ga45d5ea86fdc015f4fc100462150c92da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga45d5ea86fdc015f4fc100462150c92da">ARM_PMU_UNALIGNED_LDST_RETIRED</a>   0x000F</td></tr>
178 <tr class="memdesc:ga45d5ea86fdc015f4fc100462150c92da"><td class="mdescLeft"> </td><td class="mdescRight">Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass. <br /></td></tr>
179 <tr class="separator:ga45d5ea86fdc015f4fc100462150c92da"><td class="memSeparator" colspan="2"> </td></tr>
180 <tr class="memitem:gabfa921c85a61f0a21c9bee289e63c102"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gabfa921c85a61f0a21c9bee289e63c102">ARM_PMU_BR_MIS_PRED</a>   0x0010</td></tr>
181 <tr class="memdesc:gabfa921c85a61f0a21c9bee289e63c102"><td class="mdescLeft"> </td><td class="mdescRight">Mispredicted or not predicted branch speculatively executed. <br /></td></tr>
182 <tr class="separator:gabfa921c85a61f0a21c9bee289e63c102"><td class="memSeparator" colspan="2"> </td></tr>
183 <tr class="memitem:ga550d524d435a653b2f46acc1380a5ace"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga550d524d435a653b2f46acc1380a5ace">ARM_PMU_CPU_CYCLES</a>   0x0011</td></tr>
184 <tr class="memdesc:ga550d524d435a653b2f46acc1380a5ace"><td class="mdescLeft"> </td><td class="mdescRight">Cycle. <br /></td></tr>
185 <tr class="separator:ga550d524d435a653b2f46acc1380a5ace"><td class="memSeparator" colspan="2"> </td></tr>
186 <tr class="memitem:ga60ccf42eae576e2fde3b9e17a8defeaa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga60ccf42eae576e2fde3b9e17a8defeaa">ARM_PMU_BR_PRED</a>   0x0012</td></tr>
187 <tr class="memdesc:ga60ccf42eae576e2fde3b9e17a8defeaa"><td class="mdescLeft"> </td><td class="mdescRight">Predictable branch speculatively executed. <br /></td></tr>
188 <tr class="separator:ga60ccf42eae576e2fde3b9e17a8defeaa"><td class="memSeparator" colspan="2"> </td></tr>
189 <tr class="memitem:gab3852c2b3d59af106b9db7ea2c20c367"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab3852c2b3d59af106b9db7ea2c20c367">ARM_PMU_MEM_ACCESS</a>   0x0013</td></tr>
190 <tr class="memdesc:gab3852c2b3d59af106b9db7ea2c20c367"><td class="mdescLeft"> </td><td class="mdescRight">Data memory access. <br /></td></tr>
191 <tr class="separator:gab3852c2b3d59af106b9db7ea2c20c367"><td class="memSeparator" colspan="2"> </td></tr>
192 <tr class="memitem:gaf8e89b2b098e6bec5916517346925ce2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf8e89b2b098e6bec5916517346925ce2">ARM_PMU_L1I_CACHE</a>   0x0014</td></tr>
193 <tr class="memdesc:gaf8e89b2b098e6bec5916517346925ce2"><td class="mdescLeft"> </td><td class="mdescRight">Level 1 instruction cache access. <br /></td></tr>
194 <tr class="separator:gaf8e89b2b098e6bec5916517346925ce2"><td class="memSeparator" colspan="2"> </td></tr>
195 <tr class="memitem:ga27d1b8b2c37ae0ae41781880ed3893d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga27d1b8b2c37ae0ae41781880ed3893d0">ARM_PMU_L1D_CACHE_WB</a>   0x0015</td></tr>
196 <tr class="memdesc:ga27d1b8b2c37ae0ae41781880ed3893d0"><td class="mdescLeft"> </td><td class="mdescRight">Level 1 data cache write-back. <br /></td></tr>
197 <tr class="separator:ga27d1b8b2c37ae0ae41781880ed3893d0"><td class="memSeparator" colspan="2"> </td></tr>
198 <tr class="memitem:gafb1e1f86d091ccb735858769c700e289"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gafb1e1f86d091ccb735858769c700e289">ARM_PMU_L2D_CACHE</a>   0x0016</td></tr>
199 <tr class="memdesc:gafb1e1f86d091ccb735858769c700e289"><td class="mdescLeft"> </td><td class="mdescRight">Level 2 data cache access. <br /></td></tr>
200 <tr class="separator:gafb1e1f86d091ccb735858769c700e289"><td class="memSeparator" colspan="2"> </td></tr>
201 <tr class="memitem:gaeb414c1b0375022abc2502ab503a3284"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaeb414c1b0375022abc2502ab503a3284">ARM_PMU_L2D_CACHE_REFILL</a>   0x0017</td></tr>
202 <tr class="memdesc:gaeb414c1b0375022abc2502ab503a3284"><td class="mdescLeft"> </td><td class="mdescRight">Level 2 data cache refill. <br /></td></tr>
203 <tr class="separator:gaeb414c1b0375022abc2502ab503a3284"><td class="memSeparator" colspan="2"> </td></tr>
204 <tr class="memitem:ga1a0c4a1990eeed88edc3e1e0c4b1aca0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga1a0c4a1990eeed88edc3e1e0c4b1aca0">ARM_PMU_L2D_CACHE_WB</a>   0x0018</td></tr>
205 <tr class="memdesc:ga1a0c4a1990eeed88edc3e1e0c4b1aca0"><td class="mdescLeft"> </td><td class="mdescRight">Level 2 data cache write-back. <br /></td></tr>
206 <tr class="separator:ga1a0c4a1990eeed88edc3e1e0c4b1aca0"><td class="memSeparator" colspan="2"> </td></tr>
207 <tr class="memitem:gaa681d3db56b42775093869b8fdf1abb9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaa681d3db56b42775093869b8fdf1abb9">ARM_PMU_BUS_ACCESS</a>   0x0019</td></tr>
208 <tr class="memdesc:gaa681d3db56b42775093869b8fdf1abb9"><td class="mdescLeft"> </td><td class="mdescRight">Bus access. <br /></td></tr>
209 <tr class="separator:gaa681d3db56b42775093869b8fdf1abb9"><td class="memSeparator" colspan="2"> </td></tr>
210 <tr class="memitem:ga2c8d23cc64e87b2044bb39bf8d0bc1b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga2c8d23cc64e87b2044bb39bf8d0bc1b1">ARM_PMU_MEMORY_ERROR</a>   0x001A</td></tr>
211 <tr class="memdesc:ga2c8d23cc64e87b2044bb39bf8d0bc1b1"><td class="mdescLeft"> </td><td class="mdescRight">Local memory error. <br /></td></tr>
212 <tr class="separator:ga2c8d23cc64e87b2044bb39bf8d0bc1b1"><td class="memSeparator" colspan="2"> </td></tr>
213 <tr class="memitem:gaf7bad54617ace5c2fb48bc2e8aebf9c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf7bad54617ace5c2fb48bc2e8aebf9c7">ARM_PMU_INST_SPEC</a>   0x001B</td></tr>
214 <tr class="memdesc:gaf7bad54617ace5c2fb48bc2e8aebf9c7"><td class="mdescLeft"> </td><td class="mdescRight">Instruction speculatively executed. <br /></td></tr>
215 <tr class="separator:gaf7bad54617ace5c2fb48bc2e8aebf9c7"><td class="memSeparator" colspan="2"> </td></tr>
216 <tr class="memitem:gae4c955416707f44f066ffd2560b9ae4c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gae4c955416707f44f066ffd2560b9ae4c">ARM_PMU_BUS_CYCLES</a>   0x001D</td></tr>
217 <tr class="memdesc:gae4c955416707f44f066ffd2560b9ae4c"><td class="mdescLeft"> </td><td class="mdescRight">Bus cycles. <br /></td></tr>
218 <tr class="separator:gae4c955416707f44f066ffd2560b9ae4c"><td class="memSeparator" colspan="2"> </td></tr>
219 <tr class="memitem:gaca14907c5a1e1f9915159bc4cf323cf0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaca14907c5a1e1f9915159bc4cf323cf0">ARM_PMU_CHAIN</a>   0x001E</td></tr>
220 <tr class="memdesc:gaca14907c5a1e1f9915159bc4cf323cf0"><td class="mdescLeft"> </td><td class="mdescRight">For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE. <br /></td></tr>
221 <tr class="separator:gaca14907c5a1e1f9915159bc4cf323cf0"><td class="memSeparator" colspan="2"> </td></tr>
222 <tr class="memitem:gab55334c8510cb30c4c750913f6eb6279"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab55334c8510cb30c4c750913f6eb6279">ARM_PMU_L1D_CACHE_ALLOCATE</a>   0x001F</td></tr>
223 <tr class="memdesc:gab55334c8510cb30c4c750913f6eb6279"><td class="mdescLeft"> </td><td class="mdescRight">Level 1 data cache allocation without refill. <br /></td></tr>
224 <tr class="separator:gab55334c8510cb30c4c750913f6eb6279"><td class="memSeparator" colspan="2"> </td></tr>
225 <tr class="memitem:gaad08dcded491bf257d223e4171af41cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaad08dcded491bf257d223e4171af41cc">ARM_PMU_L2D_CACHE_ALLOCATE</a>   0x0020</td></tr>
226 <tr class="memdesc:gaad08dcded491bf257d223e4171af41cc"><td class="mdescLeft"> </td><td class="mdescRight">Level 2 data cache allocation without refill. <br /></td></tr>
227 <tr class="separator:gaad08dcded491bf257d223e4171af41cc"><td class="memSeparator" colspan="2"> </td></tr>
228 <tr class="memitem:gab3b505a8bcc2b2885626d2f2cd542b73"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab3b505a8bcc2b2885626d2f2cd542b73">ARM_PMU_BR_RETIRED</a>   0x0021</td></tr>
229 <tr class="memdesc:gab3b505a8bcc2b2885626d2f2cd542b73"><td class="mdescLeft"> </td><td class="mdescRight">Branch instruction architecturally executed. <br /></td></tr>
230 <tr class="separator:gab3b505a8bcc2b2885626d2f2cd542b73"><td class="memSeparator" colspan="2"> </td></tr>
231 <tr class="memitem:gae12baa616c5f0cdd081231fcf8cdad68"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gae12baa616c5f0cdd081231fcf8cdad68">ARM_PMU_BR_MIS_PRED_RETIRED</a>   0x0022</td></tr>
232 <tr class="memdesc:gae12baa616c5f0cdd081231fcf8cdad68"><td class="mdescLeft"> </td><td class="mdescRight">Mispredicted branch instruction architecturally executed. <br /></td></tr>
233 <tr class="separator:gae12baa616c5f0cdd081231fcf8cdad68"><td class="memSeparator" colspan="2"> </td></tr>
234 <tr class="memitem:ga5b068593baa831348664dfa7d44f5483"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga5b068593baa831348664dfa7d44f5483">ARM_PMU_STALL_FRONTEND</a>   0x0023</td></tr>
235 <tr class="memdesc:ga5b068593baa831348664dfa7d44f5483"><td class="mdescLeft"> </td><td class="mdescRight">No operation issued because of the frontend. <br /></td></tr>
236 <tr class="separator:ga5b068593baa831348664dfa7d44f5483"><td class="memSeparator" colspan="2"> </td></tr>
237 <tr class="memitem:ga8737bee352820bd7d1bc8e5e4260143c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8737bee352820bd7d1bc8e5e4260143c">ARM_PMU_STALL_BACKEND</a>   0x0024</td></tr>
238 <tr class="memdesc:ga8737bee352820bd7d1bc8e5e4260143c"><td class="mdescLeft"> </td><td class="mdescRight">No operation issued because of the backend. <br /></td></tr>
239 <tr class="separator:ga8737bee352820bd7d1bc8e5e4260143c"><td class="memSeparator" colspan="2"> </td></tr>
240 <tr class="memitem:ga3406498b2c17ca080ebd68cc40d9630e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga3406498b2c17ca080ebd68cc40d9630e">ARM_PMU_L2I_CACHE</a>   0x0027</td></tr>
241 <tr class="memdesc:ga3406498b2c17ca080ebd68cc40d9630e"><td class="mdescLeft"> </td><td class="mdescRight">Level 2 instruction cache access. <br /></td></tr>
242 <tr class="separator:ga3406498b2c17ca080ebd68cc40d9630e"><td class="memSeparator" colspan="2"> </td></tr>
243 <tr class="memitem:gaa18cee03802b46076e9ab66fd0a7c61d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaa18cee03802b46076e9ab66fd0a7c61d">ARM_PMU_L2I_CACHE_REFILL</a>   0x0028</td></tr>
244 <tr class="memdesc:gaa18cee03802b46076e9ab66fd0a7c61d"><td class="mdescLeft"> </td><td class="mdescRight">Level 2 instruction cache refill. <br /></td></tr>
245 <tr class="separator:gaa18cee03802b46076e9ab66fd0a7c61d"><td class="memSeparator" colspan="2"> </td></tr>
246 <tr class="memitem:gac11cbc6849dbad7bd8b64ab6e2a3f8d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gac11cbc6849dbad7bd8b64ab6e2a3f8d5">ARM_PMU_L3D_CACHE_ALLOCATE</a>   0x0029</td></tr>
247 <tr class="memdesc:gac11cbc6849dbad7bd8b64ab6e2a3f8d5"><td class="mdescLeft"> </td><td class="mdescRight">Level 3 data cache allocation without refill. <br /></td></tr>
248 <tr class="separator:gac11cbc6849dbad7bd8b64ab6e2a3f8d5"><td class="memSeparator" colspan="2"> </td></tr>
249 <tr class="memitem:gafe99db0693125100272247c147fb3b02"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gafe99db0693125100272247c147fb3b02">ARM_PMU_L3D_CACHE_REFILL</a>   0x002A</td></tr>
250 <tr class="memdesc:gafe99db0693125100272247c147fb3b02"><td class="mdescLeft"> </td><td class="mdescRight">Level 3 data cache refill. <br /></td></tr>
251 <tr class="separator:gafe99db0693125100272247c147fb3b02"><td class="memSeparator" colspan="2"> </td></tr>
252 <tr class="memitem:ga4e96b5a6fb13c657e78da342a02db200"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga4e96b5a6fb13c657e78da342a02db200">ARM_PMU_L3D_CACHE</a>   0x002B</td></tr>
253 <tr class="memdesc:ga4e96b5a6fb13c657e78da342a02db200"><td class="mdescLeft"> </td><td class="mdescRight">Level 3 data cache access. <br /></td></tr>
254 <tr class="separator:ga4e96b5a6fb13c657e78da342a02db200"><td class="memSeparator" colspan="2"> </td></tr>
255 <tr class="memitem:gab823f95f7ac8196a208d12381b1b2a11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab823f95f7ac8196a208d12381b1b2a11">ARM_PMU_L3D_CACHE_WB</a>   0x002C</td></tr>
256 <tr class="memdesc:gab823f95f7ac8196a208d12381b1b2a11"><td class="mdescLeft"> </td><td class="mdescRight">Level 3 data cache write-back. <br /></td></tr>
257 <tr class="separator:gab823f95f7ac8196a208d12381b1b2a11"><td class="memSeparator" colspan="2"> </td></tr>
258 <tr class="memitem:ga902562d8161fffd45726dc4cc8727545"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga902562d8161fffd45726dc4cc8727545">ARM_PMU_LL_CACHE_RD</a>   0x0036</td></tr>
259 <tr class="memdesc:ga902562d8161fffd45726dc4cc8727545"><td class="mdescLeft"> </td><td class="mdescRight">Last level data cache read. <br /></td></tr>
260 <tr class="separator:ga902562d8161fffd45726dc4cc8727545"><td class="memSeparator" colspan="2"> </td></tr>
261 <tr class="memitem:ga6979efa69af7d0e62cc3e2f88b0155b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga6979efa69af7d0e62cc3e2f88b0155b8">ARM_PMU_LL_CACHE_MISS_RD</a>   0x0037</td></tr>
262 <tr class="memdesc:ga6979efa69af7d0e62cc3e2f88b0155b8"><td class="mdescLeft"> </td><td class="mdescRight">Last level data cache read miss. <br /></td></tr>
263 <tr class="separator:ga6979efa69af7d0e62cc3e2f88b0155b8"><td class="memSeparator" colspan="2"> </td></tr>
264 <tr class="memitem:ga4687d5d7efc6f49db2db9acc25b590f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga4687d5d7efc6f49db2db9acc25b590f6">ARM_PMU_L1D_CACHE_MISS_RD</a>   0x0039</td></tr>
265 <tr class="memdesc:ga4687d5d7efc6f49db2db9acc25b590f6"><td class="mdescLeft"> </td><td class="mdescRight">Level 1 data cache read miss. <br /></td></tr>
266 <tr class="separator:ga4687d5d7efc6f49db2db9acc25b590f6"><td class="memSeparator" colspan="2"> </td></tr>
267 <tr class="memitem:ga2fe9d3ea67ce833bd6323e4ce1a4e894"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga2fe9d3ea67ce833bd6323e4ce1a4e894">ARM_PMU_OP_COMPLETE</a>   0x003A</td></tr>
268 <tr class="memdesc:ga2fe9d3ea67ce833bd6323e4ce1a4e894"><td class="mdescLeft"> </td><td class="mdescRight">Operation retired. <br /></td></tr>
269 <tr class="separator:ga2fe9d3ea67ce833bd6323e4ce1a4e894"><td class="memSeparator" colspan="2"> </td></tr>
270 <tr class="memitem:ga6c59149e9b1754987b44b62092bc9f09"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga6c59149e9b1754987b44b62092bc9f09">ARM_PMU_OP_SPEC</a>   0x003B</td></tr>
271 <tr class="memdesc:ga6c59149e9b1754987b44b62092bc9f09"><td class="mdescLeft"> </td><td class="mdescRight">Operation speculatively executed. <br /></td></tr>
272 <tr class="separator:ga6c59149e9b1754987b44b62092bc9f09"><td class="memSeparator" colspan="2"> </td></tr>
273 <tr class="memitem:ga8bf75efa06a125ee2dfa9a130e7ba9a8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8bf75efa06a125ee2dfa9a130e7ba9a8">ARM_PMU_STALL</a>   0x003C</td></tr>
274 <tr class="memdesc:ga8bf75efa06a125ee2dfa9a130e7ba9a8"><td class="mdescLeft"> </td><td class="mdescRight">Stall cycle for instruction or operation not sent for execution. <br /></td></tr>
275 <tr class="separator:ga8bf75efa06a125ee2dfa9a130e7ba9a8"><td class="memSeparator" colspan="2"> </td></tr>
276 <tr class="memitem:ga9700ec74727a9fe3cd4cd40736628a23"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga9700ec74727a9fe3cd4cd40736628a23">ARM_PMU_STALL_OP_BACKEND</a>   0x003D</td></tr>
277 <tr class="memdesc:ga9700ec74727a9fe3cd4cd40736628a23"><td class="mdescLeft"> </td><td class="mdescRight">Stall cycle for instruction or operation not sent for execution due to pipeline backend. <br /></td></tr>
278 <tr class="separator:ga9700ec74727a9fe3cd4cd40736628a23"><td class="memSeparator" colspan="2"> </td></tr>
279 <tr class="memitem:ga69cfd3558cf6c6f3bb621ee75430427c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga69cfd3558cf6c6f3bb621ee75430427c">ARM_PMU_STALL_OP_FRONTEND</a>   0x003E</td></tr>
280 <tr class="memdesc:ga69cfd3558cf6c6f3bb621ee75430427c"><td class="mdescLeft"> </td><td class="mdescRight">Stall cycle for instruction or operation not sent for execution due to pipeline frontend. <br /></td></tr>
281 <tr class="separator:ga69cfd3558cf6c6f3bb621ee75430427c"><td class="memSeparator" colspan="2"> </td></tr>
282 <tr class="memitem:ga197b491f691110fb52aef4291782b6ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga197b491f691110fb52aef4291782b6ab">ARM_PMU_STALL_OP</a>   0x003F</td></tr>
283 <tr class="memdesc:ga197b491f691110fb52aef4291782b6ab"><td class="mdescLeft"> </td><td class="mdescRight">Instruction or operation slots not occupied each cycle. <br /></td></tr>
284 <tr class="separator:ga197b491f691110fb52aef4291782b6ab"><td class="memSeparator" colspan="2"> </td></tr>
285 <tr class="memitem:gaf4236dfbcb4550d3cc98caee837e8e77"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf4236dfbcb4550d3cc98caee837e8e77">ARM_PMU_L1D_CACHE_RD</a>   0x0040</td></tr>
286 <tr class="memdesc:gaf4236dfbcb4550d3cc98caee837e8e77"><td class="mdescLeft"> </td><td class="mdescRight">Level 1 data cache read. <br /></td></tr>
287 <tr class="separator:gaf4236dfbcb4550d3cc98caee837e8e77"><td class="memSeparator" colspan="2"> </td></tr>
288 <tr class="memitem:ga345461506c990125b1f2cbc62e3be22f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga345461506c990125b1f2cbc62e3be22f">ARM_PMU_LE_RETIRED</a>   0x0100</td></tr>
289 <tr class="memdesc:ga345461506c990125b1f2cbc62e3be22f"><td class="mdescLeft"> </td><td class="mdescRight">Loop end instruction executed. <br /></td></tr>
290 <tr class="separator:ga345461506c990125b1f2cbc62e3be22f"><td class="memSeparator" colspan="2"> </td></tr>
291 <tr class="memitem:ga6a1d9f84bda091e96843665ff3913b50"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga6a1d9f84bda091e96843665ff3913b50">ARM_PMU_LE_SPEC</a>   0x0101</td></tr>
292 <tr class="memdesc:ga6a1d9f84bda091e96843665ff3913b50"><td class="mdescLeft"> </td><td class="mdescRight">Loop end instruction speculatively executed. <br /></td></tr>
293 <tr class="separator:ga6a1d9f84bda091e96843665ff3913b50"><td class="memSeparator" colspan="2"> </td></tr>
294 <tr class="memitem:gab8570f46393e3e44bb118591d33723f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab8570f46393e3e44bb118591d33723f4">ARM_PMU_BF_RETIRED</a>   0x0104</td></tr>
295 <tr class="memdesc:gab8570f46393e3e44bb118591d33723f4"><td class="mdescLeft"> </td><td class="mdescRight">Branch future instruction architecturally executed and condition code check pass. <br /></td></tr>
296 <tr class="separator:gab8570f46393e3e44bb118591d33723f4"><td class="memSeparator" colspan="2"> </td></tr>
297 <tr class="memitem:ga6b1e4823d8b45678a29a5f54b859d4e3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga6b1e4823d8b45678a29a5f54b859d4e3">ARM_PMU_BF_SPEC</a>   0x0105</td></tr>
298 <tr class="memdesc:ga6b1e4823d8b45678a29a5f54b859d4e3"><td class="mdescLeft"> </td><td class="mdescRight">Branch future instruction speculatively executed and condition code check pass. <br /></td></tr>
299 <tr class="separator:ga6b1e4823d8b45678a29a5f54b859d4e3"><td class="memSeparator" colspan="2"> </td></tr>
300 <tr class="memitem:ga8b5641a3cb0e922a2b4e16ec14052861"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8b5641a3cb0e922a2b4e16ec14052861">ARM_PMU_LE_CANCEL</a>   0x0108</td></tr>
301 <tr class="memdesc:ga8b5641a3cb0e922a2b4e16ec14052861"><td class="mdescLeft"> </td><td class="mdescRight">Loop end instruction not taken. <br /></td></tr>
302 <tr class="separator:ga8b5641a3cb0e922a2b4e16ec14052861"><td class="memSeparator" colspan="2"> </td></tr>
303 <tr class="memitem:gaf2e0a38b7c0d63d1194f08478781a3f0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf2e0a38b7c0d63d1194f08478781a3f0">ARM_PMU_BF_CANCEL</a>   0x0109</td></tr>
304 <tr class="memdesc:gaf2e0a38b7c0d63d1194f08478781a3f0"><td class="mdescLeft"> </td><td class="mdescRight">Branch future instruction not taken. <br /></td></tr>
305 <tr class="separator:gaf2e0a38b7c0d63d1194f08478781a3f0"><td class="memSeparator" colspan="2"> </td></tr>
306 <tr class="memitem:gad3ba2effbe303ca3fafdbc022fe206c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gad3ba2effbe303ca3fafdbc022fe206c1">ARM_PMU_SE_CALL_S</a>   0x0114</td></tr>
307 <tr class="memdesc:gad3ba2effbe303ca3fafdbc022fe206c1"><td class="mdescLeft"> </td><td class="mdescRight">Call to secure function, resulting in Security state change. <br /></td></tr>
308 <tr class="separator:gad3ba2effbe303ca3fafdbc022fe206c1"><td class="memSeparator" colspan="2"> </td></tr>
309 <tr class="memitem:gaaae2c32a8ecd36b59ac98cf8e23b3cab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaaae2c32a8ecd36b59ac98cf8e23b3cab">ARM_PMU_SE_CALL_NS</a>   0x0115</td></tr>
310 <tr class="memdesc:gaaae2c32a8ecd36b59ac98cf8e23b3cab"><td class="mdescLeft"> </td><td class="mdescRight">Call to non-secure function, resulting in Security state change. <br /></td></tr>
311 <tr class="separator:gaaae2c32a8ecd36b59ac98cf8e23b3cab"><td class="memSeparator" colspan="2"> </td></tr>
312 <tr class="memitem:ga18d640aa04b97c7d287e8745f6f2b23d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga18d640aa04b97c7d287e8745f6f2b23d">ARM_PMU_DWT_CMPMATCH0</a>   0x0118</td></tr>
313 <tr class="memdesc:ga18d640aa04b97c7d287e8745f6f2b23d"><td class="mdescLeft"> </td><td class="mdescRight">DWT comparator 0 match. <br /></td></tr>
314 <tr class="separator:ga18d640aa04b97c7d287e8745f6f2b23d"><td class="memSeparator" colspan="2"> </td></tr>
315 <tr class="memitem:ga5dc6eb2be1ff1afe9cbd59af4f6078ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga5dc6eb2be1ff1afe9cbd59af4f6078ab">ARM_PMU_DWT_CMPMATCH1</a>   0x0119</td></tr>
316 <tr class="memdesc:ga5dc6eb2be1ff1afe9cbd59af4f6078ab"><td class="mdescLeft"> </td><td class="mdescRight">DWT comparator 1 match. <br /></td></tr>
317 <tr class="separator:ga5dc6eb2be1ff1afe9cbd59af4f6078ab"><td class="memSeparator" colspan="2"> </td></tr>
318 <tr class="memitem:ga58a4815dba8886088b9cac7b934a332d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga58a4815dba8886088b9cac7b934a332d">ARM_PMU_DWT_CMPMATCH2</a>   0x011A</td></tr>
319 <tr class="memdesc:ga58a4815dba8886088b9cac7b934a332d"><td class="mdescLeft"> </td><td class="mdescRight">DWT comparator 2 match. <br /></td></tr>
320 <tr class="separator:ga58a4815dba8886088b9cac7b934a332d"><td class="memSeparator" colspan="2"> </td></tr>
321 <tr class="memitem:ga594337c6f3c88d8317203a8cd6f9814a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga594337c6f3c88d8317203a8cd6f9814a">ARM_PMU_DWT_CMPMATCH3</a>   0x011B</td></tr>
322 <tr class="memdesc:ga594337c6f3c88d8317203a8cd6f9814a"><td class="mdescLeft"> </td><td class="mdescRight">DWT comparator 3 match. <br /></td></tr>
323 <tr class="separator:ga594337c6f3c88d8317203a8cd6f9814a"><td class="memSeparator" colspan="2"> </td></tr>
324 <tr class="memitem:ga3c1006bed2fb82b0749386261b397727"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga3c1006bed2fb82b0749386261b397727">ARM_PMU_MVE_INST_RETIRED</a>   0x0200</td></tr>
325 <tr class="memdesc:ga3c1006bed2fb82b0749386261b397727"><td class="mdescLeft"> </td><td class="mdescRight">MVE instruction architecturally executed. <br /></td></tr>
326 <tr class="separator:ga3c1006bed2fb82b0749386261b397727"><td class="memSeparator" colspan="2"> </td></tr>
327 <tr class="memitem:ga1e276b6872345eb3b043626a11f235c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga1e276b6872345eb3b043626a11f235c6">ARM_PMU_MVE_INST_SPEC</a>   0x0201</td></tr>
328 <tr class="memdesc:ga1e276b6872345eb3b043626a11f235c6"><td class="mdescLeft"> </td><td class="mdescRight">MVE instruction speculatively executed. <br /></td></tr>
329 <tr class="separator:ga1e276b6872345eb3b043626a11f235c6"><td class="memSeparator" colspan="2"> </td></tr>
330 <tr class="memitem:ga268b0bcbd30e8a928bd0f331fdf53ccf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga268b0bcbd30e8a928bd0f331fdf53ccf">ARM_PMU_MVE_FP_RETIRED</a>   0x0204</td></tr>
331 <tr class="memdesc:ga268b0bcbd30e8a928bd0f331fdf53ccf"><td class="mdescLeft"> </td><td class="mdescRight">MVE floating-point instruction architecturally executed. <br /></td></tr>
332 <tr class="separator:ga268b0bcbd30e8a928bd0f331fdf53ccf"><td class="memSeparator" colspan="2"> </td></tr>
333 <tr class="memitem:gadf9cfd45b59acfc314ebc814a1bcdccd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gadf9cfd45b59acfc314ebc814a1bcdccd">ARM_PMU_MVE_FP_SPEC</a>   0x0205</td></tr>
334 <tr class="memdesc:gadf9cfd45b59acfc314ebc814a1bcdccd"><td class="mdescLeft"> </td><td class="mdescRight">MVE floating-point instruction speculatively executed. <br /></td></tr>
335 <tr class="separator:gadf9cfd45b59acfc314ebc814a1bcdccd"><td class="memSeparator" colspan="2"> </td></tr>
336 <tr class="memitem:gaa4c408a006a04e95ade26922669b6695"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaa4c408a006a04e95ade26922669b6695">ARM_PMU_MVE_FP_HP_RETIRED</a>   0x0208</td></tr>
337 <tr class="memdesc:gaa4c408a006a04e95ade26922669b6695"><td class="mdescLeft"> </td><td class="mdescRight">MVE half-precision floating-point instruction architecturally executed. <br /></td></tr>
338 <tr class="separator:gaa4c408a006a04e95ade26922669b6695"><td class="memSeparator" colspan="2"> </td></tr>
339 <tr class="memitem:gaf01d187b0cbf418d1fac55dd0ddd0827"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf01d187b0cbf418d1fac55dd0ddd0827">ARM_PMU_MVE_FP_HP_SPEC</a>   0x0209</td></tr>
340 <tr class="memdesc:gaf01d187b0cbf418d1fac55dd0ddd0827"><td class="mdescLeft"> </td><td class="mdescRight">MVE half-precision floating-point instruction speculatively executed. <br /></td></tr>
341 <tr class="separator:gaf01d187b0cbf418d1fac55dd0ddd0827"><td class="memSeparator" colspan="2"> </td></tr>
342 <tr class="memitem:gab21171c50ebd1f304b11260edd015f52"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab21171c50ebd1f304b11260edd015f52">ARM_PMU_MVE_FP_SP_RETIRED</a>   0x020C</td></tr>
343 <tr class="memdesc:gab21171c50ebd1f304b11260edd015f52"><td class="mdescLeft"> </td><td class="mdescRight">MVE single-precision floating-point instruction architecturally executed. <br /></td></tr>
344 <tr class="separator:gab21171c50ebd1f304b11260edd015f52"><td class="memSeparator" colspan="2"> </td></tr>
345 <tr class="memitem:gae69e310892661af852ca2d4ec947d18a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gae69e310892661af852ca2d4ec947d18a">ARM_PMU_MVE_FP_SP_SPEC</a>   0x020D</td></tr>
346 <tr class="memdesc:gae69e310892661af852ca2d4ec947d18a"><td class="mdescLeft"> </td><td class="mdescRight">MVE single-precision floating-point instruction speculatively executed. <br /></td></tr>
347 <tr class="separator:gae69e310892661af852ca2d4ec947d18a"><td class="memSeparator" colspan="2"> </td></tr>
348 <tr class="memitem:gac2dc7d92627b3caa391725a3f080288c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gac2dc7d92627b3caa391725a3f080288c">ARM_PMU_MVE_FP_MAC_RETIRED</a>   0x0214</td></tr>
349 <tr class="memdesc:gac2dc7d92627b3caa391725a3f080288c"><td class="mdescLeft"> </td><td class="mdescRight">MVE floating-point multiply or multiply-accumulate instruction architecturally executed. <br /></td></tr>
350 <tr class="separator:gac2dc7d92627b3caa391725a3f080288c"><td class="memSeparator" colspan="2"> </td></tr>
351 <tr class="memitem:gaf5302b3278a862c9264171955328a59a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf5302b3278a862c9264171955328a59a">ARM_PMU_MVE_FP_MAC_SPEC</a>   0x0215</td></tr>
352 <tr class="memdesc:gaf5302b3278a862c9264171955328a59a"><td class="mdescLeft"> </td><td class="mdescRight">MVE floating-point multiply or multiply-accumulate instruction speculatively executed. <br /></td></tr>
353 <tr class="separator:gaf5302b3278a862c9264171955328a59a"><td class="memSeparator" colspan="2"> </td></tr>
354 <tr class="memitem:ga5e3afafa91ebaeac0469a19ebb54719c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga5e3afafa91ebaeac0469a19ebb54719c">ARM_PMU_MVE_INT_RETIRED</a>   0x0224</td></tr>
355 <tr class="memdesc:ga5e3afafa91ebaeac0469a19ebb54719c"><td class="mdescLeft"> </td><td class="mdescRight">MVE integer instruction architecturally executed. <br /></td></tr>
356 <tr class="separator:ga5e3afafa91ebaeac0469a19ebb54719c"><td class="memSeparator" colspan="2"> </td></tr>
357 <tr class="memitem:ga16ed0bb1bb4718da93c41238da652d33"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga16ed0bb1bb4718da93c41238da652d33">ARM_PMU_MVE_INT_SPEC</a>   0x0225</td></tr>
358 <tr class="memdesc:ga16ed0bb1bb4718da93c41238da652d33"><td class="mdescLeft"> </td><td class="mdescRight">MVE integer instruction speculatively executed. <br /></td></tr>
359 <tr class="separator:ga16ed0bb1bb4718da93c41238da652d33"><td class="memSeparator" colspan="2"> </td></tr>
360 <tr class="memitem:ga9248c93a3f19fddc93d3804a06f7238a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga9248c93a3f19fddc93d3804a06f7238a">ARM_PMU_MVE_INT_MAC_RETIRED</a>   0x0228</td></tr>
361 <tr class="memdesc:ga9248c93a3f19fddc93d3804a06f7238a"><td class="mdescLeft"> </td><td class="mdescRight">MVE multiply or multiply-accumulate instruction architecturally executed. <br /></td></tr>
362 <tr class="separator:ga9248c93a3f19fddc93d3804a06f7238a"><td class="memSeparator" colspan="2"> </td></tr>
363 <tr class="memitem:ga7036f00faa9183ae450a3e4d9d6f2bbf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga7036f00faa9183ae450a3e4d9d6f2bbf">ARM_PMU_MVE_INT_MAC_SPEC</a>   0x0229</td></tr>
364 <tr class="memdesc:ga7036f00faa9183ae450a3e4d9d6f2bbf"><td class="mdescLeft"> </td><td class="mdescRight">MVE multiply or multiply-accumulate instruction speculatively executed. <br /></td></tr>
365 <tr class="separator:ga7036f00faa9183ae450a3e4d9d6f2bbf"><td class="memSeparator" colspan="2"> </td></tr>
366 <tr class="memitem:ga7d7d465a6c64400c49f93b6c8152296f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga7d7d465a6c64400c49f93b6c8152296f">ARM_PMU_MVE_LDST_RETIRED</a>   0x0238</td></tr>
367 <tr class="memdesc:ga7d7d465a6c64400c49f93b6c8152296f"><td class="mdescLeft"> </td><td class="mdescRight">MVE load or store instruction architecturally executed. <br /></td></tr>
368 <tr class="separator:ga7d7d465a6c64400c49f93b6c8152296f"><td class="memSeparator" colspan="2"> </td></tr>
369 <tr class="memitem:gaa98a18c06bd13daf2df6f89219ec68d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaa98a18c06bd13daf2df6f89219ec68d5">ARM_PMU_MVE_LDST_SPEC</a>   0x0239</td></tr>
370 <tr class="memdesc:gaa98a18c06bd13daf2df6f89219ec68d5"><td class="mdescLeft"> </td><td class="mdescRight">MVE load or store instruction speculatively executed. <br /></td></tr>
371 <tr class="separator:gaa98a18c06bd13daf2df6f89219ec68d5"><td class="memSeparator" colspan="2"> </td></tr>
372 <tr class="memitem:gaa3379a51350a2fda8d8ab6d7795baa7a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaa3379a51350a2fda8d8ab6d7795baa7a">ARM_PMU_MVE_LD_RETIRED</a>   0x023C</td></tr>
373 <tr class="memdesc:gaa3379a51350a2fda8d8ab6d7795baa7a"><td class="mdescLeft"> </td><td class="mdescRight">MVE load instruction architecturally executed. <br /></td></tr>
374 <tr class="separator:gaa3379a51350a2fda8d8ab6d7795baa7a"><td class="memSeparator" colspan="2"> </td></tr>
375 <tr class="memitem:ga78a6f89ab30ed01f7d8388eda697b4f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga78a6f89ab30ed01f7d8388eda697b4f8">ARM_PMU_MVE_LD_SPEC</a>   0x023D</td></tr>
376 <tr class="memdesc:ga78a6f89ab30ed01f7d8388eda697b4f8"><td class="mdescLeft"> </td><td class="mdescRight">MVE load instruction speculatively executed. <br /></td></tr>
377 <tr class="separator:ga78a6f89ab30ed01f7d8388eda697b4f8"><td class="memSeparator" colspan="2"> </td></tr>
378 <tr class="memitem:gad8d0079977fa97de4ee263703f1b2908"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gad8d0079977fa97de4ee263703f1b2908">ARM_PMU_MVE_ST_RETIRED</a>   0x0240</td></tr>
379 <tr class="memdesc:gad8d0079977fa97de4ee263703f1b2908"><td class="mdescLeft"> </td><td class="mdescRight">MVE store instruction architecturally executed. <br /></td></tr>
380 <tr class="separator:gad8d0079977fa97de4ee263703f1b2908"><td class="memSeparator" colspan="2"> </td></tr>
381 <tr class="memitem:gabd3984d299b5416aac8d630722680c55"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gabd3984d299b5416aac8d630722680c55">ARM_PMU_MVE_ST_SPEC</a>   0x0241</td></tr>
382 <tr class="memdesc:gabd3984d299b5416aac8d630722680c55"><td class="mdescLeft"> </td><td class="mdescRight">MVE store instruction speculatively executed. <br /></td></tr>
383 <tr class="separator:gabd3984d299b5416aac8d630722680c55"><td class="memSeparator" colspan="2"> </td></tr>
384 <tr class="memitem:ga8acf6a66c63798b76608caf52c96658d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8acf6a66c63798b76608caf52c96658d">ARM_PMU_MVE_LDST_CONTIG_RETIRED</a>   0x0244</td></tr>
385 <tr class="memdesc:ga8acf6a66c63798b76608caf52c96658d"><td class="mdescLeft"> </td><td class="mdescRight">MVE contiguous load or store instruction architecturally executed. <br /></td></tr>
386 <tr class="separator:ga8acf6a66c63798b76608caf52c96658d"><td class="memSeparator" colspan="2"> </td></tr>
387 <tr class="memitem:ga5a83ef6a52739e1d223be503bbdaaab6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga5a83ef6a52739e1d223be503bbdaaab6">ARM_PMU_MVE_LDST_CONTIG_SPEC</a>   0x0245</td></tr>
388 <tr class="memdesc:ga5a83ef6a52739e1d223be503bbdaaab6"><td class="mdescLeft"> </td><td class="mdescRight">MVE contiguous load or store instruction speculatively executed. <br /></td></tr>
389 <tr class="separator:ga5a83ef6a52739e1d223be503bbdaaab6"><td class="memSeparator" colspan="2"> </td></tr>
390 <tr class="memitem:ga8732a737f2b7adc43e3d1da7b3da92e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8732a737f2b7adc43e3d1da7b3da92e6">ARM_PMU_MVE_LD_CONTIG_RETIRED</a>   0x0248</td></tr>
391 <tr class="memdesc:ga8732a737f2b7adc43e3d1da7b3da92e6"><td class="mdescLeft"> </td><td class="mdescRight">MVE contiguous load instruction architecturally executed. <br /></td></tr>
392 <tr class="separator:ga8732a737f2b7adc43e3d1da7b3da92e6"><td class="memSeparator" colspan="2"> </td></tr>
393 <tr class="memitem:ga8e58fe07254256fa3bf3d42fa2062141"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8e58fe07254256fa3bf3d42fa2062141">ARM_PMU_MVE_LD_CONTIG_SPEC</a>   0x0249</td></tr>
394 <tr class="memdesc:ga8e58fe07254256fa3bf3d42fa2062141"><td class="mdescLeft"> </td><td class="mdescRight">MVE contiguous load instruction speculatively executed. <br /></td></tr>
395 <tr class="separator:ga8e58fe07254256fa3bf3d42fa2062141"><td class="memSeparator" colspan="2"> </td></tr>
396 <tr class="memitem:gacb3c0b922eae9aac321df97ec889e0ed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gacb3c0b922eae9aac321df97ec889e0ed">ARM_PMU_MVE_ST_CONTIG_RETIRED</a>   0x024C</td></tr>
397 <tr class="memdesc:gacb3c0b922eae9aac321df97ec889e0ed"><td class="mdescLeft"> </td><td class="mdescRight">MVE contiguous store instruction architecturally executed. <br /></td></tr>
398 <tr class="separator:gacb3c0b922eae9aac321df97ec889e0ed"><td class="memSeparator" colspan="2"> </td></tr>
399 <tr class="memitem:ga02cd64b9444e4babc7b69e8571d39bdd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga02cd64b9444e4babc7b69e8571d39bdd">ARM_PMU_MVE_ST_CONTIG_SPEC</a>   0x024D</td></tr>
400 <tr class="memdesc:ga02cd64b9444e4babc7b69e8571d39bdd"><td class="mdescLeft"> </td><td class="mdescRight">MVE contiguous store instruction speculatively executed. <br /></td></tr>
401 <tr class="separator:ga02cd64b9444e4babc7b69e8571d39bdd"><td class="memSeparator" colspan="2"> </td></tr>
402 <tr class="memitem:ga7065b7f0aea461858b72912d22c329f2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga7065b7f0aea461858b72912d22c329f2">ARM_PMU_MVE_LDST_NONCONTIG_RETIRED</a>   0x0250</td></tr>
403 <tr class="memdesc:ga7065b7f0aea461858b72912d22c329f2"><td class="mdescLeft"> </td><td class="mdescRight">MVE non-contiguous load or store instruction architecturally executed. <br /></td></tr>
404 <tr class="separator:ga7065b7f0aea461858b72912d22c329f2"><td class="memSeparator" colspan="2"> </td></tr>
405 <tr class="memitem:ga193605eb52709741d91a64e3ad1a5894"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga193605eb52709741d91a64e3ad1a5894">ARM_PMU_MVE_LDST_NONCONTIG_SPEC</a>   0x0251</td></tr>
406 <tr class="memdesc:ga193605eb52709741d91a64e3ad1a5894"><td class="mdescLeft"> </td><td class="mdescRight">MVE non-contiguous load or store instruction speculatively executed. <br /></td></tr>
407 <tr class="separator:ga193605eb52709741d91a64e3ad1a5894"><td class="memSeparator" colspan="2"> </td></tr>
408 <tr class="memitem:gaaf2ce8c0ea4c03c934aac6afc31fc5ff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaaf2ce8c0ea4c03c934aac6afc31fc5ff">ARM_PMU_MVE_LD_NONCONTIG_RETIRED</a>   0x0254</td></tr>
409 <tr class="memdesc:gaaf2ce8c0ea4c03c934aac6afc31fc5ff"><td class="mdescLeft"> </td><td class="mdescRight">MVE non-contiguous load instruction architecturally executed. <br /></td></tr>
410 <tr class="separator:gaaf2ce8c0ea4c03c934aac6afc31fc5ff"><td class="memSeparator" colspan="2"> </td></tr>
411 <tr class="memitem:gadbcb82b7924b7bbee5c0d42a3de38572"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gadbcb82b7924b7bbee5c0d42a3de38572">ARM_PMU_MVE_LD_NONCONTIG_SPEC</a>   0x0255</td></tr>
412 <tr class="memdesc:gadbcb82b7924b7bbee5c0d42a3de38572"><td class="mdescLeft"> </td><td class="mdescRight">MVE non-contiguous load instruction speculatively executed. <br /></td></tr>
413 <tr class="separator:gadbcb82b7924b7bbee5c0d42a3de38572"><td class="memSeparator" colspan="2"> </td></tr>
414 <tr class="memitem:ga8271f415ecc7573b57e82a24aec86ef1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8271f415ecc7573b57e82a24aec86ef1">ARM_PMU_MVE_ST_NONCONTIG_RETIRED</a>   0x0258</td></tr>
415 <tr class="memdesc:ga8271f415ecc7573b57e82a24aec86ef1"><td class="mdescLeft"> </td><td class="mdescRight">MVE non-contiguous store instruction architecturally executed. <br /></td></tr>
416 <tr class="separator:ga8271f415ecc7573b57e82a24aec86ef1"><td class="memSeparator" colspan="2"> </td></tr>
417 <tr class="memitem:ga059327c80f396918a9f8192bcd0fa4a8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga059327c80f396918a9f8192bcd0fa4a8">ARM_PMU_MVE_ST_NONCONTIG_SPEC</a>   0x0259</td></tr>
418 <tr class="memdesc:ga059327c80f396918a9f8192bcd0fa4a8"><td class="mdescLeft"> </td><td class="mdescRight">MVE non-contiguous store instruction speculatively executed. <br /></td></tr>
419 <tr class="separator:ga059327c80f396918a9f8192bcd0fa4a8"><td class="memSeparator" colspan="2"> </td></tr>
420 <tr class="memitem:ga7d669378441408fc21aa551e483866cb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga7d669378441408fc21aa551e483866cb">ARM_PMU_MVE_LDST_MULTI_RETIRED</a>   0x025C</td></tr>
421 <tr class="memdesc:ga7d669378441408fc21aa551e483866cb"><td class="mdescLeft"> </td><td class="mdescRight">MVE memory instruction targeting multiple registers architecturally executed. <br /></td></tr>
422 <tr class="separator:ga7d669378441408fc21aa551e483866cb"><td class="memSeparator" colspan="2"> </td></tr>
423 <tr class="memitem:ga7ea46cde08cb0cc4a46ef23835fb5aac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga7ea46cde08cb0cc4a46ef23835fb5aac">ARM_PMU_MVE_LDST_MULTI_SPEC</a>   0x025D</td></tr>
424 <tr class="memdesc:ga7ea46cde08cb0cc4a46ef23835fb5aac"><td class="mdescLeft"> </td><td class="mdescRight">MVE memory instruction targeting multiple registers speculatively executed. <br /></td></tr>
425 <tr class="separator:ga7ea46cde08cb0cc4a46ef23835fb5aac"><td class="memSeparator" colspan="2"> </td></tr>
426 <tr class="memitem:ga50fb13c874b3f5e2b9ed9c320a36452c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga50fb13c874b3f5e2b9ed9c320a36452c">ARM_PMU_MVE_LD_MULTI_RETIRED</a>   0x0260</td></tr>
427 <tr class="memdesc:ga50fb13c874b3f5e2b9ed9c320a36452c"><td class="mdescLeft"> </td><td class="mdescRight">MVE memory load instruction targeting multiple registers architecturally executed. <br /></td></tr>
428 <tr class="separator:ga50fb13c874b3f5e2b9ed9c320a36452c"><td class="memSeparator" colspan="2"> </td></tr>
429 <tr class="memitem:gaf2d4e3d1f06d97899de7fa791477d62b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf2d4e3d1f06d97899de7fa791477d62b">ARM_PMU_MVE_LD_MULTI_SPEC</a>   0x0261</td></tr>
430 <tr class="memdesc:gaf2d4e3d1f06d97899de7fa791477d62b"><td class="mdescLeft"> </td><td class="mdescRight">MVE memory load instruction targeting multiple registers speculatively executed. <br /></td></tr>
431 <tr class="separator:gaf2d4e3d1f06d97899de7fa791477d62b"><td class="memSeparator" colspan="2"> </td></tr>
432 <tr class="memitem:ga76057cbda353b4ad6fbc3b6a63c193a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga76057cbda353b4ad6fbc3b6a63c193a5">ARM_PMU_MVE_ST_MULTI_RETIRED</a>   0x0261</td></tr>
433 <tr class="memdesc:ga76057cbda353b4ad6fbc3b6a63c193a5"><td class="mdescLeft"> </td><td class="mdescRight">MVE memory store instruction targeting multiple registers architecturally executed. <br /></td></tr>
434 <tr class="separator:ga76057cbda353b4ad6fbc3b6a63c193a5"><td class="memSeparator" colspan="2"> </td></tr>
435 <tr class="memitem:gaf6a14402c79dba8fa765e8663dd0734d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf6a14402c79dba8fa765e8663dd0734d">ARM_PMU_MVE_ST_MULTI_SPEC</a>   0x0265</td></tr>
436 <tr class="memdesc:gaf6a14402c79dba8fa765e8663dd0734d"><td class="mdescLeft"> </td><td class="mdescRight">MVE memory store instruction targeting multiple registers speculatively executed. <br /></td></tr>
437 <tr class="separator:gaf6a14402c79dba8fa765e8663dd0734d"><td class="memSeparator" colspan="2"> </td></tr>
438 <tr class="memitem:gaf358a9ed5c83a10cb695d9b19b1b3bc1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf358a9ed5c83a10cb695d9b19b1b3bc1">ARM_PMU_MVE_LDST_UNALIGNED_RETIRED</a>   0x028C</td></tr>
439 <tr class="memdesc:gaf358a9ed5c83a10cb695d9b19b1b3bc1"><td class="mdescLeft"> </td><td class="mdescRight">MVE unaligned memory load or store instruction architecturally executed. <br /></td></tr>
440 <tr class="separator:gaf358a9ed5c83a10cb695d9b19b1b3bc1"><td class="memSeparator" colspan="2"> </td></tr>
441 <tr class="memitem:gab2264786bed578c89109859b55909c76"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab2264786bed578c89109859b55909c76">ARM_PMU_MVE_LDST_UNALIGNED_SPEC</a>   0x028D</td></tr>
442 <tr class="memdesc:gab2264786bed578c89109859b55909c76"><td class="mdescLeft"> </td><td class="mdescRight">MVE unaligned memory load or store instruction speculatively executed. <br /></td></tr>
443 <tr class="separator:gab2264786bed578c89109859b55909c76"><td class="memSeparator" colspan="2"> </td></tr>
444 <tr class="memitem:ga26ed05deaa7b993904300069f0ecfac4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga26ed05deaa7b993904300069f0ecfac4">ARM_PMU_MVE_LD_UNALIGNED_RETIRED</a>   0x0290</td></tr>
445 <tr class="memdesc:ga26ed05deaa7b993904300069f0ecfac4"><td class="mdescLeft"> </td><td class="mdescRight">MVE unaligned load instruction architecturally executed. <br /></td></tr>
446 <tr class="separator:ga26ed05deaa7b993904300069f0ecfac4"><td class="memSeparator" colspan="2"> </td></tr>
447 <tr class="memitem:gadc3bd0f32e0a08bba2d533479a59bd6e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gadc3bd0f32e0a08bba2d533479a59bd6e">ARM_PMU_MVE_LD_UNALIGNED_SPEC</a>   0x0291</td></tr>
448 <tr class="memdesc:gadc3bd0f32e0a08bba2d533479a59bd6e"><td class="mdescLeft"> </td><td class="mdescRight">MVE unaligned load instruction speculatively executed. <br /></td></tr>
449 <tr class="separator:gadc3bd0f32e0a08bba2d533479a59bd6e"><td class="memSeparator" colspan="2"> </td></tr>
450 <tr class="memitem:ga391afd8cb92cc65161b13ee3a3256d40"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga391afd8cb92cc65161b13ee3a3256d40">ARM_PMU_MVE_ST_UNALIGNED_RETIRED</a>   0x0294</td></tr>
451 <tr class="memdesc:ga391afd8cb92cc65161b13ee3a3256d40"><td class="mdescLeft"> </td><td class="mdescRight">MVE unaligned store instruction architecturally executed. <br /></td></tr>
452 <tr class="separator:ga391afd8cb92cc65161b13ee3a3256d40"><td class="memSeparator" colspan="2"> </td></tr>
453 <tr class="memitem:ga21bf105499df85196b4137cb075a6fbe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga21bf105499df85196b4137cb075a6fbe">ARM_PMU_MVE_ST_UNALIGNED_SPEC</a>   0x0295</td></tr>
454 <tr class="memdesc:ga21bf105499df85196b4137cb075a6fbe"><td class="mdescLeft"> </td><td class="mdescRight">MVE unaligned store instruction speculatively executed. <br /></td></tr>
455 <tr class="separator:ga21bf105499df85196b4137cb075a6fbe"><td class="memSeparator" colspan="2"> </td></tr>
456 <tr class="memitem:ga627920bebd935709655687d844848934"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga627920bebd935709655687d844848934">ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED</a>   0x0298</td></tr>
457 <tr class="memdesc:ga627920bebd935709655687d844848934"><td class="mdescLeft"> </td><td class="mdescRight">MVE unaligned noncontiguous load or store instruction architecturally executed. <br /></td></tr>
458 <tr class="separator:ga627920bebd935709655687d844848934"><td class="memSeparator" colspan="2"> </td></tr>
459 <tr class="memitem:gaf9ebeb1f49dba56d8f90f9bd5d3da58e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf9ebeb1f49dba56d8f90f9bd5d3da58e">ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC</a>   0x0299</td></tr>
460 <tr class="memdesc:gaf9ebeb1f49dba56d8f90f9bd5d3da58e"><td class="mdescLeft"> </td><td class="mdescRight">MVE unaligned noncontiguous load or store instruction speculatively executed. <br /></td></tr>
461 <tr class="separator:gaf9ebeb1f49dba56d8f90f9bd5d3da58e"><td class="memSeparator" colspan="2"> </td></tr>
462 <tr class="memitem:ga9546b924daa3c62e5f117026de58ad94"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga9546b924daa3c62e5f117026de58ad94">ARM_PMU_MVE_VREDUCE_RETIRED</a>   0x02A0</td></tr>
463 <tr class="memdesc:ga9546b924daa3c62e5f117026de58ad94"><td class="mdescLeft"> </td><td class="mdescRight">MVE vector reduction instruction architecturally executed. <br /></td></tr>
464 <tr class="separator:ga9546b924daa3c62e5f117026de58ad94"><td class="memSeparator" colspan="2"> </td></tr>
465 <tr class="memitem:gac714f988ae45871b2865f82c11383b36"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gac714f988ae45871b2865f82c11383b36">ARM_PMU_MVE_VREDUCE_SPEC</a>   0x02A1</td></tr>
466 <tr class="memdesc:gac714f988ae45871b2865f82c11383b36"><td class="mdescLeft"> </td><td class="mdescRight">MVE vector reduction instruction speculatively executed. <br /></td></tr>
467 <tr class="separator:gac714f988ae45871b2865f82c11383b36"><td class="memSeparator" colspan="2"> </td></tr>
468 <tr class="memitem:ga77fad5ad424271ed63fec98af071bb79"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga77fad5ad424271ed63fec98af071bb79">ARM_PMU_MVE_VREDUCE_FP_RETIRED</a>   0x02A4</td></tr>
469 <tr class="memdesc:ga77fad5ad424271ed63fec98af071bb79"><td class="mdescLeft"> </td><td class="mdescRight">MVE floating-point vector reduction instruction architecturally executed. <br /></td></tr>
470 <tr class="separator:ga77fad5ad424271ed63fec98af071bb79"><td class="memSeparator" colspan="2"> </td></tr>
471 <tr class="memitem:gaa07c698f58c622d234a0007249717265"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaa07c698f58c622d234a0007249717265">ARM_PMU_MVE_VREDUCE_FP_SPEC</a>   0x02A5</td></tr>
472 <tr class="memdesc:gaa07c698f58c622d234a0007249717265"><td class="mdescLeft"> </td><td class="mdescRight">MVE floating-point vector reduction instruction speculatively executed. <br /></td></tr>
473 <tr class="separator:gaa07c698f58c622d234a0007249717265"><td class="memSeparator" colspan="2"> </td></tr>
474 <tr class="memitem:ga649e7e81f0fd04ca6611f6a6c4035c57"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga649e7e81f0fd04ca6611f6a6c4035c57">ARM_PMU_MVE_VREDUCE_INT_RETIRED</a>   0x02A8</td></tr>
475 <tr class="memdesc:ga649e7e81f0fd04ca6611f6a6c4035c57"><td class="mdescLeft"> </td><td class="mdescRight">MVE integer vector reduction instruction architecturally executed. <br /></td></tr>
476 <tr class="separator:ga649e7e81f0fd04ca6611f6a6c4035c57"><td class="memSeparator" colspan="2"> </td></tr>
477 <tr class="memitem:ga5b6f0bcfd63207c7bab03ea20167dd4b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga5b6f0bcfd63207c7bab03ea20167dd4b">ARM_PMU_MVE_VREDUCE_INT_SPEC</a>   0x02A9</td></tr>
478 <tr class="memdesc:ga5b6f0bcfd63207c7bab03ea20167dd4b"><td class="mdescLeft"> </td><td class="mdescRight">MVE integer vector reduction instruction speculatively executed. <br /></td></tr>
479 <tr class="separator:ga5b6f0bcfd63207c7bab03ea20167dd4b"><td class="memSeparator" colspan="2"> </td></tr>
480 <tr class="memitem:ga01b4792990494b8f084ee00933a1adb0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga01b4792990494b8f084ee00933a1adb0">ARM_PMU_MVE_PRED</a>   0x02B8</td></tr>
481 <tr class="memdesc:ga01b4792990494b8f084ee00933a1adb0"><td class="mdescLeft"> </td><td class="mdescRight">Cycles where one or more predicated beats architecturally executed. <br /></td></tr>
482 <tr class="separator:ga01b4792990494b8f084ee00933a1adb0"><td class="memSeparator" colspan="2"> </td></tr>
483 <tr class="memitem:ga2a45ec75b2011bd8375d89b7562b2de6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga2a45ec75b2011bd8375d89b7562b2de6">ARM_PMU_MVE_STALL</a>   0x02CC</td></tr>
484 <tr class="memdesc:ga2a45ec75b2011bd8375d89b7562b2de6"><td class="mdescLeft"> </td><td class="mdescRight">Stall cycles caused by an MVE instruction. <br /></td></tr>
485 <tr class="separator:ga2a45ec75b2011bd8375d89b7562b2de6"><td class="memSeparator" colspan="2"> </td></tr>
486 <tr class="memitem:ga8f4949084efce03d09bf5ba74cc91edd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8f4949084efce03d09bf5ba74cc91edd">ARM_PMU_MVE_STALL_RESOURCE</a>   0x02CD</td></tr>
487 <tr class="memdesc:ga8f4949084efce03d09bf5ba74cc91edd"><td class="mdescLeft"> </td><td class="mdescRight">Stall cycles caused by an MVE instruction because of resource conflicts. <br /></td></tr>
488 <tr class="separator:ga8f4949084efce03d09bf5ba74cc91edd"><td class="memSeparator" colspan="2"> </td></tr>
489 <tr class="memitem:gab486f5753edd9f10b0f100ff78944dd3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab486f5753edd9f10b0f100ff78944dd3">ARM_PMU_MVE_STALL_RESOURCE_MEM</a>   0x02CE</td></tr>
490 <tr class="memdesc:gab486f5753edd9f10b0f100ff78944dd3"><td class="mdescLeft"> </td><td class="mdescRight">Stall cycles caused by an MVE instruction because of memory resource conflicts. <br /></td></tr>
491 <tr class="separator:gab486f5753edd9f10b0f100ff78944dd3"><td class="memSeparator" colspan="2"> </td></tr>
492 <tr class="memitem:ga7e76060791618f9b4d49ad493cfb6ba9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga7e76060791618f9b4d49ad493cfb6ba9">ARM_PMU_MVE_STALL_RESOURCE_FP</a>   0x02CF</td></tr>
493 <tr class="memdesc:ga7e76060791618f9b4d49ad493cfb6ba9"><td class="mdescLeft"> </td><td class="mdescRight">Stall cycles caused by an MVE instruction because of floating-point resource conflicts. <br /></td></tr>
494 <tr class="separator:ga7e76060791618f9b4d49ad493cfb6ba9"><td class="memSeparator" colspan="2"> </td></tr>
495 <tr class="memitem:gaef33b3ff7f12d31238ff4dded5e67a11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaef33b3ff7f12d31238ff4dded5e67a11">ARM_PMU_MVE_STALL_RESOURCE_INT</a>   0x02D0</td></tr>
496 <tr class="memdesc:gaef33b3ff7f12d31238ff4dded5e67a11"><td class="mdescLeft"> </td><td class="mdescRight">Stall cycles caused by an MVE instruction because of integer resource conflicts. <br /></td></tr>
497 <tr class="separator:gaef33b3ff7f12d31238ff4dded5e67a11"><td class="memSeparator" colspan="2"> </td></tr>
498 <tr class="memitem:ga9a1cfef96ec7cd70acf134e368d8826a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga9a1cfef96ec7cd70acf134e368d8826a">ARM_PMU_MVE_STALL_BREAK</a>   0x02D3</td></tr>
499 <tr class="memdesc:ga9a1cfef96ec7cd70acf134e368d8826a"><td class="mdescLeft"> </td><td class="mdescRight">Stall cycles caused by an MVE chain break. <br /></td></tr>
500 <tr class="separator:ga9a1cfef96ec7cd70acf134e368d8826a"><td class="memSeparator" colspan="2"> </td></tr>
501 <tr class="memitem:ga29bc4c2e820914e94e2eb68a6a3352b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga29bc4c2e820914e94e2eb68a6a3352b9">ARM_PMU_MVE_STALL_DEPENDENCY</a>   0x02D4</td></tr>
502 <tr class="memdesc:ga29bc4c2e820914e94e2eb68a6a3352b9"><td class="mdescLeft"> </td><td class="mdescRight">Stall cycles caused by MVE register dependency. <br /></td></tr>
503 <tr class="separator:ga29bc4c2e820914e94e2eb68a6a3352b9"><td class="memSeparator" colspan="2"> </td></tr>
504 <tr class="memitem:gaf23d758fe1a4cfe6f114cb3e78709237"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf23d758fe1a4cfe6f114cb3e78709237">ARM_PMU_ITCM_ACCESS</a>   0x4007</td></tr>
505 <tr class="memdesc:gaf23d758fe1a4cfe6f114cb3e78709237"><td class="mdescLeft"> </td><td class="mdescRight">Instruction TCM access. <br /></td></tr>
506 <tr class="separator:gaf23d758fe1a4cfe6f114cb3e78709237"><td class="memSeparator" colspan="2"> </td></tr>
507 <tr class="memitem:ga74aaa0fa0571f74168ee9608d5a02403"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga74aaa0fa0571f74168ee9608d5a02403">ARM_PMU_DTCM_ACCESS</a>   0x4008</td></tr>
508 <tr class="memdesc:ga74aaa0fa0571f74168ee9608d5a02403"><td class="mdescLeft"> </td><td class="mdescRight">Data TCM access. <br /></td></tr>
509 <tr class="separator:ga74aaa0fa0571f74168ee9608d5a02403"><td class="memSeparator" colspan="2"> </td></tr>
510 <tr class="memitem:gadaa75dc2ccfbf7a2263da9a9011f1603"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gadaa75dc2ccfbf7a2263da9a9011f1603">ARM_PMU_TRCEXTOUT0</a>   0x4010</td></tr>
511 <tr class="memdesc:gadaa75dc2ccfbf7a2263da9a9011f1603"><td class="mdescLeft"> </td><td class="mdescRight">ETM external output 0. <br /></td></tr>
512 <tr class="separator:gadaa75dc2ccfbf7a2263da9a9011f1603"><td class="memSeparator" colspan="2"> </td></tr>
513 <tr class="memitem:ga47fe03fe6fe9bfebd98283cb57d94560"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga47fe03fe6fe9bfebd98283cb57d94560">ARM_PMU_TRCEXTOUT1</a>   0x4011</td></tr>
514 <tr class="memdesc:ga47fe03fe6fe9bfebd98283cb57d94560"><td class="mdescLeft"> </td><td class="mdescRight">ETM external output 1. <br /></td></tr>
515 <tr class="separator:ga47fe03fe6fe9bfebd98283cb57d94560"><td class="memSeparator" colspan="2"> </td></tr>
516 <tr class="memitem:gab80e47ffebc3ae6ed2952756b020dbb9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab80e47ffebc3ae6ed2952756b020dbb9">ARM_PMU_TRCEXTOUT2</a>   0x4012</td></tr>
517 <tr class="memdesc:gab80e47ffebc3ae6ed2952756b020dbb9"><td class="mdescLeft"> </td><td class="mdescRight">ETM external output 2. <br /></td></tr>
518 <tr class="separator:gab80e47ffebc3ae6ed2952756b020dbb9"><td class="memSeparator" colspan="2"> </td></tr>
519 <tr class="memitem:gad70a3b074efd967485ffbfd3e387051d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gad70a3b074efd967485ffbfd3e387051d">ARM_PMU_TRCEXTOUT3</a>   0x4013</td></tr>
520 <tr class="memdesc:gad70a3b074efd967485ffbfd3e387051d"><td class="mdescLeft"> </td><td class="mdescRight">ETM external output 3. <br /></td></tr>
521 <tr class="separator:gad70a3b074efd967485ffbfd3e387051d"><td class="memSeparator" colspan="2"> </td></tr>
522 <tr class="memitem:ga290974d72b8cac214f4e9a152ca64a56"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga290974d72b8cac214f4e9a152ca64a56">ARM_PMU_CTI_TRIGOUT4</a>   0x4018</td></tr>
523 <tr class="memdesc:ga290974d72b8cac214f4e9a152ca64a56"><td class="mdescLeft"> </td><td class="mdescRight">Cross-trigger Interface output trigger 4. <br /></td></tr>
524 <tr class="separator:ga290974d72b8cac214f4e9a152ca64a56"><td class="memSeparator" colspan="2"> </td></tr>
525 <tr class="memitem:ga7a05420b7fae6f5c3d35e12a9846c7e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga7a05420b7fae6f5c3d35e12a9846c7e2">ARM_PMU_CTI_TRIGOUT5</a>   0x4019</td></tr>
526 <tr class="memdesc:ga7a05420b7fae6f5c3d35e12a9846c7e2"><td class="mdescLeft"> </td><td class="mdescRight">Cross-trigger Interface output trigger 5. <br /></td></tr>
527 <tr class="separator:ga7a05420b7fae6f5c3d35e12a9846c7e2"><td class="memSeparator" colspan="2"> </td></tr>
528 <tr class="memitem:gade076a5ee512a14f8882d9aec5d3dc0b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gade076a5ee512a14f8882d9aec5d3dc0b">ARM_PMU_CTI_TRIGOUT6</a>   0x401A</td></tr>
529 <tr class="memdesc:gade076a5ee512a14f8882d9aec5d3dc0b"><td class="mdescLeft"> </td><td class="mdescRight">Cross-trigger Interface output trigger 6. <br /></td></tr>
530 <tr class="separator:gade076a5ee512a14f8882d9aec5d3dc0b"><td class="memSeparator" colspan="2"> </td></tr>
531 <tr class="memitem:ga4388c85b636bd71b4ee1a03b6e96c488"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga4388c85b636bd71b4ee1a03b6e96c488">ARM_PMU_CTI_TRIGOUT7</a>   0x401B</td></tr>
532 <tr class="memdesc:ga4388c85b636bd71b4ee1a03b6e96c488"><td class="mdescLeft"> </td><td class="mdescRight">Cross-trigger Interface output trigger 7. <br /></td></tr>
533 <tr class="separator:ga4388c85b636bd71b4ee1a03b6e96c488"><td class="memSeparator" colspan="2"> </td></tr>
535 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
536 <p>IDs for Armv8.1-M architecture defined events. </p>
537 <p>These events are available on all Armv8.1-M devices including a PMU. </p>
538 <h2 class="groupheader">Macro Definition Documentation</h2>
539 <a id="gaf2e0a38b7c0d63d1194f08478781a3f0" name="gaf2e0a38b7c0d63d1194f08478781a3f0"></a>
540 <h2 class="memtitle"><span class="permalink"><a href="#gaf2e0a38b7c0d63d1194f08478781a3f0">◆ </a></span>ARM_PMU_BF_CANCEL</h2>
542 <div class="memitem">
543 <div class="memproto">
544 <table class="memname">
546 <td class="memname">#define ARM_PMU_BF_CANCEL   0x0109</td>
549 </div><div class="memdoc">
551 <p>Branch future instruction not taken. </p>
555 <a id="gab8570f46393e3e44bb118591d33723f4" name="gab8570f46393e3e44bb118591d33723f4"></a>
556 <h2 class="memtitle"><span class="permalink"><a href="#gab8570f46393e3e44bb118591d33723f4">◆ </a></span>ARM_PMU_BF_RETIRED</h2>
558 <div class="memitem">
559 <div class="memproto">
560 <table class="memname">
562 <td class="memname">#define ARM_PMU_BF_RETIRED   0x0104</td>
565 </div><div class="memdoc">
567 <p>Branch future instruction architecturally executed and condition code check pass. </p>
571 <a id="ga6b1e4823d8b45678a29a5f54b859d4e3" name="ga6b1e4823d8b45678a29a5f54b859d4e3"></a>
572 <h2 class="memtitle"><span class="permalink"><a href="#ga6b1e4823d8b45678a29a5f54b859d4e3">◆ </a></span>ARM_PMU_BF_SPEC</h2>
574 <div class="memitem">
575 <div class="memproto">
576 <table class="memname">
578 <td class="memname">#define ARM_PMU_BF_SPEC   0x0105</td>
581 </div><div class="memdoc">
583 <p>Branch future instruction speculatively executed and condition code check pass. </p>
587 <a id="ga22bfb189fff7c1ea9f81097a543ed756" name="ga22bfb189fff7c1ea9f81097a543ed756"></a>
588 <h2 class="memtitle"><span class="permalink"><a href="#ga22bfb189fff7c1ea9f81097a543ed756">◆ </a></span>ARM_PMU_BR_IMMED_RETIRED</h2>
590 <div class="memitem">
591 <div class="memproto">
592 <table class="memname">
594 <td class="memname">#define ARM_PMU_BR_IMMED_RETIRED   0x000D</td>
597 </div><div class="memdoc">
599 <p>Immediate branch architecturally executed. </p>
603 <a id="gabfa921c85a61f0a21c9bee289e63c102" name="gabfa921c85a61f0a21c9bee289e63c102"></a>
604 <h2 class="memtitle"><span class="permalink"><a href="#gabfa921c85a61f0a21c9bee289e63c102">◆ </a></span>ARM_PMU_BR_MIS_PRED</h2>
606 <div class="memitem">
607 <div class="memproto">
608 <table class="memname">
610 <td class="memname">#define ARM_PMU_BR_MIS_PRED   0x0010</td>
613 </div><div class="memdoc">
615 <p>Mispredicted or not predicted branch speculatively executed. </p>
619 <a id="gae12baa616c5f0cdd081231fcf8cdad68" name="gae12baa616c5f0cdd081231fcf8cdad68"></a>
620 <h2 class="memtitle"><span class="permalink"><a href="#gae12baa616c5f0cdd081231fcf8cdad68">◆ </a></span>ARM_PMU_BR_MIS_PRED_RETIRED</h2>
622 <div class="memitem">
623 <div class="memproto">
624 <table class="memname">
626 <td class="memname">#define ARM_PMU_BR_MIS_PRED_RETIRED   0x0022</td>
629 </div><div class="memdoc">
631 <p>Mispredicted branch instruction architecturally executed. </p>
635 <a id="ga60ccf42eae576e2fde3b9e17a8defeaa" name="ga60ccf42eae576e2fde3b9e17a8defeaa"></a>
636 <h2 class="memtitle"><span class="permalink"><a href="#ga60ccf42eae576e2fde3b9e17a8defeaa">◆ </a></span>ARM_PMU_BR_PRED</h2>
638 <div class="memitem">
639 <div class="memproto">
640 <table class="memname">
642 <td class="memname">#define ARM_PMU_BR_PRED   0x0012</td>
645 </div><div class="memdoc">
647 <p>Predictable branch speculatively executed. </p>
651 <a id="gab3b505a8bcc2b2885626d2f2cd542b73" name="gab3b505a8bcc2b2885626d2f2cd542b73"></a>
652 <h2 class="memtitle"><span class="permalink"><a href="#gab3b505a8bcc2b2885626d2f2cd542b73">◆ </a></span>ARM_PMU_BR_RETIRED</h2>
654 <div class="memitem">
655 <div class="memproto">
656 <table class="memname">
658 <td class="memname">#define ARM_PMU_BR_RETIRED   0x0021</td>
661 </div><div class="memdoc">
663 <p>Branch instruction architecturally executed. </p>
667 <a id="gab717347b1c3601cffb9c99b43b2a45c5" name="gab717347b1c3601cffb9c99b43b2a45c5"></a>
668 <h2 class="memtitle"><span class="permalink"><a href="#gab717347b1c3601cffb9c99b43b2a45c5">◆ </a></span>ARM_PMU_BR_RETURN_RETIRED</h2>
670 <div class="memitem">
671 <div class="memproto">
672 <table class="memname">
674 <td class="memname">#define ARM_PMU_BR_RETURN_RETIRED   0x000E</td>
677 </div><div class="memdoc">
679 <p>Function return instruction architecturally executed and the condition code check pass. </p>
683 <a id="gaa681d3db56b42775093869b8fdf1abb9" name="gaa681d3db56b42775093869b8fdf1abb9"></a>
684 <h2 class="memtitle"><span class="permalink"><a href="#gaa681d3db56b42775093869b8fdf1abb9">◆ </a></span>ARM_PMU_BUS_ACCESS</h2>
686 <div class="memitem">
687 <div class="memproto">
688 <table class="memname">
690 <td class="memname">#define ARM_PMU_BUS_ACCESS   0x0019</td>
693 </div><div class="memdoc">
699 <a id="gae4c955416707f44f066ffd2560b9ae4c" name="gae4c955416707f44f066ffd2560b9ae4c"></a>
700 <h2 class="memtitle"><span class="permalink"><a href="#gae4c955416707f44f066ffd2560b9ae4c">◆ </a></span>ARM_PMU_BUS_CYCLES</h2>
702 <div class="memitem">
703 <div class="memproto">
704 <table class="memname">
706 <td class="memname">#define ARM_PMU_BUS_CYCLES   0x001D</td>
709 </div><div class="memdoc">
715 <a id="gaca14907c5a1e1f9915159bc4cf323cf0" name="gaca14907c5a1e1f9915159bc4cf323cf0"></a>
716 <h2 class="memtitle"><span class="permalink"><a href="#gaca14907c5a1e1f9915159bc4cf323cf0">◆ </a></span>ARM_PMU_CHAIN</h2>
718 <div class="memitem">
719 <div class="memproto">
720 <table class="memname">
722 <td class="memname">#define ARM_PMU_CHAIN   0x001E</td>
725 </div><div class="memdoc">
727 <p>For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE. </p>
731 <a id="ga550d524d435a653b2f46acc1380a5ace" name="ga550d524d435a653b2f46acc1380a5ace"></a>
732 <h2 class="memtitle"><span class="permalink"><a href="#ga550d524d435a653b2f46acc1380a5ace">◆ </a></span>ARM_PMU_CPU_CYCLES</h2>
734 <div class="memitem">
735 <div class="memproto">
736 <table class="memname">
738 <td class="memname">#define ARM_PMU_CPU_CYCLES   0x0011</td>
741 </div><div class="memdoc">
747 <a id="ga290974d72b8cac214f4e9a152ca64a56" name="ga290974d72b8cac214f4e9a152ca64a56"></a>
748 <h2 class="memtitle"><span class="permalink"><a href="#ga290974d72b8cac214f4e9a152ca64a56">◆ </a></span>ARM_PMU_CTI_TRIGOUT4</h2>
750 <div class="memitem">
751 <div class="memproto">
752 <table class="memname">
754 <td class="memname">#define ARM_PMU_CTI_TRIGOUT4   0x4018</td>
757 </div><div class="memdoc">
759 <p>Cross-trigger Interface output trigger 4. </p>
763 <a id="ga7a05420b7fae6f5c3d35e12a9846c7e2" name="ga7a05420b7fae6f5c3d35e12a9846c7e2"></a>
764 <h2 class="memtitle"><span class="permalink"><a href="#ga7a05420b7fae6f5c3d35e12a9846c7e2">◆ </a></span>ARM_PMU_CTI_TRIGOUT5</h2>
766 <div class="memitem">
767 <div class="memproto">
768 <table class="memname">
770 <td class="memname">#define ARM_PMU_CTI_TRIGOUT5   0x4019</td>
773 </div><div class="memdoc">
775 <p>Cross-trigger Interface output trigger 5. </p>
779 <a id="gade076a5ee512a14f8882d9aec5d3dc0b" name="gade076a5ee512a14f8882d9aec5d3dc0b"></a>
780 <h2 class="memtitle"><span class="permalink"><a href="#gade076a5ee512a14f8882d9aec5d3dc0b">◆ </a></span>ARM_PMU_CTI_TRIGOUT6</h2>
782 <div class="memitem">
783 <div class="memproto">
784 <table class="memname">
786 <td class="memname">#define ARM_PMU_CTI_TRIGOUT6   0x401A</td>
789 </div><div class="memdoc">
791 <p>Cross-trigger Interface output trigger 6. </p>
795 <a id="ga4388c85b636bd71b4ee1a03b6e96c488" name="ga4388c85b636bd71b4ee1a03b6e96c488"></a>
796 <h2 class="memtitle"><span class="permalink"><a href="#ga4388c85b636bd71b4ee1a03b6e96c488">◆ </a></span>ARM_PMU_CTI_TRIGOUT7</h2>
798 <div class="memitem">
799 <div class="memproto">
800 <table class="memname">
802 <td class="memname">#define ARM_PMU_CTI_TRIGOUT7   0x401B</td>
805 </div><div class="memdoc">
807 <p>Cross-trigger Interface output trigger 7. </p>
811 <a id="ga74aaa0fa0571f74168ee9608d5a02403" name="ga74aaa0fa0571f74168ee9608d5a02403"></a>
812 <h2 class="memtitle"><span class="permalink"><a href="#ga74aaa0fa0571f74168ee9608d5a02403">◆ </a></span>ARM_PMU_DTCM_ACCESS</h2>
814 <div class="memitem">
815 <div class="memproto">
816 <table class="memname">
818 <td class="memname">#define ARM_PMU_DTCM_ACCESS   0x4008</td>
821 </div><div class="memdoc">
823 <p>Data TCM access. </p>
827 <a id="ga18d640aa04b97c7d287e8745f6f2b23d" name="ga18d640aa04b97c7d287e8745f6f2b23d"></a>
828 <h2 class="memtitle"><span class="permalink"><a href="#ga18d640aa04b97c7d287e8745f6f2b23d">◆ </a></span>ARM_PMU_DWT_CMPMATCH0</h2>
830 <div class="memitem">
831 <div class="memproto">
832 <table class="memname">
834 <td class="memname">#define ARM_PMU_DWT_CMPMATCH0   0x0118</td>
837 </div><div class="memdoc">
839 <p>DWT comparator 0 match. </p>
843 <a id="ga5dc6eb2be1ff1afe9cbd59af4f6078ab" name="ga5dc6eb2be1ff1afe9cbd59af4f6078ab"></a>
844 <h2 class="memtitle"><span class="permalink"><a href="#ga5dc6eb2be1ff1afe9cbd59af4f6078ab">◆ </a></span>ARM_PMU_DWT_CMPMATCH1</h2>
846 <div class="memitem">
847 <div class="memproto">
848 <table class="memname">
850 <td class="memname">#define ARM_PMU_DWT_CMPMATCH1   0x0119</td>
853 </div><div class="memdoc">
855 <p>DWT comparator 1 match. </p>
859 <a id="ga58a4815dba8886088b9cac7b934a332d" name="ga58a4815dba8886088b9cac7b934a332d"></a>
860 <h2 class="memtitle"><span class="permalink"><a href="#ga58a4815dba8886088b9cac7b934a332d">◆ </a></span>ARM_PMU_DWT_CMPMATCH2</h2>
862 <div class="memitem">
863 <div class="memproto">
864 <table class="memname">
866 <td class="memname">#define ARM_PMU_DWT_CMPMATCH2   0x011A</td>
869 </div><div class="memdoc">
871 <p>DWT comparator 2 match. </p>
875 <a id="ga594337c6f3c88d8317203a8cd6f9814a" name="ga594337c6f3c88d8317203a8cd6f9814a"></a>
876 <h2 class="memtitle"><span class="permalink"><a href="#ga594337c6f3c88d8317203a8cd6f9814a">◆ </a></span>ARM_PMU_DWT_CMPMATCH3</h2>
878 <div class="memitem">
879 <div class="memproto">
880 <table class="memname">
882 <td class="memname">#define ARM_PMU_DWT_CMPMATCH3   0x011B</td>
885 </div><div class="memdoc">
887 <p>DWT comparator 3 match. </p>
891 <a id="gaf9424157e9c5dca3a3689d181005c4f8" name="gaf9424157e9c5dca3a3689d181005c4f8"></a>
892 <h2 class="memtitle"><span class="permalink"><a href="#gaf9424157e9c5dca3a3689d181005c4f8">◆ </a></span>ARM_PMU_EXC_RETURN</h2>
894 <div class="memitem">
895 <div class="memproto">
896 <table class="memname">
898 <td class="memname">#define ARM_PMU_EXC_RETURN   0x000A</td>
901 </div><div class="memdoc">
903 <p>Exception return instruction architecturally executed and the condition code check pass. </p>
907 <a id="gac97858bd621eab4592569444f0a5c37f" name="gac97858bd621eab4592569444f0a5c37f"></a>
908 <h2 class="memtitle"><span class="permalink"><a href="#gac97858bd621eab4592569444f0a5c37f">◆ </a></span>ARM_PMU_EXC_TAKEN</h2>
910 <div class="memitem">
911 <div class="memproto">
912 <table class="memname">
914 <td class="memname">#define ARM_PMU_EXC_TAKEN   0x0009</td>
917 </div><div class="memdoc">
919 <p>Exception entry. </p>
923 <a id="ga8a5e60eee460addfc66e275a2c4c4800" name="ga8a5e60eee460addfc66e275a2c4c4800"></a>
924 <h2 class="memtitle"><span class="permalink"><a href="#ga8a5e60eee460addfc66e275a2c4c4800">◆ </a></span>ARM_PMU_INST_RETIRED</h2>
926 <div class="memitem">
927 <div class="memproto">
928 <table class="memname">
930 <td class="memname">#define ARM_PMU_INST_RETIRED   0x0008</td>
933 </div><div class="memdoc">
935 <p>Instruction architecturally executed. </p>
939 <a id="gaf7bad54617ace5c2fb48bc2e8aebf9c7" name="gaf7bad54617ace5c2fb48bc2e8aebf9c7"></a>
940 <h2 class="memtitle"><span class="permalink"><a href="#gaf7bad54617ace5c2fb48bc2e8aebf9c7">◆ </a></span>ARM_PMU_INST_SPEC</h2>
942 <div class="memitem">
943 <div class="memproto">
944 <table class="memname">
946 <td class="memname">#define ARM_PMU_INST_SPEC   0x001B</td>
949 </div><div class="memdoc">
951 <p>Instruction speculatively executed. </p>
955 <a id="gaf23d758fe1a4cfe6f114cb3e78709237" name="gaf23d758fe1a4cfe6f114cb3e78709237"></a>
956 <h2 class="memtitle"><span class="permalink"><a href="#gaf23d758fe1a4cfe6f114cb3e78709237">◆ </a></span>ARM_PMU_ITCM_ACCESS</h2>
958 <div class="memitem">
959 <div class="memproto">
960 <table class="memname">
962 <td class="memname">#define ARM_PMU_ITCM_ACCESS   0x4007</td>
965 </div><div class="memdoc">
967 <p>Instruction TCM access. </p>
971 <a id="ga7505ae74c1d905f01b05dd5466c1efc0" name="ga7505ae74c1d905f01b05dd5466c1efc0"></a>
972 <h2 class="memtitle"><span class="permalink"><a href="#ga7505ae74c1d905f01b05dd5466c1efc0">◆ </a></span>ARM_PMU_L1D_CACHE</h2>
974 <div class="memitem">
975 <div class="memproto">
976 <table class="memname">
978 <td class="memname">#define ARM_PMU_L1D_CACHE   0x0004</td>
981 </div><div class="memdoc">
983 <p>L1 D-Cache access. </p>
987 <a id="gab55334c8510cb30c4c750913f6eb6279" name="gab55334c8510cb30c4c750913f6eb6279"></a>
988 <h2 class="memtitle"><span class="permalink"><a href="#gab55334c8510cb30c4c750913f6eb6279">◆ </a></span>ARM_PMU_L1D_CACHE_ALLOCATE</h2>
990 <div class="memitem">
991 <div class="memproto">
992 <table class="memname">
994 <td class="memname">#define ARM_PMU_L1D_CACHE_ALLOCATE   0x001F</td>
997 </div><div class="memdoc">
999 <p>Level 1 data cache allocation without refill. </p>
1003 <a id="ga4687d5d7efc6f49db2db9acc25b590f6" name="ga4687d5d7efc6f49db2db9acc25b590f6"></a>
1004 <h2 class="memtitle"><span class="permalink"><a href="#ga4687d5d7efc6f49db2db9acc25b590f6">◆ </a></span>ARM_PMU_L1D_CACHE_MISS_RD</h2>
1006 <div class="memitem">
1007 <div class="memproto">
1008 <table class="memname">
1010 <td class="memname">#define ARM_PMU_L1D_CACHE_MISS_RD   0x0039</td>
1013 </div><div class="memdoc">
1015 <p>Level 1 data cache read miss. </p>
1019 <a id="gaf4236dfbcb4550d3cc98caee837e8e77" name="gaf4236dfbcb4550d3cc98caee837e8e77"></a>
1020 <h2 class="memtitle"><span class="permalink"><a href="#gaf4236dfbcb4550d3cc98caee837e8e77">◆ </a></span>ARM_PMU_L1D_CACHE_RD</h2>
1022 <div class="memitem">
1023 <div class="memproto">
1024 <table class="memname">
1026 <td class="memname">#define ARM_PMU_L1D_CACHE_RD   0x0040</td>
1029 </div><div class="memdoc">
1031 <p>Level 1 data cache read. </p>
1035 <a id="ga64a3d7bfb7ec9d7bdeb073a4fe1bbc38" name="ga64a3d7bfb7ec9d7bdeb073a4fe1bbc38"></a>
1036 <h2 class="memtitle"><span class="permalink"><a href="#ga64a3d7bfb7ec9d7bdeb073a4fe1bbc38">◆ </a></span>ARM_PMU_L1D_CACHE_REFILL</h2>
1038 <div class="memitem">
1039 <div class="memproto">
1040 <table class="memname">
1042 <td class="memname">#define ARM_PMU_L1D_CACHE_REFILL   0x0003</td>
1045 </div><div class="memdoc">
1047 <p>L1 D-Cache refill. </p>
1051 <a id="ga27d1b8b2c37ae0ae41781880ed3893d0" name="ga27d1b8b2c37ae0ae41781880ed3893d0"></a>
1052 <h2 class="memtitle"><span class="permalink"><a href="#ga27d1b8b2c37ae0ae41781880ed3893d0">◆ </a></span>ARM_PMU_L1D_CACHE_WB</h2>
1054 <div class="memitem">
1055 <div class="memproto">
1056 <table class="memname">
1058 <td class="memname">#define ARM_PMU_L1D_CACHE_WB   0x0015</td>
1061 </div><div class="memdoc">
1063 <p>Level 1 data cache write-back. </p>
1067 <a id="gaf8e89b2b098e6bec5916517346925ce2" name="gaf8e89b2b098e6bec5916517346925ce2"></a>
1068 <h2 class="memtitle"><span class="permalink"><a href="#gaf8e89b2b098e6bec5916517346925ce2">◆ </a></span>ARM_PMU_L1I_CACHE</h2>
1070 <div class="memitem">
1071 <div class="memproto">
1072 <table class="memname">
1074 <td class="memname">#define ARM_PMU_L1I_CACHE   0x0014</td>
1077 </div><div class="memdoc">
1079 <p>Level 1 instruction cache access. </p>
1083 <a id="gac43e0e0f9e385ea66402bdeebf3fea3e" name="gac43e0e0f9e385ea66402bdeebf3fea3e"></a>
1084 <h2 class="memtitle"><span class="permalink"><a href="#gac43e0e0f9e385ea66402bdeebf3fea3e">◆ </a></span>ARM_PMU_L1I_CACHE_REFILL</h2>
1086 <div class="memitem">
1087 <div class="memproto">
1088 <table class="memname">
1090 <td class="memname">#define ARM_PMU_L1I_CACHE_REFILL   0x0001</td>
1093 </div><div class="memdoc">
1095 <p>L1 I-Cache refill. </p>
1099 <a id="gafb1e1f86d091ccb735858769c700e289" name="gafb1e1f86d091ccb735858769c700e289"></a>
1100 <h2 class="memtitle"><span class="permalink"><a href="#gafb1e1f86d091ccb735858769c700e289">◆ </a></span>ARM_PMU_L2D_CACHE</h2>
1102 <div class="memitem">
1103 <div class="memproto">
1104 <table class="memname">
1106 <td class="memname">#define ARM_PMU_L2D_CACHE   0x0016</td>
1109 </div><div class="memdoc">
1111 <p>Level 2 data cache access. </p>
1115 <a id="gaad08dcded491bf257d223e4171af41cc" name="gaad08dcded491bf257d223e4171af41cc"></a>
1116 <h2 class="memtitle"><span class="permalink"><a href="#gaad08dcded491bf257d223e4171af41cc">◆ </a></span>ARM_PMU_L2D_CACHE_ALLOCATE</h2>
1118 <div class="memitem">
1119 <div class="memproto">
1120 <table class="memname">
1122 <td class="memname">#define ARM_PMU_L2D_CACHE_ALLOCATE   0x0020</td>
1125 </div><div class="memdoc">
1127 <p>Level 2 data cache allocation without refill. </p>
1131 <a id="gaeb414c1b0375022abc2502ab503a3284" name="gaeb414c1b0375022abc2502ab503a3284"></a>
1132 <h2 class="memtitle"><span class="permalink"><a href="#gaeb414c1b0375022abc2502ab503a3284">◆ </a></span>ARM_PMU_L2D_CACHE_REFILL</h2>
1134 <div class="memitem">
1135 <div class="memproto">
1136 <table class="memname">
1138 <td class="memname">#define ARM_PMU_L2D_CACHE_REFILL   0x0017</td>
1141 </div><div class="memdoc">
1143 <p>Level 2 data cache refill. </p>
1147 <a id="ga1a0c4a1990eeed88edc3e1e0c4b1aca0" name="ga1a0c4a1990eeed88edc3e1e0c4b1aca0"></a>
1148 <h2 class="memtitle"><span class="permalink"><a href="#ga1a0c4a1990eeed88edc3e1e0c4b1aca0">◆ </a></span>ARM_PMU_L2D_CACHE_WB</h2>
1150 <div class="memitem">
1151 <div class="memproto">
1152 <table class="memname">
1154 <td class="memname">#define ARM_PMU_L2D_CACHE_WB   0x0018</td>
1157 </div><div class="memdoc">
1159 <p>Level 2 data cache write-back. </p>
1163 <a id="ga3406498b2c17ca080ebd68cc40d9630e" name="ga3406498b2c17ca080ebd68cc40d9630e"></a>
1164 <h2 class="memtitle"><span class="permalink"><a href="#ga3406498b2c17ca080ebd68cc40d9630e">◆ </a></span>ARM_PMU_L2I_CACHE</h2>
1166 <div class="memitem">
1167 <div class="memproto">
1168 <table class="memname">
1170 <td class="memname">#define ARM_PMU_L2I_CACHE   0x0027</td>
1173 </div><div class="memdoc">
1175 <p>Level 2 instruction cache access. </p>
1179 <a id="gaa18cee03802b46076e9ab66fd0a7c61d" name="gaa18cee03802b46076e9ab66fd0a7c61d"></a>
1180 <h2 class="memtitle"><span class="permalink"><a href="#gaa18cee03802b46076e9ab66fd0a7c61d">◆ </a></span>ARM_PMU_L2I_CACHE_REFILL</h2>
1182 <div class="memitem">
1183 <div class="memproto">
1184 <table class="memname">
1186 <td class="memname">#define ARM_PMU_L2I_CACHE_REFILL   0x0028</td>
1189 </div><div class="memdoc">
1191 <p>Level 2 instruction cache refill. </p>
1195 <a id="ga4e96b5a6fb13c657e78da342a02db200" name="ga4e96b5a6fb13c657e78da342a02db200"></a>
1196 <h2 class="memtitle"><span class="permalink"><a href="#ga4e96b5a6fb13c657e78da342a02db200">◆ </a></span>ARM_PMU_L3D_CACHE</h2>
1198 <div class="memitem">
1199 <div class="memproto">
1200 <table class="memname">
1202 <td class="memname">#define ARM_PMU_L3D_CACHE   0x002B</td>
1205 </div><div class="memdoc">
1207 <p>Level 3 data cache access. </p>
1211 <a id="gac11cbc6849dbad7bd8b64ab6e2a3f8d5" name="gac11cbc6849dbad7bd8b64ab6e2a3f8d5"></a>
1212 <h2 class="memtitle"><span class="permalink"><a href="#gac11cbc6849dbad7bd8b64ab6e2a3f8d5">◆ </a></span>ARM_PMU_L3D_CACHE_ALLOCATE</h2>
1214 <div class="memitem">
1215 <div class="memproto">
1216 <table class="memname">
1218 <td class="memname">#define ARM_PMU_L3D_CACHE_ALLOCATE   0x0029</td>
1221 </div><div class="memdoc">
1223 <p>Level 3 data cache allocation without refill. </p>
1227 <a id="gafe99db0693125100272247c147fb3b02" name="gafe99db0693125100272247c147fb3b02"></a>
1228 <h2 class="memtitle"><span class="permalink"><a href="#gafe99db0693125100272247c147fb3b02">◆ </a></span>ARM_PMU_L3D_CACHE_REFILL</h2>
1230 <div class="memitem">
1231 <div class="memproto">
1232 <table class="memname">
1234 <td class="memname">#define ARM_PMU_L3D_CACHE_REFILL   0x002A</td>
1237 </div><div class="memdoc">
1239 <p>Level 3 data cache refill. </p>
1243 <a id="gab823f95f7ac8196a208d12381b1b2a11" name="gab823f95f7ac8196a208d12381b1b2a11"></a>
1244 <h2 class="memtitle"><span class="permalink"><a href="#gab823f95f7ac8196a208d12381b1b2a11">◆ </a></span>ARM_PMU_L3D_CACHE_WB</h2>
1246 <div class="memitem">
1247 <div class="memproto">
1248 <table class="memname">
1250 <td class="memname">#define ARM_PMU_L3D_CACHE_WB   0x002C</td>
1253 </div><div class="memdoc">
1255 <p>Level 3 data cache write-back. </p>
1259 <a id="ga2e8725ee07c2b2c75a1b54261bc26cc8" name="ga2e8725ee07c2b2c75a1b54261bc26cc8"></a>
1260 <h2 class="memtitle"><span class="permalink"><a href="#ga2e8725ee07c2b2c75a1b54261bc26cc8">◆ </a></span>ARM_PMU_LD_RETIRED</h2>
1262 <div class="memitem">
1263 <div class="memproto">
1264 <table class="memname">
1266 <td class="memname">#define ARM_PMU_LD_RETIRED   0x0006</td>
1269 </div><div class="memdoc">
1271 <p>Memory-reading instruction architecturally executed and condition code check pass. </p>
1275 <a id="ga8b5641a3cb0e922a2b4e16ec14052861" name="ga8b5641a3cb0e922a2b4e16ec14052861"></a>
1276 <h2 class="memtitle"><span class="permalink"><a href="#ga8b5641a3cb0e922a2b4e16ec14052861">◆ </a></span>ARM_PMU_LE_CANCEL</h2>
1278 <div class="memitem">
1279 <div class="memproto">
1280 <table class="memname">
1282 <td class="memname">#define ARM_PMU_LE_CANCEL   0x0108</td>
1285 </div><div class="memdoc">
1287 <p>Loop end instruction not taken. </p>
1291 <a id="ga345461506c990125b1f2cbc62e3be22f" name="ga345461506c990125b1f2cbc62e3be22f"></a>
1292 <h2 class="memtitle"><span class="permalink"><a href="#ga345461506c990125b1f2cbc62e3be22f">◆ </a></span>ARM_PMU_LE_RETIRED</h2>
1294 <div class="memitem">
1295 <div class="memproto">
1296 <table class="memname">
1298 <td class="memname">#define ARM_PMU_LE_RETIRED   0x0100</td>
1301 </div><div class="memdoc">
1303 <p>Loop end instruction executed. </p>
1307 <a id="ga6a1d9f84bda091e96843665ff3913b50" name="ga6a1d9f84bda091e96843665ff3913b50"></a>
1308 <h2 class="memtitle"><span class="permalink"><a href="#ga6a1d9f84bda091e96843665ff3913b50">◆ </a></span>ARM_PMU_LE_SPEC</h2>
1310 <div class="memitem">
1311 <div class="memproto">
1312 <table class="memname">
1314 <td class="memname">#define ARM_PMU_LE_SPEC   0x0101</td>
1317 </div><div class="memdoc">
1319 <p>Loop end instruction speculatively executed. </p>
1323 <a id="ga6979efa69af7d0e62cc3e2f88b0155b8" name="ga6979efa69af7d0e62cc3e2f88b0155b8"></a>
1324 <h2 class="memtitle"><span class="permalink"><a href="#ga6979efa69af7d0e62cc3e2f88b0155b8">◆ </a></span>ARM_PMU_LL_CACHE_MISS_RD</h2>
1326 <div class="memitem">
1327 <div class="memproto">
1328 <table class="memname">
1330 <td class="memname">#define ARM_PMU_LL_CACHE_MISS_RD   0x0037</td>
1333 </div><div class="memdoc">
1335 <p>Last level data cache read miss. </p>
1339 <a id="ga902562d8161fffd45726dc4cc8727545" name="ga902562d8161fffd45726dc4cc8727545"></a>
1340 <h2 class="memtitle"><span class="permalink"><a href="#ga902562d8161fffd45726dc4cc8727545">◆ </a></span>ARM_PMU_LL_CACHE_RD</h2>
1342 <div class="memitem">
1343 <div class="memproto">
1344 <table class="memname">
1346 <td class="memname">#define ARM_PMU_LL_CACHE_RD   0x0036</td>
1349 </div><div class="memdoc">
1351 <p>Last level data cache read. </p>
1355 <a id="gab3852c2b3d59af106b9db7ea2c20c367" name="gab3852c2b3d59af106b9db7ea2c20c367"></a>
1356 <h2 class="memtitle"><span class="permalink"><a href="#gab3852c2b3d59af106b9db7ea2c20c367">◆ </a></span>ARM_PMU_MEM_ACCESS</h2>
1358 <div class="memitem">
1359 <div class="memproto">
1360 <table class="memname">
1362 <td class="memname">#define ARM_PMU_MEM_ACCESS   0x0013</td>
1365 </div><div class="memdoc">
1367 <p>Data memory access. </p>
1371 <a id="ga2c8d23cc64e87b2044bb39bf8d0bc1b1" name="ga2c8d23cc64e87b2044bb39bf8d0bc1b1"></a>
1372 <h2 class="memtitle"><span class="permalink"><a href="#ga2c8d23cc64e87b2044bb39bf8d0bc1b1">◆ </a></span>ARM_PMU_MEMORY_ERROR</h2>
1374 <div class="memitem">
1375 <div class="memproto">
1376 <table class="memname">
1378 <td class="memname">#define ARM_PMU_MEMORY_ERROR   0x001A</td>
1381 </div><div class="memdoc">
1383 <p>Local memory error. </p>
1387 <a id="gaa4c408a006a04e95ade26922669b6695" name="gaa4c408a006a04e95ade26922669b6695"></a>
1388 <h2 class="memtitle"><span class="permalink"><a href="#gaa4c408a006a04e95ade26922669b6695">◆ </a></span>ARM_PMU_MVE_FP_HP_RETIRED</h2>
1390 <div class="memitem">
1391 <div class="memproto">
1392 <table class="memname">
1394 <td class="memname">#define ARM_PMU_MVE_FP_HP_RETIRED   0x0208</td>
1397 </div><div class="memdoc">
1399 <p>MVE half-precision floating-point instruction architecturally executed. </p>
1403 <a id="gaf01d187b0cbf418d1fac55dd0ddd0827" name="gaf01d187b0cbf418d1fac55dd0ddd0827"></a>
1404 <h2 class="memtitle"><span class="permalink"><a href="#gaf01d187b0cbf418d1fac55dd0ddd0827">◆ </a></span>ARM_PMU_MVE_FP_HP_SPEC</h2>
1406 <div class="memitem">
1407 <div class="memproto">
1408 <table class="memname">
1410 <td class="memname">#define ARM_PMU_MVE_FP_HP_SPEC   0x0209</td>
1413 </div><div class="memdoc">
1415 <p>MVE half-precision floating-point instruction speculatively executed. </p>
1419 <a id="gac2dc7d92627b3caa391725a3f080288c" name="gac2dc7d92627b3caa391725a3f080288c"></a>
1420 <h2 class="memtitle"><span class="permalink"><a href="#gac2dc7d92627b3caa391725a3f080288c">◆ </a></span>ARM_PMU_MVE_FP_MAC_RETIRED</h2>
1422 <div class="memitem">
1423 <div class="memproto">
1424 <table class="memname">
1426 <td class="memname">#define ARM_PMU_MVE_FP_MAC_RETIRED   0x0214</td>
1429 </div><div class="memdoc">
1431 <p>MVE floating-point multiply or multiply-accumulate instruction architecturally executed. </p>
1435 <a id="gaf5302b3278a862c9264171955328a59a" name="gaf5302b3278a862c9264171955328a59a"></a>
1436 <h2 class="memtitle"><span class="permalink"><a href="#gaf5302b3278a862c9264171955328a59a">◆ </a></span>ARM_PMU_MVE_FP_MAC_SPEC</h2>
1438 <div class="memitem">
1439 <div class="memproto">
1440 <table class="memname">
1442 <td class="memname">#define ARM_PMU_MVE_FP_MAC_SPEC   0x0215</td>
1445 </div><div class="memdoc">
1447 <p>MVE floating-point multiply or multiply-accumulate instruction speculatively executed. </p>
1451 <a id="ga268b0bcbd30e8a928bd0f331fdf53ccf" name="ga268b0bcbd30e8a928bd0f331fdf53ccf"></a>
1452 <h2 class="memtitle"><span class="permalink"><a href="#ga268b0bcbd30e8a928bd0f331fdf53ccf">◆ </a></span>ARM_PMU_MVE_FP_RETIRED</h2>
1454 <div class="memitem">
1455 <div class="memproto">
1456 <table class="memname">
1458 <td class="memname">#define ARM_PMU_MVE_FP_RETIRED   0x0204</td>
1461 </div><div class="memdoc">
1463 <p>MVE floating-point instruction architecturally executed. </p>
1467 <a id="gab21171c50ebd1f304b11260edd015f52" name="gab21171c50ebd1f304b11260edd015f52"></a>
1468 <h2 class="memtitle"><span class="permalink"><a href="#gab21171c50ebd1f304b11260edd015f52">◆ </a></span>ARM_PMU_MVE_FP_SP_RETIRED</h2>
1470 <div class="memitem">
1471 <div class="memproto">
1472 <table class="memname">
1474 <td class="memname">#define ARM_PMU_MVE_FP_SP_RETIRED   0x020C</td>
1477 </div><div class="memdoc">
1479 <p>MVE single-precision floating-point instruction architecturally executed. </p>
1483 <a id="gae69e310892661af852ca2d4ec947d18a" name="gae69e310892661af852ca2d4ec947d18a"></a>
1484 <h2 class="memtitle"><span class="permalink"><a href="#gae69e310892661af852ca2d4ec947d18a">◆ </a></span>ARM_PMU_MVE_FP_SP_SPEC</h2>
1486 <div class="memitem">
1487 <div class="memproto">
1488 <table class="memname">
1490 <td class="memname">#define ARM_PMU_MVE_FP_SP_SPEC   0x020D</td>
1493 </div><div class="memdoc">
1495 <p>MVE single-precision floating-point instruction speculatively executed. </p>
1499 <a id="gadf9cfd45b59acfc314ebc814a1bcdccd" name="gadf9cfd45b59acfc314ebc814a1bcdccd"></a>
1500 <h2 class="memtitle"><span class="permalink"><a href="#gadf9cfd45b59acfc314ebc814a1bcdccd">◆ </a></span>ARM_PMU_MVE_FP_SPEC</h2>
1502 <div class="memitem">
1503 <div class="memproto">
1504 <table class="memname">
1506 <td class="memname">#define ARM_PMU_MVE_FP_SPEC   0x0205</td>
1509 </div><div class="memdoc">
1511 <p>MVE floating-point instruction speculatively executed. </p>
1515 <a id="ga3c1006bed2fb82b0749386261b397727" name="ga3c1006bed2fb82b0749386261b397727"></a>
1516 <h2 class="memtitle"><span class="permalink"><a href="#ga3c1006bed2fb82b0749386261b397727">◆ </a></span>ARM_PMU_MVE_INST_RETIRED</h2>
1518 <div class="memitem">
1519 <div class="memproto">
1520 <table class="memname">
1522 <td class="memname">#define ARM_PMU_MVE_INST_RETIRED   0x0200</td>
1525 </div><div class="memdoc">
1527 <p>MVE instruction architecturally executed. </p>
1531 <a id="ga1e276b6872345eb3b043626a11f235c6" name="ga1e276b6872345eb3b043626a11f235c6"></a>
1532 <h2 class="memtitle"><span class="permalink"><a href="#ga1e276b6872345eb3b043626a11f235c6">◆ </a></span>ARM_PMU_MVE_INST_SPEC</h2>
1534 <div class="memitem">
1535 <div class="memproto">
1536 <table class="memname">
1538 <td class="memname">#define ARM_PMU_MVE_INST_SPEC   0x0201</td>
1541 </div><div class="memdoc">
1543 <p>MVE instruction speculatively executed. </p>
1547 <a id="ga9248c93a3f19fddc93d3804a06f7238a" name="ga9248c93a3f19fddc93d3804a06f7238a"></a>
1548 <h2 class="memtitle"><span class="permalink"><a href="#ga9248c93a3f19fddc93d3804a06f7238a">◆ </a></span>ARM_PMU_MVE_INT_MAC_RETIRED</h2>
1550 <div class="memitem">
1551 <div class="memproto">
1552 <table class="memname">
1554 <td class="memname">#define ARM_PMU_MVE_INT_MAC_RETIRED   0x0228</td>
1557 </div><div class="memdoc">
1559 <p>MVE multiply or multiply-accumulate instruction architecturally executed. </p>
1563 <a id="ga7036f00faa9183ae450a3e4d9d6f2bbf" name="ga7036f00faa9183ae450a3e4d9d6f2bbf"></a>
1564 <h2 class="memtitle"><span class="permalink"><a href="#ga7036f00faa9183ae450a3e4d9d6f2bbf">◆ </a></span>ARM_PMU_MVE_INT_MAC_SPEC</h2>
1566 <div class="memitem">
1567 <div class="memproto">
1568 <table class="memname">
1570 <td class="memname">#define ARM_PMU_MVE_INT_MAC_SPEC   0x0229</td>
1573 </div><div class="memdoc">
1575 <p>MVE multiply or multiply-accumulate instruction speculatively executed. </p>
1579 <a id="ga5e3afafa91ebaeac0469a19ebb54719c" name="ga5e3afafa91ebaeac0469a19ebb54719c"></a>
1580 <h2 class="memtitle"><span class="permalink"><a href="#ga5e3afafa91ebaeac0469a19ebb54719c">◆ </a></span>ARM_PMU_MVE_INT_RETIRED</h2>
1582 <div class="memitem">
1583 <div class="memproto">
1584 <table class="memname">
1586 <td class="memname">#define ARM_PMU_MVE_INT_RETIRED   0x0224</td>
1589 </div><div class="memdoc">
1591 <p>MVE integer instruction architecturally executed. </p>
1595 <a id="ga16ed0bb1bb4718da93c41238da652d33" name="ga16ed0bb1bb4718da93c41238da652d33"></a>
1596 <h2 class="memtitle"><span class="permalink"><a href="#ga16ed0bb1bb4718da93c41238da652d33">◆ </a></span>ARM_PMU_MVE_INT_SPEC</h2>
1598 <div class="memitem">
1599 <div class="memproto">
1600 <table class="memname">
1602 <td class="memname">#define ARM_PMU_MVE_INT_SPEC   0x0225</td>
1605 </div><div class="memdoc">
1607 <p>MVE integer instruction speculatively executed. </p>
1611 <a id="ga8732a737f2b7adc43e3d1da7b3da92e6" name="ga8732a737f2b7adc43e3d1da7b3da92e6"></a>
1612 <h2 class="memtitle"><span class="permalink"><a href="#ga8732a737f2b7adc43e3d1da7b3da92e6">◆ </a></span>ARM_PMU_MVE_LD_CONTIG_RETIRED</h2>
1614 <div class="memitem">
1615 <div class="memproto">
1616 <table class="memname">
1618 <td class="memname">#define ARM_PMU_MVE_LD_CONTIG_RETIRED   0x0248</td>
1621 </div><div class="memdoc">
1623 <p>MVE contiguous load instruction architecturally executed. </p>
1627 <a id="ga8e58fe07254256fa3bf3d42fa2062141" name="ga8e58fe07254256fa3bf3d42fa2062141"></a>
1628 <h2 class="memtitle"><span class="permalink"><a href="#ga8e58fe07254256fa3bf3d42fa2062141">◆ </a></span>ARM_PMU_MVE_LD_CONTIG_SPEC</h2>
1630 <div class="memitem">
1631 <div class="memproto">
1632 <table class="memname">
1634 <td class="memname">#define ARM_PMU_MVE_LD_CONTIG_SPEC   0x0249</td>
1637 </div><div class="memdoc">
1639 <p>MVE contiguous load instruction speculatively executed. </p>
1643 <a id="ga50fb13c874b3f5e2b9ed9c320a36452c" name="ga50fb13c874b3f5e2b9ed9c320a36452c"></a>
1644 <h2 class="memtitle"><span class="permalink"><a href="#ga50fb13c874b3f5e2b9ed9c320a36452c">◆ </a></span>ARM_PMU_MVE_LD_MULTI_RETIRED</h2>
1646 <div class="memitem">
1647 <div class="memproto">
1648 <table class="memname">
1650 <td class="memname">#define ARM_PMU_MVE_LD_MULTI_RETIRED   0x0260</td>
1653 </div><div class="memdoc">
1655 <p>MVE memory load instruction targeting multiple registers architecturally executed. </p>
1659 <a id="gaf2d4e3d1f06d97899de7fa791477d62b" name="gaf2d4e3d1f06d97899de7fa791477d62b"></a>
1660 <h2 class="memtitle"><span class="permalink"><a href="#gaf2d4e3d1f06d97899de7fa791477d62b">◆ </a></span>ARM_PMU_MVE_LD_MULTI_SPEC</h2>
1662 <div class="memitem">
1663 <div class="memproto">
1664 <table class="memname">
1666 <td class="memname">#define ARM_PMU_MVE_LD_MULTI_SPEC   0x0261</td>
1669 </div><div class="memdoc">
1671 <p>MVE memory load instruction targeting multiple registers speculatively executed. </p>
1675 <a id="gaaf2ce8c0ea4c03c934aac6afc31fc5ff" name="gaaf2ce8c0ea4c03c934aac6afc31fc5ff"></a>
1676 <h2 class="memtitle"><span class="permalink"><a href="#gaaf2ce8c0ea4c03c934aac6afc31fc5ff">◆ </a></span>ARM_PMU_MVE_LD_NONCONTIG_RETIRED</h2>
1678 <div class="memitem">
1679 <div class="memproto">
1680 <table class="memname">
1682 <td class="memname">#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED   0x0254</td>
1685 </div><div class="memdoc">
1687 <p>MVE non-contiguous load instruction architecturally executed. </p>
1691 <a id="gadbcb82b7924b7bbee5c0d42a3de38572" name="gadbcb82b7924b7bbee5c0d42a3de38572"></a>
1692 <h2 class="memtitle"><span class="permalink"><a href="#gadbcb82b7924b7bbee5c0d42a3de38572">◆ </a></span>ARM_PMU_MVE_LD_NONCONTIG_SPEC</h2>
1694 <div class="memitem">
1695 <div class="memproto">
1696 <table class="memname">
1698 <td class="memname">#define ARM_PMU_MVE_LD_NONCONTIG_SPEC   0x0255</td>
1701 </div><div class="memdoc">
1703 <p>MVE non-contiguous load instruction speculatively executed. </p>
1707 <a id="gaa3379a51350a2fda8d8ab6d7795baa7a" name="gaa3379a51350a2fda8d8ab6d7795baa7a"></a>
1708 <h2 class="memtitle"><span class="permalink"><a href="#gaa3379a51350a2fda8d8ab6d7795baa7a">◆ </a></span>ARM_PMU_MVE_LD_RETIRED</h2>
1710 <div class="memitem">
1711 <div class="memproto">
1712 <table class="memname">
1714 <td class="memname">#define ARM_PMU_MVE_LD_RETIRED   0x023C</td>
1717 </div><div class="memdoc">
1719 <p>MVE load instruction architecturally executed. </p>
1723 <a id="ga78a6f89ab30ed01f7d8388eda697b4f8" name="ga78a6f89ab30ed01f7d8388eda697b4f8"></a>
1724 <h2 class="memtitle"><span class="permalink"><a href="#ga78a6f89ab30ed01f7d8388eda697b4f8">◆ </a></span>ARM_PMU_MVE_LD_SPEC</h2>
1726 <div class="memitem">
1727 <div class="memproto">
1728 <table class="memname">
1730 <td class="memname">#define ARM_PMU_MVE_LD_SPEC   0x023D</td>
1733 </div><div class="memdoc">
1735 <p>MVE load instruction speculatively executed. </p>
1739 <a id="ga26ed05deaa7b993904300069f0ecfac4" name="ga26ed05deaa7b993904300069f0ecfac4"></a>
1740 <h2 class="memtitle"><span class="permalink"><a href="#ga26ed05deaa7b993904300069f0ecfac4">◆ </a></span>ARM_PMU_MVE_LD_UNALIGNED_RETIRED</h2>
1742 <div class="memitem">
1743 <div class="memproto">
1744 <table class="memname">
1746 <td class="memname">#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED   0x0290</td>
1749 </div><div class="memdoc">
1751 <p>MVE unaligned load instruction architecturally executed. </p>
1755 <a id="gadc3bd0f32e0a08bba2d533479a59bd6e" name="gadc3bd0f32e0a08bba2d533479a59bd6e"></a>
1756 <h2 class="memtitle"><span class="permalink"><a href="#gadc3bd0f32e0a08bba2d533479a59bd6e">◆ </a></span>ARM_PMU_MVE_LD_UNALIGNED_SPEC</h2>
1758 <div class="memitem">
1759 <div class="memproto">
1760 <table class="memname">
1762 <td class="memname">#define ARM_PMU_MVE_LD_UNALIGNED_SPEC   0x0291</td>
1765 </div><div class="memdoc">
1767 <p>MVE unaligned load instruction speculatively executed. </p>
1771 <a id="ga8acf6a66c63798b76608caf52c96658d" name="ga8acf6a66c63798b76608caf52c96658d"></a>
1772 <h2 class="memtitle"><span class="permalink"><a href="#ga8acf6a66c63798b76608caf52c96658d">◆ </a></span>ARM_PMU_MVE_LDST_CONTIG_RETIRED</h2>
1774 <div class="memitem">
1775 <div class="memproto">
1776 <table class="memname">
1778 <td class="memname">#define ARM_PMU_MVE_LDST_CONTIG_RETIRED   0x0244</td>
1781 </div><div class="memdoc">
1783 <p>MVE contiguous load or store instruction architecturally executed. </p>
1787 <a id="ga5a83ef6a52739e1d223be503bbdaaab6" name="ga5a83ef6a52739e1d223be503bbdaaab6"></a>
1788 <h2 class="memtitle"><span class="permalink"><a href="#ga5a83ef6a52739e1d223be503bbdaaab6">◆ </a></span>ARM_PMU_MVE_LDST_CONTIG_SPEC</h2>
1790 <div class="memitem">
1791 <div class="memproto">
1792 <table class="memname">
1794 <td class="memname">#define ARM_PMU_MVE_LDST_CONTIG_SPEC   0x0245</td>
1797 </div><div class="memdoc">
1799 <p>MVE contiguous load or store instruction speculatively executed. </p>
1803 <a id="ga7d669378441408fc21aa551e483866cb" name="ga7d669378441408fc21aa551e483866cb"></a>
1804 <h2 class="memtitle"><span class="permalink"><a href="#ga7d669378441408fc21aa551e483866cb">◆ </a></span>ARM_PMU_MVE_LDST_MULTI_RETIRED</h2>
1806 <div class="memitem">
1807 <div class="memproto">
1808 <table class="memname">
1810 <td class="memname">#define ARM_PMU_MVE_LDST_MULTI_RETIRED   0x025C</td>
1813 </div><div class="memdoc">
1815 <p>MVE memory instruction targeting multiple registers architecturally executed. </p>
1819 <a id="ga7ea46cde08cb0cc4a46ef23835fb5aac" name="ga7ea46cde08cb0cc4a46ef23835fb5aac"></a>
1820 <h2 class="memtitle"><span class="permalink"><a href="#ga7ea46cde08cb0cc4a46ef23835fb5aac">◆ </a></span>ARM_PMU_MVE_LDST_MULTI_SPEC</h2>
1822 <div class="memitem">
1823 <div class="memproto">
1824 <table class="memname">
1826 <td class="memname">#define ARM_PMU_MVE_LDST_MULTI_SPEC   0x025D</td>
1829 </div><div class="memdoc">
1831 <p>MVE memory instruction targeting multiple registers speculatively executed. </p>
1835 <a id="ga7065b7f0aea461858b72912d22c329f2" name="ga7065b7f0aea461858b72912d22c329f2"></a>
1836 <h2 class="memtitle"><span class="permalink"><a href="#ga7065b7f0aea461858b72912d22c329f2">◆ </a></span>ARM_PMU_MVE_LDST_NONCONTIG_RETIRED</h2>
1838 <div class="memitem">
1839 <div class="memproto">
1840 <table class="memname">
1842 <td class="memname">#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED   0x0250</td>
1845 </div><div class="memdoc">
1847 <p>MVE non-contiguous load or store instruction architecturally executed. </p>
1851 <a id="ga193605eb52709741d91a64e3ad1a5894" name="ga193605eb52709741d91a64e3ad1a5894"></a>
1852 <h2 class="memtitle"><span class="permalink"><a href="#ga193605eb52709741d91a64e3ad1a5894">◆ </a></span>ARM_PMU_MVE_LDST_NONCONTIG_SPEC</h2>
1854 <div class="memitem">
1855 <div class="memproto">
1856 <table class="memname">
1858 <td class="memname">#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC   0x0251</td>
1861 </div><div class="memdoc">
1863 <p>MVE non-contiguous load or store instruction speculatively executed. </p>
1867 <a id="ga7d7d465a6c64400c49f93b6c8152296f" name="ga7d7d465a6c64400c49f93b6c8152296f"></a>
1868 <h2 class="memtitle"><span class="permalink"><a href="#ga7d7d465a6c64400c49f93b6c8152296f">◆ </a></span>ARM_PMU_MVE_LDST_RETIRED</h2>
1870 <div class="memitem">
1871 <div class="memproto">
1872 <table class="memname">
1874 <td class="memname">#define ARM_PMU_MVE_LDST_RETIRED   0x0238</td>
1877 </div><div class="memdoc">
1879 <p>MVE load or store instruction architecturally executed. </p>
1883 <a id="gaa98a18c06bd13daf2df6f89219ec68d5" name="gaa98a18c06bd13daf2df6f89219ec68d5"></a>
1884 <h2 class="memtitle"><span class="permalink"><a href="#gaa98a18c06bd13daf2df6f89219ec68d5">◆ </a></span>ARM_PMU_MVE_LDST_SPEC</h2>
1886 <div class="memitem">
1887 <div class="memproto">
1888 <table class="memname">
1890 <td class="memname">#define ARM_PMU_MVE_LDST_SPEC   0x0239</td>
1893 </div><div class="memdoc">
1895 <p>MVE load or store instruction speculatively executed. </p>
1899 <a id="ga627920bebd935709655687d844848934" name="ga627920bebd935709655687d844848934"></a>
1900 <h2 class="memtitle"><span class="permalink"><a href="#ga627920bebd935709655687d844848934">◆ </a></span>ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED</h2>
1902 <div class="memitem">
1903 <div class="memproto">
1904 <table class="memname">
1906 <td class="memname">#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED   0x0298</td>
1909 </div><div class="memdoc">
1911 <p>MVE unaligned noncontiguous load or store instruction architecturally executed. </p>
1915 <a id="gaf9ebeb1f49dba56d8f90f9bd5d3da58e" name="gaf9ebeb1f49dba56d8f90f9bd5d3da58e"></a>
1916 <h2 class="memtitle"><span class="permalink"><a href="#gaf9ebeb1f49dba56d8f90f9bd5d3da58e">◆ </a></span>ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC</h2>
1918 <div class="memitem">
1919 <div class="memproto">
1920 <table class="memname">
1922 <td class="memname">#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC   0x0299</td>
1925 </div><div class="memdoc">
1927 <p>MVE unaligned noncontiguous load or store instruction speculatively executed. </p>
1931 <a id="gaf358a9ed5c83a10cb695d9b19b1b3bc1" name="gaf358a9ed5c83a10cb695d9b19b1b3bc1"></a>
1932 <h2 class="memtitle"><span class="permalink"><a href="#gaf358a9ed5c83a10cb695d9b19b1b3bc1">◆ </a></span>ARM_PMU_MVE_LDST_UNALIGNED_RETIRED</h2>
1934 <div class="memitem">
1935 <div class="memproto">
1936 <table class="memname">
1938 <td class="memname">#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED   0x028C</td>
1941 </div><div class="memdoc">
1943 <p>MVE unaligned memory load or store instruction architecturally executed. </p>
1947 <a id="gab2264786bed578c89109859b55909c76" name="gab2264786bed578c89109859b55909c76"></a>
1948 <h2 class="memtitle"><span class="permalink"><a href="#gab2264786bed578c89109859b55909c76">◆ </a></span>ARM_PMU_MVE_LDST_UNALIGNED_SPEC</h2>
1950 <div class="memitem">
1951 <div class="memproto">
1952 <table class="memname">
1954 <td class="memname">#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC   0x028D</td>
1957 </div><div class="memdoc">
1959 <p>MVE unaligned memory load or store instruction speculatively executed. </p>
1963 <a id="ga01b4792990494b8f084ee00933a1adb0" name="ga01b4792990494b8f084ee00933a1adb0"></a>
1964 <h2 class="memtitle"><span class="permalink"><a href="#ga01b4792990494b8f084ee00933a1adb0">◆ </a></span>ARM_PMU_MVE_PRED</h2>
1966 <div class="memitem">
1967 <div class="memproto">
1968 <table class="memname">
1970 <td class="memname">#define ARM_PMU_MVE_PRED   0x02B8</td>
1973 </div><div class="memdoc">
1975 <p>Cycles where one or more predicated beats architecturally executed. </p>
1979 <a id="gacb3c0b922eae9aac321df97ec889e0ed" name="gacb3c0b922eae9aac321df97ec889e0ed"></a>
1980 <h2 class="memtitle"><span class="permalink"><a href="#gacb3c0b922eae9aac321df97ec889e0ed">◆ </a></span>ARM_PMU_MVE_ST_CONTIG_RETIRED</h2>
1982 <div class="memitem">
1983 <div class="memproto">
1984 <table class="memname">
1986 <td class="memname">#define ARM_PMU_MVE_ST_CONTIG_RETIRED   0x024C</td>
1989 </div><div class="memdoc">
1991 <p>MVE contiguous store instruction architecturally executed. </p>
1995 <a id="ga02cd64b9444e4babc7b69e8571d39bdd" name="ga02cd64b9444e4babc7b69e8571d39bdd"></a>
1996 <h2 class="memtitle"><span class="permalink"><a href="#ga02cd64b9444e4babc7b69e8571d39bdd">◆ </a></span>ARM_PMU_MVE_ST_CONTIG_SPEC</h2>
1998 <div class="memitem">
1999 <div class="memproto">
2000 <table class="memname">
2002 <td class="memname">#define ARM_PMU_MVE_ST_CONTIG_SPEC   0x024D</td>
2005 </div><div class="memdoc">
2007 <p>MVE contiguous store instruction speculatively executed. </p>
2011 <a id="ga76057cbda353b4ad6fbc3b6a63c193a5" name="ga76057cbda353b4ad6fbc3b6a63c193a5"></a>
2012 <h2 class="memtitle"><span class="permalink"><a href="#ga76057cbda353b4ad6fbc3b6a63c193a5">◆ </a></span>ARM_PMU_MVE_ST_MULTI_RETIRED</h2>
2014 <div class="memitem">
2015 <div class="memproto">
2016 <table class="memname">
2018 <td class="memname">#define ARM_PMU_MVE_ST_MULTI_RETIRED   0x0261</td>
2021 </div><div class="memdoc">
2023 <p>MVE memory store instruction targeting multiple registers architecturally executed. </p>
2027 <a id="gaf6a14402c79dba8fa765e8663dd0734d" name="gaf6a14402c79dba8fa765e8663dd0734d"></a>
2028 <h2 class="memtitle"><span class="permalink"><a href="#gaf6a14402c79dba8fa765e8663dd0734d">◆ </a></span>ARM_PMU_MVE_ST_MULTI_SPEC</h2>
2030 <div class="memitem">
2031 <div class="memproto">
2032 <table class="memname">
2034 <td class="memname">#define ARM_PMU_MVE_ST_MULTI_SPEC   0x0265</td>
2037 </div><div class="memdoc">
2039 <p>MVE memory store instruction targeting multiple registers speculatively executed. </p>
2043 <a id="ga8271f415ecc7573b57e82a24aec86ef1" name="ga8271f415ecc7573b57e82a24aec86ef1"></a>
2044 <h2 class="memtitle"><span class="permalink"><a href="#ga8271f415ecc7573b57e82a24aec86ef1">◆ </a></span>ARM_PMU_MVE_ST_NONCONTIG_RETIRED</h2>
2046 <div class="memitem">
2047 <div class="memproto">
2048 <table class="memname">
2050 <td class="memname">#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED   0x0258</td>
2053 </div><div class="memdoc">
2055 <p>MVE non-contiguous store instruction architecturally executed. </p>
2059 <a id="ga059327c80f396918a9f8192bcd0fa4a8" name="ga059327c80f396918a9f8192bcd0fa4a8"></a>
2060 <h2 class="memtitle"><span class="permalink"><a href="#ga059327c80f396918a9f8192bcd0fa4a8">◆ </a></span>ARM_PMU_MVE_ST_NONCONTIG_SPEC</h2>
2062 <div class="memitem">
2063 <div class="memproto">
2064 <table class="memname">
2066 <td class="memname">#define ARM_PMU_MVE_ST_NONCONTIG_SPEC   0x0259</td>
2069 </div><div class="memdoc">
2071 <p>MVE non-contiguous store instruction speculatively executed. </p>
2075 <a id="gad8d0079977fa97de4ee263703f1b2908" name="gad8d0079977fa97de4ee263703f1b2908"></a>
2076 <h2 class="memtitle"><span class="permalink"><a href="#gad8d0079977fa97de4ee263703f1b2908">◆ </a></span>ARM_PMU_MVE_ST_RETIRED</h2>
2078 <div class="memitem">
2079 <div class="memproto">
2080 <table class="memname">
2082 <td class="memname">#define ARM_PMU_MVE_ST_RETIRED   0x0240</td>
2085 </div><div class="memdoc">
2087 <p>MVE store instruction architecturally executed. </p>
2091 <a id="gabd3984d299b5416aac8d630722680c55" name="gabd3984d299b5416aac8d630722680c55"></a>
2092 <h2 class="memtitle"><span class="permalink"><a href="#gabd3984d299b5416aac8d630722680c55">◆ </a></span>ARM_PMU_MVE_ST_SPEC</h2>
2094 <div class="memitem">
2095 <div class="memproto">
2096 <table class="memname">
2098 <td class="memname">#define ARM_PMU_MVE_ST_SPEC   0x0241</td>
2101 </div><div class="memdoc">
2103 <p>MVE store instruction speculatively executed. </p>
2107 <a id="ga391afd8cb92cc65161b13ee3a3256d40" name="ga391afd8cb92cc65161b13ee3a3256d40"></a>
2108 <h2 class="memtitle"><span class="permalink"><a href="#ga391afd8cb92cc65161b13ee3a3256d40">◆ </a></span>ARM_PMU_MVE_ST_UNALIGNED_RETIRED</h2>
2110 <div class="memitem">
2111 <div class="memproto">
2112 <table class="memname">
2114 <td class="memname">#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED   0x0294</td>
2117 </div><div class="memdoc">
2119 <p>MVE unaligned store instruction architecturally executed. </p>
2123 <a id="ga21bf105499df85196b4137cb075a6fbe" name="ga21bf105499df85196b4137cb075a6fbe"></a>
2124 <h2 class="memtitle"><span class="permalink"><a href="#ga21bf105499df85196b4137cb075a6fbe">◆ </a></span>ARM_PMU_MVE_ST_UNALIGNED_SPEC</h2>
2126 <div class="memitem">
2127 <div class="memproto">
2128 <table class="memname">
2130 <td class="memname">#define ARM_PMU_MVE_ST_UNALIGNED_SPEC   0x0295</td>
2133 </div><div class="memdoc">
2135 <p>MVE unaligned store instruction speculatively executed. </p>
2139 <a id="ga2a45ec75b2011bd8375d89b7562b2de6" name="ga2a45ec75b2011bd8375d89b7562b2de6"></a>
2140 <h2 class="memtitle"><span class="permalink"><a href="#ga2a45ec75b2011bd8375d89b7562b2de6">◆ </a></span>ARM_PMU_MVE_STALL</h2>
2142 <div class="memitem">
2143 <div class="memproto">
2144 <table class="memname">
2146 <td class="memname">#define ARM_PMU_MVE_STALL   0x02CC</td>
2149 </div><div class="memdoc">
2151 <p>Stall cycles caused by an MVE instruction. </p>
2155 <a id="ga9a1cfef96ec7cd70acf134e368d8826a" name="ga9a1cfef96ec7cd70acf134e368d8826a"></a>
2156 <h2 class="memtitle"><span class="permalink"><a href="#ga9a1cfef96ec7cd70acf134e368d8826a">◆ </a></span>ARM_PMU_MVE_STALL_BREAK</h2>
2158 <div class="memitem">
2159 <div class="memproto">
2160 <table class="memname">
2162 <td class="memname">#define ARM_PMU_MVE_STALL_BREAK   0x02D3</td>
2165 </div><div class="memdoc">
2167 <p>Stall cycles caused by an MVE chain break. </p>
2171 <a id="ga29bc4c2e820914e94e2eb68a6a3352b9" name="ga29bc4c2e820914e94e2eb68a6a3352b9"></a>
2172 <h2 class="memtitle"><span class="permalink"><a href="#ga29bc4c2e820914e94e2eb68a6a3352b9">◆ </a></span>ARM_PMU_MVE_STALL_DEPENDENCY</h2>
2174 <div class="memitem">
2175 <div class="memproto">
2176 <table class="memname">
2178 <td class="memname">#define ARM_PMU_MVE_STALL_DEPENDENCY   0x02D4</td>
2181 </div><div class="memdoc">
2183 <p>Stall cycles caused by MVE register dependency. </p>
2187 <a id="ga8f4949084efce03d09bf5ba74cc91edd" name="ga8f4949084efce03d09bf5ba74cc91edd"></a>
2188 <h2 class="memtitle"><span class="permalink"><a href="#ga8f4949084efce03d09bf5ba74cc91edd">◆ </a></span>ARM_PMU_MVE_STALL_RESOURCE</h2>
2190 <div class="memitem">
2191 <div class="memproto">
2192 <table class="memname">
2194 <td class="memname">#define ARM_PMU_MVE_STALL_RESOURCE   0x02CD</td>
2197 </div><div class="memdoc">
2199 <p>Stall cycles caused by an MVE instruction because of resource conflicts. </p>
2203 <a id="ga7e76060791618f9b4d49ad493cfb6ba9" name="ga7e76060791618f9b4d49ad493cfb6ba9"></a>
2204 <h2 class="memtitle"><span class="permalink"><a href="#ga7e76060791618f9b4d49ad493cfb6ba9">◆ </a></span>ARM_PMU_MVE_STALL_RESOURCE_FP</h2>
2206 <div class="memitem">
2207 <div class="memproto">
2208 <table class="memname">
2210 <td class="memname">#define ARM_PMU_MVE_STALL_RESOURCE_FP   0x02CF</td>
2213 </div><div class="memdoc">
2215 <p>Stall cycles caused by an MVE instruction because of floating-point resource conflicts. </p>
2219 <a id="gaef33b3ff7f12d31238ff4dded5e67a11" name="gaef33b3ff7f12d31238ff4dded5e67a11"></a>
2220 <h2 class="memtitle"><span class="permalink"><a href="#gaef33b3ff7f12d31238ff4dded5e67a11">◆ </a></span>ARM_PMU_MVE_STALL_RESOURCE_INT</h2>
2222 <div class="memitem">
2223 <div class="memproto">
2224 <table class="memname">
2226 <td class="memname">#define ARM_PMU_MVE_STALL_RESOURCE_INT   0x02D0</td>
2229 </div><div class="memdoc">
2231 <p>Stall cycles caused by an MVE instruction because of integer resource conflicts. </p>
2235 <a id="gab486f5753edd9f10b0f100ff78944dd3" name="gab486f5753edd9f10b0f100ff78944dd3"></a>
2236 <h2 class="memtitle"><span class="permalink"><a href="#gab486f5753edd9f10b0f100ff78944dd3">◆ </a></span>ARM_PMU_MVE_STALL_RESOURCE_MEM</h2>
2238 <div class="memitem">
2239 <div class="memproto">
2240 <table class="memname">
2242 <td class="memname">#define ARM_PMU_MVE_STALL_RESOURCE_MEM   0x02CE</td>
2245 </div><div class="memdoc">
2247 <p>Stall cycles caused by an MVE instruction because of memory resource conflicts. </p>
2251 <a id="ga77fad5ad424271ed63fec98af071bb79" name="ga77fad5ad424271ed63fec98af071bb79"></a>
2252 <h2 class="memtitle"><span class="permalink"><a href="#ga77fad5ad424271ed63fec98af071bb79">◆ </a></span>ARM_PMU_MVE_VREDUCE_FP_RETIRED</h2>
2254 <div class="memitem">
2255 <div class="memproto">
2256 <table class="memname">
2258 <td class="memname">#define ARM_PMU_MVE_VREDUCE_FP_RETIRED   0x02A4</td>
2261 </div><div class="memdoc">
2263 <p>MVE floating-point vector reduction instruction architecturally executed. </p>
2267 <a id="gaa07c698f58c622d234a0007249717265" name="gaa07c698f58c622d234a0007249717265"></a>
2268 <h2 class="memtitle"><span class="permalink"><a href="#gaa07c698f58c622d234a0007249717265">◆ </a></span>ARM_PMU_MVE_VREDUCE_FP_SPEC</h2>
2270 <div class="memitem">
2271 <div class="memproto">
2272 <table class="memname">
2274 <td class="memname">#define ARM_PMU_MVE_VREDUCE_FP_SPEC   0x02A5</td>
2277 </div><div class="memdoc">
2279 <p>MVE floating-point vector reduction instruction speculatively executed. </p>
2283 <a id="ga649e7e81f0fd04ca6611f6a6c4035c57" name="ga649e7e81f0fd04ca6611f6a6c4035c57"></a>
2284 <h2 class="memtitle"><span class="permalink"><a href="#ga649e7e81f0fd04ca6611f6a6c4035c57">◆ </a></span>ARM_PMU_MVE_VREDUCE_INT_RETIRED</h2>
2286 <div class="memitem">
2287 <div class="memproto">
2288 <table class="memname">
2290 <td class="memname">#define ARM_PMU_MVE_VREDUCE_INT_RETIRED   0x02A8</td>
2293 </div><div class="memdoc">
2295 <p>MVE integer vector reduction instruction architecturally executed. </p>
2299 <a id="ga5b6f0bcfd63207c7bab03ea20167dd4b" name="ga5b6f0bcfd63207c7bab03ea20167dd4b"></a>
2300 <h2 class="memtitle"><span class="permalink"><a href="#ga5b6f0bcfd63207c7bab03ea20167dd4b">◆ </a></span>ARM_PMU_MVE_VREDUCE_INT_SPEC</h2>
2302 <div class="memitem">
2303 <div class="memproto">
2304 <table class="memname">
2306 <td class="memname">#define ARM_PMU_MVE_VREDUCE_INT_SPEC   0x02A9</td>
2309 </div><div class="memdoc">
2311 <p>MVE integer vector reduction instruction speculatively executed. </p>
2315 <a id="ga9546b924daa3c62e5f117026de58ad94" name="ga9546b924daa3c62e5f117026de58ad94"></a>
2316 <h2 class="memtitle"><span class="permalink"><a href="#ga9546b924daa3c62e5f117026de58ad94">◆ </a></span>ARM_PMU_MVE_VREDUCE_RETIRED</h2>
2318 <div class="memitem">
2319 <div class="memproto">
2320 <table class="memname">
2322 <td class="memname">#define ARM_PMU_MVE_VREDUCE_RETIRED   0x02A0</td>
2325 </div><div class="memdoc">
2327 <p>MVE vector reduction instruction architecturally executed. </p>
2331 <a id="gac714f988ae45871b2865f82c11383b36" name="gac714f988ae45871b2865f82c11383b36"></a>
2332 <h2 class="memtitle"><span class="permalink"><a href="#gac714f988ae45871b2865f82c11383b36">◆ </a></span>ARM_PMU_MVE_VREDUCE_SPEC</h2>
2334 <div class="memitem">
2335 <div class="memproto">
2336 <table class="memname">
2338 <td class="memname">#define ARM_PMU_MVE_VREDUCE_SPEC   0x02A1</td>
2341 </div><div class="memdoc">
2343 <p>MVE vector reduction instruction speculatively executed. </p>
2347 <a id="ga2fe9d3ea67ce833bd6323e4ce1a4e894" name="ga2fe9d3ea67ce833bd6323e4ce1a4e894"></a>
2348 <h2 class="memtitle"><span class="permalink"><a href="#ga2fe9d3ea67ce833bd6323e4ce1a4e894">◆ </a></span>ARM_PMU_OP_COMPLETE</h2>
2350 <div class="memitem">
2351 <div class="memproto">
2352 <table class="memname">
2354 <td class="memname">#define ARM_PMU_OP_COMPLETE   0x003A</td>
2357 </div><div class="memdoc">
2359 <p>Operation retired. </p>
2363 <a id="ga6c59149e9b1754987b44b62092bc9f09" name="ga6c59149e9b1754987b44b62092bc9f09"></a>
2364 <h2 class="memtitle"><span class="permalink"><a href="#ga6c59149e9b1754987b44b62092bc9f09">◆ </a></span>ARM_PMU_OP_SPEC</h2>
2366 <div class="memitem">
2367 <div class="memproto">
2368 <table class="memname">
2370 <td class="memname">#define ARM_PMU_OP_SPEC   0x003B</td>
2373 </div><div class="memdoc">
2375 <p>Operation speculatively executed. </p>
2379 <a id="ga54fd2c392399221077c67866a395e587" name="ga54fd2c392399221077c67866a395e587"></a>
2380 <h2 class="memtitle"><span class="permalink"><a href="#ga54fd2c392399221077c67866a395e587">◆ </a></span>ARM_PMU_PC_WRITE_RETIRED</h2>
2382 <div class="memitem">
2383 <div class="memproto">
2384 <table class="memname">
2386 <td class="memname">#define ARM_PMU_PC_WRITE_RETIRED   0x000C</td>
2389 </div><div class="memdoc">
2391 <p>Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass. </p>
2395 <a id="gaaae2c32a8ecd36b59ac98cf8e23b3cab" name="gaaae2c32a8ecd36b59ac98cf8e23b3cab"></a>
2396 <h2 class="memtitle"><span class="permalink"><a href="#gaaae2c32a8ecd36b59ac98cf8e23b3cab">◆ </a></span>ARM_PMU_SE_CALL_NS</h2>
2398 <div class="memitem">
2399 <div class="memproto">
2400 <table class="memname">
2402 <td class="memname">#define ARM_PMU_SE_CALL_NS   0x0115</td>
2405 </div><div class="memdoc">
2407 <p>Call to non-secure function, resulting in Security state change. </p>
2411 <a id="gad3ba2effbe303ca3fafdbc022fe206c1" name="gad3ba2effbe303ca3fafdbc022fe206c1"></a>
2412 <h2 class="memtitle"><span class="permalink"><a href="#gad3ba2effbe303ca3fafdbc022fe206c1">◆ </a></span>ARM_PMU_SE_CALL_S</h2>
2414 <div class="memitem">
2415 <div class="memproto">
2416 <table class="memname">
2418 <td class="memname">#define ARM_PMU_SE_CALL_S   0x0114</td>
2421 </div><div class="memdoc">
2423 <p>Call to secure function, resulting in Security state change. </p>
2427 <a id="ga8179d1144f8ec993bd1343e276d7b49b" name="ga8179d1144f8ec993bd1343e276d7b49b"></a>
2428 <h2 class="memtitle"><span class="permalink"><a href="#ga8179d1144f8ec993bd1343e276d7b49b">◆ </a></span>ARM_PMU_ST_RETIRED</h2>
2430 <div class="memitem">
2431 <div class="memproto">
2432 <table class="memname">
2434 <td class="memname">#define ARM_PMU_ST_RETIRED   0x0007</td>
2437 </div><div class="memdoc">
2439 <p>Memory-writing instruction architecturally executed and condition code check pass. </p>
2443 <a id="ga8bf75efa06a125ee2dfa9a130e7ba9a8" name="ga8bf75efa06a125ee2dfa9a130e7ba9a8"></a>
2444 <h2 class="memtitle"><span class="permalink"><a href="#ga8bf75efa06a125ee2dfa9a130e7ba9a8">◆ </a></span>ARM_PMU_STALL</h2>
2446 <div class="memitem">
2447 <div class="memproto">
2448 <table class="memname">
2450 <td class="memname">#define ARM_PMU_STALL   0x003C</td>
2453 </div><div class="memdoc">
2455 <p>Stall cycle for instruction or operation not sent for execution. </p>
2459 <a id="ga8737bee352820bd7d1bc8e5e4260143c" name="ga8737bee352820bd7d1bc8e5e4260143c"></a>
2460 <h2 class="memtitle"><span class="permalink"><a href="#ga8737bee352820bd7d1bc8e5e4260143c">◆ </a></span>ARM_PMU_STALL_BACKEND</h2>
2462 <div class="memitem">
2463 <div class="memproto">
2464 <table class="memname">
2466 <td class="memname">#define ARM_PMU_STALL_BACKEND   0x0024</td>
2469 </div><div class="memdoc">
2471 <p>No operation issued because of the backend. </p>
2475 <a id="ga5b068593baa831348664dfa7d44f5483" name="ga5b068593baa831348664dfa7d44f5483"></a>
2476 <h2 class="memtitle"><span class="permalink"><a href="#ga5b068593baa831348664dfa7d44f5483">◆ </a></span>ARM_PMU_STALL_FRONTEND</h2>
2478 <div class="memitem">
2479 <div class="memproto">
2480 <table class="memname">
2482 <td class="memname">#define ARM_PMU_STALL_FRONTEND   0x0023</td>
2485 </div><div class="memdoc">
2487 <p>No operation issued because of the frontend. </p>
2491 <a id="ga197b491f691110fb52aef4291782b6ab" name="ga197b491f691110fb52aef4291782b6ab"></a>
2492 <h2 class="memtitle"><span class="permalink"><a href="#ga197b491f691110fb52aef4291782b6ab">◆ </a></span>ARM_PMU_STALL_OP</h2>
2494 <div class="memitem">
2495 <div class="memproto">
2496 <table class="memname">
2498 <td class="memname">#define ARM_PMU_STALL_OP   0x003F</td>
2501 </div><div class="memdoc">
2503 <p>Instruction or operation slots not occupied each cycle. </p>
2507 <a id="ga9700ec74727a9fe3cd4cd40736628a23" name="ga9700ec74727a9fe3cd4cd40736628a23"></a>
2508 <h2 class="memtitle"><span class="permalink"><a href="#ga9700ec74727a9fe3cd4cd40736628a23">◆ </a></span>ARM_PMU_STALL_OP_BACKEND</h2>
2510 <div class="memitem">
2511 <div class="memproto">
2512 <table class="memname">
2514 <td class="memname">#define ARM_PMU_STALL_OP_BACKEND   0x003D</td>
2517 </div><div class="memdoc">
2519 <p>Stall cycle for instruction or operation not sent for execution due to pipeline backend. </p>
2523 <a id="ga69cfd3558cf6c6f3bb621ee75430427c" name="ga69cfd3558cf6c6f3bb621ee75430427c"></a>
2524 <h2 class="memtitle"><span class="permalink"><a href="#ga69cfd3558cf6c6f3bb621ee75430427c">◆ </a></span>ARM_PMU_STALL_OP_FRONTEND</h2>
2526 <div class="memitem">
2527 <div class="memproto">
2528 <table class="memname">
2530 <td class="memname">#define ARM_PMU_STALL_OP_FRONTEND   0x003E</td>
2533 </div><div class="memdoc">
2535 <p>Stall cycle for instruction or operation not sent for execution due to pipeline frontend. </p>
2539 <a id="ga6e02b08550d7e9b273ff7913f1b57bea" name="ga6e02b08550d7e9b273ff7913f1b57bea"></a>
2540 <h2 class="memtitle"><span class="permalink"><a href="#ga6e02b08550d7e9b273ff7913f1b57bea">◆ </a></span>ARM_PMU_SW_INCR</h2>
2542 <div class="memitem">
2543 <div class="memproto">
2544 <table class="memname">
2546 <td class="memname">#define ARM_PMU_SW_INCR   0x0000</td>
2549 </div><div class="memdoc">
2551 <p>Software update to the PMU_SWINC register, architecturally executed and condition code check pass. </p>
2555 <a id="gadaa75dc2ccfbf7a2263da9a9011f1603" name="gadaa75dc2ccfbf7a2263da9a9011f1603"></a>
2556 <h2 class="memtitle"><span class="permalink"><a href="#gadaa75dc2ccfbf7a2263da9a9011f1603">◆ </a></span>ARM_PMU_TRCEXTOUT0</h2>
2558 <div class="memitem">
2559 <div class="memproto">
2560 <table class="memname">
2562 <td class="memname">#define ARM_PMU_TRCEXTOUT0   0x4010</td>
2565 </div><div class="memdoc">
2567 <p>ETM external output 0. </p>
2571 <a id="ga47fe03fe6fe9bfebd98283cb57d94560" name="ga47fe03fe6fe9bfebd98283cb57d94560"></a>
2572 <h2 class="memtitle"><span class="permalink"><a href="#ga47fe03fe6fe9bfebd98283cb57d94560">◆ </a></span>ARM_PMU_TRCEXTOUT1</h2>
2574 <div class="memitem">
2575 <div class="memproto">
2576 <table class="memname">
2578 <td class="memname">#define ARM_PMU_TRCEXTOUT1   0x4011</td>
2581 </div><div class="memdoc">
2583 <p>ETM external output 1. </p>
2587 <a id="gab80e47ffebc3ae6ed2952756b020dbb9" name="gab80e47ffebc3ae6ed2952756b020dbb9"></a>
2588 <h2 class="memtitle"><span class="permalink"><a href="#gab80e47ffebc3ae6ed2952756b020dbb9">◆ </a></span>ARM_PMU_TRCEXTOUT2</h2>
2590 <div class="memitem">
2591 <div class="memproto">
2592 <table class="memname">
2594 <td class="memname">#define ARM_PMU_TRCEXTOUT2   0x4012</td>
2597 </div><div class="memdoc">
2599 <p>ETM external output 2. </p>
2603 <a id="gad70a3b074efd967485ffbfd3e387051d" name="gad70a3b074efd967485ffbfd3e387051d"></a>
2604 <h2 class="memtitle"><span class="permalink"><a href="#gad70a3b074efd967485ffbfd3e387051d">◆ </a></span>ARM_PMU_TRCEXTOUT3</h2>
2606 <div class="memitem">
2607 <div class="memproto">
2608 <table class="memname">
2610 <td class="memname">#define ARM_PMU_TRCEXTOUT3   0x4013</td>
2613 </div><div class="memdoc">
2615 <p>ETM external output 3. </p>
2619 <a id="ga45d5ea86fdc015f4fc100462150c92da" name="ga45d5ea86fdc015f4fc100462150c92da"></a>
2620 <h2 class="memtitle"><span class="permalink"><a href="#ga45d5ea86fdc015f4fc100462150c92da">◆ </a></span>ARM_PMU_UNALIGNED_LDST_RETIRED</h2>
2622 <div class="memitem">
2623 <div class="memproto">
2624 <table class="memname">
2626 <td class="memname">#define ARM_PMU_UNALIGNED_LDST_RETIRED   0x000F</td>
2629 </div><div class="memdoc">
2631 <p>Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass. </p>
2635 </div><!-- contents -->
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