begriffs open source - cmsis/blob - CMSIS/DoxyGen/Core_A/src/ref_gic.txt

   1 /* ##########################  GIC functions  ###################################### */
   2 /**
   3 \defgroup GIC_functions Generic Interrupt Controller Functions
   4 \ingroup CMSIS_Core_FunctionInterface
   5 \brief The Generic Interrupt Controller Functions grant access to the configuration, control and
   6 status registers of the Generic Interrupt Controller (GIC).
   7
   8 Reference: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069c/index.html">Generic Interrupt Controller Architecture Specificaton</a>.
   9
  10 The following table shows the register naming of CMSIS in correlation with various technical reference manuals.
  11
  12 | CMSIS Register Name                                                  | Cortex-A5 TRM  | Cortex-A7 TRM    | Cortex-A9 TRM  |
  13 | :------------------------------------------------------------------- | :------------- | :--------------- | :------------- |
  14 | <b>GIC Distributor</b>                                               |                |                  |                |
  15 | \ref GICDistributor_Type::CTLR "GICDistributor->CTLR"                | ICDDCR         | GICD_CTLR        | ICDDCR         |
  16 | \ref GICDistributor_Type::TYPER "GICDistributor->TYPER"              | ICDICTR        | GICD_TYPER       | ICDICTR        |
  17 | \ref GICDistributor_Type::IIDR "GICDistributor->IIDR"                | ICDIIDR        | GICD_IIDR        | ICDIIDR        |
  18 | \ref GICDistributor_Type::STATUSR "GICDistributor->STATUSR"          |                |                  |                |
  19 | \ref GICDistributor_Type::SETSPI_NSR "GICDistributor->SETSPI_NSR"    |                |                  |                |
  20 | \ref GICDistributor_Type::CLRSPI_NSR "GICDistributor->CLRSPI_NSR"    |                |                  |                |
  21 | \ref GICDistributor_Type::IGROUPR "GICDistributor->IGROUPR[]"        | ICDISR         | GICD_IGROUPRn    | ICDISRn        |
  22 | \ref GICDistributor_Type::ISENABLER "GICDistributor->ISENABLER[]"    | ICDISER        | GICD_ISENABLERn  | ICDISERn       |
  23 | \ref GICDistributor_Type::ICENABLER "GICDistributor->ICENABLER[]"    | ICDICER        | GICD_ICENABLERn  | ICDICERn       |
  24 | \ref GICDistributor_Type::ISPENDR "GICDistributor->ISPENDR[]"        | ICDISPR        | GICD_ISPENDRn    | ICDISPRn       |
  25 | \ref GICDistributor_Type::ICPENDR "GICDistributor->ICPENDR[]"        | ICDICPR        | GICD_ICPENDRn    | ICDICPRn       |
  26 | \ref GICDistributor_Type::ISACTIVER "GICDistributor->ISACTIVER[]"    | ICDABR         | GICD_ISACTIVERn  | ICDABRn        |
  27 | \ref GICDistributor_Type::ICACTIVER "GICDistributor->ICACTIVER[]"    |                | GICD_ICACTIVERn  |                |
  28 | \ref GICDistributor_Type::IPRIORITYR "GICDistributor->IPRIORITYR[]"  | ICDIPR         | GICD_IPRIORITYRn | ICDIPRn        |
  29 | \ref GICDistributor_Type::ITARGETSR "GICDistributor->ITARGETSR[]"    | ICDIPTR        | GICD_ITARGETSRn  | ICDIPTRn       |
  30 | \ref GICDistributor_Type::ICFGR "GICDistributor->ICFGR[]"            | ICDICFR        | GICD_ICFGRn      | ICDICFRn       |
  31 | \ref GICDistributor_Type::IGRPMODR "GICDistributor->IGRPMODR[0]"     | ICDPPIS        | GICD_PPISR       | ppi_status     |
  32 | \ref GICDistributor_Type::IGRPMODR "GICDistributor->IGRPMODR[31:1]"  | ICDSPIS        | GICD_SPISRn      | spi_status     |
  33 | \ref GICDistributor_Type::NSACR "GICDistributor->NSACR[]"            |                |                  |                |
  34 | \ref GICDistributor_Type::SGIR "GICDistributor->SGIR"                | ICDSGIR        | GICD_SGIR        | ICDSGIR        |
  35 | \ref GICDistributor_Type::CPENDSGIR "GICDistributor->CPENDSGIR[]"    |                | GICD_CPENDSGIRn  |                |
  36 | \ref GICDistributor_Type::SPENDSGIR "GICDistributor->SPENDSGIR[]"    |                | GICD_SPENDSGIRn  |                |
  37 | \ref GICDistributor_Type::IROUTER "GICDistributor->IROUTER[]"        |                |                  |                |
  38 | <b>GIC Interface</b>                                                 |                |                  |                |
  39 | \ref GICInterface_Type::CTLR "GICInterface->CTLR"                    | ICPICR         | GICC_CTLR        | ICCICR         |
  40 | \ref GICInterface_Type::PMR "GICInterface->PMR"                      | ICCIPMR        | GICC_PMRn        | ICCPMR         |
  41 | \ref GICInterface_Type::BPR "GICInterface->BPR"                      | ICCBPR         | GICC_BPR         | ICCBPR         |
  42 | \ref GICInterface_Type::IAR "GICInterface->IAR"                      | ICCIAR         | GICC_IAR         | ICCIAR         |
  43 | \ref GICInterface_Type::EOIR "GICInterface->EOIR"                    | ICCEOIR        | GICC_EOIR        | ICCEOIR        |
  44 | \ref GICInterface_Type::RPR "GICInterface->RPR"                      | ICCRPR         | GICC_RPR         | ICCRPR         |
  45 | \ref GICInterface_Type::HPPIR "GICInterface->HPPIR"                  | ICCHPIR        | GICC_HPPIR       | ICCHPIR        |
  46 | \ref GICInterface_Type::ABPR "GICInterface->ABPR"                    | ICCABPR        | GICC_ABPR        | ICCABPR        |
  47 | \ref GICInterface_Type::AIAR "GICInterface->AIAR"                    |                | GICC_AIAR        |                |
  48 | \ref GICInterface_Type::AEOIR "GICInterface->AEOIR"                  |                | GICC_AEOIR       |                |
  49 | \ref GICInterface_Type::AHPPIR "GICInterface->AHPPIR"                |                | GICC_AHPPIR      |                |
  50 | \ref GICInterface_Type::STATUSR "GICInterface->STATUSR"              |                |                  |                |
  51 | \ref GICInterface_Type::APR "GICInterface->APR[]"                    |                | GICC_APR0        |                |
  52 | \ref GICInterface_Type::NSAPR "GICInterface->NSAPR[]"                |                | GICC_NSAPR0      |                |
  53 | \ref GICInterface_Type::IIDR "GICInterface->IIDR"                    | ICCIIDR        | GICC_IIDR        | ICCIDR         |
  54 | \ref GICInterface_Type::DIR "GICInterface->DIR"                      |                | GICC_DIR         |                |
  55
  56 */
  57
  58 /** @{ */
  59
  60 /**
  61 \fn __STATIC_INLINE void GIC_EnableDistributor(void)
  62 \details Globally enable the forwarding of interrupts to the CPU interfaces.
  63
  64 \fn __STATIC_INLINE void GIC_DisableDistributor(void)
  65 \details Globally disable the forwarding of interrupts to the CPU interfaces.
  66 \see GIC_EnableDistributor
  67
  68 \fn __STATIC_INLINE uint32_t GIC_DistributorInfo(void)
  69 \details
  70 Provides information about the configuration of the GIC. It indicates:
  71  - whether the GIC implements the Security Extensions
  72  - the maximum number of interrupt IDs that the GIC supports
  73  - the number of CPU interfaces implemented
  74  - if the GIC implements the Security Extensions, the maximum number of
  75 implemented Lockable Shared Peripheral Interrupts (LSPIs).
  76
  77 \fn __STATIC_INLINE uint32_t GIC_DistributorImplementer(void)
  78 \details
  79 Provides information about the implementer and revision of the Distributor.
  80
  81 \fn __STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
  82 \details
  83 The \ref GICDistributor_Type.ITARGETSR "ITARGETSR" registers provide an 8-bit CPU targets field
  84 for each interrupt supported by the GIC. This field stores the list of target processors for the
  85 interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the
  86 interrupt if it is asserted and has sufficient priority.
  87
  88 \fn __STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn)
  89 \details
  90 Read the current interrupt to CPU assignment for the given interrupt.
  91 \see GIC_SetTarget
  92
  93 \fn __STATIC_INLINE void GIC_EnableInterface(void)
  94 \details
  95 Sets the Enable bit in the local CPUs \ref GICInterface_Type.CTLR "CTLR" register.
  96 Only the CPU executing the call is affected.
  97
  98 \fn __STATIC_INLINE void GIC_DisableInterface(void)
  99 \details
 100 Resets the Enable bit in the local CPUs \ref GICInterface_Type.CTLR "CTLR" register.
 101 Only the CPU executing the call is affected.
 102
 103 \fn __STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void)
 104 \details
 105 Provides the interrupt number of the highest priority interrupt pending.
 106 A read of this register acts as an acknowledge for the interrupt.
 107
 108 The read returns a spurious interrupt number of 1023 if any of the following apply:
 109  - Forwarding of interrupts by the Distributor to the CPU interface is disabled.
 110  - Signaling of interrupts by the CPU interface to the connected PE is disabled.
 111  - There are no pending interrupts on the CPU interface with sufficient priority for the interface to signal it to the PE.
 112
 113 \see GIC_EndInterrupt
 114
 115 \fn __STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn)
 116 A write to this register performs priority drop for the specified interrupt.
 117
 118 For nested interrupts, the order of calls to this function must be the reverse of the order of interrupt
 119 acknowledgement, i.e. calls to \ref GIC_AcknowledgePending. Behavior is UNPREDICTABLE if:
 120  - This ordering constraint is not maintained.
 121  - The given interrupt number does not match an active interrupt, or the ID of a spurious interrupt.
 122  - The given interrupt number does not match the last valid interrupt value returned by \ref GIC_AcknowledgePending.
 123
 124 \fn __STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn)
 125 \details
 126 Enables forwarding of the corresponding interrupt to the CPU interfaces.
 127
 128 \fn __STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn)
 129 \details
 130 Disables forwarding of the corresponding interrupt to the CPU interfaces.
 131
 132 \fn __STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn)
 133 \details
 134 Adds the pending state to the corresponding interrupt.
 135
 136 \fn __STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn)
 137 \details
 138 Removes the pending state from the corresponding interrupt.
 139
 140 \fn __STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 141 \details
 142 Configures the priority of the given interrupt.
 143
 144 The available interrupt priorities are IMPLEMENTATION DEFINED. In order to
 145 query the actual priorities one can
 146
 147 \code
 148 GIC_SetPriority(IRQn_TIM1, UINT32_MAX);       // try to configure lowest possible priority
 149 uint32_t actual = GIC_GetPriority(IRQn_TIM1); // retrieve actual lowest priority usable
 150 \endcode
 151
 152 \fn __STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)
 153 \details
 154 Can be used to retrieve the actual priority depending on the GIC implementation.
 155 \see GIC_SetPriority
 156
 157 \fn __STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority)
 158 \details
 159 Only interrupts with a higher priority (lower values) than the value provided are signaled.
 160
 161 \fn __STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void)
 162 \see GIC_SetInterfacePriorityMask
 163
 164 \fn __STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point)
 165 \details
 166 The binary point defines the amount of priority bits used as a group priority and subpriorities.
 167
 168 Interrupts sharing the same group priority do not preempt each other. But interrupts having a
 169 higher group priority (lower value) preempt interrups with a lower group priority.
 170
 171 The subpriority defines the execution sequence of interrupts with the same group priority if
 172 multiple are pending at time.
 173
 174 \fn __STATIC_INLINE uint32_t GIC_GetBinaryPoint(void)
 175 \details
 176 \see GIC_SetBinaryPoint
 177
 178 \fn __STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
 179 \details
 180 The return value is a combination of GIC's \ref GICDistributor_Type::ISACTIVER "ISACTIVER"
 181 and \ref GICDistributor_Type::ISPENDR "ISPENDR" registers.
 182
 183 Bit 0 denotes interrupts pending bit (interrupt should be handled) and bit 1 denotes interrupts
 184 active bit (interrupt is currently handled).
 185
 186 \fn __STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
 187 \fn __STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void)
 188 \fn __STATIC_INLINE uint32_t GIC_GetInterfaceId(void)
 189 \fn __STATIC_INLINE void GIC_DistInit(void)
 190 \details
 191 All shared peripheral interrupts (SPIs) are initialized to be
 192  - disabled
 193  - level-sensitive, 1-N model
 194  - priority 0x7F
 195  - targeting CPU0
 196 and the distributor is enabled.
 197
 198 \see
 199 GIC_DisableIRQ\n
 200 GIC_SetLevelModel\n
 201 GIC_SetPriority\n
 202 GIC_SetTarget\n
 203 GIC_EnableDistributor
 204
 205 \fn __STATIC_INLINE void GIC_CPUInterfaceInit(void)
 206 \details
 207 All software generated (SGIs) and private peripheral interrupts (PPIs) are initialized to be
 208  - disabled
 209  - level-sensitive, 1-N model
 210  - priority 0x7F
 211 and the interrupt interface is enabled.
 212
 213 The binary point is set to zero.
 214
 215 The interrupt priority mask is set to 0xFF.
 216
 217 \see
 218 GIC_DisableIRQ\n
 219 GIC_SetLevelModel\n
 220 GIC_SetPriority\n
 221 GIC_EnableInterface\n
 222 GIC_SetBinaryPoint\n
 223 GIC_SetInterfacePriorityMask\n
 224
 225 \fn __STATIC_INLINE void GIC_Enable(void)
 226 \details
 227 Initializes the distributor and the cpu interface.
 228
 229 \see
 230 GIC_DistInit
 231 GIC_CPUInterfaceInit
 232 */
 233
 234 /**
 235 \def GICDistributor
 236 \details
 237 Use GICDistributor to access the GIC Distributor registers.
 238
 239 \b Example:
 240 \code
 241 GICDistributor->CTRL |= 1; // Enable group 0 interrupts
 242 \endcode
 243 */
 244
 245 /**
 246 \def GICInterface
 247 \details
 248 Use GICInterface to access the GIC Interface registers.
 249
 250 \b Example:
 251 \code
 252 GICInterface->CTLR |= 1; // Enable interrupt signaling
 253 \endcode
 254 */
 255
 256 /**
 257 \struct GICInterface_Type
 258
 259 \struct GICDistributor_Type
 260 */
 261
 262 /** @} */
 263
 264 /* ########################## GICInterface_Type Member ########################## */
 265 /**
 266 \var __IOM uint32_t GICInterface_Type::CTLR
 267 \details CPU Interface Control Register
 268
 269 Enables the signaling of interrupts by the CPU interface to the connected processor, and
 270 provides additional top-level control of the CPU interface. In a GICv2 implementation, this
 271 includes control of the end of interrupt (EOI) behavior.
 272
 273 | Bits    | Name          | Function                                                       |
 274 | :------ | :------------ | :------------------------------------------------------------- |
 275 | [31:1]  | -             | Reserved.                                                      |
 276 | [0]     | Enable        | Interrupt signaling: 0 - Disable. 1 - Enable.                  |
 277
 278 \var __IM uint32_t GICInterface_Type::IAR
 279 \details CPU Interface Interrupt Acknowledge Register
 280
 281 | Bits    | Name          | Function                                                       |
 282 | :------ | :------------ | :------------------------------------------------------------- |
 283 | [31:24] | -             | Reserved.                                                      |
 284 | [23:0]  | INTID         | The interrupt number of the signaled interrupt.                |
 285
 286 \var __OM uint32_t GICInterface_Type::EOIR
 287 \details CPU Interface End Of Interrupt Register
 288
 289 | Bits    | Name          | Function                                                       |
 290 | :------ | :------------ | :------------------------------------------------------------- |
 291 | [31:24] | -             | Reserved.                                                      |
 292 | [23:0]  | INTID         | The interrupt number of the finished interrupt.                |
 293
 294  \var __IM uint32_t GICInterface_Type::HPPIR
 295 \details CPU Interface Highest Priority Pending Interrupt Register
 296
 297 | Bits    | Name          | Function                                                       |
 298 | :------ | :------------ | :------------------------------------------------------------- |
 299 | [31:24] | -             | Reserved.                                                      |
 300 | [23:0]  | INTID         | The INTID of the signaled interrupt.                           |
 301
 302 \var  __IM uint32_t GICInterface_Type::IIDR
 303 \details CPU Interface Identification Register
 304
 305 | Bits    | Name          | Function                                                       |
 306 | :------ | :------------ | :------------------------------------------------------------- |
 307 | [31:20] | ProductID     | An IMPLEMENTATION DEFINED product identifier                   |
 308 | [19:16] | Arch_version  | The version of the GIC architecture that is implemented.       |
 309 | [15:12] | Revision      | An IMPLEMENTATION DEFINED revision number for the CPU interface. |
 310 | [11:0]  | Implementer   | Contains the JEP106 code of the company that implemented the CPU interface. |
 311
 312
 313 \var __IOM uint32_t GICInterface_Type::PMR
 314 \details CPU Interface Priority Mask Register
 315
 316 | Bits    | Name          | Function                                                       |
 317 | :------ | :------------ | :------------------------------------------------------------- |
 318 | [31:8]  | -             | Reserved.                                                      |
 319 | [7:0]   | Priority      | The priority mask level for the CPU interface.                 |
 320
 321 \note IMPLEMENTATION DEFINED unsupported priority bits might be RAZ/WI.
 322
 323 \var __IOM uint32_t GICInterface_Type::BPR
 324 \details CPU Interface Binary Point Register
 325
 326 | Bits    | Name          | Function                                                       |
 327 | :------ | :------------ | :------------------------------------------------------------- |
 328 | [31:3]  | -             | Reserved.                                                      |
 329 | [2:0]   | Binary_Point  | Controls how the 8-bit interrupt priority field is split into a group priority field and a subpriority field. |
 330
 331 The binary point (values 0-7) defines the amount of priority bits used as subpriority. Please
 332 refer to the section Interrupt prioritization in the
 333 <a href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0048b/index.html">Arm Generic Interrupt Controller Architecture Specificaton</a>
 334 for details.
 335
 336 \var __IOM uint32_t GICInterface_Type::ABPR
 337 \details CPU Interface Aliased Binary Point Register
 338 \see GICInterface_Type::BPR
 339
 340 \var __OM uint32_t GICInterface_Type::AEOIR
 341 \details CPU Interface Aliased End Of Interrupt Register
 342 \see GICInterface_Type::EOIR
 343
 344 \var __IM uint32_t GICInterface_Type::AHPPIR
 345 \details CPU Interface Aliased Highest Priority Pending Interrupt Register
 346 \see GICInterface_Type::HPPIR
 347
 348 \var __IM uint32_t GICInterface_Type::AIAR
 349 \details CPU Interface Aliased Interrupt Acknowledge Register
 350 \see GICInterface_Type::IAR
 351
 352 \var __IOM uint32_t GICInterface_Type::APR[4]
 353 \details CPU Interface Active Priorities Registers
 354 \note The register values are IMPLEMENTATION DEFINED.
 355
 356 \var __OM uint32_t GICInterface_Type::DIR
 357 \details CPU Interface Deactivate Interrupt Register
 358
 359 | Bits    | Name  | Function                                                       |
 360 | :------ | :---- | :------------------------------------------------------------- |
 361 | [31:24] | -     | Reserved.                                                      |
 362 | [23:0]  | INTID | The INTID of the interrupt to be disabled.                     |
 363
 364 \var __IOM uint32_t GICInterface_Type::NSAPR[4]
 365 \details CPU Interface Non-secure Active Priorities Registers
 366 \note The register values are IMPLEMENTATION DEFINED.
 367 \see GICInterface_Type::APR[4]
 368
 369 \var __IM uint32_t GICInterface_Type::RPR
 370 \details CPU Interface Running Priority Register
 371
 372 | Bits    | Name     | Function                                                       |
 373 | :------ | :------- | :------------------------------------------------------------- |
 374 | [31:8]  | -        | Reserved.                                                      |
 375 | [7:0]   | Priority | The current running priority on the CPU interface.             |
 376
 377 \var __IOM uint32_t GICInterface_Type::STATUSR
 378 \details CPU Interface Status Register
 379
 380 | Bits    | Name     | Function                                                       |
 381 | :------ | :------- | :------------------------------------------------------------- |
 382 | [31:5]  | -        | Reserved.                                                      |
 383 | [4]     | ASV      | Attempted security violation.                                  |
 384 | [3]     | WROD     | Write to an RO location.                                       |
 385 | [2]     | RWOD     | Read of a WO location.                                         |
 386 | [1]     | WRD      | Write to a reserved location.                                  |
 387 | [0]     | RRD      | Read of a reserved location.                                   |
 388 */
 389
 390 /* ########################## GICDistributor_Type Member ########################## */
 391 /**
 392 \var __IOM uint32_t GICDistributor_Type::CTLR
 393 \details Distributor Control Register
 394
 395 When access is Secure, in a system that supports two Security states:
 396
 397 | Bits    | Name          | Function                                                       |
 398 | :------ | :------------ | :------------------------------------------------------------- |
 399 | [31]    | RWP           | Indicates whether a register write is in progress or not.      |
 400 | [30:8]  | -             | Reserved.                                                      |
 401 | [7]     | EINWF         | Enable 1 of N Wakeup Functionality, if available.              |
 402 | [6]     | DS            | Disable Security.                                              |
 403 | [5]     | ARE_NS        | Affinity Routing Enable, Non-secure state.                     |
 404 | [4]     | ARE_S         | Affinity Routing Enable, Secure state.                         |
 405 | [3]     | -             | Reserved.                                                      |
 406 | [2]     | EnableGrp1S   | Enable Secure Group 1 interrupts.                              |
 407 | [1]     | EnableGrp1NS  | Enable Non-secure Group 1 interrupts.                          |
 408 | [0]     | EnableGrp0    | Enable Group 0 interrupts.                                     |
 409
 410 When access is Non-secure, in a system that supports two Security states:
 411
 412 | Bits    | Name          | Function                                                       |
 413 | :------ | :------------ | :------------------------------------------------------------- |
 414 | [31]    | RWP           | Indicates whether a register write is in progress or not.      |
 415 | [30:5]  | -             | Reserved.                                                      |
 416 | [4]     | ARE_NS        | Affinity Routing Enable, Non-secure state.                     |
 417 | [3:2]   | -             | Reserved.                                                      |
 418 | [1]     | EnableGrp1A   | Enable Non-secure Group 1 interrupts.                          |
 419 | [0]     | EnableGrp1    | Enable Non-secure Group 1 interrupts.                          |
 420
 421 When in a system that supports only a single Security state:
 422
 423 | Bits    | Name          | Function                                                       |
 424 | :------ | :------------ | :------------------------------------------------------------- |
 425 | [31]    | RWP           | Indicates whether a register write is in progress or not.      |
 426 | [30:8]  | -             | Reserved.                                                      |
 427 | [7]     | EINWF         | Enable 1 of N Wakeup Functionality, if available.              |
 428 | [6]     | DS            | Disable Security.                                              |
 429 | [5]     | -             | Reserved.                                                      |
 430 | [4]     | ARE           | Affinity Routing Enable.                                       |
 431 | [3:2]   | -             | Reserved.                                                      |
 432 | [1]     | EnableGrp1    | Enable Group 1 interrupts.                                     |
 433 | [0]     | EnableGrp0    | Enable Group 0 interrupts.                                     |
 434
 435 \var __IM uint32_t GICDistributor_Type::TYPER
 436 \details Interrupt Controller Type Register
 437
 438 | Bits    | Name          | Function                                                       |
 439 | :------ | :------------ | :------------------------------------------------------------- |
 440 | [31:16] | -             | Reserved.                                                      |
 441 | [15:11] | LSPI          | Maximum number of lockable shared interrupts.                  |
 442 | [10]    | SecurityExtn  | Security Extensions: 0 - not implemented. 1 - implemented.     |
 443 | [9:8]   | -             | Reserved.                                                      |
 444 | [7:5]   | CPUNumber     | Number of implemented CPU interfaces [=CPUNumber+1]            |
 445 | [4:0]   | ITLinesNumber | Maximum number of interrups supported [=32*(ITLinesNumber+1)]. |
 446
 447 \var __IM uint32_t GICDistributor_Type::IIDR
 448 \details Distributor Implementer Identification Register
 449
 450 | Bits    | Name          | Function                                                       |
 451 | :------ | :------------ | :------------------------------------------------------------- |
 452 | [31:24] | ProductID     | An IMPLEMENTATION DEFINED product identifier                   |
 453 | [23:20] | -             | Reserved.                                                      |
 454 | [19:16] | Variant       | An IMPLEMENTATION DEFINED variant number.                      |
 455 | [15:12] | Revision      | An IMPLEMENTATION DEFINED revision number.                     |
 456 | [11:0]  | Implementer   | Contains the JEP106 code of the company implemented the GICD.  |
 457
 458 \var __IOM uint8_t GICDistributor_Type::ITARGETSR[1020]
 459 \details Interrupt Processor Targets Registers
 460
 461 Each bit in the target field corresponds to one CPU interface. A CPU targets field bit that corresponds
 462 to an unimplemented CPU interface is RAZ/WI.
 463
 464 | CPU target field value | Interrupt targets |
 465 | :--------------------- | :---------------- |
 466 | 0bxxxxxxx1             | CPU interface 0   |
 467 | 0bxxxxxx1x             | CPU interface 1   |
 468 | 0bxxxxx1xx             | CPU interface 2   |
 469 | 0bxxxx1xxx             | CPU interface 3   |
 470 | 0bxxx1xxxx             | CPU interface 4   |
 471 | 0bxx1xxxxx             | CPU interface 5   |
 472 | 0bx1xxxxxx             | CPU interface 6   |
 473 | 0b1xxxxxxx             | CPU interface 7   |
 474
 475 \var __IOM uint32_t GICDistributor_Type::IGROUPR[32]
 476 \details Interrupt Group Registers
 477
 478 Each bit corresponds to one interrupt:
 479  - Register index is given by INTID/32
 480  - Bit number is given by INTID%32
 481
 482 And the value denotes:
 483 - 0 When \ref GICDistributor_Type::CTLR "CTLR".DS==1, the corresponding interrupt is Group 0\n
 484     When \ref GICDistributor_Type::CTLR "CTLR".DS==0, the corresponding interrupt is Secure.
 485 - 1 When \ref GICDistributor_Type::CTLR "CTLR".DS==1, the corresponding interrupt is Group 1.\n
 486     When \ref GICDistributor_Type::CTLR "CTLR".DS==0, the corresponding interrupt is Non-secure Group 1.
 487
 488 \var __IO uint32_t GICDistributor_Type::CLRSPI_NSR
 489 \details Clear Non-secure SPI Pending Register
 490
 491 | Bits    | Name          | Function                                          |
 492 | :------ | :------------ | :------------------------------------------------ |
 493 | [31:10] | -             | Reserved.                                         |
 494 | [9:0]   | INTID         | The interrupt number to clear pending state from. |
 495
 496 \var __IO uint32_t GICDistributor_Type::CLRSPI_SR
 497 \details Clear Secure SPI Pending Register
 498
 499 | Bits    | Name          | Function                                          |
 500 | :------ | :------------ | :------------------------------------------------ |
 501 | [31:10] | -             | Reserved.                                         |
 502 | [9:0]   | INTID         | The interrupt number to clear pending state from. |
 503
 504 \var __IOM uint32_t GICDistributor_Type::IGRPMODR[32]
 505 \details Interrupt Group Modifier Registers
 506
 507 Each bit corresponds to one interrupt:
 508  - Register index is given by INTID/32
 509  - Bit number is given by INTID%32
 510
 511 \var __IOM uint64_t GICDistributor_Type::IROUTER[988]
 512 \details Interrupt Routing Registers
 513
 514 | Bits    | Name          | Function                                                      |
 515 | :------ | :------------ | :------------------------------------------------------------ |
 516 | [63:40] | -             | Reserved.                                                     |
 517 | [39:32] | Aff3          | Affinity level 3, the least significant affinity level field. |
 518 | [31]    | IRM           | Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy. |
 519 | [30:24] | -             | Reserved.                                                     |
 520 | [23:16] | Aff2          | Affinity level 2, an intermediate affinity level field.       |
 521 | [15:8]  | Aff1          | Affinity level 1, an intermediate affinity level field.       |
 522 | [7:0]   | Aff0          | Affinity level 0, the most significant affinity level field.  |
 523
 524 \var __IOM uint32_t GICDistributor_Type::NSACR[64]
 525 \details Non-secure Access Control Registers
 526
 527 Each two bits corresponds to one interrupt:
 528  - Register index is given by INTID/16
 529  - Bit number is given by 2*INTID%16
 530
 531 The possible values of each 2-bit field are:
 532  - 00 - Non-secure accesses to all fields associated with the corresponding interrupt are permitted.
 533  - 01 - Non-secure accesses are only permitted to requesting fields.
 534  - 10 - As 01, additionally accesses to clearing field are permitted.
 535  - 11 - As 10, additionally accesses to target and routing fields are permitted.
 536
 537 \var __IO uint32_t GICDistributor_Type::SETSPI_NSR
 538 \details Set Non-secure SPI Pending Register
 539
 540 | Bits    | Name          | Function                                          |
 541 | :------ | :------------ | :------------------------------------------------ |
 542 | [31:10] | -             | Reserved.                                         |
 543 | [9:0]   | INTID         | The interrupt number to set pending state for.    |
 544
 545 \var __IO uint32_t GICDistributor_Type::SETSPI_SR
 546 \details Set Secure SPI Pending Register
 547
 548 | Bits    | Name          | Function                                          |
 549 | :------ | :------------ | :------------------------------------------------ |
 550 | [31:10] | -             | Reserved.                                         |
 551 | [9:0]   | INTID         | The interrupt number to set pending state for.    |
 552
 553 \var __IOM uint8_t GICDistributor_Type::SPENDSGIR[16]
 554 \details SGI Set-Pending Registers
 555 Each register corresponds to one software generated interrupt (SGI).
 556
 557 Reading from this register reveals
 558  - 0 - interrupt is not pending
 559  - 1 - interrupt is pending
 560
 561 Writing to this register causes
 562  - 0 - no effect
 563  - 1 - adds the pending state
 564
 565 \var __IOM uint8_t GICDistributor_Type::CPENDSGIR[16]
 566 \details SGI Clear-Pending Registers
 567 Each register corresponds to one software generated interrupt (SGI).
 568
 569 Reading from this register reveals
 570  - 0 - interrupt is not pending
 571  - 1 - interrupt is pending
 572
 573 Writing to this register causes
 574  - 0 - no effect
 575  - 1 - removes the pending state
 576
 577 \var __IOM uint32_t GICDistributor_Type::STATUSR
 578 \details Error Reporting Status Register
 579
 580 | Bits    | Name          | Function                                          |
 581 | :------ | :------------ | :------------------------------------------------ |
 582 | [31:4]  | -             | Reserved.                                         |
 583 | [3]     | WROD          | Write to an RO location.                          |
 584 | [2]     | RWOD          | Read of a WO location.                            |
 585 | [1]     | WRD           | Write to a reserved location.                     |
 586 | [0]     | RRD           | Read of a reserved location.                      |
 587
 588 \var __IOM uint32_t GICDistributor_Type::ISENABLER[32]
 589 \details Interrupt Set-Enable Registers
 590
 591 Each bit corresponds to one interrupt:
 592  - Register index is given by INTID/32
 593  - Bit number is given by INTID%32
 594
 595 \note Bits corresponding to unimplemented interrupts are RAZ/WI.
 596
 597 \var __IOM uint32_t GICDistributor_Type::ICENABLER[32]
 598 \details Interrupt Clear-Enable Registers
 599
 600 Each bit corresponds to one interrupt:
 601  - Register index is given by INTID/32
 602  - Bit number is given by INTID%32
 603
 604 \note Bits corresponding to unimplemented interrupts are RAZ/WI.
 605
 606 \var __IOM uint32_t GICDistributor_Type::ISPENDR[32]
 607 \details Interrupt Set-Pending Registers
 608
 609 Each bit corresponds to one interrupt:
 610  - Register index is given by INTID/32
 611  - Bit number is given by INTID%32
 612
 613 \note Bits corresponding to unimplemented interrupts are RAZ/WI.
 614
 615 \var __IOM uint32_t GICDistributor_Type::ICPENDR[32]
 616 \details Interrupt Clear-Pending Registers
 617
 618 Each bit corresponds to one interrupt:
 619  - Register index is given by INTID/32
 620  - Bit number is given by INTID%32
 621
 622 \note Bits corresponding to unimplemented interrupts are RAZ/WI.
 623
 624 \var __IOM uint32_t GICDistributor_Type::ICFGR[64]
 625 \details Interrupt Configuration Registers
 626
 627 Each interrupt can be configured by two corresponding bits:
 628
 629 | Bits           | Name          | Function                                                       |
 630 | :------------- | :------------ | :------------------------------------------------------------- |
 631 | [2*INTID%16+1] | Edge          | Interrupt is: 0 - level sensitive, 1 - edge triggered          |
 632 | [2*INTID%16]   | Model         | 0 - N-N Model, 1 - 1-N Model; RAZ/WI when unsupported          |
 633
 634 \var __IOM uint8_t GICDistributor_Type::IPRIORITYR[1020]
 635 \details Interrupt Priority Registers
 636
 637 A GIC might implement fewer than eight priority bits, but must implement at least bits [7:4] of each
 638 field. In each field, unimplemented bits are RAZ/WI.
 639
 640 \note A register field corresponding to an unimplemented interrupt is RAZ/WI.
 641
 642 \var __IOM uint32_t GICDistributor_Type::ISACTIVER[32]
 643 \details Interrupt Set-Active Registers
 644
 645 Each bit corresponds to one interrupt:
 646  - Register index is given by INTID/32
 647  - Bit number is given by INTID%32
 648
 649 \note Bits corresponding to unimplemented interrupts are RAZ/WI.
 650
 651 \var __IOM uint32_t GICDistributor_Type::ICACTIVER[32]
 652 \details Interrupt Clear-Active Registers
 653
 654 Each bit corresponds to one interrupt:
 655  - Register index is given by INTID/32
 656  - Bit number is given by INTID%32
 657
 658 \note Bits corresponding to unimplemented interrupts are RAZ/WI.
 659
 660 \var __OM uint32_t GICDistributor_Type::SGIR
 661 \details Software Generated Interrupt Register
 662
 663 | Bits    | Name             | Function                                                         |
 664 | :------ | :------------    | :--------------------------------------------------------------- |
 665 | [31:26] | -                | Reserved.                                                        |
 666 | [25:24] | TargetFilterList | Determines how the Distributor processes the requested SGI.      |
 667 | [23:16] | CPUTargetList    | When TargetListFilter is 00, this field defines the CPU interfaces to which the Distributor must forward the interrupt. |
 668 | [15]    | NSATT            | Specifies the required group of the SGI.                         |
 669 | [14:4]  | -                | Reserved.                                                        |
 670 | [3:0]   | INTID            | The INTID of the SGI to forward to the specified CPU interfaces. |
 671
 672 Refer to \ref GICDistributor_Type::ITARGETSR "ITARGETSR" for details on TargetFilterList field.
 673
 674 */