begriffs open source - cmsis/blob - CMSIS/DoxyGen/Core/src/RegMap_CMSIS2ARM_Doc.txt

   1 /** \r
   2 \page RegMap_pg  Register Mapping\r
   3 \r
   4 \details \r
   5 \r
   6 The table below associates some common register names used in CMSIS to the register names \r
   7 used in Technical Reference Manuals.\r
   8 \r
   9 <table class="cmtable" summary="Register Mapping">\r
  10     <tr>\r
  11       <th>CMSIS Register Name</th>\r
  12       <th>Cortex-M3, Cortex-M4, and Cortex-M7</th>\r
  13       <th>Cortex-M0 and Cortex-M0+</th>\r
  14       <th>Register Name</th>\r
  15     </tr>\r
  16     <tr>\r
  17       <th colspan="4">Nested Vectored Interrupt Controller (NVIC) Register Access</th>\r
  18     </tr>\r
  19     <tr>\r
  20       <td>NVIC->ISER[]</td>\r
  21       <td>NVIC_ISER0..7</td>\r
  22       <td>ISER</td>\r
  23       <td>Interrupt Set-Enable Registers</td>\r
  24     </tr>\r
  25     <tr>\r
  26       <td>NVIC->ICER[]</td>\r
  27       <td>NVIC_ICER0..7</td>\r
  28       <td>ICER</td>\r
  29       <td>Interrupt Clear-Enable Registers</td>\r
  30     </tr>\r
  31    <tr>\r
  32       <td>NVIC->ISPR[]</td>\r
  33       <td>NVIC_ISPR0..7</td>\r
  34       <td>ISPR</td>\r
  35       <td>Interrupt Set-Pending Registers</td>\r
  36     </tr>\r
  37   <tr>\r
  38       <td>NVIC->ICPR[]</td>\r
  39       <td>NVIC_ICPR0..7</td>\r
  40       <td>ICPR</td>\r
  41       <td>Interrupt Clear-Pending Registers</td>\r
  42     </tr>\r
  43   <tr>\r
  44       <td>NVIC->IABR[]</td>\r
  45       <td>NVIC_IABR0..7</td>\r
  46       <td>-</td>\r
  47       <td>Interrupt Active Bit Register</td>\r
  48   </tr>\r
  49   <tr>\r
  50       <td>NVIC->IP[]</td>\r
  51       <td>NVIC_IPR0..59</td>\r
  52       <td>IPR0..7</td>\r
  53       <td>Interrupt Priority Register</td>\r
  54   </tr>\r
  55   <tr>\r
  56       <td>NVIC->STIR</td>\r
  57       <td>STIR</td>\r
  58       <td>-</td>\r
  59       <td>Software Triggered Interrupt Register</td>\r
  60   </tr>\r
  61   <tr>\r
  62     <th colspan="4">System Control Block (SCB) Register Access</th>\r
  63   </tr>\r
  64   <tr>\r
  65       <td>SCB->CPUID</td>\r
  66       <td>CPUID</td>\r
  67       <td>CPUID</td>\r
  68       <td>CPUID Base Register</td>\r
  69   </tr>\r
  70   <tr>\r
  71       <td>SCB->ICSR</td>\r
  72       <td>ICSR</td>\r
  73       <td>ICSR</td>\r
  74       <td>Interrupt Control and State Register</td>\r
  75   </tr>\r
  76   <tr>\r
  77       <td>SCB->VTOR</td>\r
  78       <td>VTOR</td>\r
  79       <td>-</td>\r
  80       <td>Vector Table Offset Register</td>\r
  81   </tr>\r
  82   <tr>\r
  83       <td>SCB->AIRCR</td>\r
  84       <td>AIRCR</td>\r
  85       <td>AIRCR</td>\r
  86       <td>Application Interrupt and Reset Control Register</td>\r
  87   </tr>\r
  88   <tr>\r
  89       <td>SCB->SCR</td>\r
  90       <td>SCR</td>\r
  91       <td>SCR</td>\r
  92       <td>System Control Register</td>\r
  93   </tr>\r
  94   <tr>\r
  95       <td>SCB->CCR</td>\r
  96       <td>CCR</td>\r
  97       <td>CCR</td>\r
  98       <td>Configuration and Control Register</td>\r
  99   </tr>\r
 100   <tr>\r
 101       <td>SCB->SHP[]</td>\r
 102       <td>SHPR1..3</td>\r
 103       <td>SHPR2..3</td>\r
 104       <td>System Handler Priority Registers</td>\r
 105   </tr>\r
 106   <tr>\r
 107       <td>SCB->SHCSR</td>\r
 108       <td>SHCSR</td>\r
 109       <td>SHCSR</td>\r
 110       <td>System Handler Control and State Register</td>\r
 111   </tr>\r
 112   <tr>\r
 113       <td>SCB->CFSR</td>\r
 114       <td>CFSR</td>\r
 115       <td>-</td>\r
 116       <td>Configurable Fault Status Registers</td>\r
 117   </tr>\r
 118   <tr>\r
 119       <td>SCB->HFSR</td>\r
 120       <td>HFSR</td>\r
 121       <td>-</td>\r
 122       <td>HardFault Status Register</td>\r
 123   </tr>\r
 124   <tr>\r
 125       <td>SCB->DFSR</td>\r
 126       <td>DFSR</td>\r
 127       <td>-</td>\r
 128       <td>Debug Fault Status Register</td>\r
 129   </tr>\r
 130   <tr>\r
 131       <td>SCB->MMFAR</td>\r
 132       <td>MMFAR</td>\r
 133       <td>-</td>\r
 134       <td>MemManage Fault Address Register</td>\r
 135   </tr>\r
 136   <tr>\r
 137       <td>SCB->BFAR</td>\r
 138       <td>BFAR</td>\r
 139       <td>-</td>\r
 140       <td>BusFault Address Register</td>\r
 141   </tr>\r
 142   <tr>\r
 143       <td>SCB->AFSR</td>\r
 144       <td>AFSR</td>\r
 145       <td>-</td>\r
 146       <td>Auxiliary Fault Status Register</td>\r
 147   </tr>\r
 148   <tr>\r
 149       <td>SCB->PFR[]</td>\r
 150       <td>ID_PFR0..1</td>\r
 151       <td>-</td>\r
 152       <td>Processor Feature Registers</td>\r
 153   </tr>\r
 154   <tr>\r
 155       <td>SCB->DFR</td>\r
 156       <td>ID_DFR0</td>\r
 157       <td>-</td>\r
 158       <td>Debug Feature Register</td>\r
 159   </tr>\r
 160   <tr>\r
 161       <td>SCB->ADR</td>\r
 162       <td>ID_AFR0</td>\r
 163       <td>-</td>\r
 164       <td>Auxiliary Feature Register</td>\r
 165   </tr>\r
 166   <tr>\r
 167       <td>SCB->MMFR[]</td>\r
 168       <td>ID_MMFR0..3</td>\r
 169       <td>-</td>\r
 170       <td>Memory Model Feature Registers</td>\r
 171   </tr>\r
 172   <tr>\r
 173       <td>SCB->ISAR[]</td>\r
 174       <td>ID_ISAR0..4</td>\r
 175       <td>-</td>\r
 176       <td>Instruction Set Attributes Registers</td>\r
 177   </tr>\r
 178   <tr>\r
 179       <td>SCB->CPACR</td>\r
 180       <td>CPACR</td>\r
 181       <td>-</td>\r
 182       <td>Coprocessor Access Control Register</td>\r
 183   </tr>\r
 184   <tr>\r
 185     <th colspan="4">System Control and ID Registers not in the SCB (SCnSCB) Register Access</th>\r
 186   </tr>\r
 187   <tr>\r
 188       <td>SCnSCB->ICTR</td>\r
 189       <td>ICTR</td>\r
 190       <td>-</td>\r
 191       <td>Interrupt Controller Type Register</td>\r
 192   </tr>\r
 193   <tr>\r
 194       <td>SCnSCB->ACTLR</td>\r
 195       <td>ACTLR</td>\r
 196       <td>-</td>\r
 197       <td>Auxiliary Control Register</td>\r
 198   </tr>\r
 199   <tr>\r
 200     <th colspan="4">System Timer (SysTick) Control and Status Register Access</th>\r
 201   </tr>\r
 202   <tr>\r
 203       <td>SysTick->CTRL</td>\r
 204       <td>STCSR</td>\r
 205       <td>SYST_CSR</td>\r
 206       <td>SysTick Control and Status Register</td>\r
 207   </tr>\r
 208   <tr>\r
 209       <td>SysTick->LOAD</td>\r
 210       <td>STRVR</td>\r
 211       <td>SYST_RVR</td>\r
 212       <td>SysTick Reload Value Register</td>\r
 213   </tr>\r
 214   <tr>\r
 215       <td>SysTick->VAL</td>\r
 216       <td>STCVR</td>\r
 217       <td>SYST_CVR</td>\r
 218       <td>SysTick Current Value Register</td>\r
 219   </tr>\r
 220   <tr>\r
 221       <td>SysTick->CALIB</td>\r
 222       <td>STCR</td>\r
 223       <td>SYST_CALIB</td>\r
 224       <td>SysTick Calibaration Value Register</td>\r
 225   </tr>\r
 226   <tr>\r
 227     <th colspan="4">Data Watchpoint and Trace (DWT) Register Access</th>\r
 228   </tr>\r
 229   <tr>\r
 230       <td>DWT->CTRL</td>\r
 231       <td>DWT_CTRL</td>\r
 232       <td>-</td>\r
 233       <td>Control Register</td>\r
 234   </tr>\r
 235   <tr>\r
 236       <td>DWT->CYCCNT</td>\r
 237       <td>DWT_CYCCNT</td>\r
 238       <td>-</td>\r
 239       <td>Cycle Count Register</td>\r
 240   </tr>\r
 241   <tr>\r
 242       <td>DWT->CPICNT</td>\r
 243       <td>DWT_CPICNT</td>\r
 244       <td>-</td>\r
 245       <td>CPI Count Register</td>\r
 246   </tr>\r
 247   <tr>\r
 248       <td>DWT->EXCCNT</td>\r
 249       <td>DWT_EXCCNT</td>\r
 250       <td>-</td>\r
 251       <td>Exception Overhead Count Register</td>\r
 252   </tr>\r
 253   <tr>\r
 254       <td>DWT->SLEEPCNT</td>\r
 255       <td>DWT_SLEEPCNT</td>\r
 256       <td>-</td>\r
 257       <td>Sleep Count Register</td>\r
 258   </tr>\r
 259   <tr>\r
 260       <td>DWT->LSUCNT</td>\r
 261       <td>DWT_LSUCNT</td>\r
 262       <td>-</td>\r
 263       <td>LSU Count Register</td>\r
 264   </tr>\r
 265   <tr>\r
 266       <td>DWT->FOLDCNT</td>\r
 267       <td>DWT_FOLDCNT</td>\r
 268       <td>-</td>\r
 269       <td>Folded-instruction Count Register</td>\r
 270   </tr>\r
 271   <tr>\r
 272       <td>DWT->PCSR</td>\r
 273       <td>DWT_PCSR</td>\r
 274       <td>-</td>\r
 275       <td>Program Counter Sample Register</td>\r
 276   </tr>\r
 277   <tr>\r
 278       <td>DWT->COMP0..3</td>\r
 279       <td>DWT_COMP0..3</td>\r
 280       <td>-</td>\r
 281       <td>Comparator Register 0..3</td>\r
 282   </tr>\r
 283   <tr>\r
 284       <td>DWT->MASK0..3</td>\r
 285       <td>DWT_MASK0..3</td>\r
 286       <td>-</td>\r
 287       <td>Mask Register 0..3</td>\r
 288   </tr>\r
 289   <tr>\r
 290       <td>DWT->FUNCTION0..3</td>\r
 291       <td>DWT_FUNCTION0..3</td>\r
 292       <td>-</td>\r
 293       <td>Function Register 0..3</td>\r
 294   </tr>\r
 295   <tr>\r
 296     <th colspan="4">Instrumentation Trace Macrocell (ITM) Register Access</th>\r
 297   </tr>\r
 298   <tr>\r
 299       <td>ITM->PORT[]</td>\r
 300       <td>ITM_STIM0..31</td>\r
 301       <td>-</td>\r
 302       <td>Stimulus Port Registers</td>\r
 303   </tr>\r
 304   <tr>\r
 305       <td>ITM->TER</td>\r
 306       <td>ITM_TER</td>\r
 307       <td>-</td>\r
 308       <td>Trace Enable Register</td>\r
 309   </tr>\r
 310   <tr>\r
 311       <td>ITM->TPR</td>\r
 312       <td>ITM_TPR</td>\r
 313       <td>-</td>\r
 314       <td>ITM Trace Privilege Register</td>\r
 315   </tr>\r
 316   <tr>\r
 317       <td>ITM->TCR</td>\r
 318       <td>ITM_TCR</td>\r
 319       <td>-</td>\r
 320       <td>Trace Control Register</td>\r
 321   </tr>\r
 322   <tr>\r
 323     <th colspan="4">Trace Port Interface (TPIU) Register Access</th>\r
 324   </tr>\r
 325   <tr>\r
 326       <td>TPI->SSPSR</td>\r
 327       <td>TPIU_SSPR</td>\r
 328       <td>-</td>\r
 329       <td>Supported Parallel Port Size Register</td>\r
 330   </tr>\r
 331   <tr>\r
 332       <td>TPI->CSPSR</td>\r
 333       <td>TPIU_CSPSR</td>\r
 334       <td>-</td>\r
 335       <td>Current Parallel Port Size Register</td>\r
 336   </tr>\r
 337   <tr>\r
 338       <td>TPI->ACPR</td>\r
 339       <td>TPIU_ACPR</td>\r
 340       <td>-</td>\r
 341       <td>Asynchronous Clock Prescaler Register</td>\r
 342   </tr>\r
 343   <tr>\r
 344       <td>TPI->SPPR</td>\r
 345       <td>TPIU_SPPR</td>\r
 346       <td>-</td>\r
 347       <td>Selected Pin Protocol Register</td>\r
 348   </tr>\r
 349   <tr>\r
 350       <td>TPI->FFSR</td>\r
 351       <td>TPIU_FFSR</td>\r
 352       <td>-</td>\r
 353       <td>Formatter and Flush Status Register</td>\r
 354   </tr>\r
 355   <tr>\r
 356       <td>TPI->FFCR</td>\r
 357       <td>TPIU_FFCR</td>\r
 358       <td>-</td>\r
 359       <td>Formatter and Flush Control Register</td>\r
 360   </tr>\r
 361   <tr>\r
 362       <td>TPI->FSCR</td>\r
 363       <td>TPIU_FSCR</td>\r
 364       <td>-</td>\r
 365       <td>Formatter Synchronization Counter Register</td>\r
 366   </tr>\r
 367   <tr>\r
 368       <td>TPI->TRIGGER</td>\r
 369       <td>TRIGGER</td>\r
 370       <td>-</td>\r
 371       <td>TRIGGER</td>\r
 372   </tr>\r
 373   <tr>\r
 374       <td>TPI->FIFO0</td>\r
 375       <td>FIFO data 0</td>\r
 376       <td>-</td>\r
 377       <td>Integration ETM Data</td>\r
 378   </tr>\r
 379   <tr>\r
 380       <td>TPI->ITATBCTR2</td>\r
 381       <td>ITATBCTR2</td>\r
 382       <td>-</td>\r
 383       <td>ITATBCTR2</td>\r
 384   </tr>\r
 385   <tr>\r
 386       <td>TPI->ITATBCTR0</td>\r
 387       <td>ITATBCTR0</td>\r
 388       <td>-</td>\r
 389       <td>ITATBCTR0</td>\r
 390   </tr>\r
 391   <tr>\r
 392       <td>TPI->FIFO1</td>\r
 393       <td>FIFO data 1</td>\r
 394       <td>-</td>\r
 395       <td>Integration ITM Data</td>\r
 396   </tr>\r
 397   <tr>\r
 398       <td>TPI->ITCTRL</td>\r
 399       <td>TPIU_ITCTRL</td>\r
 400       <td>-</td>\r
 401       <td>Integration Mode Control</td>\r
 402   </tr>\r
 403   <tr>\r
 404       <td>TPI->CLAIMSET</td>\r
 405       <td>CLAIMSET</td>\r
 406       <td>-</td>\r
 407       <td>Claim tag set</td>\r
 408   </tr>\r
 409   <tr>\r
 410       <td>TPI->CLAIMCLR</td>\r
 411       <td>CLAIMCLR</td>\r
 412       <td>-</td>\r
 413       <td>Claim tag clear</td>\r
 414   </tr>\r
 415   <tr>\r
 416       <td>TPI->DEVID</td>\r
 417       <td>TPIU_DEVID</td>\r
 418       <td>-</td>\r
 419       <td>TPIU_DEVID</td>\r
 420   </tr>\r
 421   <tr>\r
 422       <td>TPI->DEVTYPE</td>\r
 423       <td>TPIU_DEVTYPE</td>\r
 424       <td>-</td>\r
 425       <td>TPIU_DEVTYPE</td>\r
 426   </tr>\r
 427   <tr>\r
 428     <th colspan="4">Memory Protection Unit (MPU) Register Access</th>\r
 429   </tr>\r
 430   <tr>\r
 431       <td>MPU->TYPE</td>\r
 432       <td>MPU_TYPE</td>\r
 433       <td>-</td>\r
 434       <td>MPU Type Register</td>\r
 435   </tr>\r
 436   <tr>\r
 437       <td>MPU->CTRL</td>\r
 438       <td>MPU_CTRL</td>\r
 439       <td>-</td>\r
 440       <td>MPU Control Register</td>\r
 441   </tr>\r
 442   <tr>\r
 443       <td>MPU->RNR</td>\r
 444       <td>MPU_RNR</td>\r
 445       <td>-</td>\r
 446       <td>MPU Region Number Register</td>\r
 447   </tr>\r
 448   <tr>\r
 449       <td>MPU->RBAR</td>\r
 450       <td>MPU_RBAR</td>\r
 451       <td>-</td>\r
 452       <td>MPU Region Base Address Register</td>\r
 453   </tr>\r
 454   <tr>\r
 455       <td>MPU->RASR</td>\r
 456       <td>MPU_RASR</td>\r
 457       <td>-</td>\r
 458       <td>MPU Region Attribute and Size Register</td>\r
 459   </tr>\r
 460   <tr>\r
 461       <td>MPU->RBAR_A1..3</td>\r
 462       <td>MPU_RBAR_A1..3</td>\r
 463       <td>-</td>\r
 464       <td>MPU alias Register</td>\r
 465   </tr>\r
 466   <tr>\r
 467       <td>MPU->RSAR_A1..3</td>\r
 468       <td>MPU_RSAR_A1..3</td>\r
 469       <td>-</td>\r
 470       <td>MPU alias Register</td>\r
 471   </tr>\r
 472   <tr>\r
 473     <th colspan="4">Floating Point Unit (FPU) Register Access [only Cortex-M4 and Cortex-M7 both with FPU]</th>\r
 474   </tr>\r
 475   <tr>\r
 476       <td>FPU->FPCCR</td>\r
 477       <td>FPCCR</td>\r
 478       <td>-</td>\r
 479       <td>FP Context Control Register</td>\r
 480   </tr>\r
 481   <tr>\r
 482       <td>FPU->FPCAR</td>\r
 483       <td>FPCAR</td>\r
 484       <td>-</td>\r
 485       <td>FP Context Address Register</td>\r
 486   </tr>\r
 487   <tr>\r
 488       <td>FPU->FPDSCR</td>\r
 489       <td>FPDSCR</td>\r
 490       <td>-</td>\r
 491       <td>FP Default Status Control Register</td>\r
 492   </tr>\r
 493   <tr>\r
 494       <td>FPU->MVFR0..1</td>\r
 495       <td>MVFR0..1</td>\r
 496       <td>-</td>\r
 497       <td>Media and VFP Feature Registers</td>\r
 498   </tr>\r
 499 </table>\r
 500 */