begriffs open source - cmsis/blob - ARM.CMSIS.pdsc

   1 <?xml version="1.0" encoding="UTF-8"?>
   2
   3 <package schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="PACK.xsd">
   4   <name>CMSIS</name>
   5   <description>CMSIS (Cortex Microcontroller Software Interface Standard)</description>
   6   <vendor>ARM</vendor>
   7   <!-- <license>license.txt</license> -->
   8   <url>http://www.keil.com/pack/</url>
   9
  10   <releases>
  11     <release version="5.3.1-dev7">
  12       Generic Arm Device:
  13        - Reworked ARM device support files.
  14        - Updated RTOS2 examples.
  15        - Updated DSP examples.
  16     </release>
  17     <release version="5.3.1-dev6">
  18       Utilities:
  19       - updated SVDConv and PackChk for Win32 and Linux
  20     </release>
  21     <release version="5.3.1-dev5">
  22       Aligned pack structure with repository.
  23       The following folders are deprecated:
  24       - CMSIS/Include/
  25       - CMSIS/DSP_Lib/
  26     </release>
  27     <release version="5.3.1-dev4">
  28       CMSIS-RTOS2:
  29         - API 2.1.3 (see revision history for details)
  30     </release>
  31     <release version="5.3.1-dev3">
  32       RTX5 (Cortex-A): updated exception handling
  33     </release>
  34     <release version="5.3.1-dev2">
  35       CMSIS-RTOS2:
  36         - RTX 5.4.0 (see revision history for details)
  37     </release>
  38     <release version="5.3.1-dev1">
  39       CMSIS-Core(M): 5.1.2 (see revision history for details)
  40       CMSIS-Core(A): 1.1.2 (see revision history for details)
  41       CMSIS-RTOS2:
  42         - RTX 5.3.1 (see revision history for details)
  43       CMSIS-Driver:
  44         - Flash Driver API V2.2.0
  45     </release>
  46     <release version="5.3.1-dev0">
  47       Patch release scheduled for after EW18.
  48     </release>
  49     <release version="5.3.0" date="2018-02-22">
  50       Updated Arm company brand.
  51       CMSIS-Core(M): 5.1.1 (see revision history for details)
  52       CMSIS-Core(A): 1.1.1 (see revision history for details)
  53       CMSIS-DAP: 2.0.0 (see revision history for details)
  54       CMSIS-NN: 1.0.0
  55         - Initial contribution of the bare metal Neural Network Library.
  56       CMSIS-RTOS2:
  57         - RTX 5.3.0 (see revision history for details)
  58         - OS Tick API 1.0.1
  59     </release>
  60     <release version="5.2.0" date="2017-11-16">
  61       CMSIS-Core(M): 5.1.0 (see revision history for details)
  62         - Added MPU Functions for ARMv8-M for Cortex-M23/M33.
  63         - Added compiler_iccarm.h to replace compiler_iar.h shipped with the compiler.
  64       CMSIS-Core(A): 1.1.0 (see revision history for details)
  65         - Added compiler_iccarm.h.
  66         - Added additional access functions for physical timer.
  67       CMSIS-DAP: 1.2.0 (see revision history for details)
  68       CMSIS-DSP: 1.5.2 (see revision history for details)
  69       CMSIS-Driver: 2.6.0 (see revision history for details)
  70         - CAN Driver API V1.2.0
  71         - NAND Driver API V2.3.0
  72       CMSIS-RTOS:
  73         - RTX: added variant for Infineon XMC4 series affected by PMU_CM.001 errata.
  74       CMSIS-RTOS2:
  75         - API 2.1.2 (see revision history for details)
  76         - RTX 5.2.3 (see revision history for details)
  77       Devices:
  78         - Added GCC startup and linker script for Cortex-A9.
  79         - Added device ARMCM0plus_MPU for Cortex-M0+ with MPU.
  80         - Added IAR startup code for Cortex-A9
  81     </release>
  82     <release version="5.1.1" date="2017-09-19">
  83       CMSIS-RTOS2:
  84       - RTX 5.2.1 (see revision history for details)
  85     </release>
  86     <release version="5.1.0" date="2017-08-04">
  87       CMSIS-Core(M): 5.0.2 (see revision history for details)
  88       - Changed Version Control macros to be core agnostic.
  89       - Added MPU Functions for ARMv7-M for Cortex-M0+/M3/M4/M7.
  90       CMSIS-Core(A): 1.0.0 (see revision history for details)
  91       - Initial release
  92       - IRQ Controller API 1.0.0
  93       CMSIS-Driver: 2.05 (see revision history for details)
  94       - All typedefs related to status have been made volatile.
  95       CMSIS-RTOS2:
  96       - API 2.1.1 (see revision history for details)
  97       - RTX 5.2.0 (see revision history for details)
  98       - OS Tick API 1.0.0
  99       CMSIS-DSP: 1.5.2 (see revision history for details)
 100       - Fixed GNU Compiler specific diagnostics.
 101       CMSIS-PACK: 1.5.0 (see revision history for details)
 102       - added System Description File (*.SDF) Format
 103       CMSIS-Zone: 0.0.1 (Preview)
 104       - Initial specification draft
 105     </release>
 106     <release version="5.0.1" date="2017-02-03">
 107       Package Description:
 108       - added taxonomy for Cclass RTOS
 109       CMSIS-RTOS2:
 110       - API 2.1   (see revision history for details)
 111       - RTX 5.1.0 (see revision history for details)
 112       CMSIS-Core: 5.0.1 (see revision history for details)
 113       - Added __PACKED_STRUCT macro
 114       - Added uVisior support
 115       - Updated cmsis_armcc.h: corrected macro __ARM_ARCH_6M__
 116       - Updated template for secure main function (main_s.c)
 117       - Updated template for Context Management for ARMv8-M TrustZone (tz_context.c)
 118       CMSIS-DSP: 1.5.1 (see revision history for details)
 119       - added ARMv8M DSP libraries.
 120       CMSIS-PACK:1.4.9 (see revision history for details)
 121       - added Pack Index File specification and schema file
 122     </release>
 123     <release version="5.0.0" date="2016-11-11">
 124       Changed open source license to Apache 2.0
 125       CMSIS_Core:
 126        - Added support for Cortex-M23 and Cortex-M33.
 127        - Added ARMv8-M device configurations for mainline and baseline.
 128        - Added CMSE support and thread context management for TrustZone for ARMv8-M
 129        - Added cmsis_compiler.h to unify compiler behaviour.
 130        - Updated function SCB_EnableICache (for Cortex-M7).
 131        - Added functions: NVIC_GetEnableIRQ, SCB_GetFPUType
 132       CMSIS-RTOS:
 133         - bug fix in RTX 4.82 (see revision history for details)
 134       CMSIS-RTOS2:
 135         - new API including compatibility layer to CMSIS-RTOS
 136         - reference implementation based on RTX5
 137         - supports all Cortex-M variants including TrustZone for ARMv8-M
 138       CMSIS-SVD:
 139        - reworked SVD format documentation
 140        - removed SVD file database documentation as SVD files are distributed in packs
 141        - updated SVDConv for Win32 and Linux
 142       CMSIS-DSP:
 143        - Moved DSP libraries from CMSIS/DSP/Lib to CMSIS/Lib.
 144        - Added DSP libraries build projects to CMSIS pack.
 145     </release>
 146     <release version="4.5.0" date="2015-10-28">
 147       - CMSIS-Core     4.30.0  (see revision history for details)
 148       - CMSIS-DAP      1.1.0   (unchanged)
 149       - CMSIS-Driver   2.04.0  (see revision history for details)
 150       - CMSIS-DSP      1.4.7   (no source code change [still labeled 1.4.5], see revision history for details)
 151       - CMSIS-PACK     1.4.1   (see revision history for details)
 152       - CMSIS-RTOS     4.80.0  Restored time delay parameter 'millisec' old behavior (prior V4.79) for software compatibility. (see revision history for details)
 153       - CMSIS-SVD      1.3.1   (see revision history for details)
 154     </release>
 155     <release version="4.4.0" date="2015-09-11">
 156       - CMSIS-Core     4.20   (see revision history for details)
 157       - CMSIS-DSP      1.4.6  (no source code change [still labeled 1.4.5], see revision history for details)
 158       - CMSIS-PACK     1.4.0  (adding memory attributes, algorithm style)
 159       - CMSIS-Driver   2.03.0 (adding CAN [Controller Area Network] API)
 160       - CMSIS-RTOS
 161         -- API         1.02   (unchanged)
 162         -- RTX         4.79   (see revision history for details)
 163       - CMSIS-SVD      1.3.0  (see revision history for details)
 164       - CMSIS-DAP      1.1.0  (extended with SWO support)
 165     </release>
 166     <release version="4.3.0" date="2015-03-20">
 167       - CMSIS-Core     4.10   (Cortex-M7 extended Cache Maintenance functions)
 168       - CMSIS-DSP      1.4.5  (see revision history for details)
 169       - CMSIS-Driver   2.02   (adding SAI (Serial Audio Interface) API)
 170       - CMSIS-PACK     1.3.3  (Semantic Versioning, Generator extensions)
 171       - CMSIS-RTOS
 172         -- API         1.02   (unchanged)
 173         -- RTX         4.78   (see revision history for details)
 174       - CMSIS-SVD      1.2    (unchanged)
 175     </release>
 176     <release version="4.2.0" date="2014-09-24">
 177       Adding Cortex-M7 support
 178       - CMSIS-Core     4.00  (Cortex-M7 support, corrected C++ include guards in core header files)
 179       - CMSIS-DSP      1.4.4 (Cortex-M7 support and corrected out of bound issues)
 180       - CMSIS-PACK     1.3.1 (Cortex-M7 updates, clarification, corrected batch files in Tutorial)
 181       - CMSIS-SVD      1.2   (Cortex-M7 extensions)
 182       - CMSIS-RTOS RTX 4.75  (see revision history for details)
 183     </release>
 184     <release version="4.1.1" date="2014-06-30">
 185       - fixed conditions preventing the inclusion of the DSP library in projects for Infineon XMC4000 series devices
 186     </release>
 187     <release version="4.1.0" date="2014-06-12">
 188       - CMSIS-Driver   2.02  (incompatible update)
 189       - CMSIS-Pack     1.3   (see revision history for details)
 190       - CMSIS-DSP      1.4.2 (unchanged)
 191       - CMSIS-Core     3.30  (unchanged)
 192       - CMSIS-RTOS RTX 4.74  (unchanged)
 193       - CMSIS-RTOS API 1.02  (unchanged)
 194       - CMSIS-SVD      1.10  (unchanged)
 195       PACK:
 196       - removed G++ specific files from PACK
 197       - added Component Startup variant "C Startup"
 198       - added Pack Checking Utility
 199       - updated conditions to reflect tool-chain dependency
 200       - added Taxonomy for Graphics
 201       - updated Taxonomy for unified drivers from "Drivers" to "CMSIS Drivers"
 202     </release>
 203     <release version="4.0.0">
 204       - CMSIS-Driver   2.00  Preliminary (incompatible update)
 205       - CMSIS-Pack     1.1   Preliminary
 206       - CMSIS-DSP      1.4.2 (see revision history for details)
 207       - CMSIS-Core     3.30  (see revision history for details)
 208       - CMSIS-RTOS RTX 4.74  (see revision history for details)
 209       - CMSIS-RTOS API 1.02  (unchanged)
 210       - CMSIS-SVD      1.10  (unchanged)
 211     </release>
 212     <release version="3.20.4">
 213       - CMSIS-RTOS 4.74 (see revision history for details)
 214       - PACK Extensions (Boards, Device Features, Flash Programming, Generators, Configuration Wizard). Schema version 1.1.
 215     </release>
 216     <release version="3.20.3">
 217       - CMSIS-Driver API Version 1.10 ARM prefix added (incompatible change)
 218       - CMSIS-RTOS 4.73 (see revision history for details)
 219     </release>
 220     <release version="3.20.2">
 221       - CMSIS-Pack documentation has been added
 222       - CMSIS-Drivers header and documentation have been added to PACK
 223       - CMSIS-CORE, CMSIS-DSP, CMSIS-RTOS API and CMSIS-SVD remain unchanged
 224     </release>
 225     <release version="3.20.1">
 226       - CMSIS-RTOS Keil RTX V4.72 has been added to PACK
 227       - CMSIS-CORE, CMSIS-DSP, CMSIS-RTOS API and CMSIS-SVD remain unchanged
 228     </release>
 229     <release version="3.20.0">
 230       The software portions that are deployed in the application program are now under a BSD license which allows usage
 231       of CMSIS components in any commercial or open source projects.  The Pack Description file Arm.CMSIS.pdsc describes the use cases
 232       The individual components have been update as listed below:
 233       - CMSIS-CORE adds functions for setting breakpoints, supports the latest GCC Compiler, and contains several corrections.
 234       - CMSIS-DSP library is optimized for more performance and contains several bug fixes.
 235       - CMSIS-RTOS API is extended with capabilities for short timeouts, Kernel initialization, and prepared for a C++ interface.
 236       - CMSIS-SVD is unchanged.
 237     </release>
 238   </releases>
 239
 240   <taxonomy>
 241     <description Cclass="Board Support">Generic Interfaces for Evaluation and Development Boards</description>
 242     <description Cclass="CMSIS" doc="CMSIS/Documentation/General/html/index.html">Cortex Microcontroller Software Interface Components</description>
 243     <description Cclass="Device" doc="CMSIS/Documentation/Core/html/index.html">Startup, System Setup</description>
 244     <description Cclass="CMSIS Driver" doc="CMSIS/Documentation/Driver/html/index.html">Unified Device Drivers compliant to CMSIS-Driver Specifications</description>
 245     <description Cclass="File System">File Drive Support and File System</description>
 246     <description Cclass="Graphics">Graphical User Interface</description>
 247     <description Cclass="Network">Network Stack using Internet Protocols</description>
 248     <description Cclass="USB">Universal Serial Bus Stack</description>
 249     <description Cclass="Compiler">Compiler Software Extensions</description>
 250     <description Cclass="RTOS">Real-time Operating System</description>
 251   </taxonomy>
 252
 253   <devices>
 254     <!-- ******************************  Cortex-M0  ****************************** -->
 255     <family Dfamily="ARM Cortex M0" Dvendor="ARM:82">
 256       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/index.html" title="Cortex-M0 Device Generic Users Guide"/>
 257       <description>
 258 The Cortex-M0 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 259 - simple, easy-to-use programmers model
 260 - highly efficient ultra-low power operation
 261 - excellent code density
 262 - deterministic, high-performance interrupt handling
 263 - upward compatibility with the rest of the Cortex-M processor family.
 264       </description>
 265       <!-- debug svd="Device/ARM/SVD/ARMCM0.svd"/ SVD files do not contain any peripheral -->
 266       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 267       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 268       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 269
 270       <device Dname="ARMCM0">
 271         <processor Dcore="Cortex-M0" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
 272         <compile header="Device/ARM/ARMCM0/Include/ARMCM0.h" define="ARMCM0"/>
 273       </device>
 274     </family>
 275
 276     <!-- ******************************  Cortex-M0P  ****************************** -->
 277     <family Dfamily="ARM Cortex M0 plus" Dvendor="ARM:82">
 278       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0662b/index.html" title="Cortex-M0+ Device Generic Users Guide"/>
 279       <description>
 280 The Cortex-M0+ processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 281 - simple, easy-to-use programmers model
 282 - highly efficient ultra-low power operation
 283 - excellent code density
 284 - deterministic, high-performance interrupt handling
 285 - upward compatibility with the rest of the Cortex-M processor family.
 286       </description>
 287       <!-- debug svd="Device/ARM/SVD/ARMCM0P.svd"/ SVD files do not contain any peripheral -->
 288       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 289       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 290       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 291
 292       <device Dname="ARMCM0P">
 293         <processor Dcore="Cortex-M0+" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
 294         <compile header="Device/ARM/ARMCM0plus/Include/ARMCM0plus.h" define="ARMCM0P"/>
 295       </device>
 296
 297       <device Dname="ARMCM0P_MPU">
 298         <processor Dcore="Cortex-M0+" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 299         <compile header="Device/ARM/ARMCM0plus/Include/ARMCM0plus_MPU.h" define="ARMCM0P_MPU"/>
 300       </device>
 301     </family>
 302
 303     <!-- ******************************  Cortex-M3  ****************************** -->
 304     <family Dfamily="ARM Cortex M3" Dvendor="ARM:82">
 305       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/index.html" title="Cortex-M3 Device Generic Users Guide"/>
 306       <description>
 307 The Cortex-M3 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 308 - simple, easy-to-use programmers model
 309 - highly efficient ultra-low power operation
 310 - excellent code density
 311 - deterministic, high-performance interrupt handling
 312 - upward compatibility with the rest of the Cortex-M processor family.
 313       </description>
 314       <!-- debug svd="Device/ARM/SVD/ARMCM3.svd"/ SVD files do not contain any peripheral -->
 315       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 316       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 317       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 318
 319       <device Dname="ARMCM3">
 320         <processor Dcore="Cortex-M3" DcoreVersion="r2p1" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 321         <compile header="Device/ARM/ARMCM3/Include/ARMCM3.h" define="ARMCM3"/>
 322       </device>
 323     </family>
 324
 325     <!-- ******************************  Cortex-M4  ****************************** -->
 326     <family Dfamily="ARM Cortex M4" Dvendor="ARM:82">
 327       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/index.html" title="Cortex-M4 Device Generic Users Guide"/>
 328       <description>
 329 The Cortex-M4 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 330 - simple, easy-to-use programmers model
 331 - highly efficient ultra-low power operation
 332 - excellent code density
 333 - deterministic, high-performance interrupt handling
 334 - upward compatibility with the rest of the Cortex-M processor family.
 335       </description>
 336       <!-- debug svd="Device/ARM/SVD/ARMCM4.svd"/ SVD files do not contain any peripheral -->
 337       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 338       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 339       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 340
 341       <device Dname="ARMCM4">
 342         <processor Dcore="Cortex-M4" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 343         <compile header="Device/ARM/ARMCM4/Include/ARMCM4.h"    define="ARMCM4"/>
 344       </device>
 345
 346       <device Dname="ARMCM4_FP">
 347         <processor Dcore="Cortex-M4" DcoreVersion="r0p1" Dfpu="SP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 348         <compile header="Device/ARM/ARMCM4/Include/ARMCM4_FP.h" define="ARMCM4_FP"/>
 349       </device>
 350     </family>
 351
 352     <!-- ******************************  Cortex-M7  ****************************** -->
 353     <family Dfamily="ARM Cortex M7" Dvendor="ARM:82">
 354       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0646b/index.html" title="Cortex-M7 Device Generic Users Guide"/>
 355       <description>
 356 The Cortex-M7 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 357 - simple, easy-to-use programmers model
 358 - highly efficient ultra-low power operation
 359 - excellent code density
 360 - deterministic, high-performance interrupt handling
 361 - upward compatibility with the rest of the Cortex-M processor family.
 362       </description>
 363       <!-- debug svd="Device/ARM/SVD/ARMCM7.svd"/ SVD files do not contain any peripheral -->
 364       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 365       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 366       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 367
 368       <device Dname="ARMCM7">
 369         <processor Dcore="Cortex-M7" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 370         <compile header="Device/ARM/ARMCM7/Include/ARMCM7.h" define="ARMCM7"/>
 371       </device>
 372
 373       <device Dname="ARMCM7_SP">
 374         <processor Dcore="Cortex-M7" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 375         <compile header="Device/ARM/ARMCM7/Include/ARMCM7_SP.h" define="ARMCM7_SP"/>
 376       </device>
 377
 378       <device Dname="ARMCM7_DP">
 379         <processor Dcore="Cortex-M7" DcoreVersion="r0p0" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 380         <compile header="Device/ARM/ARMCM7/Include/ARMCM7_DP.h" define="ARMCM7_DP"/>
 381       </device>
 382     </family>
 383
 384     <!-- ******************************  Cortex-M23  ********************** -->
 385     <family Dfamily="ARM Cortex M23" Dvendor="ARM:82">
 386       <!--book name="Device/ARM/Documents/??_dgug.pdf"       title="?? Device Generic Users Guide"/-->
 387       <description>
 388 The Arm Cortex-M23 is based on the Armv8-M baseline architecture.
 389 It is the smallest and most energy efficient Arm processor with Arm TrustZone technology.
 390 Cortex-M23 is the ideal processor for constrained embedded applications requiring efficient security.
 391       </description>
 392       <!-- debug svd="Device/ARM/SVD/ARMCM23.svd"/ SVD files do not contain any peripheral -->
 393       <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
 394       <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
 395       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 396       <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
 397       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 398
 399       <device Dname="ARMCM23">
 400         <processor Dcore="Cortex-M23" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
 401         <compile header="Device/ARM/ARMCM23/Include/ARMCM23.h" define="ARMCM23"/>
 402       </device>
 403
 404       <device Dname="ARMCM23_TZ">
 405         <processor Dcore="Cortex-M23" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 406         <compile header="Device/ARM/ARMCM23/Include/ARMCM23_TZ.h" define="ARMCM23_TZ"/>
 407       </device>
 408     </family>
 409
 410     <!-- ******************************  Cortex-M33  ****************************** -->
 411     <family Dfamily="ARM Cortex M33" Dvendor="ARM:82">
 412       <!--book name="Device/ARM/Documents/??_dgug.pdf"       title="?? Device Generic Users Guide"/-->
 413       <description>
 414 The Arm Cortex-M33 is the most configurable of all Cortex-M processors. It is a full featured microcontroller
 415 class processor based on the Armv8-M mainline architecture with Arm TrustZone security.
 416       </description>
 417       <!-- debug svd="Device/ARM/SVD/ARMCM33.svd"/ SVD files do not contain any peripheral -->
 418       <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
 419       <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
 420       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 421       <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
 422       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"          default="1"/-->
 423
 424       <device Dname="ARMCM33">
 425         <processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
 426         <description>
 427           no DSP Instructions, no Floating Point Unit, no TrustZone
 428         </description>
 429         <compile header="Device/ARM/ARMCM33/Include/ARMCM33.h" define="ARMCM33"/>
 430       </device>
 431
 432       <device Dname="ARMCM33_TZ">
 433         <processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 434         <description>
 435           no DSP Instructions, no Floating Point Unit, TrustZone
 436         </description>
 437         <compile header="Device/ARM/ARMCM33/Include/ARMCM33_TZ.h" define="ARMCM33_TZ"/>
 438       </device>
 439
 440       <device Dname="ARMCM33_DSP_FP">
 441         <processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
 442         <description>
 443           DSP Instructions, Single Precision Floating Point Unit, no TrustZone
 444         </description>
 445         <compile header="Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP.h" define="ARMCM33_DSP_FP"/>
 446       </device>
 447
 448       <device Dname="ARMCM33_DSP_FP_TZ">
 449         <processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 450         <description>
 451           DSP Instructions, Single Precision Floating Point Unit, TrustZone
 452         </description>
 453         <compile header="Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h" define="ARMCM33_DSP_FP_TZ"/>
 454       </device>
 455     </family>
 456
 457     <!-- ******************************  ARMSC000  ****************************** -->
 458     <family Dfamily="ARM SC000" Dvendor="ARM:82">
 459       <description>
 460 The Arm SC000 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including:
 461 - simple, easy-to-use programmers model
 462 - highly efficient ultra-low power operation
 463 - excellent code density
 464 - deterministic, high-performance interrupt handling
 465       </description>
 466       <!-- debug svd="Device/ARM/SVD/ARMSC000.svd"/ SVD files do not contain any peripheral -->
 467       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 468       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 469       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 470
 471       <device Dname="ARMSC000">
 472         <processor Dcore="SC000" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
 473         <compile header="Device/ARM/ARMSC000/Include/ARMSC000.h" define="ARMSC000"/>
 474       </device>
 475     </family>
 476
 477     <!-- ******************************  ARMSC300  ****************************** -->
 478     <family Dfamily="ARM SC300" Dvendor="ARM:82">
 479       <description>
 480 The ARM SC300 processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including:
 481 - simple, easy-to-use programmers model
 482 - highly efficient ultra-low power operation
 483 - excellent code density
 484 - deterministic, high-performance interrupt handling
 485       </description>
 486       <!-- debug svd="Device/ARM/SVD/ARMSC300.svd"/ SVD files do not contain any peripheral -->
 487       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 488       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 489       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 490
 491       <device Dname="ARMSC300">
 492         <processor Dcore="SC300" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
 493         <compile header="Device/ARM/ARMSC300/Include/ARMSC300.h" define="ARMSC300"/>
 494       </device>
 495     </family>
 496
 497     <!-- ******************************  ARMv8-M Baseline  ********************** -->
 498     <family Dfamily="ARMv8-M Baseline" Dvendor="ARM:82">
 499       <!--book name="Device/ARM/Documents/ARMv8MBL_dgug.pdf"       title="ARMv8MBL Device Generic Users Guide"/-->
 500       <description>
 501 Armv8-M Baseline based device with TrustZone
 502       </description>
 503       <!-- debug svd="Device/ARM/SVD/ARMv8MBL.svd"/ SVD files do not contain any peripheral -->
 504       <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
 505       <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
 506       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 507       <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
 508       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 509
 510       <device Dname="ARMv8MBL">
 511         <processor Dcore="ARMV8MBL" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 512         <compile header="Device/ARM/ARMv8MBL/Include/ARMv8MBL.h" define="ARMv8MBL"/>
 513       </device>
 514     </family>
 515
 516     <!-- ******************************  ARMv8-M Mainline  ****************************** -->
 517     <family Dfamily="ARMv8-M Mainline" Dvendor="ARM:82">
 518       <!--book name="Device/ARM/Documents/ARMv8MML_dgug.pdf"       title="ARMv8MML Device Generic Users Guide"/-->
 519       <description>
 520 Armv8-M Mainline based device with TrustZone
 521       </description>
 522       <!-- debug svd="Device/ARM/SVD/ARMv8MML.svd"/ SVD files do not contain any peripheral -->
 523       <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
 524       <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
 525       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 526       <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
 527       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 528
 529       <device Dname="ARMv8MML">
 530         <processor Dcore="ARMV8MML" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 531         <description>
 532           no DSP Instructions, no Floating Point Unit, TrustZone
 533         </description>
 534         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML.h" define="ARMv8MML"/>
 535       </device>
 536
 537       <device Dname="ARMv8MML_DSP">
 538         <processor Dcore="ARMV8MML" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 539         <description>
 540           DSP Instructions, no Floating Point Unit, TrustZone
 541         </description>
 542         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DSP.h" define="ARMv8MML_DSP"/>
 543       </device>
 544
 545       <device Dname="ARMv8MML_SP">
 546         <processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 547         <description>
 548           no DSP Instructions, Single Precision Floating Point Unit, TrustZone
 549         </description>
 550         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_SP.h" define="ARMv8MML_SP"/>
 551       </device>
 552
 553       <device Dname="ARMv8MML_DSP_SP">
 554         <processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 555         <description>
 556           DSP Instructions, Single Precision Floating Point Unit, TrustZone
 557         </description>
 558         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_SP.h" define="ARMv8MML_DSP_SP"/>
 559       </device>
 560
 561       <device Dname="ARMv8MML_DP">
 562         <processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="DP_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 563         <description>
 564           no DSP Instructions, Double Precision Floating Point Unit, TrustZone
 565         </description>
 566         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DP.h" define="ARMv8MML_DP"/>
 567       </device>
 568
 569       <device Dname="ARMv8MML_DSP_DP">
 570         <processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="DP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 571         <description>
 572           DSP Instructions, Double Precision Floating Point Unit, TrustZone
 573         </description>
 574         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h" define="ARMv8MML_DSP_DP"/>
 575       </device>
 576     </family>
 577
 578     <!-- ******************************  Cortex-A5  ****************************** -->
 579     <family Dfamily="ARM Cortex A5" Dvendor="ARM:82">
 580       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0433c/index.html" title="Cortex-A5 Technical Reference Manual"/>
 581       <description>
 582 The Arm Cortex-A5 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full
 583 virtual memory capabilities. The Cortex-A5 processor implements the Armv7-A architecture profile and can execute 32-bit
 584 Arm instructions and 16-bit and 32-bit Thumb instructions. The Cortex-A5 is the smallest member of the Cortex-A processor family.
 585       </description>
 586
 587       <memory id="IROM1"                                start="0x80000000" size="0x00200000" startup="1" default="1"/>
 588       <memory id="IRAM1"                                start="0x80200000" size="0x00200000" init   ="0" default="1"/>
 589
 590       <device Dname="ARMCA5">
 591         <processor Dcore="Cortex-A5" DcoreVersion="r0p1" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable"/>
 592         <compile header="Device/ARM/ARMCA5/Include/ARMCA5.h" define="ARMCA5"/>
 593       </device>
 594     </family>
 595
 596     <!-- ******************************  Cortex-A7  ****************************** -->
 597     <family Dfamily="ARM Cortex A7" Dvendor="ARM:82">
 598       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/index.html" title="Cortex-A7 MPCore Technical Reference Manual"/>
 599       <description>
 600 The Cortex-A7 MPCore processor is a high-performance, low-power processor that implements the Armv7-A architecture.
 601 The Cortex-A7 MPCore processor has one to four processors in a single multiprocessor device with a L1 cache subsystem,
 602 an optional integrated GIC, and an optional L2 cache controller.
 603       </description>
 604
 605       <memory id="IROM1"                                start="0x80000000" size="0x00200000" startup="1" default="1"/>
 606       <memory id="IRAM1"                                start="0x80200000" size="0x00200000" init   ="0" default="1"/>
 607
 608       <device Dname="ARMCA7">
 609         <processor Dcore="Cortex-A7" DcoreVersion="r0p5" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable"/>
 610         <compile header="Device/ARM/ARMCA7/Include/ARMCA7.h" define="ARMCA7"/>
 611       </device>
 612     </family>
 613
 614     <!-- ******************************  Cortex-A9  ****************************** -->
 615     <family Dfamily="ARM Cortex A9" Dvendor="ARM:82">
 616       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.100511_0401_10_en/index.html" title="Cortex-A9 Technical Reference Manual"/>
 617       <description>
 618 The Cortex-A9 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full virtual memory capabilities.
 619 The Cortex-A9 processor implements the Armv7-A architecture and runs 32-bit Arm instructions, 16-bit and 32-bit Thumb instructions,
 620 and 8-bit Java bytecodes in Jazelle state.
 621       </description>
 622
 623       <memory id="IROM1"                                start="0x80000000" size="0x00200000" startup="1" default="1"/>
 624       <memory id="IRAM1"                                start="0x80200000" size="0x00200000" init   ="0" default="1"/>
 625
 626       <device Dname="ARMCA9">
 627         <processor Dcore="Cortex-A9" DcoreVersion="r4p1" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable"/>
 628         <compile header="Device/ARM/ARMCA9/Include/ARMCA9.h" define="ARMCA9"/>
 629       </device>
 630     </family>
 631   </devices>
 632
 633
 634   <apis>
 635     <!-- CMSIS Device API -->
 636     <api Cclass="Device" Cgroup="IRQ Controller" Capiversion="1.0.0" exclusive="1">
 637       <description>Device interrupt controller interface</description>
 638       <files>
 639         <file category="header" name="CMSIS/Core_A/Include/irq_ctrl.h"/>
 640       </files>
 641     </api>
 642     <api Cclass="Device" Cgroup="OS Tick" Capiversion="1.0.1" exclusive="1">
 643       <description>RTOS Kernel system tick timer interface</description>
 644       <files>
 645         <file category="header" name="CMSIS/RTOS2/Include/os_tick.h"/>
 646       </files>
 647     </api>
 648     <!-- CMSIS-RTOS API -->
 649     <api Cclass="CMSIS" Cgroup="RTOS" Capiversion="1.0.0" exclusive="1">
 650       <description>CMSIS-RTOS API for Cortex-M, SC000, and SC300</description>
 651       <files>
 652         <file category="doc" name="CMSIS/Documentation/RTOS/html/index.html"/>
 653       </files>
 654     </api>
 655     <api Cclass="CMSIS" Cgroup="RTOS2" Capiversion="2.1.3" exclusive="1">
 656       <description>CMSIS-RTOS API for Cortex-M, SC000, and SC300</description>
 657       <files>
 658         <file category="doc" name="CMSIS/Documentation/RTOS2/html/index.html"/>
 659         <file category="header" name="CMSIS/RTOS2/Include/cmsis_os2.h"/>
 660       </files>
 661     </api>
 662     <!-- CMSIS Driver API -->
 663     <api Cclass="CMSIS Driver" Cgroup="USART" Capiversion="2.3.0" exclusive="0">
 664       <description>USART Driver API for Cortex-M</description>
 665       <files>
 666         <file category="doc" name="CMSIS/Documentation/Driver/html/group__usart__interface__gr.html" />
 667         <file category="header" name="CMSIS/Driver/Include/Driver_USART.h" />
 668       </files>
 669     </api>
 670     <api Cclass="CMSIS Driver" Cgroup="SPI" Capiversion="2.2.0" exclusive="0">
 671       <description>SPI Driver API for Cortex-M</description>
 672       <files>
 673         <file category="doc" name="CMSIS/Documentation/Driver/html/group__spi__interface__gr.html" />
 674         <file category="header" name="CMSIS/Driver/Include/Driver_SPI.h" />
 675       </files>
 676     </api>
 677     <api Cclass="CMSIS Driver" Cgroup="SAI" Capiversion="1.1.0" exclusive="0">
 678       <description>SAI Driver API for Cortex-M</description>
 679       <files>
 680         <file category="doc" name="CMSIS/Documentation/Driver/html/group__sai__interface__gr.html"/>
 681         <file category="header" name="CMSIS/Driver/Include/Driver_SAI.h" />
 682       </files>
 683     </api>
 684     <api Cclass="CMSIS Driver" Cgroup="I2C" Capiversion="2.3.0" exclusive="0">
 685       <description>I2C Driver API for Cortex-M</description>
 686       <files>
 687         <file category="doc" name="CMSIS/Documentation/Driver/html/group__i2c__interface__gr.html"/>
 688         <file category="header" name="CMSIS/Driver/Include/Driver_I2C.h" />
 689       </files>
 690     </api>
 691     <api Cclass="CMSIS Driver" Cgroup="CAN" Capiversion="1.2.0" exclusive="0">
 692       <description>CAN Driver API for Cortex-M</description>
 693       <files>
 694         <file category="doc" name="CMSIS/Documentation/Driver/html/group__can__interface__gr.html"/>
 695         <file category="header" name="CMSIS/Driver/Include/Driver_CAN.h" />
 696       </files>
 697     </api>
 698     <api Cclass="CMSIS Driver" Cgroup="Flash" Capiversion="2.2.0" exclusive="0">
 699       <description>Flash Driver API for Cortex-M</description>
 700       <files>
 701         <file category="doc" name="CMSIS/Documentation/Driver/html/group__flash__interface__gr.html" />
 702         <file category="header" name="CMSIS/Driver/Include/Driver_Flash.h" />
 703       </files>
 704     </api>
 705     <api Cclass="CMSIS Driver" Cgroup="MCI" Capiversion="2.3.0" exclusive="0">
 706       <description>MCI Driver API for Cortex-M</description>
 707       <files>
 708         <file category="doc" name="CMSIS/Documentation/Driver/html/group__mci__interface__gr.html" />
 709         <file category="header" name="CMSIS/Driver/Include/Driver_MCI.h" />
 710       </files>
 711     </api>
 712     <api Cclass="CMSIS Driver" Cgroup="NAND" Capiversion="2.3.0" exclusive="0">
 713       <description>NAND Flash Driver API for Cortex-M</description>
 714       <files>
 715         <file category="doc" name="CMSIS/Documentation/Driver/html/group__nand__interface__gr.html" />
 716         <file category="header" name="CMSIS/Driver/Include/Driver_NAND.h" />
 717       </files>
 718     </api>
 719     <api Cclass="CMSIS Driver" Cgroup="Ethernet" Capiversion="2.1.0" exclusive="0">
 720       <description>Ethernet MAC and PHY Driver API for Cortex-M</description>
 721       <files>
 722         <file category="doc" name="CMSIS/Documentation/Driver/html/group__eth__interface__gr.html" />
 723         <file category="header" name="CMSIS/Driver/Include/Driver_ETH_MAC.h" />
 724         <file category="header" name="CMSIS/Driver/Include/Driver_ETH_PHY.h" />
 725       </files>
 726     </api>
 727     <api Cclass="CMSIS Driver" Cgroup="Ethernet MAC" Capiversion="2.1.0" exclusive="0">
 728       <description>Ethernet MAC Driver API for Cortex-M</description>
 729       <files>
 730         <file category="doc" name="CMSIS/Documentation/Driver/html/group__eth__mac__interface__gr.html" />
 731         <file category="header" name="CMSIS/Driver/Include/Driver_ETH_MAC.h" />
 732       </files>
 733     </api>
 734     <api Cclass="CMSIS Driver" Cgroup="Ethernet PHY" Capiversion="2.1.0" exclusive="0">
 735       <description>Ethernet PHY Driver API for Cortex-M</description>
 736       <files>
 737         <file category="doc" name="CMSIS/Documentation/Driver/html/group__eth__phy__interface__gr.html" />
 738         <file category="header" name="CMSIS/Driver/Include/Driver_ETH_PHY.h" />
 739       </files>
 740     </api>
 741     <api Cclass="CMSIS Driver" Cgroup="USB Device" Capiversion="2.2.0" exclusive="0">
 742       <description>USB Device Driver API for Cortex-M</description>
 743       <files>
 744         <file category="doc" name="CMSIS/Documentation/Driver/html/group__usbd__interface__gr.html" />
 745         <file category="header" name="CMSIS/Driver/Include/Driver_USBD.h" />
 746       </files>
 747     </api>
 748     <api Cclass="CMSIS Driver" Cgroup="USB Host" Capiversion="2.2.0" exclusive="0">
 749       <description>USB Host Driver API for Cortex-M</description>
 750       <files>
 751         <file category="doc" name="CMSIS/Documentation/Driver/html/group__usbh__interface__gr.html" />
 752         <file category="header" name="CMSIS/Driver/Include/Driver_USBH.h" />
 753       </files>
 754     </api>
 755   </apis>
 756
 757   <!-- conditions are dependency rules that can apply to a component or an individual file -->
 758   <conditions>
 759     <!-- compiler -->
 760     <condition id="ARMCC6">
 761       <accept Tcompiler="ARMCC" Toptions="AC6"/>
 762       <accept Tcompiler="ARMCC" Toptions="AC6LTO"/>
 763     </condition>
 764     <condition id="ARMCC5">
 765       <require Tcompiler="ARMCC" Toptions="AC5"/>
 766     </condition>
 767     <condition id="ARMCC">
 768       <require Tcompiler="ARMCC"/>
 769     </condition>
 770     <condition id="GCC">
 771       <require Tcompiler="GCC"/>
 772     </condition>
 773     <condition id="IAR">
 774       <require Tcompiler="IAR"/>
 775     </condition>
 776     <condition id="ARMCC GCC">
 777       <accept Tcompiler="ARMCC"/>
 778       <accept Tcompiler="GCC"/>
 779     </condition>
 780     <condition id="ARMCC GCC IAR">
 781       <accept Tcompiler="ARMCC"/>
 782       <accept Tcompiler="GCC"/>
 783       <accept Tcompiler="IAR"/>
 784     </condition>
 785
 786     <!-- Arm architecture -->
 787     <condition id="ARMv6-M Device">
 788       <description>Armv6-M architecture based device</description>
 789       <accept Dcore="Cortex-M0"/>
 790       <accept Dcore="Cortex-M0+"/>
 791       <accept Dcore="SC000"/>
 792     </condition>
 793     <condition id="ARMv7-M Device">
 794       <description>Armv7-M architecture based device</description>
 795       <accept Dcore="Cortex-M3"/>
 796       <accept Dcore="Cortex-M4"/>
 797       <accept Dcore="Cortex-M7"/>
 798       <accept Dcore="SC300"/>
 799     </condition>
 800     <condition id="ARMv8-M Device">
 801       <description>Armv8-M architecture based device</description>
 802       <accept Dcore="ARMV8MBL"/>
 803       <accept Dcore="ARMV8MML"/>
 804       <accept Dcore="Cortex-M23"/>
 805       <accept Dcore="Cortex-M33"/>
 806     </condition>
 807     <condition id="ARMv8-M TZ Device">
 808       <description>Armv8-M architecture based device with TrustZone</description>
 809       <require condition="ARMv8-M Device"/>
 810       <require Dtz="TZ"/>
 811     </condition>
 812     <condition id="ARMv6_7-M Device">
 813       <description>Armv6_7-M architecture based device</description>
 814       <accept condition="ARMv6-M Device"/>
 815       <accept condition="ARMv7-M Device"/>
 816     </condition>
 817     <condition id="ARMv6_7_8-M Device">
 818       <description>Armv6_7_8-M architecture based device</description>
 819       <accept condition="ARMv6-M Device"/>
 820       <accept condition="ARMv7-M Device"/>
 821       <accept condition="ARMv8-M Device"/>
 822     </condition>
 823     <condition id="ARMv7-A Device">
 824       <description>Armv7-A architecture based device</description>
 825       <accept Dcore="Cortex-A5"/>
 826       <accept Dcore="Cortex-A7"/>
 827       <accept Dcore="Cortex-A9"/>
 828     </condition>
 829
 830     <!-- ARM core -->
 831     <condition id="CM0">
 832       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device</description>
 833       <accept Dcore="Cortex-M0"/>
 834       <accept Dcore="Cortex-M0+"/>
 835       <accept Dcore="SC000"/>
 836     </condition>
 837     <condition id="CM3">
 838       <description>Cortex-M3 or SC300 processor based device</description>
 839       <accept Dcore="Cortex-M3"/>
 840       <accept Dcore="SC300"/>
 841     </condition>
 842     <condition id="CM4">
 843       <description>Cortex-M4 processor based device</description>
 844       <require Dcore="Cortex-M4" Dfpu="NO_FPU"/>
 845     </condition>
 846     <condition id="CM4_FP">
 847       <description>Cortex-M4 processor based device using Floating Point Unit</description>
 848       <accept Dcore="Cortex-M4" Dfpu="FPU"/>
 849       <accept Dcore="Cortex-M4" Dfpu="SP_FPU"/>
 850       <accept Dcore="Cortex-M4" Dfpu="DP_FPU"/>
 851     </condition>
 852     <condition id="CM7">
 853       <description>Cortex-M7 processor based device</description>
 854       <require Dcore="Cortex-M7" Dfpu="NO_FPU"/>
 855     </condition>
 856     <condition id="CM7_FP">
 857       <description>Cortex-M7 processor based device using Floating Point Unit</description>
 858       <accept Dcore="Cortex-M7" Dfpu="SP_FPU"/>
 859       <accept Dcore="Cortex-M7" Dfpu="DP_FPU"/>
 860     </condition>
 861     <condition id="CM7_SP">
 862       <description>Cortex-M7 processor based device using Floating Point Unit (SP)</description>
 863       <require Dcore="Cortex-M7" Dfpu="SP_FPU"/>
 864     </condition>
 865     <condition id="CM7_DP">
 866       <description>Cortex-M7 processor based device using Floating Point Unit (DP)</description>
 867       <require Dcore="Cortex-M7" Dfpu="DP_FPU"/>
 868     </condition>
 869     <condition id="CM23">
 870       <description>Cortex-M23 processor based device</description>
 871       <require Dcore="Cortex-M23"/>
 872     </condition>
 873     <condition id="CM33">
 874       <description>Cortex-M33 processor based device</description>
 875       <require Dcore="Cortex-M33" Dfpu="NO_FPU"/>
 876     </condition>
 877     <condition id="CM33_FP">
 878       <description>Cortex-M33 processor based device using Floating Point Unit</description>
 879       <require Dcore="Cortex-M33" Dfpu="SP_FPU"/>
 880     </condition>
 881     <condition id="ARMv8MBL">
 882       <description>Armv8-M Baseline processor based device</description>
 883       <require Dcore="ARMV8MBL"/>
 884     </condition>
 885     <condition id="ARMv8MML">
 886       <description>Armv8-M Mainline processor based device</description>
 887       <require Dcore="ARMV8MML" Dfpu="NO_FPU"/>
 888     </condition>
 889     <condition id="ARMv8MML_FP">
 890       <description>Armv8-M Mainline processor based device using Floating Point Unit</description>
 891       <accept Dcore="ARMV8MML" Dfpu="SP_FPU"/>
 892       <accept Dcore="ARMV8MML" Dfpu="DP_FPU"/>
 893     </condition>
 894
 895     <condition id="CM33_NODSP_NOFPU">
 896       <description>CM33, no DSP, no FPU</description>
 897       <require Dcore="Cortex-M33" Ddsp="NO_DSP" Dfpu="NO_FPU"/>
 898     </condition>
 899     <condition id="CM33_DSP_NOFPU">
 900       <description>CM33, DSP, no FPU</description>
 901       <require Dcore="Cortex-M33" Ddsp="DSP" Dfpu="NO_FPU"/>
 902     </condition>
 903     <condition id="CM33_NODSP_SP">
 904       <description>CM33, no DSP, SP FPU</description>
 905       <require Dcore="Cortex-M33" Ddsp="NO_DSP" Dfpu="SP_FPU"/>
 906     </condition>
 907     <condition id="CM33_DSP_SP">
 908       <description>CM33, DSP, SP FPU</description>
 909       <require Dcore="Cortex-M33" Ddsp="DSP" Dfpu="SP_FPU"/>
 910     </condition>
 911
 912     <condition id="ARMv8MML_NODSP_NOFPU">
 913       <description>Armv8-M Mainline, no DSP, no FPU</description>
 914       <require Dcore="ARMV8MML" Ddsp="NO_DSP" Dfpu="NO_FPU"/>
 915     </condition>
 916     <condition id="ARMv8MML_DSP_NOFPU">
 917       <description>Armv8-M Mainline, DSP, no FPU</description>
 918       <require Dcore="ARMV8MML" Ddsp="DSP" Dfpu="NO_FPU"/>
 919     </condition>
 920     <condition id="ARMv8MML_NODSP_SP">
 921       <description>Armv8-M Mainline, no DSP, SP FPU</description>
 922       <require Dcore="ARMV8MML" Ddsp="NO_DSP" Dfpu="SP_FPU"/>
 923     </condition>
 924     <condition id="ARMv8MML_DSP_SP">
 925       <description>Armv8-M Mainline, DSP, SP FPU</description>
 926       <require Dcore="ARMV8MML" Ddsp="DSP" Dfpu="SP_FPU"/>
 927     </condition>
 928
 929     <condition id="CA5_CA9">
 930       <description>Cortex-A5 or Cortex-A9 processor based device</description>
 931       <accept Dcore="Cortex-A5"/>
 932       <accept Dcore="Cortex-A9"/>
 933     </condition>
 934
 935     <condition id="CA7">
 936       <description>Cortex-A7 processor based device</description>
 937       <accept Dcore="Cortex-A7"/>
 938     </condition>
 939
 940     <!-- ARMCC compiler -->
 941     <condition id="CA_ARMCC5">
 942       <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the Arm Compiler 5</description>
 943       <require condition="ARMv7-A Device"/>
 944       <require condition="ARMCC5"/>
 945     </condition>
 946     <condition id="CA_ARMCC6">
 947       <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the Arm Compiler 6</description>
 948       <require condition="ARMv7-A Device"/>
 949       <require condition="ARMCC6"/>
 950     </condition>
 951
 952     <condition id="CM0_ARMCC">
 953       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device for the Arm Compiler</description>
 954       <require condition="CM0"/>
 955       <require Tcompiler="ARMCC"/>
 956     </condition>
 957     <condition id="CM0_LE_ARMCC">
 958       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the Arm Compiler</description>
 959       <require condition="CM0_ARMCC"/>
 960       <require Dendian="Little-endian"/>
 961     </condition>
 962     <condition id="CM0_BE_ARMCC">
 963       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the Arm Compiler</description>
 964       <require condition="CM0_ARMCC"/>
 965       <require Dendian="Big-endian"/>
 966     </condition>
 967
 968     <condition id="CM3_ARMCC">
 969       <description>Cortex-M3 or SC300 processor based device for the Arm Compiler</description>
 970       <require condition="CM3"/>
 971       <require Tcompiler="ARMCC"/>
 972     </condition>
 973     <condition id="CM3_LE_ARMCC">
 974       <description>Cortex-M3 or SC300 processor based device in little endian mode for the Arm Compiler</description>
 975       <require condition="CM3_ARMCC"/>
 976       <require Dendian="Little-endian"/>
 977     </condition>
 978     <condition id="CM3_BE_ARMCC">
 979       <description>Cortex-M3 or SC300 processor based device in big endian mode for the Arm Compiler</description>
 980       <require condition="CM3_ARMCC"/>
 981       <require Dendian="Big-endian"/>
 982     </condition>
 983
 984     <condition id="CM4_ARMCC">
 985       <description>Cortex-M4 processor based device for the Arm Compiler</description>
 986       <require condition="CM4"/>
 987       <require Tcompiler="ARMCC"/>
 988     </condition>
 989     <condition id="CM4_LE_ARMCC">
 990       <description>Cortex-M4 processor based device in little endian mode for the Arm Compiler</description>
 991       <require condition="CM4_ARMCC"/>
 992       <require Dendian="Little-endian"/>
 993     </condition>
 994     <condition id="CM4_BE_ARMCC">
 995       <description>Cortex-M4 processor based device in big endian mode for the Arm Compiler</description>
 996       <require condition="CM4_ARMCC"/>
 997       <require Dendian="Big-endian"/>
 998     </condition>
 999
1000     <condition id="CM4_FP_ARMCC">
1001       <description>Cortex-M4 processor based device using Floating Point Unit for the Arm Compiler</description>
1002       <require condition="CM4_FP"/>
1003       <require Tcompiler="ARMCC"/>
1004     </condition>
1005     <condition id="CM4_FP_LE_ARMCC">
1006       <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
1007       <require condition="CM4_FP_ARMCC"/>
1008       <require Dendian="Little-endian"/>
1009     </condition>
1010     <condition id="CM4_FP_BE_ARMCC">
1011       <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
1012       <require condition="CM4_FP_ARMCC"/>
1013       <require Dendian="Big-endian"/>
1014     </condition>
1015
1016     <condition id="CM7_ARMCC">
1017       <description>Cortex-M7 processor based device for the Arm Compiler</description>
1018       <require condition="CM7"/>
1019       <require Tcompiler="ARMCC"/>
1020     </condition>
1021     <condition id="CM7_LE_ARMCC">
1022       <description>Cortex-M7 processor based device in little endian mode for the Arm Compiler</description>
1023       <require condition="CM7_ARMCC"/>
1024       <require Dendian="Little-endian"/>
1025     </condition>
1026     <condition id="CM7_BE_ARMCC">
1027       <description>Cortex-M7 processor based device in big endian mode for the Arm Compiler</description>
1028       <require condition="CM7_ARMCC"/>
1029       <require Dendian="Big-endian"/>
1030     </condition>
1031
1032     <condition id="CM7_FP_ARMCC">
1033       <description>Cortex-M7 processor based device using Floating Point Unit for the Arm Compiler</description>
1034       <require condition="CM7_FP"/>
1035       <require Tcompiler="ARMCC"/>
1036     </condition>
1037     <condition id="CM7_FP_LE_ARMCC">
1038       <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
1039       <require condition="CM7_FP_ARMCC"/>
1040       <require Dendian="Little-endian"/>
1041     </condition>
1042     <condition id="CM7_FP_BE_ARMCC">
1043       <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
1044       <require condition="CM7_FP_ARMCC"/>
1045       <require Dendian="Big-endian"/>
1046     </condition>
1047
1048     <condition id="CM7_SP_ARMCC">
1049       <description>Cortex-M7 processor based device using Floating Point Unit (SP) for the Arm Compiler</description>
1050       <require condition="CM7_SP"/>
1051       <require Tcompiler="ARMCC"/>
1052     </condition>
1053     <condition id="CM7_SP_LE_ARMCC">
1054       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the Arm Compiler</description>
1055       <require condition="CM7_SP_ARMCC"/>
1056       <require Dendian="Little-endian"/>
1057     </condition>
1058     <condition id="CM7_SP_BE_ARMCC">
1059       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the Arm Compiler</description>
1060       <require condition="CM7_SP_ARMCC"/>
1061       <require Dendian="Big-endian"/>
1062     </condition>
1063
1064     <condition id="CM7_DP_ARMCC">
1065       <description>Cortex-M7 processor based device using Floating Point Unit (DP) for the Arm Compiler</description>
1066       <require condition="CM7_DP"/>
1067       <require Tcompiler="ARMCC"/>
1068     </condition>
1069     <condition id="CM7_DP_LE_ARMCC">
1070       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the Arm Compiler</description>
1071       <require condition="CM7_DP_ARMCC"/>
1072       <require Dendian="Little-endian"/>
1073     </condition>
1074     <condition id="CM7_DP_BE_ARMCC">
1075       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the Arm Compiler</description>
1076       <require condition="CM7_DP_ARMCC"/>
1077       <require Dendian="Big-endian"/>
1078     </condition>
1079
1080     <condition id="CM23_ARMCC">
1081       <description>Cortex-M23 processor based device for the Arm Compiler</description>
1082       <require condition="CM23"/>
1083       <require Tcompiler="ARMCC"/>
1084     </condition>
1085     <condition id="CM23_LE_ARMCC">
1086       <description>Cortex-M23 processor based device in little endian mode for the Arm Compiler</description>
1087       <require condition="CM23_ARMCC"/>
1088       <require Dendian="Little-endian"/>
1089     </condition>
1090     <condition id="CM23_BE_ARMCC">
1091       <description>Cortex-M23 processor based device in big endian mode for the Arm Compiler</description>
1092       <require condition="CM23_ARMCC"/>
1093       <require Dendian="Big-endian"/>
1094     </condition>
1095
1096     <condition id="CM33_ARMCC">
1097       <description>Cortex-M33 processor based device for the Arm Compiler</description>
1098       <require condition="CM33"/>
1099       <require Tcompiler="ARMCC"/>
1100     </condition>
1101     <condition id="CM33_LE_ARMCC">
1102       <description>Cortex-M33 processor based device in little endian mode for the Arm Compiler</description>
1103       <require condition="CM33_ARMCC"/>
1104       <require Dendian="Little-endian"/>
1105     </condition>
1106     <condition id="CM33_BE_ARMCC">
1107       <description>Cortex-M33 processor based device in big endian mode for the Arm Compiler</description>
1108       <require condition="CM33_ARMCC"/>
1109       <require Dendian="Big-endian"/>
1110     </condition>
1111
1112     <condition id="CM33_FP_ARMCC">
1113       <description>Cortex-M33 processor based device using Floating Point Unit for the Arm Compiler</description>
1114       <require condition="CM33_FP"/>
1115       <require Tcompiler="ARMCC"/>
1116     </condition>
1117     <condition id="CM33_FP_LE_ARMCC">
1118       <description>Cortex-M33 processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
1119       <require condition="CM33_FP_ARMCC"/>
1120       <require Dendian="Little-endian"/>
1121     </condition>
1122     <condition id="CM33_FP_BE_ARMCC">
1123       <description>Cortex-M33 processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
1124       <require condition="CM33_FP_ARMCC"/>
1125       <require Dendian="Big-endian"/>
1126     </condition>
1127
1128     <condition id="CM33_NODSP_NOFPU_ARMCC">
1129       <description>Cortex-M33 processor, no DSP, no FPU, Arm Compiler</description>
1130       <require condition="CM33_NODSP_NOFPU"/>
1131       <require Tcompiler="ARMCC"/>
1132     </condition>
1133     <condition id="CM33_DSP_NOFPU_ARMCC">
1134       <description>Cortex-M33 processor, DSP, no FPU, Arm Compiler</description>
1135       <require condition="CM33_DSP_NOFPU"/>
1136       <require Tcompiler="ARMCC"/>
1137     </condition>
1138     <condition id="CM33_NODSP_SP_ARMCC">
1139       <description>Cortex-M33 processor, no DSP, SP FPU, Arm Compiler</description>
1140       <require condition="CM33_NODSP_SP"/>
1141       <require Tcompiler="ARMCC"/>
1142     </condition>
1143     <condition id="CM33_DSP_SP_ARMCC">
1144       <description>Cortex-M33 processor, DSP, SP FPU, Arm Compiler</description>
1145       <require condition="CM33_DSP_SP"/>
1146       <require Tcompiler="ARMCC"/>
1147     </condition>
1148     <condition id="CM33_NODSP_NOFPU_LE_ARMCC">
1149       <description>Cortex-M33 processor, little endian, no DSP, no FPU, Arm Compiler</description>
1150       <require condition="CM33_NODSP_NOFPU_ARMCC"/>
1151       <require Dendian="Little-endian"/>
1152     </condition>
1153     <condition id="CM33_DSP_NOFPU_LE_ARMCC">
1154       <description>Cortex-M33 processor, little endian, DSP, no FPU, Arm Compiler</description>
1155       <require condition="CM33_DSP_NOFPU_ARMCC"/>
1156       <require Dendian="Little-endian"/>
1157     </condition>
1158     <condition id="CM33_NODSP_SP_LE_ARMCC">
1159       <description>Cortex-M33 processor, little endian, no DSP, SP FPU, Arm Compiler</description>
1160       <require condition="CM33_NODSP_SP_ARMCC"/>
1161       <require Dendian="Little-endian"/>
1162     </condition>
1163     <condition id="CM33_DSP_SP_LE_ARMCC">
1164       <description>Cortex-M33 processor, little endian, DSP, SP FPU, Arm Compiler</description>
1165       <require condition="CM33_DSP_SP_ARMCC"/>
1166       <require Dendian="Little-endian"/>
1167     </condition>
1168
1169     <condition id="ARMv8MBL_ARMCC">
1170       <description>Armv8-M Baseline processor based device for the Arm Compiler</description>
1171       <require condition="ARMv8MBL"/>
1172       <require Tcompiler="ARMCC"/>
1173     </condition>
1174     <condition id="ARMv8MBL_LE_ARMCC">
1175       <description>Armv8-M Baseline processor based device in little endian mode for the Arm Compiler</description>
1176       <require condition="ARMv8MBL_ARMCC"/>
1177       <require Dendian="Little-endian"/>
1178     </condition>
1179     <condition id="ARMv8MBL_BE_ARMCC">
1180       <description>Armv8-M Baseline processor based device in big endian mode for the Arm Compiler</description>
1181       <require condition="ARMv8MBL_ARMCC"/>
1182       <require Dendian="Big-endian"/>
1183     </condition>
1184
1185     <condition id="ARMv8MML_ARMCC">
1186       <description>Armv8-M Mainline processor based device for the Arm Compiler</description>
1187       <require condition="ARMv8MML"/>
1188       <require Tcompiler="ARMCC"/>
1189     </condition>
1190     <condition id="ARMv8MML_LE_ARMCC">
1191       <description>Armv8-M Mainline processor based device in little endian mode for the Arm Compiler</description>
1192       <require condition="ARMv8MML_ARMCC"/>
1193       <require Dendian="Little-endian"/>
1194     </condition>
1195     <condition id="ARMv8MML_BE_ARMCC">
1196       <description>Armv8-M Mainline processor based device in big endian mode for the Arm Compiler</description>
1197       <require condition="ARMv8MML_ARMCC"/>
1198       <require Dendian="Big-endian"/>
1199     </condition>
1200
1201     <condition id="ARMv8MML_FP_ARMCC">
1202       <description>Armv8-M Mainline processor based device using Floating Point Unit for the Arm Compiler</description>
1203       <require condition="ARMv8MML_FP"/>
1204       <require Tcompiler="ARMCC"/>
1205     </condition>
1206     <condition id="ARMv8MML_FP_LE_ARMCC">
1207       <description>Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
1208       <require condition="ARMv8MML_FP_ARMCC"/>
1209       <require Dendian="Little-endian"/>
1210     </condition>
1211     <condition id="ARMv8MML_FP_BE_ARMCC">
1212       <description>Armv8-M Mainline processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
1213       <require condition="ARMv8MML_FP_ARMCC"/>
1214       <require Dendian="Big-endian"/>
1215     </condition>
1216
1217     <condition id="ARMv8MML_NODSP_NOFPU_ARMCC">
1218       <description>Armv8-M Mainline, no DSP, no FPU, Arm Compiler</description>
1219       <require condition="ARMv8MML_NODSP_NOFPU"/>
1220       <require Tcompiler="ARMCC"/>
1221     </condition>
1222     <condition id="ARMv8MML_DSP_NOFPU_ARMCC">
1223       <description>Armv8-M Mainline, DSP, no FPU, Arm Compiler</description>
1224       <require condition="ARMv8MML_DSP_NOFPU"/>
1225       <require Tcompiler="ARMCC"/>
1226     </condition>
1227     <condition id="ARMv8MML_NODSP_SP_ARMCC">
1228       <description>Armv8-M Mainline, no DSP, SP FPU, Arm Compiler</description>
1229       <require condition="ARMv8MML_NODSP_SP"/>
1230       <require Tcompiler="ARMCC"/>
1231     </condition>
1232     <condition id="ARMv8MML_DSP_SP_ARMCC">
1233       <description>Armv8-M Mainline, DSP, SP FPU, Arm Compiler</description>
1234       <require condition="ARMv8MML_DSP_SP"/>
1235       <require Tcompiler="ARMCC"/>
1236     </condition>
1237     <condition id="ARMv8MML_NODSP_NOFPU_LE_ARMCC">
1238       <description>Armv8-M Mainline, little endian, no DSP, no FPU, Arm Compiler</description>
1239       <require condition="ARMv8MML_NODSP_NOFPU_ARMCC"/>
1240       <require Dendian="Little-endian"/>
1241     </condition>
1242     <condition id="ARMv8MML_DSP_NOFPU_LE_ARMCC">
1243       <description>Armv8-M Mainline, little endian, DSP, no FPU, Arm Compiler</description>
1244       <require condition="ARMv8MML_DSP_NOFPU_ARMCC"/>
1245       <require Dendian="Little-endian"/>
1246     </condition>
1247     <condition id="ARMv8MML_NODSP_SP_LE_ARMCC">
1248       <description>Armv8-M Mainline, little endian, no DSP, SP FPU, Arm Compiler</description>
1249       <require condition="ARMv8MML_NODSP_SP_ARMCC"/>
1250       <require Dendian="Little-endian"/>
1251     </condition>
1252     <condition id="ARMv8MML_DSP_SP_LE_ARMCC">
1253       <description>Armv8-M Mainline, little endian, DSP, SP FPU, Arm Compiler</description>
1254       <require condition="ARMv8MML_DSP_SP_ARMCC"/>
1255       <require Dendian="Little-endian"/>
1256     </condition>
1257
1258     <!-- GCC compiler -->
1259     <condition id="CA_GCC">
1260       <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the GCC Compiler</description>
1261       <require condition="ARMv7-A Device"/>
1262       <require Tcompiler="GCC"/>
1263     </condition>
1264
1265     <condition id="CM0_GCC">
1266       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device for the GCC Compiler</description>
1267       <require condition="CM0"/>
1268       <require Tcompiler="GCC"/>
1269     </condition>
1270     <condition id="CM0_LE_GCC">
1271       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the GCC Compiler</description>
1272       <require condition="CM0_GCC"/>
1273       <require Dendian="Little-endian"/>
1274     </condition>
1275     <condition id="CM0_BE_GCC">
1276       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the GCC Compiler</description>
1277       <require condition="CM0_GCC"/>
1278       <require Dendian="Big-endian"/>
1279     </condition>
1280
1281     <condition id="CM3_GCC">
1282       <description>Cortex-M3 or SC300 processor based device for the GCC Compiler</description>
1283       <require condition="CM3"/>
1284       <require Tcompiler="GCC"/>
1285     </condition>
1286     <condition id="CM3_LE_GCC">
1287       <description>Cortex-M3 or SC300 processor based device in little endian mode for the GCC Compiler</description>
1288       <require condition="CM3_GCC"/>
1289       <require Dendian="Little-endian"/>
1290     </condition>
1291     <condition id="CM3_BE_GCC">
1292       <description>Cortex-M3 or SC300 processor based device in big endian mode for the GCC Compiler</description>
1293       <require condition="CM3_GCC"/>
1294       <require Dendian="Big-endian"/>
1295     </condition>
1296
1297     <condition id="CM4_GCC">
1298       <description>Cortex-M4 processor based device for the GCC Compiler</description>
1299       <require condition="CM4"/>
1300       <require Tcompiler="GCC"/>
1301     </condition>
1302     <condition id="CM4_LE_GCC">
1303       <description>Cortex-M4 processor based device in little endian mode for the GCC Compiler</description>
1304       <require condition="CM4_GCC"/>
1305       <require Dendian="Little-endian"/>
1306     </condition>
1307     <condition id="CM4_BE_GCC">
1308       <description>Cortex-M4 processor based device in big endian mode for the GCC Compiler</description>
1309       <require condition="CM4_GCC"/>
1310       <require Dendian="Big-endian"/>
1311     </condition>
1312
1313     <condition id="CM4_FP_GCC">
1314       <description>Cortex-M4 processor based device using Floating Point Unit for the GCC Compiler</description>
1315       <require condition="CM4_FP"/>
1316       <require Tcompiler="GCC"/>
1317     </condition>
1318     <condition id="CM4_FP_LE_GCC">
1319       <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
1320       <require condition="CM4_FP_GCC"/>
1321       <require Dendian="Little-endian"/>
1322     </condition>
1323     <condition id="CM4_FP_BE_GCC">
1324       <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
1325       <require condition="CM4_FP_GCC"/>
1326       <require Dendian="Big-endian"/>
1327     </condition>
1328
1329     <condition id="CM7_GCC">
1330       <description>Cortex-M7 processor based device for the GCC Compiler</description>
1331       <require condition="CM7"/>
1332       <require Tcompiler="GCC"/>
1333     </condition>
1334     <condition id="CM7_LE_GCC">
1335       <description>Cortex-M7 processor based device in little endian mode for the GCC Compiler</description>
1336       <require condition="CM7_GCC"/>
1337       <require Dendian="Little-endian"/>
1338     </condition>
1339     <condition id="CM7_BE_GCC">
1340       <description>Cortex-M7 processor based device in big endian mode for the GCC Compiler</description>
1341       <require condition="CM7_GCC"/>
1342       <require Dendian="Big-endian"/>
1343     </condition>
1344
1345     <condition id="CM7_FP_GCC">
1346       <description>Cortex-M7 processor based device using Floating Point Unit for the GCC Compiler</description>
1347       <require condition="CM7_FP"/>
1348       <require Tcompiler="GCC"/>
1349     </condition>
1350     <condition id="CM7_FP_LE_GCC">
1351       <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
1352       <require condition="CM7_FP_GCC"/>
1353       <require Dendian="Little-endian"/>
1354     </condition>
1355     <condition id="CM7_FP_BE_GCC">
1356       <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
1357       <require condition="CM7_FP_GCC"/>
1358       <require Dendian="Big-endian"/>
1359     </condition>
1360
1361     <condition id="CM7_SP_GCC">
1362       <description>Cortex-M7 processor based device using Floating Point Unit (SP) for the GCC Compiler</description>
1363       <require condition="CM7_SP"/>
1364       <require Tcompiler="GCC"/>
1365     </condition>
1366     <condition id="CM7_SP_LE_GCC">
1367       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the GCC Compiler</description>
1368       <require condition="CM7_SP_GCC"/>
1369       <require Dendian="Little-endian"/>
1370     </condition>
1371     <condition id="CM7_SP_BE_GCC">
1372       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the GCC Compiler</description>
1373       <require condition="CM7_SP_GCC"/>
1374       <require Dendian="Big-endian"/>
1375     </condition>
1376
1377     <condition id="CM7_DP_GCC">
1378       <description>Cortex-M7 processor based device using Floating Point Unit (DP) for the GCC Compiler</description>
1379       <require condition="CM7_DP"/>
1380       <require Tcompiler="GCC"/>
1381     </condition>
1382     <condition id="CM7_DP_LE_GCC">
1383       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the GCC Compiler</description>
1384       <require condition="CM7_DP_GCC"/>
1385       <require Dendian="Little-endian"/>
1386     </condition>
1387     <condition id="CM7_DP_BE_GCC">
1388       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the GCC Compiler</description>
1389       <require condition="CM7_DP_GCC"/>
1390       <require Dendian="Big-endian"/>
1391     </condition>
1392
1393     <condition id="CM23_GCC">
1394       <description>Cortex-M23 processor based device for the GCC Compiler</description>
1395       <require condition="CM23"/>
1396       <require Tcompiler="GCC"/>
1397     </condition>
1398     <condition id="CM23_LE_GCC">
1399       <description>Cortex-M23 processor based device in little endian mode for the GCC Compiler</description>
1400       <require condition="CM23_GCC"/>
1401       <require Dendian="Little-endian"/>
1402     </condition>
1403     <condition id="CM23_BE_GCC">
1404       <description>Cortex-M23 processor based device in big endian mode for the GCC Compiler</description>
1405       <require condition="CM23_GCC"/>
1406       <require Dendian="Big-endian"/>
1407     </condition>
1408
1409     <condition id="CM33_GCC">
1410       <description>Cortex-M33 processor based device for the GCC Compiler</description>
1411       <require condition="CM33"/>
1412       <require Tcompiler="GCC"/>
1413     </condition>
1414     <condition id="CM33_LE_GCC">
1415       <description>Cortex-M33 processor based device in little endian mode for the GCC Compiler</description>
1416       <require condition="CM33_GCC"/>
1417       <require Dendian="Little-endian"/>
1418     </condition>
1419     <condition id="CM33_BE_GCC">
1420       <description>Cortex-M33 processor based device in big endian mode for the GCC Compiler</description>
1421       <require condition="CM33_GCC"/>
1422       <require Dendian="Big-endian"/>
1423     </condition>
1424
1425     <condition id="CM33_FP_GCC">
1426       <description>Cortex-M33 processor based device using Floating Point Unit for the GCC Compiler</description>
1427       <require condition="CM33_FP"/>
1428       <require Tcompiler="GCC"/>
1429     </condition>
1430     <condition id="CM33_FP_LE_GCC">
1431       <description>Cortex-M33 processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
1432       <require condition="CM33_FP_GCC"/>
1433       <require Dendian="Little-endian"/>
1434     </condition>
1435     <condition id="CM33_FP_BE_GCC">
1436       <description>Cortex-M33 processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
1437       <require condition="CM33_FP_GCC"/>
1438       <require Dendian="Big-endian"/>
1439     </condition>
1440
1441     <condition id="CM33_NODSP_NOFPU_GCC">
1442       <description>CM33, no DSP, no FPU, GCC Compiler</description>
1443       <require condition="CM33_NODSP_NOFPU"/>
1444       <require Tcompiler="GCC"/>
1445     </condition>
1446     <condition id="CM33_DSP_NOFPU_GCC">
1447       <description>CM33, DSP, no FPU, GCC Compiler</description>
1448       <require condition="CM33_DSP_NOFPU"/>
1449       <require Tcompiler="GCC"/>
1450     </condition>
1451     <condition id="CM33_NODSP_SP_GCC">
1452       <description>CM33, no DSP, SP FPU, GCC Compiler</description>
1453       <require condition="CM33_NODSP_SP"/>
1454       <require Tcompiler="GCC"/>
1455     </condition>
1456     <condition id="CM33_DSP_SP_GCC">
1457       <description>CM33, DSP, SP FPU, GCC Compiler</description>
1458       <require condition="CM33_DSP_SP"/>
1459       <require Tcompiler="GCC"/>
1460     </condition>
1461     <condition id="CM33_NODSP_NOFPU_LE_GCC">
1462       <description>CM33, little endian, no DSP, no FPU, GCC Compiler</description>
1463       <require condition="CM33_NODSP_NOFPU_GCC"/>
1464       <require Dendian="Little-endian"/>
1465     </condition>
1466     <condition id="CM33_DSP_NOFPU_LE_GCC">
1467       <description>CM33, little endian, DSP, no FPU, GCC Compiler</description>
1468       <require condition="CM33_DSP_NOFPU_GCC"/>
1469       <require Dendian="Little-endian"/>
1470     </condition>
1471     <condition id="CM33_NODSP_SP_LE_GCC">
1472       <description>CM33, little endian, no DSP, SP FPU, GCC Compiler</description>
1473       <require condition="CM33_NODSP_SP_GCC"/>
1474       <require Dendian="Little-endian"/>
1475     </condition>
1476     <condition id="CM33_DSP_SP_LE_GCC">
1477       <description>CM33, little endian, DSP, SP FPU, GCC Compiler</description>
1478       <require condition="CM33_DSP_SP_GCC"/>
1479       <require Dendian="Little-endian"/>
1480     </condition>
1481
1482     <condition id="ARMv8MBL_GCC">
1483       <description>Armv8-M Baseline processor based device for the GCC Compiler</description>
1484       <require condition="ARMv8MBL"/>
1485       <require Tcompiler="GCC"/>
1486     </condition>
1487     <condition id="ARMv8MBL_LE_GCC">
1488       <description>Armv8-M Baseline processor based device in little endian mode for the GCC Compiler</description>
1489       <require condition="ARMv8MBL_GCC"/>
1490       <require Dendian="Little-endian"/>
1491     </condition>
1492     <condition id="ARMv8MBL_BE_GCC">
1493       <description>Armv8-M Baseline processor based device in big endian mode for the GCC Compiler</description>
1494       <require condition="ARMv8MBL_GCC"/>
1495       <require Dendian="Big-endian"/>
1496     </condition>
1497
1498     <condition id="ARMv8MML_GCC">
1499       <description>Armv8-M Mainline processor based device for the GCC Compiler</description>
1500       <require condition="ARMv8MML"/>
1501       <require Tcompiler="GCC"/>
1502     </condition>
1503     <condition id="ARMv8MML_LE_GCC">
1504       <description>Armv8-M Mainline processor based device in little endian mode for the GCC Compiler</description>
1505       <require condition="ARMv8MML_GCC"/>
1506       <require Dendian="Little-endian"/>
1507     </condition>
1508     <condition id="ARMv8MML_BE_GCC">
1509       <description>Armv8-M Mainline processor based device in big endian mode for the GCC Compiler</description>
1510       <require condition="ARMv8MML_GCC"/>
1511       <require Dendian="Big-endian"/>
1512     </condition>
1513
1514     <condition id="ARMv8MML_FP_GCC">
1515       <description>Armv8-M Mainline processor based device using Floating Point Unit for the GCC Compiler</description>
1516       <require condition="ARMv8MML_FP"/>
1517       <require Tcompiler="GCC"/>
1518     </condition>
1519     <condition id="ARMv8MML_FP_LE_GCC">
1520       <description>Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
1521       <require condition="ARMv8MML_FP_GCC"/>
1522       <require Dendian="Little-endian"/>
1523     </condition>
1524     <condition id="ARMv8MML_FP_BE_GCC">
1525       <description>Armv8-M Mainline processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
1526       <require condition="ARMv8MML_FP_GCC"/>
1527       <require Dendian="Big-endian"/>
1528     </condition>
1529
1530     <condition id="ARMv8MML_NODSP_NOFPU_GCC">
1531       <description>Armv8-M Mainline, no DSP, no FPU, GCC Compiler</description>
1532       <require condition="ARMv8MML_NODSP_NOFPU"/>
1533       <require Tcompiler="GCC"/>
1534     </condition>
1535     <condition id="ARMv8MML_DSP_NOFPU_GCC">
1536       <description>Armv8-M Mainline, DSP, no FPU, GCC Compiler</description>
1537       <require condition="ARMv8MML_DSP_NOFPU"/>
1538       <require Tcompiler="GCC"/>
1539     </condition>
1540     <condition id="ARMv8MML_NODSP_SP_GCC">
1541       <description>Armv8-M Mainline, no DSP, SP FPU, GCC Compiler</description>
1542       <require condition="ARMv8MML_NODSP_SP"/>
1543       <require Tcompiler="GCC"/>
1544     </condition>
1545     <condition id="ARMv8MML_DSP_SP_GCC">
1546       <description>Armv8-M Mainline, DSP, SP FPU, GCC Compiler</description>
1547       <require condition="ARMv8MML_DSP_SP"/>
1548       <require Tcompiler="GCC"/>
1549     </condition>
1550     <condition id="ARMv8MML_NODSP_NOFPU_LE_GCC">
1551       <description>Armv8-M Mainline, little endian, no DSP, no FPU, GCC Compiler</description>
1552       <require condition="ARMv8MML_NODSP_NOFPU_GCC"/>
1553       <require Dendian="Little-endian"/>
1554     </condition>
1555     <condition id="ARMv8MML_DSP_NOFPU_LE_GCC">
1556       <description>Armv8-M Mainline, little endian, DSP, no FPU, GCC Compiler</description>
1557       <require condition="ARMv8MML_DSP_NOFPU_GCC"/>
1558       <require Dendian="Little-endian"/>
1559     </condition>
1560     <condition id="ARMv8MML_NODSP_SP_LE_GCC">
1561       <description>Armv8-M Mainline, little endian, no DSP, SP FPU, GCC Compiler</description>
1562       <require condition="ARMv8MML_NODSP_SP_GCC"/>
1563       <require Dendian="Little-endian"/>
1564     </condition>
1565     <condition id="ARMv8MML_DSP_SP_LE_GCC">
1566       <description>Armv8-M Mainline, little endian, DSP, SP FPU, GCC Compiler</description>
1567       <require condition="ARMv8MML_DSP_SP_GCC"/>
1568       <require Dendian="Little-endian"/>
1569     </condition>
1570
1571     <!-- IAR compiler -->
1572     <condition id="CA_IAR">
1573       <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the IAR Compiler</description>
1574       <require condition="ARMv7-A Device"/>
1575       <require Tcompiler="IAR"/>
1576     </condition>
1577
1578     <condition id="CM0_IAR">
1579       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device for the IAR Compiler</description>
1580       <require condition="CM0"/>
1581       <require Tcompiler="IAR"/>
1582     </condition>
1583     <condition id="CM0_LE_IAR">
1584       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the IAR Compiler</description>
1585       <require condition="CM0_IAR"/>
1586       <require Dendian="Little-endian"/>
1587     </condition>
1588     <condition id="CM0_BE_IAR">
1589       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the IAR Compiler</description>
1590       <require condition="CM0_IAR"/>
1591       <require Dendian="Big-endian"/>
1592     </condition>
1593
1594     <condition id="CM3_IAR">
1595       <description>Cortex-M3 or SC300 processor based device for the IAR Compiler</description>
1596       <require condition="CM3"/>
1597       <require Tcompiler="IAR"/>
1598     </condition>
1599     <condition id="CM3_LE_IAR">
1600       <description>Cortex-M3 or SC300 processor based device in little endian mode for the IAR Compiler</description>
1601       <require condition="CM3_IAR"/>
1602       <require Dendian="Little-endian"/>
1603     </condition>
1604     <condition id="CM3_BE_IAR">
1605       <description>Cortex-M3 or SC300 processor based device in big endian mode for the IAR Compiler</description>
1606       <require condition="CM3_IAR"/>
1607       <require Dendian="Big-endian"/>
1608     </condition>
1609
1610     <condition id="CM4_IAR">
1611       <description>Cortex-M4 processor based device for the IAR Compiler</description>
1612       <require condition="CM4"/>
1613       <require Tcompiler="IAR"/>
1614     </condition>
1615     <condition id="CM4_LE_IAR">
1616       <description>Cortex-M4 processor based device in little endian mode for the IAR Compiler</description>
1617       <require condition="CM4_IAR"/>
1618       <require Dendian="Little-endian"/>
1619     </condition>
1620     <condition id="CM4_BE_IAR">
1621       <description>Cortex-M4 processor based device in big endian mode for the IAR Compiler</description>
1622       <require condition="CM4_IAR"/>
1623       <require Dendian="Big-endian"/>
1624     </condition>
1625
1626     <condition id="CM4_FP_IAR">
1627       <description>Cortex-M4 processor based device using Floating Point Unit for the IAR Compiler</description>
1628       <require condition="CM4_FP"/>
1629       <require Tcompiler="IAR"/>
1630     </condition>
1631     <condition id="CM4_FP_LE_IAR">
1632       <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
1633       <require condition="CM4_FP_IAR"/>
1634       <require Dendian="Little-endian"/>
1635     </condition>
1636     <condition id="CM4_FP_BE_IAR">
1637       <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
1638       <require condition="CM4_FP_IAR"/>
1639       <require Dendian="Big-endian"/>
1640     </condition>
1641
1642     <condition id="CM7_IAR">
1643       <description>Cortex-M7 processor based device for the IAR Compiler</description>
1644       <require condition="CM7"/>
1645       <require Tcompiler="IAR"/>
1646     </condition>
1647     <condition id="CM7_LE_IAR">
1648       <description>Cortex-M7 processor based device in little endian mode for the IAR Compiler</description>
1649       <require condition="CM7_IAR"/>
1650       <require Dendian="Little-endian"/>
1651     </condition>
1652     <condition id="CM7_BE_IAR">
1653       <description>Cortex-M7 processor based device in big endian mode for the IAR Compiler</description>
1654       <require condition="CM7_IAR"/>
1655       <require Dendian="Big-endian"/>
1656     </condition>
1657
1658     <condition id="CM7_FP_IAR">
1659       <description>Cortex-M7 processor based device using Floating Point Unit for the IAR Compiler</description>
1660       <require condition="CM7_FP"/>
1661       <require Tcompiler="IAR"/>
1662     </condition>
1663     <condition id="CM7_FP_LE_IAR">
1664       <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
1665       <require condition="CM7_FP_IAR"/>
1666       <require Dendian="Little-endian"/>
1667     </condition>
1668     <condition id="CM7_FP_BE_IAR">
1669       <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
1670       <require condition="CM7_FP_IAR"/>
1671       <require Dendian="Big-endian"/>
1672     </condition>
1673
1674     <condition id="CM7_SP_IAR">
1675       <description>Cortex-M7 processor based device using Floating Point Unit (SP) for the IAR Compiler</description>
1676       <require condition="CM7_SP"/>
1677       <require Tcompiler="IAR"/>
1678     </condition>
1679     <condition id="CM7_SP_LE_IAR">
1680       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the IAR Compiler</description>
1681       <require condition="CM7_SP_IAR"/>
1682       <require Dendian="Little-endian"/>
1683     </condition>
1684     <condition id="CM7_SP_BE_IAR">
1685       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the IAR Compiler</description>
1686       <require condition="CM7_SP_IAR"/>
1687       <require Dendian="Big-endian"/>
1688     </condition>
1689
1690     <condition id="CM7_DP_IAR">
1691       <description>Cortex-M7 processor based device using Floating Point Unit (DP) for the IAR Compiler</description>
1692       <require condition="CM7_DP"/>
1693       <require Tcompiler="IAR"/>
1694     </condition>
1695     <condition id="CM7_DP_LE_IAR">
1696       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the IAR Compiler</description>
1697       <require condition="CM7_DP_IAR"/>
1698       <require Dendian="Little-endian"/>
1699     </condition>
1700     <condition id="CM7_DP_BE_IAR">
1701       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the IAR Compiler</description>
1702       <require condition="CM7_DP_IAR"/>
1703       <require Dendian="Big-endian"/>
1704     </condition>
1705
1706     <condition id="CM23_IAR">
1707       <description>Cortex-M23 processor based device for the IAR Compiler</description>
1708       <require condition="CM23"/>
1709       <require Tcompiler="IAR"/>
1710     </condition>
1711     <condition id="CM23_LE_IAR">
1712       <description>Cortex-M23 processor based device in little endian mode for the IAR Compiler</description>
1713       <require condition="CM23_IAR"/>
1714       <require Dendian="Little-endian"/>
1715     </condition>
1716     <condition id="CM23_BE_IAR">
1717       <description>Cortex-M23 processor based device in big endian mode for the IAR Compiler</description>
1718       <require condition="CM23_IAR"/>
1719       <require Dendian="Big-endian"/>
1720     </condition>
1721
1722     <condition id="CM33_IAR">
1723       <description>Cortex-M33 processor based device for the IAR Compiler</description>
1724       <require condition="CM33"/>
1725       <require Tcompiler="IAR"/>
1726     </condition>
1727     <condition id="CM33_LE_IAR">
1728       <description>Cortex-M33 processor based device in little endian mode for the IAR Compiler</description>
1729       <require condition="CM33_IAR"/>
1730       <require Dendian="Little-endian"/>
1731     </condition>
1732     <condition id="CM33_BE_IAR">
1733       <description>Cortex-M33 processor based device in big endian mode for the IAR Compiler</description>
1734       <require condition="CM33_IAR"/>
1735       <require Dendian="Big-endian"/>
1736     </condition>
1737
1738     <condition id="CM33_FP_IAR">
1739       <description>Cortex-M33 processor based device using Floating Point Unit for the IAR Compiler</description>
1740       <require condition="CM33_FP"/>
1741       <require Tcompiler="IAR"/>
1742     </condition>
1743     <condition id="CM33_FP_LE_IAR">
1744       <description>Cortex-M33 processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
1745       <require condition="CM33_FP_IAR"/>
1746       <require Dendian="Little-endian"/>
1747     </condition>
1748     <condition id="CM33_FP_BE_IAR">
1749       <description>Cortex-M33 processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
1750       <require condition="CM33_FP_IAR"/>
1751       <require Dendian="Big-endian"/>
1752     </condition>
1753
1754     <condition id="CM33_NODSP_NOFPU_IAR">
1755       <description>CM33, no DSP, no FPU, IAR Compiler</description>
1756       <require condition="CM33_NODSP_NOFPU"/>
1757       <require Tcompiler="IAR"/>
1758     </condition>
1759     <condition id="CM33_DSP_NOFPU_IAR">
1760       <description>CM33, DSP, no FPU, IAR Compiler</description>
1761       <require condition="CM33_DSP_NOFPU"/>
1762       <require Tcompiler="IAR"/>
1763     </condition>
1764     <condition id="CM33_NODSP_SP_IAR">
1765       <description>CM33, no DSP, SP FPU, IAR Compiler</description>
1766       <require condition="CM33_NODSP_SP"/>
1767       <require Tcompiler="IAR"/>
1768     </condition>
1769     <condition id="CM33_DSP_SP_IAR">
1770       <description>CM33, DSP, SP FPU, IAR Compiler</description>
1771       <require condition="CM33_DSP_SP"/>
1772       <require Tcompiler="IAR"/>
1773     </condition>
1774     <condition id="CM33_NODSP_NOFPU_LE_IAR">
1775       <description>CM33, little endian, no DSP, no FPU, IAR Compiler</description>
1776       <require condition="CM33_NODSP_NOFPU_IAR"/>
1777       <require Dendian="Little-endian"/>
1778     </condition>
1779     <condition id="CM33_DSP_NOFPU_LE_IAR">
1780       <description>CM33, little endian, DSP, no FPU, IAR Compiler</description>
1781       <require condition="CM33_DSP_NOFPU_IAR"/>
1782       <require Dendian="Little-endian"/>
1783     </condition>
1784     <condition id="CM33_NODSP_SP_LE_IAR">
1785       <description>CM33, little endian, no DSP, SP FPU, IAR Compiler</description>
1786       <require condition="CM33_NODSP_SP_IAR"/>
1787       <require Dendian="Little-endian"/>
1788     </condition>
1789     <condition id="CM33_DSP_SP_LE_IAR">
1790       <description>CM33, little endian, DSP, SP FPU, IAR Compiler</description>
1791       <require condition="CM33_DSP_SP_IAR"/>
1792       <require Dendian="Little-endian"/>
1793     </condition>
1794
1795     <condition id="ARMv8MBL_IAR">
1796       <description>Armv8-M Baseline processor based device for the IAR Compiler</description>
1797       <require condition="ARMv8MBL"/>
1798       <require Tcompiler="IAR"/>
1799     </condition>
1800     <condition id="ARMv8MBL_LE_IAR">
1801       <description>Armv8-M Baseline processor based device in little endian mode for the IAR Compiler</description>
1802       <require condition="ARMv8MBL_IAR"/>
1803       <require Dendian="Little-endian"/>
1804     </condition>
1805     <condition id="ARMv8MBL_BE_IAR">
1806       <description>Armv8-M Baseline processor based device in big endian mode for the IAR Compiler</description>
1807       <require condition="ARMv8MBL_IAR"/>
1808       <require Dendian="Big-endian"/>
1809     </condition>
1810
1811     <condition id="ARMv8MML_IAR">
1812       <description>Armv8-M Mainline processor based device for the IAR Compiler</description>
1813       <require condition="ARMv8MML"/>
1814       <require Tcompiler="IAR"/>
1815     </condition>
1816     <condition id="ARMv8MML_LE_IAR">
1817       <description>Armv8-M Mainline processor based device in little endian mode for the IAR Compiler</description>
1818       <require condition="ARMv8MML_IAR"/>
1819       <require Dendian="Little-endian"/>
1820     </condition>
1821     <condition id="ARMv8MML_BE_IAR">
1822       <description>Armv8-M Mainline processor based device in big endian mode for the IAR Compiler</description>
1823       <require condition="ARMv8MML_IAR"/>
1824       <require Dendian="Big-endian"/>
1825     </condition>
1826
1827     <condition id="ARMv8MML_FP_IAR">
1828       <description>Armv8-M Mainline processor based device using Floating Point Unit for the IAR Compiler</description>
1829       <require condition="ARMv8MML_FP"/>
1830       <require Tcompiler="IAR"/>
1831     </condition>
1832     <condition id="ARMv8MML_FP_LE_IAR">
1833       <description>Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
1834       <require condition="ARMv8MML_FP_IAR"/>
1835       <require Dendian="Little-endian"/>
1836     </condition>
1837     <condition id="ARMv8MML_FP_BE_IAR">
1838       <description>Armv8-M Mainline processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
1839       <require condition="ARMv8MML_FP_IAR"/>
1840       <require Dendian="Big-endian"/>
1841     </condition>
1842
1843     <condition id="ARMv8MML_NODSP_NOFPU_IAR">
1844       <description>Armv8-M Mainline, no DSP, no FPU, IAR Compiler</description>
1845       <require condition="ARMv8MML_NODSP_NOFPU"/>
1846       <require Tcompiler="IAR"/>
1847     </condition>
1848     <condition id="ARMv8MML_DSP_NOFPU_IAR">
1849       <description>Armv8-M Mainline, DSP, no FPU, IAR Compiler</description>
1850       <require condition="ARMv8MML_DSP_NOFPU"/>
1851       <require Tcompiler="IAR"/>
1852     </condition>
1853     <condition id="ARMv8MML_NODSP_SP_IAR">
1854       <description>Armv8-M Mainline, no DSP, SP FPU, IAR Compiler</description>
1855       <require condition="ARMv8MML_NODSP_SP"/>
1856       <require Tcompiler="IAR"/>
1857     </condition>
1858     <condition id="ARMv8MML_DSP_SP_IAR">
1859       <description>Armv8-M Mainline, DSP, SP FPU, IAR Compiler</description>
1860       <require condition="ARMv8MML_DSP_SP"/>
1861       <require Tcompiler="IAR"/>
1862     </condition>
1863     <condition id="ARMv8MML_NODSP_NOFPU_LE_IAR">
1864       <description>Armv8-M Mainline, little endian, no DSP, no FPU, IAR Compiler</description>
1865       <require condition="ARMv8MML_NODSP_NOFPU_IAR"/>
1866       <require Dendian="Little-endian"/>
1867     </condition>
1868     <condition id="ARMv8MML_DSP_NOFPU_LE_IAR">
1869       <description>Armv8-M Mainline, little endian, DSP, no FPU, IAR Compiler</description>
1870       <require condition="ARMv8MML_DSP_NOFPU_IAR"/>
1871       <require Dendian="Little-endian"/>
1872     </condition>
1873     <condition id="ARMv8MML_NODSP_SP_LE_IAR">
1874       <description>Armv8-M Mainline, little endian, no DSP, SP FPU, IAR Compiler</description>
1875       <require condition="ARMv8MML_NODSP_SP_IAR"/>
1876       <require Dendian="Little-endian"/>
1877     </condition>
1878     <condition id="ARMv8MML_DSP_SP_LE_IAR">
1879       <description>Armv8-M Mainline, little endian, DSP, SP FPU, IAR Compiler</description>
1880       <require condition="ARMv8MML_DSP_SP_IAR"/>
1881       <require Dendian="Little-endian"/>
1882     </condition>
1883
1884     <!-- conditions selecting single devices and CMSIS Core -->
1885     <!-- used for component startup, GCC version is used for C-Startup -->
1886     <condition id="ARMCM0 CMSIS">
1887       <description>Generic Arm Cortex-M0 device startup and depends on CMSIS Core</description>
1888       <require Dvendor="ARM:82" Dname="ARMCM0"/>
1889       <require Cclass="CMSIS" Cgroup="CORE"/>
1890     </condition>
1891     <condition id="ARMCM0 CMSIS GCC">
1892       <description>Generic ARM Cortex-M0 device startup and depends on CMSIS Core requiring GCC</description>
1893       <require condition="ARMCM0 CMSIS"/>
1894       <require condition="GCC"/>
1895     </condition>
1896
1897     <condition id="ARMCM0+ CMSIS">
1898       <description>Generic Arm Cortex-M0+ device startup and depends on CMSIS Core</description>
1899       <require Dvendor="ARM:82" Dname="ARMCM0P*"/>
1900       <require Cclass="CMSIS" Cgroup="CORE"/>
1901     </condition>
1902     <condition id="ARMCM0+ CMSIS GCC">
1903       <description>Generic Arm Cortex-M0+ device startup and depends CMSIS Core requiring GCC</description>
1904       <require condition="ARMCM0+ CMSIS"/>
1905       <require condition="GCC"/>
1906     </condition>
1907
1908     <condition id="ARMCM3 CMSIS">
1909       <description>Generic Arm Cortex-M3 device startup and depends on CMSIS Core</description>
1910       <require Dvendor="ARM:82" Dname="ARMCM3"/>
1911       <require Cclass="CMSIS" Cgroup="CORE"/>
1912     </condition>
1913     <condition id="ARMCM3 CMSIS GCC">
1914       <description>Generic Arm Cortex-M3 device startup and depends on CMSIS Core requiring GCC</description>
1915       <require condition="ARMCM3 CMSIS"/>
1916       <require condition="GCC"/>
1917     </condition>
1918
1919     <condition id="ARMCM4 CMSIS">
1920       <description>Generic Arm Cortex-M4 device startup and depends on CMSIS Core</description>
1921       <require Dvendor="ARM:82" Dname="ARMCM4*"/>
1922       <require Cclass="CMSIS" Cgroup="CORE"/>
1923     </condition>
1924     <condition id="ARMCM4 CMSIS GCC">
1925       <description>Generic Arm Cortex-M4 device startup and depends on CMSIS Core requiring GCC</description>
1926       <require condition="ARMCM4 CMSIS"/>
1927       <require condition="GCC"/>
1928     </condition>
1929
1930     <condition id="ARMCM7 CMSIS">
1931       <description>Generic Arm Cortex-M7 device startup and depends on CMSIS Core</description>
1932       <require Dvendor="ARM:82" Dname="ARMCM7*"/>
1933       <require Cclass="CMSIS" Cgroup="CORE"/>
1934     </condition>
1935     <condition id="ARMCM7 CMSIS GCC">
1936       <description>Generic Arm Cortex-M7 device startup and depends on CMSIS Core requiring GCC</description>
1937       <require condition="ARMCM7 CMSIS"/>
1938       <require condition="GCC"/>
1939     </condition>
1940
1941     <condition id="ARMCM23 CMSIS">
1942       <description>Generic Arm Cortex-M23 device startup and depends on CMSIS Core</description>
1943       <require Dvendor="ARM:82" Dname="ARMCM23*"/>
1944       <require Cclass="CMSIS" Cgroup="CORE"/>
1945     </condition>
1946     <condition id="ARMCM23 CMSIS GCC">
1947       <description>Generic Arm Cortex-M23 device startup and depends on CMSIS Core requiring GCC</description>
1948       <require condition="ARMCM23 CMSIS"/>
1949       <require condition="GCC"/>
1950     </condition>
1951
1952     <condition id="ARMCM33 CMSIS">
1953       <description>Generic Arm Cortex-M33 device startup and depends on CMSIS Core</description>
1954       <require Dvendor="ARM:82" Dname="ARMCM33*"/>
1955       <require Cclass="CMSIS" Cgroup="CORE"/>
1956     </condition>
1957     <condition id="ARMCM33 CMSIS GCC">
1958       <description>Generic Arm Cortex-M33 device startup and depends on CMSIS Core requiring GCC</description>
1959       <require condition="ARMCM33 CMSIS"/>
1960       <require condition="GCC"/>
1961     </condition>
1962
1963     <condition id="ARMSC000 CMSIS">
1964       <description>Generic Arm SC000 device startup and depends on CMSIS Core</description>
1965       <require Dvendor="ARM:82" Dname="ARMSC000"/>
1966       <require Cclass="CMSIS" Cgroup="CORE"/>
1967     </condition>
1968     <condition id="ARMSC000 CMSIS GCC">
1969       <description>Generic Arm SC000 device startup and depends on CMSIS Core requiring GCC</description>
1970       <require condition="ARMSC000 CMSIS"/>
1971       <require condition="GCC"/>
1972     </condition>
1973
1974     <condition id="ARMSC300 CMSIS">
1975       <description>Generic Arm SC300 device startup and depends on CMSIS Core</description>
1976       <require Dvendor="ARM:82" Dname="ARMSC300"/>
1977       <require Cclass="CMSIS" Cgroup="CORE"/>
1978     </condition>
1979     <condition id="ARMSC300 CMSIS GCC">
1980       <description>Generic Arm SC300 device startup and dependson CMSIS Core requiring GCC</description>
1981       <require condition="ARMSC300 CMSIS"/>
1982       <require condition="GCC"/>
1983     </condition>
1984
1985     <condition id="ARMv8MBL CMSIS">
1986       <description>Generic Armv8-M Baseline device startup and depends on CMSIS Core</description>
1987       <require Dvendor="ARM:82" Dname="ARMv8MBL"/>
1988       <require Cclass="CMSIS" Cgroup="CORE"/>
1989     </condition>
1990     <condition id="ARMv8MBL CMSIS GCC">
1991       <description>Generic Armv8-M Baseline device startup and depends on CMSIS Core requiring GCC</description>
1992       <require condition="ARMv8MBL CMSIS"/>
1993       <require condition="GCC"/>
1994     </condition>
1995
1996     <condition id="ARMv8MML CMSIS">
1997       <description>Generic Armv8-M Mainline device startup and depends on CMSIS Core</description>
1998       <require Dvendor="ARM:82" Dname="ARMv8MML*"/>
1999       <require Cclass="CMSIS" Cgroup="CORE"/>
2000     </condition>
2001     <condition id="ARMv8MML CMSIS GCC">
2002       <description>Generic Armv8-M Mainline device startup and depends on CMSIS Core requiring GCC</description>
2003       <require condition="ARMv8MML CMSIS"/>
2004       <require condition="GCC"/>
2005     </condition>
2006
2007     <condition id="ARMCA5 CMSIS">
2008       <description>Generic Arm Cortex-A5 device startup and depends on CMSIS Core</description>
2009       <require Dvendor="ARM:82" Dname="ARMCA5"/>
2010       <require Cclass="CMSIS" Cgroup="CORE"/>
2011     </condition>
2012
2013     <condition id="ARMCA7 CMSIS">
2014       <description>Generic Arm Cortex-A7 device startup and depends on CMSIS Core</description>
2015       <require Dvendor="ARM:82" Dname="ARMCA7"/>
2016       <require Cclass="CMSIS" Cgroup="CORE"/>
2017     </condition>
2018
2019     <condition id="ARMCA9 CMSIS">
2020       <description>Generic Arm Cortex-A9 device startup and depends on CMSIS Core</description>
2021       <require Dvendor="ARM:82" Dname="ARMCA9"/>
2022       <require Cclass="CMSIS" Cgroup="CORE"/>
2023     </condition>
2024
2025     <!-- CMSIS DSP -->
2026     <condition id="CMSIS DSP">
2027       <description>Components required for DSP</description>
2028       <require condition="ARMv6_7_8-M Device"/>
2029       <require condition="ARMCC GCC IAR"/>
2030       <require Cclass="CMSIS" Cgroup="CORE"/>
2031     </condition>
2032
2033     <!-- CMSIS NN -->
2034     <condition id="CMSIS NN">
2035       <description>Components required for NN</description>
2036       <require condition="CMSIS DSP"/>
2037     </condition>
2038
2039     <!-- RTOS RTX -->
2040     <condition id="RTOS RTX">
2041       <description>Components required for RTOS RTX</description>
2042       <require condition="ARMv6_7-M Device"/>
2043       <require condition="ARMCC GCC IAR"/>
2044       <require Cclass="Device" Cgroup="Startup"/>
2045       <deny    Cclass="CMSIS"  Cgroup="RTOS2" Csub="Keil RTX5"/>
2046     </condition>
2047     <condition id="RTOS RTX IFX">
2048       <description>Components required for RTOS RTX IFX</description>
2049       <require condition="ARMv6_7-M Device"/>
2050       <require condition="ARMCC GCC IAR"/>
2051       <require Dvendor="Infineon:7" Dname="XMC4*"/>
2052       <require Cclass="Device" Cgroup="Startup"/>
2053       <deny    Cclass="CMSIS"  Cgroup="RTOS2" Csub="Keil RTX5"/>
2054     </condition>
2055     <condition id="RTOS RTX5">
2056       <description>Components required for RTOS RTX5</description>
2057       <require condition="ARMv6_7_8-M Device"/>
2058       <require condition="ARMCC GCC IAR"/>
2059       <require Cclass="CMSIS"  Cgroup="RTOS2" Csub="Keil RTX5"/>
2060     </condition>
2061     <condition id="RTOS2 RTX5">
2062       <description>Components required for RTOS2 RTX5</description>
2063       <require condition="ARMv6_7_8-M Device"/>
2064       <require condition="ARMCC GCC IAR"/>
2065       <require Cclass="CMSIS"  Cgroup="CORE"/>
2066       <require Cclass="Device" Cgroup="Startup"/>
2067     </condition>
2068     <condition id="RTOS2 RTX5 v7-A">
2069       <description>Components required for RTOS2 RTX5 on Armv7-A</description>
2070       <require condition="ARMv7-A Device"/>
2071       <require condition="ARMCC GCC IAR"/>
2072       <require Cclass="CMSIS"  Cgroup="CORE"/>
2073       <require Cclass="Device" Cgroup="Startup"/>
2074       <require Cclass="Device" Cgroup="OS Tick"/>
2075       <require Cclass="Device" Cgroup="IRQ Controller"/>
2076     </condition>
2077     <condition id="RTOS2 RTX5 Lib">
2078       <description>Components required for RTOS2 RTX5 Library</description>
2079       <require condition="ARMv6_7_8-M Device"/>
2080       <require condition="ARMCC GCC IAR"/>
2081       <require Cclass="CMSIS"  Cgroup="CORE"/>
2082       <require Cclass="Device" Cgroup="Startup"/>
2083     </condition>
2084     <condition id="RTOS2 RTX5 NS">
2085       <description>Components required for RTOS2 RTX5 in Non-Secure Domain</description>
2086       <require condition="ARMv8-M TZ Device"/>
2087       <require condition="ARMCC GCC IAR"/>
2088       <require Cclass="CMSIS"  Cgroup="CORE"/>
2089       <require Cclass="Device" Cgroup="Startup"/>
2090     </condition>
2091
2092     <!-- OS Tick -->
2093     <condition id="OS Tick PTIM">
2094       <description>Components required for OS Tick Private Timer</description>
2095       <require condition="CA5_CA9"/>
2096       <require Cclass="Device" Cgroup="IRQ Controller"/>
2097     </condition>
2098
2099     <condition id="OS Tick GTIM">
2100       <description>Components required for OS Tick Generic Physical Timer</description>
2101       <require condition="CA7"/>
2102       <require Cclass="Device" Cgroup="IRQ Controller"/>
2103     </condition>
2104
2105   </conditions>
2106
2107   <components>
2108     <!-- CMSIS-Core component -->
2109     <component Cclass="CMSIS" Cgroup="CORE" Cversion="5.1.1"  condition="ARMv6_7_8-M Device" >
2110       <description>CMSIS-CORE for Cortex-M, SC000, SC300, ARMv8-M</description>
2111       <files>
2112         <!-- CPU independent -->
2113         <file category="doc"     name="CMSIS/Documentation/Core/html/index.html"/>
2114         <file category="include" name="CMSIS/Core/Include/"/>
2115         <file category="header"  name="CMSIS/Core/Include/tz_context.h" condition="ARMv8-M TZ Device"/>
2116         <!-- Code template -->
2117         <file category="sourceC" attr="template" condition="ARMv8-M TZ Device" name="CMSIS/Core/Template/ARMv8-M/main_s.c"     version="1.1.0" select="Secure mode 'main' module for ARMv8-M"/>
2118         <file category="sourceC" attr="template" condition="ARMv8-M TZ Device" name="CMSIS/Core/Template/ARMv8-M/tz_context.c" version="1.1.0" select="RTOS Context Management (TrustZone for ARMv8-M)" />
2119       </files>
2120     </component>
2121
2122     <component Cclass="CMSIS" Cgroup="CORE" Cversion="1.1.1"  condition="ARMv7-A Device" >
2123       <description>CMSIS-CORE for Cortex-A</description>
2124       <files>
2125         <!-- CPU independent -->
2126         <file category="doc"     name="CMSIS/Documentation/Core_A/html/index.html"/>
2127         <file category="include" name="CMSIS/Core_A/Include/"/>
2128       </files>
2129     </component>
2130
2131     <!-- CMSIS-Startup components -->
2132     <!-- Cortex-M0 -->
2133     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM0 CMSIS">
2134       <description>System and Startup for Generic Arm Cortex-M0 device</description>
2135       <files>
2136         <!-- include folder / device header file -->
2137         <file category="header"  name="Device/ARM/ARMCM0/Include/ARMCM0.h"/>
2138         <!-- startup / system file -->
2139         <file category="sourceAsm"    name="Device/ARM/ARMCM0/Source/ARM/startup_ARMCM0.s" version="1.0.0" attr="config" condition="ARMCC"/>
2140         <file category="sourceAsm"    name="Device/ARM/ARMCM0/Source/GCC/startup_ARMCM0.S" version="1.0.0" attr="config" condition="GCC"/>
2141         <file category="linkerScript" name="Device/ARM/ARMCM0/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2142         <file category="sourceAsm"    name="Device/ARM/ARMCM0/Source/IAR/startup_ARMCM0.s" version="1.0.0" attr="config" condition="IAR"/>
2143         <file category="sourceC"      name="Device/ARM/ARMCM0/Source/system_ARMCM0.c"      version="1.0.0" attr="config"/>
2144       </files>
2145     </component>
2146     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM0 CMSIS GCC">
2147       <description>System and Startup for Generic Arm Cortex-M0 device</description>
2148       <files>
2149         <!-- include folder / device header file -->
2150         <file category="header"  name="Device/ARM/ARMCM0/Include/ARMCM0.h"/>
2151         <!-- startup / system file -->
2152         <file category="sourceC"      name="Device/ARM/ARMCM0/Source/GCC/startup_ARMCM0.c" version="1.0.0" attr="config" condition="GCC"/>
2153         <file category="linkerScript" name="Device/ARM/ARMCM0/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2154         <file category="sourceC"      name="Device/ARM/ARMCM0/Source/system_ARMCM0.c"      version="1.0.0" attr="config"/>
2155       </files>
2156     </component>
2157
2158     <!-- Cortex-M0+ -->
2159     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM0+ CMSIS">
2160       <description>System and Startup for Generic Arm Cortex-M0+ device</description>
2161       <files>
2162         <!-- include folder / device header file -->
2163         <file category="header"  name="Device/ARM/ARMCM0plus/Include/ARMCM0plus.h"/>
2164         <!-- startup / system file -->
2165         <file category="sourceAsm"    name="Device/ARM/ARMCM0plus/Source/ARM/startup_ARMCM0plus.s" version="1.0.0" attr="config" condition="ARMCC"/>
2166         <file category="sourceAsm"    name="Device/ARM/ARMCM0plus/Source/GCC/startup_ARMCM0plus.S" version="1.0.0" attr="config" condition="GCC"/>
2167         <file category="linkerScript" name="Device/ARM/ARMCM0plus/Source/GCC/gcc_arm.ld"           version="1.0.0" attr="config" condition="GCC"/>
2168         <file category="sourceAsm"    name="Device/ARM/ARMCM0plus/Source/IAR/startup_ARMCM0plus.s" version="1.0.0" attr="config" condition="IAR"/>
2169         <file category="sourceC"      name="Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c"      version="1.0.0" attr="config"/>
2170       </files>
2171     </component>
2172     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM0+ CMSIS GCC">
2173       <description>System and Startup for Generic Arm Cortex-M0+ device</description>
2174       <files>
2175         <!-- include folder / device header file -->
2176         <file category="header"  name="Device/ARM/ARMCM0plus/Include/ARMCM0plus.h"/>
2177         <!-- startup / system file -->
2178         <file category="sourceC"      name="Device/ARM/ARMCM0plus/Source/GCC/startup_ARMCM0plus.c" version="1.0.0" attr="config" condition="GCC"/>
2179         <file category="linkerScript" name="Device/ARM/ARMCM0plus/Source/GCC/gcc_arm.ld"           version="1.0.0" attr="config" condition="GCC"/>
2180         <file category="sourceC"      name="Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c"      version="1.0.0" attr="config"/>
2181       </files>
2182     </component>
2183
2184     <!-- Cortex-M3 -->
2185     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM3 CMSIS">
2186       <description>System and Startup for Generic Arm Cortex-M3 device</description>
2187       <files>
2188         <!-- include folder / device header file -->
2189         <file category="header"  name="Device/ARM/ARMCM3/Include/ARMCM3.h"/>
2190         <!-- startup / system file -->
2191         <file category="sourceAsm"    name="Device/ARM/ARMCM3/Source/ARM/startup_ARMCM3.s" version="1.0.0" attr="config" condition="ARMCC"/>
2192         <file category="sourceAsm"    name="Device/ARM/ARMCM3/Source/GCC/startup_ARMCM3.S" version="1.0.0" attr="config" condition="GCC"/>
2193         <file category="linkerScript" name="Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2194         <file category="sourceAsm"    name="Device/ARM/ARMCM3/Source/IAR/startup_ARMCM3.s" version="1.0.0" attr="config" condition="IAR"/>
2195         <file category="sourceC"      name="Device/ARM/ARMCM3/Source/system_ARMCM3.c"      version="1.0.0" attr="config"/>
2196       </files>
2197     </component>
2198     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM3 CMSIS GCC">
2199       <description>System and Startup for Generic Arm Cortex-M3 device</description>
2200       <files>
2201         <!-- include folder / device header file -->
2202         <file category="header"  name="Device/ARM/ARMCM3/Include/ARMCM3.h"/>
2203         <!-- startup / system file -->
2204         <file category="sourceC"      name="Device/ARM/ARMCM3/Source/GCC/startup_ARMCM3.c" version="1.0.0" attr="config" condition="GCC"/>
2205         <file category="linkerScript" name="Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2206         <file category="sourceC"      name="Device/ARM/ARMCM3/Source/system_ARMCM3.c"      version="1.0.0" attr="config"/>
2207       </files>
2208     </component>
2209
2210     <!-- Cortex-M4 -->
2211     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM4 CMSIS">
2212       <description>System and Startup for Generic Arm Cortex-M4 device</description>
2213       <files>
2214         <!-- include folder / device header file -->
2215         <file category="include" name="Device/ARM/ARMCM4/Include/"/>
2216         <!-- startup / system file -->
2217         <file category="sourceAsm"    name="Device/ARM/ARMCM4/Source/ARM/startup_ARMCM4.s" version="1.0.0" attr="config" condition="ARMCC"/>
2218         <file category="sourceAsm"    name="Device/ARM/ARMCM4/Source/GCC/startup_ARMCM4.S" version="1.0.0" attr="config" condition="GCC"/>
2219         <file category="linkerScript" name="Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2220         <file category="sourceAsm"    name="Device/ARM/ARMCM4/Source/IAR/startup_ARMCM4.s" version="1.0.0" attr="config" condition="IAR"/>
2221         <file category="sourceC"      name="Device/ARM/ARMCM4/Source/system_ARMCM4.c"      version="1.0.0" attr="config"/>
2222       </files>
2223     </component>
2224     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM4 CMSIS GCC">
2225       <description>System and Startup for Generic Arm Cortex-M4 device</description>
2226       <files>
2227         <!-- include folder / device header file -->
2228         <file category="include" name="Device/ARM/ARMCM4/Include/"/>
2229         <!-- startup / system file -->
2230         <file category="sourceC"      name="Device/ARM/ARMCM4/Source/GCC/startup_ARMCM4.c" version="1.0.0" attr="config" condition="GCC"/>
2231         <file category="linkerScript" name="Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2232         <file category="sourceC"      name="Device/ARM/ARMCM4/Source/system_ARMCM4.c"      version="1.0.0" attr="config"/>
2233       </files>
2234     </component>
2235
2236     <!-- Cortex-M7 -->
2237     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM7 CMSIS">
2238       <description>System and Startup for Generic Arm Cortex-M7 device</description>
2239       <files>
2240         <!-- include folder / device header file -->
2241         <file category="include"  name="Device/ARM/ARMCM7/Include/"/>
2242         <!-- startup / system file -->
2243         <file category="sourceAsm"    name="Device/ARM/ARMCM7/Source/ARM/startup_ARMCM7.s" version="1.0.0" attr="config" condition="ARMCC"/>
2244         <file category="sourceAsm"    name="Device/ARM/ARMCM7/Source/GCC/startup_ARMCM7.S" version="1.0.0" attr="config" condition="GCC"/>
2245         <file category="linkerScript" name="Device/ARM/ARMCM7/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2246         <file category="sourceAsm"    name="Device/ARM/ARMCM7/Source/IAR/startup_ARMCM7.s" version="1.0.0" attr="config" condition="IAR"/>
2247         <file category="sourceC"      name="Device/ARM/ARMCM7/Source/system_ARMCM7.c"      version="1.0.0" attr="config"/>
2248       </files>
2249     </component>
2250     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM7 CMSIS GCC">
2251       <description>System and Startup for Generic Arm Cortex-M7 device</description>
2252       <files>
2253         <!-- include folder / device header file -->
2254         <file category="include"  name="Device/ARM/ARMCM7/Include/"/>
2255         <!-- startup / system file -->
2256         <file category="sourceC"      name="Device/ARM/ARMCM7/Source/GCC/startup_ARMCM7.c" version="1.0.0" attr="config" condition="GCC"/>
2257         <file category="linkerScript" name="Device/ARM/ARMCM7/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2258         <file category="sourceC"      name="Device/ARM/ARMCM7/Source/system_ARMCM7.c"      version="1.0.0" attr="config"/>
2259       </files>
2260     </component>
2261
2262     <!-- Cortex-M23 -->
2263     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.0" condition="ARMCM23 CMSIS">
2264       <description>System and Startup for Generic Arm Cortex-M23 device</description>
2265       <files>
2266         <!-- include folder / device header file -->
2267         <file category="include"      name="Device/ARM/ARMCM23/Include/"/>
2268         <!-- startup / system file -->
2269         <file category="sourceAsm"    name="Device/ARM/ARMCM23/Source/ARM/startup_ARMCM23.s" version="1.0.0" attr="config" condition="ARMCC"/>
2270         <file category="sourceAsm"    name="Device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.S" version="1.0.0" attr="config" condition="GCC"/>
2271         <file category="linkerScript" name="Device/ARM/ARMCM23/Source/GCC/gcc_arm.ld"        version="1.0.0" attr="config" condition="GCC"/>
2272         <file category="sourceAsm"    name="Device/ARM/ARMCM23/Source/IAR/startup_ARMCM23.s" version="1.0.0" attr="config" condition="IAR"/>
2273         <file category="sourceC"      name="Device/ARM/ARMCM23/Source/system_ARMCM23.c"      version="1.0.0" attr="config"/>
2274         <!-- SAU configuration -->
2275         <file category="header"       name="Device/ARM/ARMCM23/Include/Template/partition_ARMCM23.h" version="1.0.0" attr="config" condition="ARMv8-M TZ Device"/>
2276       </files>
2277     </component>
2278     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.0" condition="ARMCM23 CMSIS GCC">
2279       <description>System and Startup for Generic Arm Cortex-M23 device</description>
2280       <files>
2281         <!-- include folder / device header file -->
2282         <file category="include"  name="Device/ARM/ARMCM23/Include/"/>
2283         <!-- startup / system file -->
2284         <file category="sourceC"      name="Device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.c" version="1.0.0" attr="config" condition="GCC"/>
2285         <file category="linkerScript" name="Device/ARM/ARMCM23/Source/GCC/gcc_arm.ld"        version="1.0.0" attr="config" condition="GCC"/>
2286         <file category="sourceC"      name="Device/ARM/ARMCM23/Source/system_ARMCM23.c"      version="1.0.0" attr="config"/>
2287         <!-- SAU configuration -->
2288         <file category="header"       name="Device/ARM/ARMCM23/Include/Template/partition_ARMCM23.h" version="1.0.0" attr="config" condition="ARMv8-M TZ Device"/>
2289       </files>
2290     </component>
2291
2292     <!-- Cortex-M33 -->
2293     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.1.0" condition="ARMCM33 CMSIS">
2294       <description>System and Startup for Generic Arm Cortex-M33 device</description>
2295       <files>
2296         <!-- include folder / device header file -->
2297         <file category="include"      name="Device/ARM/ARMCM33/Include/"/>
2298         <!-- startup / system file -->
2299         <file category="sourceAsm"    name="Device/ARM/ARMCM33/Source/ARM/startup_ARMCM33.s"         version="1.0.0" attr="config" condition="ARMCC"/>
2300         <file category="sourceAsm"    name="Device/ARM/ARMCM33/Source/GCC/startup_ARMCM33.S"         version="1.0.0" attr="config" condition="GCC"/>
2301         <file category="linkerScript" name="Device/ARM/ARMCM33/Source/GCC/gcc_arm.ld"                version="1.0.0" attr="config" condition="GCC"/>
2302         <file category="sourceAsm"    name="Device/ARM/ARMCM33/Source/IAR/startup_ARMCM33.s"         version="1.0.0" attr="config" condition="IAR"/>
2303         <file category="sourceC"      name="Device/ARM/ARMCM33/Source/system_ARMCM33.c"              version="1.0.0" attr="config"/>
2304         <!-- SAU configuration -->
2305         <file category="header"       name="Device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2306       </files>
2307     </component>
2308     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.1.0" condition="ARMCM33 CMSIS GCC">
2309       <description>System and Startup for Generic Arm Cortex-M33 device</description>
2310       <files>
2311         <!-- include folder / device header file -->
2312         <file category="include"  name="Device/ARM/ARMCM33/Include/"/>
2313         <!-- startup / system file -->
2314         <file category="sourceC"      name="Device/ARM/ARMCM33/Source/GCC/startup_ARMCM33.c"         version="1.0.0" attr="config" condition="GCC"/>
2315         <file category="linkerScript" name="Device/ARM/ARMCM33/Source/GCC/gcc_arm.ld"                version="1.0.0" attr="config" condition="GCC"/>
2316         <file category="sourceC"      name="Device/ARM/ARMCM33/Source/system_ARMCM33.c"              version="1.0.0" attr="config"/>
2317         <!-- SAU configuration -->
2318         <file category="header"       name="Device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2319       </files>
2320     </component>
2321
2322     <!-- Cortex-SC000 -->
2323     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMSC000 CMSIS">
2324       <description>System and Startup for Generic Arm SC000 device</description>
2325       <files>
2326         <!-- include folder / device header file -->
2327         <file category="header"  name="Device/ARM/ARMSC000/Include/ARMSC000.h"/>
2328         <!-- startup / system file -->
2329         <file category="sourceAsm"    name="Device/ARM/ARMSC000/Source/ARM/startup_ARMSC000.s" version="1.0.0" attr="config" condition="ARMCC"/>
2330         <file category="sourceAsm"    name="Device/ARM/ARMSC000/Source/GCC/startup_ARMSC000.S" version="1.0.0" attr="config" condition="GCC"/>
2331         <file category="linkerScript" name="Device/ARM/ARMSC000/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2332         <file category="sourceAsm"    name="Device/ARM/ARMSC000/Source/IAR/startup_ARMSC000.s" version="1.0.0" attr="config" condition="IAR"/>
2333         <file category="sourceC"      name="Device/ARM/ARMSC000/Source/system_ARMSC000.c"      version="1.0.0" attr="config"/>
2334       </files>
2335     </component>
2336     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMSC000 CMSIS GCC">
2337       <description>System and Startup for Generic Arm SC000 device</description>
2338       <files>
2339         <!-- include folder / device header file -->
2340         <file category="header"  name="Device/ARM/ARMSC000/Include/ARMSC000.h"/>
2341         <!-- startup / system file -->
2342         <file category="sourceC"      name="Device/ARM/ARMSC000/Source/GCC/startup_ARMSC000.c" version="1.0.0" attr="config" condition="GCC"/>
2343         <file category="linkerScript" name="Device/ARM/ARMSC000/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2344         <file category="sourceC"      name="Device/ARM/ARMSC000/Source/system_ARMSC000.c"      version="1.0.0" attr="config"/>
2345       </files>
2346     </component>
2347
2348     <!-- Cortex-SC300 -->
2349     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMSC300 CMSIS">
2350       <description>System and Startup for Generic Arm SC300 device</description>
2351       <files>
2352         <!-- include folder / device header file -->
2353         <file category="header"  name="Device/ARM/ARMSC300/Include/ARMSC300.h"/>
2354         <!-- startup / system file -->
2355         <file category="sourceAsm"    name="Device/ARM/ARMSC300/Source/ARM/startup_ARMSC300.s" version="1.0.0" attr="config" condition="ARMCC"/>
2356         <file category="sourceAsm"    name="Device/ARM/ARMSC300/Source/GCC/startup_ARMSC300.S" version="1.0.0" attr="config" condition="GCC"/>
2357         <file category="linkerScript" name="Device/ARM/ARMSC300/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2358         <file category="sourceAsm"    name="Device/ARM/ARMSC300/Source/IAR/startup_ARMSC300.s" version="1.0.0" attr="config" condition="IAR"/>
2359         <file category="sourceC"      name="Device/ARM/ARMSC300/Source/system_ARMSC300.c"      version="1.0.0" attr="config"/>
2360       </files>
2361     </component>
2362     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMSC300 CMSIS GCC">
2363       <description>System and Startup for Generic Arm SC300 device</description>
2364       <files>
2365         <!-- include folder / device header file -->
2366         <file category="header"  name="Device/ARM/ARMSC300/Include/ARMSC300.h"/>
2367         <!-- startup / system file -->
2368         <file category="sourceC"      name="Device/ARM/ARMSC300/Source/GCC/startup_ARMSC300.c" version="1.0.0" attr="config" condition="GCC"/>
2369         <file category="linkerScript" name="Device/ARM/ARMSC300/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2370         <file category="sourceC"      name="Device/ARM/ARMSC300/Source/system_ARMSC300.c"      version="1.0.0" attr="config"/>
2371       </files>
2372     </component>
2373
2374     <!-- ARMv8MBL -->
2375     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.0" condition="ARMv8MBL CMSIS">
2376       <description>System and Startup for Generic Armv8-M Baseline device</description>
2377       <files>
2378         <!-- include folder / device header file -->
2379         <file category="include"      name="Device/ARM/ARMv8MBL/Include/"/>
2380         <!-- startup / system file -->
2381         <file category="sourceAsm"    name="Device/ARM/ARMv8MBL/Source/ARM/startup_ARMv8MBL.s" version="1.0.0" attr="config" condition="ARMCC"/>
2382         <file category="sourceAsm"    name="Device/ARM/ARMv8MBL/Source/GCC/startup_ARMv8MBL.S" version="1.0.0" attr="config" condition="GCC"/>
2383         <file category="linkerScript" name="Device/ARM/ARMv8MBL/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2384         <file category="sourceC"      name="Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c"      version="1.0.0" attr="config" condition="ARMCC GCC"/>
2385         <!-- SAU configuration -->
2386         <file category="header"       name="Device/ARM/ARMv8MBL/Include/Template/partition_ARMv8MBL.h" version="1.0.0" attr="config"/>
2387       </files>
2388     </component>
2389     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.0" condition="ARMv8MBL CMSIS GCC">
2390       <description>System and Startup for Generic Armv8-M Baseline device</description>
2391       <files>
2392         <!-- include folder / device header file -->
2393         <file category="include"  name="Device/ARM/ARMv8MBL/Include/"/>
2394         <!-- startup / system file -->
2395         <file category="sourceC"      name="Device/ARM/ARMv8MBL/Source/GCC/startup_ARMv8MBL.c" version="1.0.0" attr="config" condition="GCC"/>
2396         <file category="linkerScript" name="Device/ARM/ARMv8MBL/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2397         <file category="sourceC"      name="Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c"      version="1.0.0" attr="config"/>
2398         <!-- SAU configuration -->
2399         <file category="header"       name="Device/ARM/ARMv8MBL/Include/Template/partition_ARMv8MBL.h" version="1.0.0" attr="config" condition="ARMv8-M TZ Device"/>
2400       </files>
2401     </component>
2402
2403     <!-- ARMv8MML -->
2404     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.1.0" condition="ARMv8MML CMSIS">
2405       <description>System and Startup for Generic Armv8-M Mainline device</description>
2406       <files>
2407         <!-- include folder / device header file -->
2408         <file category="include"      name="Device/ARM/ARMv8MML/Include/"/>
2409         <!-- startup / system file -->
2410         <file category="sourceAsm"    name="Device/ARM/ARMv8MML/Source/ARM/startup_ARMv8MML.s"         version="1.0.0" attr="config" condition="ARMCC"/>
2411         <file category="sourceAsm"    name="Device/ARM/ARMv8MML/Source/GCC/startup_ARMv8MML.S"         version="1.0.0" attr="config" condition="GCC"/>
2412         <file category="linkerScript" name="Device/ARM/ARMv8MML/Source/GCC/gcc_arm.ld"                 version="1.0.0" attr="config" condition="GCC"/>
2413         <file category="sourceC"      name="Device/ARM/ARMv8MML/Source/system_ARMv8MML.c"              version="1.0.0" attr="config" condition="ARMCC GCC"/>
2414         <!-- SAU configuration -->
2415         <file category="header"       name="Device/ARM/ARMv8MML/Include/Template/partition_ARMv8MML.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2416       </files>
2417     </component>
2418     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.1.0" condition="ARMv8MML CMSIS GCC">
2419       <description>System and Startup for Generic Armv8-M Mainline device</description>
2420       <files>
2421         <!-- include folder / device header file -->
2422         <file category="include"      name="Device/ARM/ARMv8MML/Include/"/>
2423         <!-- startup / system file -->
2424         <file category="sourceC"      name="Device/ARM/ARMv8MML/Source/GCC/startup_ARMv8MML.c"         version="1.0.0" attr="config" condition="GCC"/>
2425         <file category="linkerScript" name="Device/ARM/ARMv8MML/Source/GCC/gcc_arm.ld"                 version="1.0.0" attr="config" condition="GCC"/>
2426         <file category="sourceC"      name="Device/ARM/ARMv8MML/Source/system_ARMv8MML.c"              version="1.0.0" attr="config"/>
2427         <!-- SAU configuration -->
2428         <file category="header"       name="Device/ARM/ARMv8MML/Include/Template/partition_ARMv8MML.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2429       </files>
2430     </component>
2431
2432     <!-- Cortex-A5 -->
2433     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.0" condition="ARMCA5 CMSIS">
2434       <description>System and Startup for Generic Arm Cortex-A5 device</description>
2435       <files>
2436         <!-- include folder / device header file -->
2437         <file category="include"      name="Device/ARM/ARMCA5/Include/"/>
2438         <!-- startup / system / mmu files -->
2439         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/AC5/startup_ARMCA5.c" version="1.0.0" attr="config" condition="ARMCC5"/>
2440         <file category="linkerScript" name="Device/ARM/ARMCA5/Source/AC5/ARMCA5.sct"       version="1.0.0" attr="config" condition="ARMCC5"/>
2441         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/AC6/startup_ARMCA5.c" version="1.0.0" attr="config" condition="ARMCC6"/>
2442         <file category="linkerScript" name="Device/ARM/ARMCA5/Source/AC6/ARMCA5.sct"       version="1.0.0" attr="config" condition="ARMCC6"/>
2443         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/GCC/startup_ARMCA5.c" version="1.0.0" attr="config" condition="GCC"/>
2444         <file category="other"        name="Device/ARM/ARMCA5/Source/GCC/ARMCA5.ld"        version="1.0.0" attr="config" condition="GCC"/>
2445         <file category="sourceAsm"    name="Device/ARM/ARMCA5/Source/IAR/startup_ARMCA5.s" version="1.0.0" attr="config" condition="IAR"/>
2446         <file category="linkerScript" name="Device/ARM/ARMCA5/Source/IAR/ARMCA5.icf"       version="1.0.0" attr="config" condition="IAR"/>
2447         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/system_ARMCA5.c"      version="1.0.0" attr="config"/>
2448         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/mmu_ARMCA5.c"         version="1.0.0" attr="config"/>
2449         <file category="header"       name="Device/ARM/ARMCA5/Include/system_ARMCA5.h"     version="1.0.0" attr="config"/>
2450         <file category="header"       name="Device/ARM/ARMCA5/Include/mem_ARMCA5.h"        version="1.0.0" attr="config"/>
2451
2452       </files>
2453     </component>
2454
2455     <!-- Cortex-A7 -->
2456     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.0" condition="ARMCA7 CMSIS">
2457       <description>System and Startup for Generic Arm Cortex-A7 device</description>
2458       <files>
2459         <!-- include folder / device header file -->
2460         <file category="include"      name="Device/ARM/ARMCA7/Include/"/>
2461         <!-- startup / system / mmu files -->
2462         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/AC5/startup_ARMCA7.c" version="1.0.0" attr="config" condition="ARMCC5"/>
2463         <file category="linkerScript" name="Device/ARM/ARMCA7/Source/AC5/ARMCA7.sct"       version="1.0.0" attr="config" condition="ARMCC5"/>
2464         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/AC6/startup_ARMCA7.c" version="1.0.0" attr="config" condition="ARMCC6"/>
2465         <file category="linkerScript" name="Device/ARM/ARMCA7/Source/AC6/ARMCA7.sct"       version="1.0.0" attr="config" condition="ARMCC6"/>
2466         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/GCC/startup_ARMCA7.c" version="1.0.0" attr="config" condition="GCC"/>
2467         <file category="other"        name="Device/ARM/ARMCA7/Source/GCC/ARMCA7.ld"        version="1.0.0" attr="config" condition="GCC"/>
2468         <file category="sourceAsm"    name="Device/ARM/ARMCA7/Source/IAR/startup_ARMCA7.s" version="1.0.0" attr="config" condition="IAR"/>
2469         <file category="linkerScript" name="Device/ARM/ARMCA7/Source/IAR/ARMCA7.icf"       version="1.0.0" attr="config" condition="IAR"/>
2470         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/system_ARMCA7.c"      version="1.0.0" attr="config"/>
2471         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/mmu_ARMCA7.c"         version="1.0.0" attr="config"/>
2472         <file category="header"       name="Device/ARM/ARMCA7/Include/system_ARMCA7.h"     version="1.0.0" attr="config"/>
2473         <file category="header"       name="Device/ARM/ARMCA7/Include/mem_ARMCA7.h"        version="1.0.0" attr="config"/>
2474       </files>
2475     </component>
2476
2477     <!-- Cortex-A9 -->
2478     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCA9 CMSIS">
2479       <description>System and Startup for Generic Arm Cortex-A9 device</description>
2480       <files>
2481         <!-- include folder / device header file -->
2482         <file category="include"  name="Device/ARM/ARMCA9/Include/"/>
2483         <!-- startup / system / mmu files -->
2484         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/AC5/startup_ARMCA9.c" version="1.0.0" attr="config" condition="ARMCC5"/>
2485         <file category="linkerScript" name="Device/ARM/ARMCA9/Source/AC5/ARMCA9.sct"       version="1.0.0" attr="config" condition="ARMCC5"/>
2486         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/AC6/startup_ARMCA9.c" version="1.0.0" attr="config" condition="ARMCC6"/>
2487         <file category="linkerScript" name="Device/ARM/ARMCA9/Source/AC6/ARMCA9.sct"       version="1.0.0" attr="config" condition="ARMCC6"/>
2488         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/GCC/startup_ARMCA9.c" version="1.0.0" attr="config" condition="GCC"/>
2489         <file category="other"        name="Device/ARM/ARMCA9/Source/GCC/ARMCA9.ld"        version="1.0.0" attr="config" condition="GCC"/>
2490         <file category="sourceAsm"    name="Device/ARM/ARMCA9/Source/IAR/startup_ARMCA9.s" version="1.0.0" attr="config" condition="IAR"/>
2491         <file category="linkerScript" name="Device/ARM/ARMCA9/Source/IAR/ARMCA9.icf"       version="1.0.0" attr="config" condition="IAR"/>
2492         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/system_ARMCA9.c"      version="1.0.0" attr="config"/>
2493         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/mmu_ARMCA9.c"         version="1.0.0" attr="config"/>
2494         <file category="header"       name="Device/ARM/ARMCA9/Include/system_ARMCA9.h"     version="1.0.0" attr="config"/>
2495         <file category="header"       name="Device/ARM/ARMCA9/Include/mem_ARMCA9.h"        version="1.0.0" attr="config"/>
2496       </files>
2497     </component>
2498
2499     <!-- IRQ Controller -->
2500     <component Cclass="Device" Cgroup="IRQ Controller" Csub="GIC" Capiversion="1.0.0" Cversion="1.0.1" condition="ARMv7-A Device">
2501       <description>IRQ Controller implementation using GIC</description>
2502       <files>
2503         <file category="sourceC" name="CMSIS/Core_A/Source/irq_ctrl_gic.c"/>
2504       </files>
2505     </component>
2506
2507     <!-- OS Tick -->
2508     <component Cclass="Device" Cgroup="OS Tick" Csub="Private Timer" Capiversion="1.0.1" Cversion="1.0.2" condition="OS Tick PTIM">
2509       <description>OS Tick implementation using Private Timer</description>
2510       <files>
2511         <file category="sourceC" name="CMSIS/RTOS2/Source/os_tick_ptim.c"/>
2512       </files>
2513     </component>
2514
2515     <component Cclass="Device" Cgroup="OS Tick" Csub="Generic Physical Timer" Capiversion="1.0.1" Cversion="1.0.1" condition="OS Tick GTIM">
2516       <description>OS Tick implementation using Generic Physical Timer</description>
2517       <files>
2518         <file category="sourceC" name="CMSIS/RTOS2/Source/os_tick_gtim.c"/>
2519       </files>
2520     </component>
2521
2522     <!-- CMSIS-DSP component -->
2523     <component Cclass="CMSIS" Cgroup="DSP" Cversion="1.5.2" condition="CMSIS DSP">
2524       <description>CMSIS-DSP Library for Cortex-M, SC000, and SC300</description>
2525       <files>
2526         <!-- CPU independent -->
2527         <file category="doc" name="CMSIS/Documentation/DSP/html/index.html"/>
2528         <file category="header" name="CMSIS/DSP/Include/arm_math.h"/>
2529
2530         <!-- CPU and Compiler dependent -->
2531         <!-- ARMCC -->
2532         <file category="library" condition="CM0_LE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM0l_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2533         <file category="library" condition="CM0_BE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM0b_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2534         <file category="library" condition="CM3_LE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM3l_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2535         <file category="library" condition="CM3_BE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM3b_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2536         <file category="library" condition="CM4_LE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM4l_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2537         <file category="library" condition="CM4_BE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM4b_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2538         <file category="library" condition="CM4_FP_LE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM4lf_math.lib"     src="CMSIS/DSP/Source/ARM"/>
2539         <file category="library" condition="CM4_FP_BE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM4bf_math.lib"     src="CMSIS/DSP/Source/ARM"/>
2540         <file category="library" condition="CM7_LE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM7l_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2541         <file category="library" condition="CM7_BE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM7b_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2542         <file category="library" condition="CM7_SP_LE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM7lfsp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
2543         <file category="library" condition="CM7_SP_BE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM7bfsp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
2544         <file category="library" condition="CM7_DP_LE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM7lfdp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
2545         <file category="library" condition="CM7_DP_BE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM7bfdp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
2546
2547         <file category="library" condition="CM23_LE_ARMCC"                  name="CMSIS/Lib/ARM/arm_ARMv8MBLl_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2548         <file category="library" condition="CM33_NODSP_NOFPU_LE_ARMCC"      name="CMSIS/Lib/ARM/arm_ARMv8MMLl_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2549         <file category="library" condition="CM33_DSP_NOFPU_LE_ARMCC"        name="CMSIS/Lib/ARM/arm_ARMv8MMLld_math.lib"     src="CMSIS/DSP/Source/ARM"/>
2550         <file category="library" condition="CM33_NODSP_SP_LE_ARMCC"         name="CMSIS/Lib/ARM/arm_ARMv8MMLlfsp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
2551         <file category="library" condition="CM33_DSP_SP_LE_ARMCC"           name="CMSIS/Lib/ARM/arm_ARMv8MMLldfsp_math.lib"  src="CMSIS/DSP/Source/ARM"/>
2552         <file category="library" condition="ARMv8MBL_LE_ARMCC"              name="CMSIS/Lib/ARM/arm_ARMv8MBLl_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2553         <file category="library" condition="ARMv8MML_NODSP_NOFPU_LE_ARMCC"  name="CMSIS/Lib/ARM/arm_ARMv8MMLl_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2554         <file category="library" condition="ARMv8MML_DSP_NOFPU_LE_ARMCC"    name="CMSIS/Lib/ARM/arm_ARMv8MMLld_math.lib"     src="CMSIS/DSP/Source/ARM"/>
2555         <file category="library" condition="ARMv8MML_NODSP_SP_LE_ARMCC"     name="CMSIS/Lib/ARM/arm_ARMv8MMLlfsp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
2556         <file category="library" condition="ARMv8MML_DSP_SP_LE_ARMCC"       name="CMSIS/Lib/ARM/arm_ARMv8MMLldfsp_math.lib"  src="CMSIS/DSP/Source/ARM"/>
2557         <!--file category="library" condition="ARMv8MML_DP_NOFPU_LE_ARMCC"     name="CMSIS/Lib/ARM/arm_ARMv8MMLlfdp_math.lib"   src="CMSIS/DSP/Source/ARM"/-->
2558         <!--file category="library" condition="ARMv8MML_DSP_DP_LE_ARMCC"       name="CMSIS/Lib/ARM/arm_ARMv8MMLldfdp_math.lib"  src="CMSIS/DSP/Source/ARM"/-->
2559
2560         <!-- GCC -->
2561         <file category="library" condition="CM0_LE_GCC"               name="CMSIS/Lib/GCC/libarm_cortexM0l_math.a"     src="CMSIS/DSP/Source/GCC"/>
2562         <file category="library" condition="CM3_LE_GCC"               name="CMSIS/Lib/GCC/libarm_cortexM3l_math.a"     src="CMSIS/DSP/Source/GCC"/>
2563         <file category="library" condition="CM4_LE_GCC"               name="CMSIS/Lib/GCC/libarm_cortexM4l_math.a"     src="CMSIS/DSP/Source/GCC"/>
2564         <file category="library" condition="CM4_FP_LE_GCC"            name="CMSIS/Lib/GCC/libarm_cortexM4lf_math.a"    src="CMSIS/DSP/Source/GCC"/>
2565         <file category="library" condition="CM7_LE_GCC"               name="CMSIS/Lib/GCC/libarm_cortexM7l_math.a"     src="CMSIS/DSP/Source/GCC"/>
2566         <file category="library" condition="CM7_SP_LE_GCC"            name="CMSIS/Lib/GCC/libarm_cortexM7lfsp_math.a"  src="CMSIS/DSP/Source/GCC"/>
2567         <file category="library" condition="CM7_DP_LE_GCC"            name="CMSIS/Lib/GCC/libarm_cortexM7lfdp_math.a"  src="CMSIS/DSP/Source/GCC"/>
2568
2569         <file category="library" condition="CM23_LE_GCC"                    name="CMSIS/Lib/GCC/libarm_ARMv8MBLl_math.a"     src="CMSIS/DSP/Source/GCC"/>
2570         <file category="library" condition="CM33_NODSP_NOFPU_LE_GCC"        name="CMSIS/Lib/GCC/libarm_ARMv8MMLl_math.a"     src="CMSIS/DSP/Source/GCC"/>
2571         <file category="library" condition="CM33_DSP_NOFPU_LE_GCC"          name="CMSIS/Lib/GCC/libarm_ARMv8MMLld_math.a"    src="CMSIS/DSP/Source/GCC"/>
2572         <file category="library" condition="CM33_NODSP_SP_LE_GCC"           name="CMSIS/Lib/GCC/libarm_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP/Source/GCC"/>
2573         <file category="library" condition="CM33_DSP_SP_LE_GCC"             name="CMSIS/Lib/GCC/libarm_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
2574         <file category="library" condition="ARMv8MBL_LE_GCC"                name="CMSIS/Lib/GCC/libarm_ARMv8MBLl_math.a"     src="CMSIS/DSP/Source/GCC"/>
2575         <file category="library" condition="ARMv8MML_NODSP_NOFPU_LE_GCC"    name="CMSIS/Lib/GCC/libarm_ARMv8MMLl_math.a"     src="CMSIS/DSP/Source/GCC"/>
2576         <file category="library" condition="ARMv8MML_DSP_NOFPU_LE_GCC"      name="CMSIS/Lib/GCC/libarm_ARMv8MMLld_math.a"    src="CMSIS/DSP/Source/GCC"/>
2577         <file category="library" condition="ARMv8MML_NODSP_SP_LE_GCC"       name="CMSIS/Lib/GCC/libarm_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP/Source/GCC"/>
2578         <file category="library" condition="ARMv8MML_DSP_SP_LE_GCC"         name="CMSIS/Lib/GCC/libarm_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
2579         <!--file category="library" condition="ARMv8MML_DP_NOFPU_LE_GCC"       name="CMSIS/Lib/GCC/libarm_ARMv8MMLlfdp_math.a"  src="CMSIS/DSP/Source/GCC"/-->
2580         <!--file category="library" condition="ARMv8MML_DSP_DP_LE_GCC"         name="CMSIS/Lib/GCC/libarm_ARMv8MMLldfdp_math.a" src="CMSIS/DSP/Source/GCC"/-->
2581
2582         <!-- IAR -->
2583         <file category="library" condition="CM0_LE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM0l_math.a"     src="CMSIS/DSP/Source/IAR"/>
2584         <file category="library" condition="CM0_BE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM0b_math.a"     src="CMSIS/DSP/Source/IAR"/>
2585         <file category="library" condition="CM3_LE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM3l_math.a"     src="CMSIS/DSP/Source/IAR"/>
2586         <file category="library" condition="CM3_BE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM3b_math.a"     src="CMSIS/DSP/Source/IAR"/>
2587         <file category="library" condition="CM4_LE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM4l_math.a"     src="CMSIS/DSP/Source/IAR"/>
2588         <file category="library" condition="CM4_BE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM4b_math.a"     src="CMSIS/DSP/Source/IAR"/>
2589         <file category="library" condition="CM4_FP_LE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM4lf_math.a"    src="CMSIS/DSP/Source/IAR"/>
2590         <file category="library" condition="CM4_FP_BE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM4bf_math.a"    src="CMSIS/DSP/Source/IAR"/>
2591         <file category="library" condition="CM7_LE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM7l_math.a"     src="CMSIS/DSP/Source/IAR"/>
2592         <file category="library" condition="CM7_BE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM7b_math.a"     src="CMSIS/DSP/Source/IAR"/>
2593         <file category="library" condition="CM7_DP_LE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM7lf_math.a"    src="CMSIS/DSP/Source/IAR"/>
2594         <file category="library" condition="CM7_DP_BE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM7bf_math.a"    src="CMSIS/DSP/Source/IAR"/>
2595         <file category="library" condition="CM7_SP_LE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM7ls_math.a"    src="CMSIS/DSP/Source/IAR"/>
2596         <file category="library" condition="CM7_SP_BE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM7bs_math.a"    src="CMSIS/DSP/Source/IAR"/>
2597
2598         <file category="library" condition="CM23_LE_IAR"              name="CMSIS/Lib/IAR/iar_ARMv8MBLl_math.a"     src="CMSIS/DSP/Source/IAR"/>
2599         <file category="library" condition="CM33_LE_IAR"              name="CMSIS/Lib/IAR/iar_ARMv8MMLl_math.a"     src="CMSIS/DSP/Source/IAR"/>
2600         <file category="library" condition="CM33_DSP_SP_LE_IAR"       name="CMSIS/Lib/IAR/iar_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP/Source/IAR"/>
2601         <file category="library" condition="CM33_FP_LE_IAR"           name="CMSIS/Lib/IAR/iar_ARMv8MMLlfdp_math.a"  src="CMSIS/DSP/Source/IAR"/>
2602         <file category="library" condition="CM33_DSP_NOFPU_LE_IAR"    name="CMSIS/Lib/IAR/iar_ARMv8MMLld_math.a"    src="CMSIS/DSP/Source/IAR"/>
2603         <file category="library" condition="CM33_DSP_SP_LE_IAR"       name="CMSIS/Lib/IAR/iar_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
2604         <!--file category="library" condition="CM33_DSP_DP_LE_IAR"       name="CMSIS/Lib/IAR/iar_ARMv8MMLldfdp_math.a" src="CMSIS/DSP/Source/IAR"/-->
2605         <file category="library" condition="ARMv8MBL_LE_IAR"          name="CMSIS/Lib/IAR/iar_ARMv8MBLl_math.a"     src="CMSIS/DSP/Source/IAR"/>
2606         <file category="library" condition="ARMv8MML_LE_IAR"          name="CMSIS/Lib/IAR/iar_ARMv8MMLl_math.a"     src="CMSIS/DSP/Source/IAR"/>
2607         <file category="library" condition="ARMv8MML_DSP_SP_LE_IAR"   name="CMSIS/Lib/IAR/iar_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP/Source/IAR"/>
2608         <file category="library" condition="ARMv8MML_FP_LE_IAR"       name="CMSIS/Lib/IAR/iar_ARMv8MMLlfdp_math.a"  src="CMSIS/DSP/Source/IAR"/>
2609         <file category="library" condition="ARMv8MML_DSP_NOFPU_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLld_math.a"    src="CMSIS/DSP/Source/IAR"/>
2610         <file category="library" condition="ARMv8MML_DSP_SP_LE_IAR"   name="CMSIS/Lib/IAR/iar_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
2611         <!--file category="library" condition="ARMv8MML_DSP_DP_LE_IAR"   name="CMSIS/Lib/IAR/iar_ARMv8MMLldfdp_math.a" src="CMSIS/DSP/Source/IAR"/-->
2612
2613       </files>
2614     </component>
2615
2616     <!-- CMSIS-NN component -->
2617     <component Cclass="CMSIS" Cgroup="NN Lib" Cversion="1.0.0" condition="CMSIS NN">
2618       <description>CMSIS-NN Neural Network Library</description>
2619       <files>
2620         <file category="doc" name="CMSIS/Documentation/NN/html/index.html"/>
2621         <file category="header" name="CMSIS/NN/Include/arm_nnfunctions.h"/>
2622
2623         <file category="source" name="CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c"/>
2624         <file category="source" name="CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c"/>
2625         <file category="source" name="CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c"/>
2626         <file category="source" name="CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c"/>
2627
2628         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c"/>
2629         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c"/>
2630         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c"/>
2631         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c"/>
2632         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c"/>
2633         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c"/>
2634         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c"/>
2635         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c"/>
2636         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c"/>
2637         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c"/>
2638         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c"/>
2639         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c"/>
2640
2641         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c"/>
2642         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c"/>
2643         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c"/>
2644         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c"/>
2645         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c"/>
2646         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c"/>
2647
2648         <file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c"/>
2649         <file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c"/>
2650         <file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c"/>
2651         <file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.c"/>
2652         <file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.c"/>
2653
2654         <file category="source" name="CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c"/>
2655
2656         <file category="source" name="CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.c"/>
2657         <file category="source" name="CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.c"/>
2658       </files>
2659     </component>
2660
2661     <!-- CMSIS-RTOS Keil RTX component -->
2662     <component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX" Cversion="4.81.1" Capiversion="1.0.0" isDefaultVariant="1" condition="RTOS RTX">
2663       <description>CMSIS-RTOS RTX implementation for Cortex-M, SC000, and SC300</description>
2664       <RTE_Components_h>
2665         <!-- the following content goes into file 'RTE_Components.h' -->
2666         #define RTE_CMSIS_RTOS                  /* CMSIS-RTOS */
2667         #define RTE_CMSIS_RTOS_RTX              /* CMSIS-RTOS Keil RTX */
2668       </RTE_Components_h>
2669       <files>
2670         <!-- CPU independent -->
2671         <file category="doc" name="CMSIS/Documentation/RTOS/html/rtxImplementation.html"/>
2672         <file category="header" name="CMSIS/RTOS/RTX/INC/cmsis_os.h"/>
2673         <file category="source" attr="config"   name="CMSIS/RTOS/RTX/Templates/RTX_Conf_CM.c" version="4.70.1"/>
2674
2675         <!-- RTX templates -->
2676         <file category="header" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/osObjects.h" select="CMSIS-RTOS 'main' function"/>
2677         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/main.c"      select="CMSIS-RTOS 'main' function"/>
2678         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MailQueue.c" select="CMSIS-RTOS Mail Queue"/>
2679         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MemPool.c"   select="CMSIS-RTOS Memory Pool"/>
2680         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MsgQueue.c"  select="CMSIS-RTOS Message Queue"/>
2681         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Mutex.c"     select="CMSIS-RTOS Mutex"/>
2682         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Semaphore.c" select="CMSIS-RTOS Semaphore"/>
2683         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Thread.c"    select="CMSIS-RTOS Thread"/>
2684         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Timer.c"     select="CMSIS-RTOS Timer"/>
2685         <!-- tool-chain specific template file -->
2686         <file category="source" attr="template" condition="ARMCC" name="CMSIS/RTOS/RTX/SRC/ARM/SVC_Table.s" select="CMSIS-RTOS User SVC"/>
2687         <file category="source" attr="template" condition="GCC"   name="CMSIS/RTOS/RTX/SRC/GCC/SVC_Table.S" select="CMSIS-RTOS User SVC"/>
2688         <file category="source" attr="template" condition="IAR"   name="CMSIS/RTOS/RTX/SRC/IAR/SVC_Table.s" select="CMSIS-RTOS User SVC"/>
2689
2690         <!-- CPU and Compiler dependent -->
2691         <!-- ARMCC -->
2692         <file category="library" condition="CM0_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
2693         <file category="library" condition="CM0_BE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
2694         <file category="library" condition="CM3_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
2695         <file category="library" condition="CM3_BE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
2696         <file category="library" condition="CM4_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
2697         <file category="library" condition="CM4_BE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
2698         <file category="library" condition="CM4_FP_LE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
2699         <file category="library" condition="CM4_FP_BE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
2700         <file category="library" condition="CM7_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
2701         <file category="library" condition="CM7_BE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
2702         <file category="library" condition="CM7_FP_LE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
2703         <file category="library" condition="CM7_FP_BE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
2704         <!-- GCC -->
2705         <file category="library" condition="CM0_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
2706         <file category="library" condition="CM0_BE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
2707         <file category="library" condition="CM3_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
2708         <file category="library" condition="CM3_BE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
2709         <file category="library" condition="CM4_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
2710         <file category="library" condition="CM4_BE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
2711         <file category="library" condition="CM4_FP_LE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
2712         <file category="library" condition="CM4_FP_BE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
2713         <file category="library" condition="CM7_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
2714         <file category="library" condition="CM7_BE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
2715         <file category="library" condition="CM7_FP_LE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
2716         <file category="library" condition="CM7_FP_BE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
2717         <!-- IAR -->
2718         <file category="library" condition="CM0_LE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
2719         <file category="library" condition="CM0_BE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
2720         <file category="library" condition="CM3_LE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
2721         <file category="library" condition="CM3_BE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
2722         <file category="library" condition="CM4_LE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
2723         <file category="library" condition="CM4_BE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
2724         <file category="library" condition="CM4_FP_LE_IAR"   name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
2725         <file category="library" condition="CM4_FP_BE_IAR"   name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
2726         <file category="library" condition="CM7_LE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
2727         <file category="library" condition="CM7_BE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
2728         <file category="library" condition="CM7_FP_LE_IAR"   name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
2729         <file category="library" condition="CM7_FP_BE_IAR"   name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
2730       </files>
2731     </component>
2732     <!-- CMSIS-RTOS Keil RTX component (IFX variant) -->
2733     <component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX" Cvariant="IFX" Cversion="4.81.1" Capiversion="1.0.0" condition="RTOS RTX IFX">
2734       <description>CMSIS-RTOS RTX implementation for Infineon XMC4 series affected by PMU_CM.001 errata</description>
2735       <RTE_Components_h>
2736         <!-- the following content goes into file 'RTE_Components.h' -->
2737         #define RTE_CMSIS_RTOS                  /* CMSIS-RTOS */
2738         #define RTE_CMSIS_RTOS_RTX              /* CMSIS-RTOS Keil RTX */
2739       </RTE_Components_h>
2740       <files>
2741         <!-- CPU independent -->
2742         <file category="doc" name="CMSIS/Documentation/RTOS/html/rtxImplementation.html"/>
2743         <file category="header" name="CMSIS/RTOS/RTX/INC/cmsis_os.h"/>
2744         <file category="source" attr="config"   name="CMSIS/RTOS/RTX/Templates/RTX_Conf_CM.c" version="4.70.1"/>
2745
2746         <!-- RTX templates -->
2747         <file category="header" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/osObjects.h" select="CMSIS-RTOS 'main' function"/>
2748         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/main.c"      select="CMSIS-RTOS 'main' function"/>
2749         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MailQueue.c" select="CMSIS-RTOS Mail Queue"/>
2750         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MemPool.c"   select="CMSIS-RTOS Memory Pool"/>
2751         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MsgQueue.c"  select="CMSIS-RTOS Message Queue"/>
2752         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Mutex.c"     select="CMSIS-RTOS Mutex"/>
2753         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Semaphore.c" select="CMSIS-RTOS Semaphore"/>
2754         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Thread.c"    select="CMSIS-RTOS Thread"/>
2755         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Timer.c"     select="CMSIS-RTOS Timer"/>
2756         <!-- tool-chain specific template file -->
2757         <file category="source" attr="template" condition="ARMCC" name="CMSIS/RTOS/RTX/SRC/ARM/SVC_Table.s" select="CMSIS-RTOS User SVC"/>
2758         <file category="source" attr="template" condition="GCC"   name="CMSIS/RTOS/RTX/SRC/GCC/SVC_Table.S" select="CMSIS-RTOS User SVC"/>
2759         <file category="source" attr="template" condition="IAR"   name="CMSIS/RTOS/RTX/SRC/IAR/SVC_Table.s" select="CMSIS-RTOS User SVC"/>
2760
2761         <!-- CPU and Compiler dependent -->
2762         <!-- ARMCC -->
2763         <file category="library" condition="CM4_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_IFX.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
2764         <file category="library" condition="CM4_FP_LE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_IFX.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
2765         <!-- GCC -->
2766         <file category="library" condition="CM4_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_IFX.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
2767         <file category="library" condition="CM4_FP_LE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_IFX.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
2768         <!-- IAR -->
2769       </files>
2770     </component>
2771
2772     <!-- CMSIS-RTOS Keil RTX5 component -->
2773     <component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX5" Cversion="5.4.0" Capiversion="1.0.0" condition="RTOS RTX5">
2774       <description>CMSIS-RTOS RTX5 implementation for Cortex-M, SC000, and SC300</description>
2775       <RTE_Components_h>
2776         <!-- the following content goes into file 'RTE_Components.h' -->
2777         #define RTE_CMSIS_RTOS                  /* CMSIS-RTOS */
2778         #define RTE_CMSIS_RTOS_RTX5             /* CMSIS-RTOS Keil RTX5 */
2779       </RTE_Components_h>
2780       <files>
2781         <!-- RTX header file -->
2782         <file category="header" name="CMSIS/RTOS2/RTX/Include1/cmsis_os.h"/>
2783         <!-- RTX compatibility module for API V1 -->
2784         <file category="source" name="CMSIS/RTOS2/RTX/Library/cmsis_os1.c"/>
2785       </files>
2786     </component>
2787
2788     <!-- CMSIS-RTOS2 Keil RTX5 component -->
2789     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cversion="5.4.0" Capiversion="2.1.3" condition="RTOS2 RTX5 Lib">
2790       <description>CMSIS-RTOS2 RTX5 for Cortex-M, SC000, C300 and Armv8-M (Library)</description>
2791       <RTE_Components_h>
2792         <!-- the following content goes into file 'RTE_Components.h' -->
2793         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
2794         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
2795       </RTE_Components_h>
2796       <files>
2797         <!-- RTX documentation -->
2798         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
2799
2800         <!-- RTX header files -->
2801         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
2802
2803         <!-- RTX configuration -->
2804         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.4.0"/>
2805         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
2806
2807         <!-- RTX templates -->
2808         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.0.0" select="CMSIS-RTOS2 'main' function"/>
2809         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
2810         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
2811         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
2812         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
2813         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
2814         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
2815         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
2816         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
2817         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
2818
2819         <!-- RTX library configuration -->
2820         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
2821
2822         <!-- RTX libraries (CPU and Compiler dependent) -->
2823         <!-- ARMCC -->
2824         <file category="library" condition="CM0_LE_ARMCC"         name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM0.lib"    src="CMSIS/RTOS2/RTX/Source"/>
2825         <file category="library" condition="CM3_LE_ARMCC"         name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM3.lib"    src="CMSIS/RTOS2/RTX/Source"/>
2826         <file category="library" condition="CM4_LE_ARMCC"         name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM3.lib"    src="CMSIS/RTOS2/RTX/Source"/>
2827         <file category="library" condition="CM4_FP_LE_ARMCC"      name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM4F.lib"   src="CMSIS/RTOS2/RTX/Source"/>
2828         <file category="library" condition="CM7_LE_ARMCC"         name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM3.lib"    src="CMSIS/RTOS2/RTX/Source"/>
2829         <file category="library" condition="CM7_FP_LE_ARMCC"      name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM4F.lib"   src="CMSIS/RTOS2/RTX/Source"/>
2830         <file category="library" condition="CM23_LE_ARMCC"        name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MB.lib"   src="CMSIS/RTOS2/RTX/Source"/>
2831         <file category="library" condition="CM33_LE_ARMCC"        name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib"   src="CMSIS/RTOS2/RTX/Source"/>
2832         <file category="library" condition="CM33_FP_LE_ARMCC"     name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib"  src="CMSIS/RTOS2/RTX/Source"/>
2833         <file category="library" condition="ARMv8MBL_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MB.lib"   src="CMSIS/RTOS2/RTX/Source"/>
2834         <file category="library" condition="ARMv8MML_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib"   src="CMSIS/RTOS2/RTX/Source"/>
2835         <file category="library" condition="ARMv8MML_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib"  src="CMSIS/RTOS2/RTX/Source"/>
2836         <!-- GCC -->
2837         <file category="library" condition="CM0_LE_GCC"           name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM0.a"   src="CMSIS/RTOS2/RTX/Source"/>
2838         <file category="library" condition="CM3_LE_GCC"           name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a"   src="CMSIS/RTOS2/RTX/Source"/>
2839         <file category="library" condition="CM4_LE_GCC"           name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a"   src="CMSIS/RTOS2/RTX/Source"/>
2840         <file category="library" condition="CM4_FP_LE_GCC"        name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM4F.a"  src="CMSIS/RTOS2/RTX/Source"/>
2841         <file category="library" condition="CM7_LE_GCC"           name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a"   src="CMSIS/RTOS2/RTX/Source"/>
2842         <file category="library" condition="CM7_FP_LE_GCC"        name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM4F.a"  src="CMSIS/RTOS2/RTX/Source"/>
2843         <file category="library" condition="CM23_LE_GCC"          name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MB.a"  src="CMSIS/RTOS2/RTX/Source"/>
2844         <file category="library" condition="CM33_LE_GCC"          name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a"  src="CMSIS/RTOS2/RTX/Source"/>
2845         <file category="library" condition="CM33_FP_LE_GCC"       name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
2846         <file category="library" condition="ARMv8MBL_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MB.a"  src="CMSIS/RTOS2/RTX/Source"/>
2847         <file category="library" condition="ARMv8MML_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a"  src="CMSIS/RTOS2/RTX/Source"/>
2848         <file category="library" condition="ARMv8MML_FP_LE_GCC"   name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
2849         <!-- IAR -->
2850         <file category="library" condition="CM0_LE_IAR"           name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM0.a"      src="CMSIS/RTOS2/RTX/Source"/>
2851         <file category="library" condition="CM3_LE_IAR"           name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM3.a"      src="CMSIS/RTOS2/RTX/Source"/>
2852         <file category="library" condition="CM4_LE_IAR"           name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM3.a"      src="CMSIS/RTOS2/RTX/Source"/>
2853         <file category="library" condition="CM4_FP_LE_IAR"        name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM4F.a"     src="CMSIS/RTOS2/RTX/Source"/>
2854         <file category="library" condition="CM7_LE_IAR"           name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM3.a"      src="CMSIS/RTOS2/RTX/Source"/>
2855         <file category="library" condition="CM7_FP_LE_IAR"        name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM4F.a"     src="CMSIS/RTOS2/RTX/Source"/>
2856       </files>
2857     </component>
2858     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library_NS" Cversion="5.4.0" Capiversion="2.1.3" condition="RTOS2 RTX5 NS">
2859       <description>CMSIS-RTOS2 RTX5 for Armv8-M Non-Secure Domain (Library)</description>
2860       <RTE_Components_h>
2861         <!-- the following content goes into file 'RTE_Components.h' -->
2862         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
2863         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
2864         #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS  /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */
2865       </RTE_Components_h>
2866       <files>
2867         <!-- RTX documentation -->
2868         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
2869
2870         <!-- RTX header files -->
2871         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
2872
2873         <!-- RTX configuration -->
2874         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.4.0"/>
2875         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
2876
2877         <!-- RTX templates -->
2878         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.0.0" select="CMSIS-RTOS2 'main' function"/>
2879         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
2880         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
2881         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
2882         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
2883         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
2884         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
2885         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
2886         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
2887         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
2888
2889         <!-- RTX library configuration -->
2890         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
2891
2892         <!-- RTX libraries (CPU and Compiler dependent) -->
2893         <!-- ARMCC -->
2894         <file category="library" condition="CM23_LE_ARMCC"        name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MBN.lib"   src="CMSIS/RTOS2/RTX/Source"/>
2895         <file category="library" condition="CM33_LE_ARMCC"        name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib"   src="CMSIS/RTOS2/RTX/Source"/>
2896         <file category="library" condition="CM33_FP_LE_ARMCC"     name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib"  src="CMSIS/RTOS2/RTX/Source"/>
2897         <file category="library" condition="ARMv8MBL_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MBN.lib"   src="CMSIS/RTOS2/RTX/Source"/>
2898         <file category="library" condition="ARMv8MML_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib"   src="CMSIS/RTOS2/RTX/Source"/>
2899         <file category="library" condition="ARMv8MML_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib"  src="CMSIS/RTOS2/RTX/Source"/>
2900         <!-- GCC -->
2901         <file category="library" condition="CM23_LE_GCC"          name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MBN.a"  src="CMSIS/RTOS2/RTX/Source"/>
2902         <file category="library" condition="CM33_LE_GCC"          name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a"  src="CMSIS/RTOS2/RTX/Source"/>
2903         <file category="library" condition="CM33_FP_LE_GCC"       name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
2904         <file category="library" condition="ARMv8MBL_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MBN.a"  src="CMSIS/RTOS2/RTX/Source"/>
2905         <file category="library" condition="ARMv8MML_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a"  src="CMSIS/RTOS2/RTX/Source"/>
2906         <file category="library" condition="ARMv8MML_FP_LE_GCC"   name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
2907       </files>
2908     </component>
2909     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cversion="5.4.0" Capiversion="2.1.3" condition="RTOS2 RTX5">
2910       <description>CMSIS-RTOS2 RTX5 for Cortex-M, SC000, C300 and Armv8-M (Source)</description>
2911       <RTE_Components_h>
2912         <!-- the following content goes into file 'RTE_Components.h' -->
2913         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
2914         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
2915         #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
2916       </RTE_Components_h>
2917       <files>
2918         <!-- RTX documentation -->
2919         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
2920
2921         <!-- RTX header files -->
2922         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
2923
2924         <!-- RTX configuration -->
2925         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.4.0"/>
2926         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
2927
2928         <!-- RTX templates -->
2929         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.0.0" select="CMSIS-RTOS2 'main' function"/>
2930         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
2931         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
2932         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
2933         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
2934         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
2935         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
2936         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
2937         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
2938         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
2939
2940         <!-- RTX sources (core) -->
2941         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_kernel.c"/>
2942         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_thread.c"/>
2943         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_delay.c"/>
2944         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_timer.c"/>
2945         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evflags.c"/>
2946         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mutex.c"/>
2947         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_semaphore.c"/>
2948         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_memory.c"/>
2949         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mempool.c"/>
2950         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c"/>
2951         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_system.c"/>
2952         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evr.c"/>
2953         <!-- RTX sources (library configuration) -->
2954         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
2955         <!-- RTX sources (handlers ARMCC) -->
2956         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm0.s"         condition="CM0_ARMCC"/>
2957         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm3.s"         condition="CM3_ARMCC"/>
2958         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm3.s"         condition="CM4_ARMCC"/>
2959         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm4f.s"        condition="CM4_FP_ARMCC"/>
2960         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm3.s"         condition="CM7_ARMCC"/>
2961         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm4f.s"        condition="CM7_FP_ARMCC"/>
2962         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl.s"    condition="CM23_ARMCC"/>
2963         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="CM33_ARMCC"/>
2964         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="CM33_FP_ARMCC"/>
2965         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl.s"    condition="ARMv8MBL_ARMCC"/>
2966         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="ARMv8MML_ARMCC"/>
2967         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="ARMv8MML_FP_ARMCC"/>
2968         <!-- RTX sources (handlers GCC) -->
2969         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm0.S"         condition="CM0_GCC"/>
2970         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm3.S"         condition="CM3_GCC"/>
2971         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm3.S"         condition="CM4_GCC"/>
2972         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm4f.S"        condition="CM4_FP_GCC"/>
2973         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm3.S"         condition="CM7_GCC"/>
2974         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm4f.S"        condition="CM7_FP_GCC"/>
2975         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S"    condition="CM23_GCC"/>
2976         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S"    condition="CM33_GCC"/>
2977         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp.S" condition="CM33_FP_GCC"/>
2978         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S"    condition="ARMv8MBL_GCC"/>
2979         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S"    condition="ARMv8MML_GCC"/>
2980         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp.S" condition="ARMv8MML_FP_GCC"/>
2981         <!-- RTX sources (handlers IAR) -->
2982         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm0.s"         condition="CM0_IAR"/>
2983         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm3.s"         condition="CM3_IAR"/>
2984         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm3.s"         condition="CM4_IAR"/>
2985         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm4f.s"        condition="CM4_FP_IAR"/>
2986         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm3.s"         condition="CM7_IAR"/>
2987         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm4f.s"        condition="CM7_FP_IAR"/>
2988         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s"    condition="CM23_IAR"/>
2989         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="CM33_IAR"/>
2990         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="CM33_FP_IAR"/>
2991         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s"    condition="ARMv8MBL_IAR"/>
2992         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="ARMv8MML_IAR"/>
2993         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="ARMv8MML_FP_IAR"/>
2994         <!-- OS Tick (SysTick) -->
2995         <file category="source" name="CMSIS/RTOS2/Source/os_systick.c"/>
2996       </files>
2997     </component>
2998     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cversion="5.4.0" Capiversion="2.1.3" condition="RTOS2 RTX5 v7-A">
2999       <description>CMSIS-RTOS2 RTX5 for Armv7-A (Source)</description>
3000       <RTE_Components_h>
3001         <!-- the following content goes into file 'RTE_Components.h' -->
3002         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
3003         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
3004         #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
3005       </RTE_Components_h>
3006       <files>
3007         <!-- RTX documentation -->
3008         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
3009
3010         <!-- RTX header files -->
3011         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
3012
3013         <!-- RTX configuration -->
3014         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.4.0"/>
3015         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
3016
3017         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/handlers.c"    version="5.1.0"/>
3018
3019         <!-- RTX templates -->
3020         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.0.0" select="CMSIS-RTOS2 'main' function"/>
3021         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
3022         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
3023         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
3024         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
3025         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
3026         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
3027         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
3028         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
3029         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
3030
3031         <!-- RTX sources (core) -->
3032         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_kernel.c"/>
3033         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_thread.c"/>
3034         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_delay.c"/>
3035         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_timer.c"/>
3036         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evflags.c"/>
3037         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mutex.c"/>
3038         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_semaphore.c"/>
3039         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_memory.c"/>
3040         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mempool.c"/>
3041         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c"/>
3042         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_system.c"/>
3043         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evr.c"/>
3044         <!-- RTX sources (library configuration) -->
3045         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
3046         <!-- RTX sources (handlers ARMCC) -->
3047         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_ca.s"          condition="CA_ARMCC5"/>
3048         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_ca.S"          condition="CA_ARMCC6"/>
3049         <!-- RTX sources (handlers GCC) -->
3050         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_ca.S"          condition="CA_GCC"/>
3051         <!-- RTX sources (handlers IAR) -->
3052         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_ca.s"          condition="CA_IAR"/>
3053       </files>
3054     </component>
3055     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source_NS" Cversion="5.4.0" Capiversion="2.1.3" condition="RTOS2 RTX5 NS">
3056       <description>CMSIS-RTOS2 RTX5 for Armv8-M Non-Secure Domain (Source)</description>
3057       <RTE_Components_h>
3058         <!-- the following content goes into file 'RTE_Components.h' -->
3059         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
3060         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
3061         #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
3062         #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS  /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */
3063       </RTE_Components_h>
3064       <files>
3065         <!-- RTX documentation -->
3066         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
3067
3068         <!-- RTX header files -->
3069         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
3070
3071         <!-- RTX configuration -->
3072         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.4.0"/>
3073         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
3074
3075         <!-- RTX templates -->
3076         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.0.0" select="CMSIS-RTOS2 'main' function"/>
3077         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
3078         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
3079         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
3080         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
3081         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
3082         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
3083         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
3084         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
3085         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
3086
3087         <!-- RTX sources (core) -->
3088         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_kernel.c"/>
3089         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_thread.c"/>
3090         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_delay.c"/>
3091         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_timer.c"/>
3092         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evflags.c"/>
3093         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mutex.c"/>
3094         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_semaphore.c"/>
3095         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_memory.c"/>
3096         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mempool.c"/>
3097         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c"/>
3098         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_system.c"/>
3099         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evr.c"/>
3100         <!-- RTX sources (library configuration) -->
3101         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
3102         <!-- RTX sources (ARMCC handlers) -->
3103         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl_ns.s"    condition="CM23_ARMCC"/>
3104         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="CM33_ARMCC"/>
3105         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="CM33_FP_ARMCC"/>
3106         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl_ns.s"    condition="ARMv8MBL_ARMCC"/>
3107         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="ARMv8MML_ARMCC"/>
3108         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="ARMv8MML_FP_ARMCC"/>
3109         <!-- RTX sources (GCC handlers) -->
3110         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl_ns.S"    condition="CM23_GCC"/>
3111         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_ns.S"    condition="CM33_GCC"/>
3112         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp_ns.S" condition="CM33_FP_GCC"/>
3113         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl_ns.S"    condition="ARMv8MBL_GCC"/>
3114         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_ns.S"    condition="ARMv8MML_GCC"/>
3115         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp_ns.S" condition="ARMv8MML_FP_GCC"/>
3116         <!-- RTX sources (IAR handlers) -->
3117         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl_ns.s"    condition="CM23_IAR"/>
3118         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="CM33_IAR"/>
3119         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="CM33_FP_IAR"/>
3120         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl_ns.s"    condition="ARMv8MBL_IAR"/>
3121         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="ARMv8MML_IAR"/>
3122         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="ARMv8MML_FP_IAR"/>
3123         <!-- OS Tick (SysTick) -->
3124         <file category="source" name="CMSIS/RTOS2/Source/os_systick.c"/>
3125       </files>
3126     </component>
3127
3128   </components>
3129
3130   <boards>
3131     <board name="uVision Simulator" vendor="Keil">
3132       <description>uVision Simulator</description>
3133       <mountedDevice    deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0"/>
3134       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0P"/>
3135       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0P_MPU"/>
3136       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM3"/>
3137       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM4"/>
3138       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM4_FP"/>
3139       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7"/>
3140       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7_SP"/>
3141       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7_DP"/>
3142       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MBL"/>
3143       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML"/>
3144       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML_SP"/>
3145       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML_DP"/>
3146       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM23"/>
3147       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM23_TZ"/>
3148       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33"/>
3149       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_TZ"/>
3150       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_DSP_FP"/>
3151       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_DSP_FP_TZ"/>
3152     </board>
3153
3154     <board name="Fixed Virtual Platform" vendor="ARM">
3155       <description>Fixed Virtual Platform</description>
3156       <mountedDevice    deviceIndex="0" Dvendor="ARM:82" Dname="ARMCA5"/>
3157       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCA7"/>
3158       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCA9"/>
3159     </board>
3160   </boards>
3161
3162   <examples>
3163     <example name="DSP_Lib Class Marks example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_class_marks_example">
3164       <description>DSP_Lib Class Marks example</description>
3165       <board name="uVision Simulator" vendor="Keil"/>
3166       <project>
3167         <environment name="uv" load="arm_class_marks_example.uvprojx"/>
3168       </project>
3169       <attributes>
3170         <component Cclass="CMSIS" Cgroup="CORE"/>
3171         <component Cclass="CMSIS" Cgroup="DSP"/>
3172         <component Cclass="Device" Cgroup="Startup"/>
3173         <category>Getting Started</category>
3174       </attributes>
3175     </example>
3176
3177     <example name="DSP_Lib Convolution example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_convolution_example">
3178       <description>DSP_Lib Convolution example</description>
3179       <board name="uVision Simulator" vendor="Keil"/>
3180       <project>
3181         <environment name="uv" load="arm_convolution_example.uvprojx"/>
3182       </project>
3183       <attributes>
3184         <component Cclass="CMSIS" Cgroup="CORE"/>
3185         <component Cclass="CMSIS" Cgroup="DSP"/>
3186         <component Cclass="Device" Cgroup="Startup"/>
3187         <category>Getting Started</category>
3188       </attributes>
3189     </example>
3190
3191     <example name="DSP_Lib Dotproduct example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_dotproduct_example">
3192       <description>DSP_Lib Dotproduct example</description>
3193       <board name="uVision Simulator" vendor="Keil"/>
3194       <project>
3195         <environment name="uv" load="arm_dotproduct_example.uvprojx"/>
3196       </project>
3197       <attributes>
3198         <component Cclass="CMSIS" Cgroup="CORE"/>
3199         <component Cclass="CMSIS" Cgroup="DSP"/>
3200         <component Cclass="Device" Cgroup="Startup"/>
3201         <category>Getting Started</category>
3202       </attributes>
3203     </example>
3204
3205     <example name="DSP_Lib FFT Bin example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_fft_bin_example">
3206       <description>DSP_Lib FFT Bin example</description>
3207       <board name="uVision Simulator" vendor="Keil"/>
3208       <project>
3209         <environment name="uv" load="arm_fft_bin_example.uvprojx"/>
3210       </project>
3211       <attributes>
3212         <component Cclass="CMSIS" Cgroup="CORE"/>
3213         <component Cclass="CMSIS" Cgroup="DSP"/>
3214         <component Cclass="Device" Cgroup="Startup"/>
3215         <category>Getting Started</category>
3216       </attributes>
3217     </example>
3218
3219     <example name="DSP_Lib FIR example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_fir_example">
3220       <description>DSP_Lib FIR example</description>
3221       <board name="uVision Simulator" vendor="Keil"/>
3222       <project>
3223         <environment name="uv" load="arm_fir_example.uvprojx"/>
3224       </project>
3225       <attributes>
3226         <component Cclass="CMSIS" Cgroup="CORE"/>
3227         <component Cclass="CMSIS" Cgroup="DSP"/>
3228         <component Cclass="Device" Cgroup="Startup"/>
3229         <category>Getting Started</category>
3230       </attributes>
3231     </example>
3232
3233     <example name="DSP_Lib Graphic Equalizer example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example">
3234       <description>DSP_Lib Graphic Equalizer example</description>
3235       <board name="uVision Simulator" vendor="Keil"/>
3236       <project>
3237         <environment name="uv" load="arm_graphic_equalizer_example.uvprojx"/>
3238       </project>
3239       <attributes>
3240         <component Cclass="CMSIS" Cgroup="CORE"/>
3241         <component Cclass="CMSIS" Cgroup="DSP"/>
3242         <component Cclass="Device" Cgroup="Startup"/>
3243         <category>Getting Started</category>
3244       </attributes>
3245     </example>
3246
3247     <example name="DSP_Lib Linear Interpolation example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_linear_interp_example">
3248       <description>DSP_Lib Linear Interpolation example</description>
3249       <board name="uVision Simulator" vendor="Keil"/>
3250       <project>
3251         <environment name="uv" load="arm_linear_interp_example.uvprojx"/>
3252       </project>
3253       <attributes>
3254         <component Cclass="CMSIS" Cgroup="CORE"/>
3255         <component Cclass="CMSIS" Cgroup="DSP"/>
3256         <component Cclass="Device" Cgroup="Startup"/>
3257         <category>Getting Started</category>
3258       </attributes>
3259     </example>
3260
3261     <example name="DSP_Lib Matrix example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_matrix_example">
3262       <description>DSP_Lib Matrix example</description>
3263       <board name="uVision Simulator" vendor="Keil"/>
3264       <project>
3265         <environment name="uv" load="arm_matrix_example.uvprojx"/>
3266       </project>
3267       <attributes>
3268         <component Cclass="CMSIS" Cgroup="CORE"/>
3269         <component Cclass="CMSIS" Cgroup="DSP"/>
3270         <component Cclass="Device" Cgroup="Startup"/>
3271         <category>Getting Started</category>
3272       </attributes>
3273     </example>
3274
3275     <example name="DSP_Lib Signal Convergence example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_signal_converge_example">
3276       <description>DSP_Lib Signal Convergence example</description>
3277       <board name="uVision Simulator" vendor="Keil"/>
3278       <project>
3279         <environment name="uv" load="arm_signal_converge_example.uvprojx"/>
3280       </project>
3281       <attributes>
3282         <component Cclass="CMSIS" Cgroup="CORE"/>
3283         <component Cclass="CMSIS" Cgroup="DSP"/>
3284         <component Cclass="Device" Cgroup="Startup"/>
3285         <category>Getting Started</category>
3286       </attributes>
3287     </example>
3288
3289     <example name="DSP_Lib Sinus/Cosinus example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_sin_cos_example">
3290       <description>DSP_Lib Sinus/Cosinus example</description>
3291       <board name="uVision Simulator" vendor="Keil"/>
3292       <project>
3293         <environment name="uv" load="arm_sin_cos_example.uvprojx"/>
3294       </project>
3295       <attributes>
3296         <component Cclass="CMSIS" Cgroup="CORE"/>
3297         <component Cclass="CMSIS" Cgroup="DSP"/>
3298         <component Cclass="Device" Cgroup="Startup"/>
3299         <category>Getting Started</category>
3300       </attributes>
3301     </example>
3302
3303     <example name="DSP_Lib Variance example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_variance_example">
3304       <description>DSP_Lib Variance example</description>
3305       <board name="uVision Simulator" vendor="Keil"/>
3306       <project>
3307         <environment name="uv" load="arm_variance_example.uvprojx"/>
3308       </project>
3309       <attributes>
3310         <component Cclass="CMSIS" Cgroup="CORE"/>
3311         <component Cclass="CMSIS" Cgroup="DSP"/>
3312         <component Cclass="Device" Cgroup="Startup"/>
3313         <category>Getting Started</category>
3314       </attributes>
3315     </example>
3316
3317     <example name="NN Library CIFAR10" doc="readme.txt" folder="CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10">
3318       <description>Neural Network CIFAR10 example</description>
3319       <board name="uVision Simulator" vendor="Keil"/>
3320       <project>
3321         <environment name="uv" load="arm_nnexamples_cifar10.uvprojx"/>
3322       </project>
3323       <attributes>
3324         <component Cclass="CMSIS" Cgroup="CORE"/>
3325         <component Cclass="CMSIS" Cgroup="DSP"/>
3326         <component Cclass="CMSIS" Cgroup="NN Lib"/>
3327         <component Cclass="Device" Cgroup="Startup"/>
3328         <category>Getting Started</category>
3329       </attributes>
3330     </example>
3331
3332     <example name="NN Library GRU" doc="readme.txt" folder="CMSIS/NN/Examples/ARM/arm_nn_examples/gru">
3333       <description>Neural Network GRU example</description>
3334       <board name="uVision Simulator" vendor="Keil"/>
3335       <project>
3336         <environment name="uv" load="arm_nnexamples_gru.uvprojx"/>
3337       </project>
3338       <attributes>
3339         <component Cclass="CMSIS" Cgroup="CORE"/>
3340         <component Cclass="CMSIS" Cgroup="DSP"/>
3341         <component Cclass="CMSIS" Cgroup="NN Lib"/>
3342         <component Cclass="Device" Cgroup="Startup"/>
3343         <category>Getting Started</category>
3344       </attributes>
3345     </example>
3346
3347     <example name="CMSIS-RTOS2 Blinky" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/Blinky">
3348       <description>CMSIS-RTOS2 Blinky example</description>
3349       <board name="uVision Simulator" vendor="Keil"/>
3350       <project>
3351         <environment name="uv" load="Blinky.uvprojx"/>
3352       </project>
3353       <attributes>
3354         <component Cclass="CMSIS" Cgroup="CORE"/>
3355         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3356         <component Cclass="Device" Cgroup="Startup"/>
3357         <category>Getting Started</category>
3358       </attributes>
3359     </example>
3360
3361     <example name="CMSIS-RTOS2 RTX5 Migration" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/Migration">
3362       <description>CMSIS-RTOS2 mixed API v1 and v2</description>
3363       <board name="uVision Simulator" vendor="Keil"/>
3364       <project>
3365         <environment name="uv" load="Blinky.uvprojx"/>
3366       </project>
3367       <attributes>
3368         <component Cclass="CMSIS" Cgroup="CORE"/>
3369         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3370         <component Cclass="Device" Cgroup="Startup"/>
3371         <category>Getting Started</category>
3372       </attributes>
3373     </example>
3374
3375     <example name="CMSIS-RTOS2 RTX5 Message Queue" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/MsgQueue">
3376       <description>CMSIS-RTOS2 Message Queue Example</description>
3377       <board name="uVision Simulator" vendor="Keil"/>
3378       <project>
3379         <environment name="uv" load="MsqQueue.uvprojx"/>
3380       </project>
3381       <attributes>
3382         <component Cclass="CMSIS" Cgroup="CORE"/>
3383         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3384         <component Cclass="Compiler" Cgroup="EventRecorder"/>
3385         <component Cclass="Device" Cgroup="Startup"/>
3386         <category>Getting Started</category>
3387       </attributes>
3388     </example>
3389
3390     <example name="CMSIS-RTOS2 RTX5 Memory Pool" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/MemPool">
3391       <description>CMSIS-RTOS2 Memory Pool Example</description>
3392       <board name="Fixed Virtual Platform" vendor="ARM"/>
3393       <project>
3394         <environment name="uv" load="MemPool.uvprojx"/>
3395       </project>
3396       <attributes>
3397         <component Cclass="CMSIS" Cgroup="CORE"/>
3398         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3399         <component Cclass="Compiler" Cgroup="EventRecorder"/>
3400         <component Cclass="Device" Cgroup="Startup"/>
3401         <category>Getting Started</category>
3402       </attributes>
3403     </example>
3404
3405     <example name="TrustZone for ARMv8-M No RTOS" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/NoRTOS">
3406       <description>Bare-metal secure/non-secure example without RTOS</description>
3407       <board name="uVision Simulator" vendor="Keil"/>
3408       <project>
3409         <environment name="uv" load="NoRTOS.uvmpw"/>
3410       </project>
3411       <attributes>
3412         <component Cclass="CMSIS" Cgroup="CORE"/>
3413         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3414         <component Cclass="Device" Cgroup="Startup"/>
3415         <category>Getting Started</category>
3416       </attributes>
3417     </example>
3418
3419     <example name="TrustZone for ARMv8-M RTOS"  doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS">
3420       <description>Secure/non-secure RTOS example with thread context management</description>
3421       <board name="uVision Simulator" vendor="Keil"/>
3422       <project>
3423         <environment name="uv" load="RTOS.uvmpw"/>
3424       </project>
3425       <attributes>
3426         <component Cclass="CMSIS" Cgroup="CORE"/>
3427         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3428         <component Cclass="Device" Cgroup="Startup"/>
3429         <category>Getting Started</category>
3430       </attributes>
3431     </example>
3432
3433     <example name="TrustZone for ARMv8-M RTOS Security Tests"  doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults">
3434       <description>Secure/non-secure RTOS example with security test cases and system recovery</description>
3435       <board name="uVision Simulator" vendor="Keil"/>
3436       <project>
3437         <environment name="uv" load="RTOS_Faults.uvmpw"/>
3438       </project>
3439       <attributes>
3440         <component Cclass="CMSIS" Cgroup="CORE"/>
3441         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3442         <component Cclass="Device" Cgroup="Startup"/>
3443         <category>Getting Started</category>
3444       </attributes>
3445     </example>
3446
3447   </examples>
3448
3449 </package>