begriffs open source - cmsis/blob - ARM.CMSIS.pdsc

   1 <?xml version="1.0" encoding="UTF-8"?>
   2
   3 <package schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="PACK.xsd">
   4   <name>CMSIS</name>
   5   <description>CMSIS (Cortex Microcontroller Software Interface Standard)</description>
   6   <vendor>ARM</vendor>
   7   <!-- <license>license.txt</license> -->
   8   <url>http://www.keil.com/pack/</url>
   9
  10   <releases>
  11     <release version="5.5.0-dev0">
  12       Active development ...
  13       Added Cortex-M35P device support.
  14       CMSIS-RTOS2:
  15         - RTX 5.5.0 (see revision history for details)
  16     </release>
  17     <release version="5.4.0" date="2018-08-01">
  18       Aligned pack structure with repository.
  19       The following folders are deprecated:
  20         - CMSIS/Include/
  21         - CMSIS/DSP_Lib/
  22
  23       CMSIS-Core(M): 5.1.2 (see revision history for details)
  24         - Added Cortex-M1 support (beta).
  25       CMSIS-Core(A): 1.1.2 (see revision history for details)
  26       CMSIS-NN: 1.1.0
  27         - Added new math functions.
  28       CMSIS-RTOS2:
  29         - API 2.1.3 (see revision history for details)
  30         - RTX 5.4.0 (see revision history for details)
  31           * Updated exception handling on Cortex-A
  32       CMSIS-Driver:
  33         - Flash Driver API V2.2.0
  34       Utilities:
  35         - SVDConv 3.3.21
  36         - PackChk 1.3.71
  37     </release>
  38     <release version="5.3.0" date="2018-02-22">
  39       Updated Arm company brand.
  40       CMSIS-Core(M): 5.1.1 (see revision history for details)
  41       CMSIS-Core(A): 1.1.1 (see revision history for details)
  42       CMSIS-DAP: 2.0.0 (see revision history for details)
  43       CMSIS-NN: 1.0.0
  44         - Initial contribution of the bare metal Neural Network Library.
  45       CMSIS-RTOS2:
  46         - RTX 5.3.0 (see revision history for details)
  47         - OS Tick API 1.0.1
  48     </release>
  49     <release version="5.2.0" date="2017-11-16">
  50       CMSIS-Core(M): 5.1.0 (see revision history for details)
  51         - Added MPU Functions for ARMv8-M for Cortex-M23/M33.
  52         - Added compiler_iccarm.h to replace compiler_iar.h shipped with the compiler.
  53       CMSIS-Core(A): 1.1.0 (see revision history for details)
  54         - Added compiler_iccarm.h.
  55         - Added additional access functions for physical timer.
  56       CMSIS-DAP: 1.2.0 (see revision history for details)
  57       CMSIS-DSP: 1.5.2 (see revision history for details)
  58       CMSIS-Driver: 2.6.0 (see revision history for details)
  59         - CAN Driver API V1.2.0
  60         - NAND Driver API V2.3.0
  61       CMSIS-RTOS:
  62         - RTX: added variant for Infineon XMC4 series affected by PMU_CM.001 errata.
  63       CMSIS-RTOS2:
  64         - API 2.1.2 (see revision history for details)
  65         - RTX 5.2.3 (see revision history for details)
  66       Devices:
  67         - Added GCC startup and linker script for Cortex-A9.
  68         - Added device ARMCM0plus_MPU for Cortex-M0+ with MPU.
  69         - Added IAR startup code for Cortex-A9
  70     </release>
  71     <release version="5.1.1" date="2017-09-19">
  72       CMSIS-RTOS2:
  73       - RTX 5.2.1 (see revision history for details)
  74     </release>
  75     <release version="5.1.0" date="2017-08-04">
  76       CMSIS-Core(M): 5.0.2 (see revision history for details)
  77       - Changed Version Control macros to be core agnostic.
  78       - Added MPU Functions for ARMv7-M for Cortex-M0+/M3/M4/M7.
  79       CMSIS-Core(A): 1.0.0 (see revision history for details)
  80       - Initial release
  81       - IRQ Controller API 1.0.0
  82       CMSIS-Driver: 2.05 (see revision history for details)
  83       - All typedefs related to status have been made volatile.
  84       CMSIS-RTOS2:
  85       - API 2.1.1 (see revision history for details)
  86       - RTX 5.2.0 (see revision history for details)
  87       - OS Tick API 1.0.0
  88       CMSIS-DSP: 1.5.2 (see revision history for details)
  89       - Fixed GNU Compiler specific diagnostics.
  90       CMSIS-Pack: 1.5.0 (see revision history for details)
  91       - added System Description File (*.SDF) Format
  92       CMSIS-Zone: 0.0.1 (Preview)
  93       - Initial specification draft
  94     </release>
  95     <release version="5.0.1" date="2017-02-03">
  96       Package Description:
  97       - added taxonomy for Cclass RTOS
  98       CMSIS-RTOS2:
  99       - API 2.1   (see revision history for details)
 100       - RTX 5.1.0 (see revision history for details)
 101       CMSIS-Core: 5.0.1 (see revision history for details)
 102       - Added __PACKED_STRUCT macro
 103       - Added uVisior support
 104       - Updated cmsis_armcc.h: corrected macro __ARM_ARCH_6M__
 105       - Updated template for secure main function (main_s.c)
 106       - Updated template for Context Management for ARMv8-M TrustZone (tz_context.c)
 107       CMSIS-DSP: 1.5.1 (see revision history for details)
 108       - added ARMv8M DSP libraries.
 109       CMSIS-Pack:1.4.9 (see revision history for details)
 110       - added Pack Index File specification and schema file
 111     </release>
 112     <release version="5.0.0" date="2016-11-11">
 113       Changed open source license to Apache 2.0
 114       CMSIS_Core:
 115        - Added support for Cortex-M23 and Cortex-M33.
 116        - Added ARMv8-M device configurations for mainline and baseline.
 117        - Added CMSE support and thread context management for TrustZone for ARMv8-M
 118        - Added cmsis_compiler.h to unify compiler behaviour.
 119        - Updated function SCB_EnableICache (for Cortex-M7).
 120        - Added functions: NVIC_GetEnableIRQ, SCB_GetFPUType
 121       CMSIS-RTOS:
 122         - bug fix in RTX 4.82 (see revision history for details)
 123       CMSIS-RTOS2:
 124         - new API including compatibility layer to CMSIS-RTOS
 125         - reference implementation based on RTX5
 126         - supports all Cortex-M variants including TrustZone for ARMv8-M
 127       CMSIS-SVD:
 128        - reworked SVD format documentation
 129        - removed SVD file database documentation as SVD files are distributed in packs
 130        - updated SVDConv for Win32 and Linux
 131       CMSIS-DSP:
 132        - Moved DSP libraries from CMSIS/DSP/Lib to CMSIS/Lib.
 133        - Added DSP libraries build projects to CMSIS pack.
 134     </release>
 135     <release version="4.5.0" date="2015-10-28">
 136       - CMSIS-Core     4.30.0  (see revision history for details)
 137       - CMSIS-DAP      1.1.0   (unchanged)
 138       - CMSIS-Driver   2.04.0  (see revision history for details)
 139       - CMSIS-DSP      1.4.7   (no source code change [still labeled 1.4.5], see revision history for details)
 140       - CMSIS-Pack     1.4.1   (see revision history for details)
 141       - CMSIS-RTOS     4.80.0  Restored time delay parameter 'millisec' old behavior (prior V4.79) for software compatibility. (see revision history for details)
 142       - CMSIS-SVD      1.3.1   (see revision history for details)
 143     </release>
 144     <release version="4.4.0" date="2015-09-11">
 145       - CMSIS-Core     4.20   (see revision history for details)
 146       - CMSIS-DSP      1.4.6  (no source code change [still labeled 1.4.5], see revision history for details)
 147       - CMSIS-Pack     1.4.0  (adding memory attributes, algorithm style)
 148       - CMSIS-Driver   2.03.0 (adding CAN [Controller Area Network] API)
 149       - CMSIS-RTOS
 150         -- API         1.02   (unchanged)
 151         -- RTX         4.79   (see revision history for details)
 152       - CMSIS-SVD      1.3.0  (see revision history for details)
 153       - CMSIS-DAP      1.1.0  (extended with SWO support)
 154     </release>
 155     <release version="4.3.0" date="2015-03-20">
 156       - CMSIS-Core     4.10   (Cortex-M7 extended Cache Maintenance functions)
 157       - CMSIS-DSP      1.4.5  (see revision history for details)
 158       - CMSIS-Driver   2.02   (adding SAI (Serial Audio Interface) API)
 159       - CMSIS-Pack     1.3.3  (Semantic Versioning, Generator extensions)
 160       - CMSIS-RTOS
 161         -- API         1.02   (unchanged)
 162         -- RTX         4.78   (see revision history for details)
 163       - CMSIS-SVD      1.2    (unchanged)
 164     </release>
 165     <release version="4.2.0" date="2014-09-24">
 166       Adding Cortex-M7 support
 167       - CMSIS-Core     4.00  (Cortex-M7 support, corrected C++ include guards in core header files)
 168       - CMSIS-DSP      1.4.4 (Cortex-M7 support and corrected out of bound issues)
 169       - CMSIS-Pack     1.3.1 (Cortex-M7 updates, clarification, corrected batch files in Tutorial)
 170       - CMSIS-SVD      1.2   (Cortex-M7 extensions)
 171       - CMSIS-RTOS RTX 4.75  (see revision history for details)
 172     </release>
 173     <release version="4.1.1" date="2014-06-30">
 174       - fixed conditions preventing the inclusion of the DSP library in projects for Infineon XMC4000 series devices
 175     </release>
 176     <release version="4.1.0" date="2014-06-12">
 177       - CMSIS-Driver   2.02  (incompatible update)
 178       - CMSIS-Pack     1.3   (see revision history for details)
 179       - CMSIS-DSP      1.4.2 (unchanged)
 180       - CMSIS-Core     3.30  (unchanged)
 181       - CMSIS-RTOS RTX 4.74  (unchanged)
 182       - CMSIS-RTOS API 1.02  (unchanged)
 183       - CMSIS-SVD      1.10  (unchanged)
 184       PACK:
 185       - removed G++ specific files from PACK
 186       - added Component Startup variant "C Startup"
 187       - added Pack Checking Utility
 188       - updated conditions to reflect tool-chain dependency
 189       - added Taxonomy for Graphics
 190       - updated Taxonomy for unified drivers from "Drivers" to "CMSIS Drivers"
 191     </release>
 192     <release version="4.0.0">
 193       - CMSIS-Driver   2.00  Preliminary (incompatible update)
 194       - CMSIS-Pack     1.1   Preliminary
 195       - CMSIS-DSP      1.4.2 (see revision history for details)
 196       - CMSIS-Core     3.30  (see revision history for details)
 197       - CMSIS-RTOS RTX 4.74  (see revision history for details)
 198       - CMSIS-RTOS API 1.02  (unchanged)
 199       - CMSIS-SVD      1.10  (unchanged)
 200     </release>
 201     <release version="3.20.4">
 202       - CMSIS-RTOS 4.74 (see revision history for details)
 203       - PACK Extensions (Boards, Device Features, Flash Programming, Generators, Configuration Wizard). Schema version 1.1.
 204     </release>
 205     <release version="3.20.3">
 206       - CMSIS-Driver API Version 1.10 ARM prefix added (incompatible change)
 207       - CMSIS-RTOS 4.73 (see revision history for details)
 208     </release>
 209     <release version="3.20.2">
 210       - CMSIS-Pack documentation has been added
 211       - CMSIS-Drivers header and documentation have been added to PACK
 212       - CMSIS-CORE, CMSIS-DSP, CMSIS-RTOS API and CMSIS-SVD remain unchanged
 213     </release>
 214     <release version="3.20.1">
 215       - CMSIS-RTOS Keil RTX V4.72 has been added to PACK
 216       - CMSIS-CORE, CMSIS-DSP, CMSIS-RTOS API and CMSIS-SVD remain unchanged
 217     </release>
 218     <release version="3.20.0">
 219       The software portions that are deployed in the application program are now under a BSD license which allows usage
 220       of CMSIS components in any commercial or open source projects.  The Pack Description file Arm.CMSIS.pdsc describes the use cases
 221       The individual components have been update as listed below:
 222       - CMSIS-CORE adds functions for setting breakpoints, supports the latest GCC Compiler, and contains several corrections.
 223       - CMSIS-DSP library is optimized for more performance and contains several bug fixes.
 224       - CMSIS-RTOS API is extended with capabilities for short timeouts, Kernel initialization, and prepared for a C++ interface.
 225       - CMSIS-SVD is unchanged.
 226     </release>
 227   </releases>
 228
 229   <taxonomy>
 230     <description Cclass="Board Support">Generic Interfaces for Evaluation and Development Boards</description>
 231     <description Cclass="CMSIS" doc="CMSIS/Documentation/General/html/index.html">Cortex Microcontroller Software Interface Components</description>
 232     <description Cclass="Device" doc="CMSIS/Documentation/Core/html/index.html">Startup, System Setup</description>
 233     <description Cclass="CMSIS Driver" doc="CMSIS/Documentation/Driver/html/index.html">Unified Device Drivers compliant to CMSIS-Driver Specifications</description>
 234     <description Cclass="File System">File Drive Support and File System</description>
 235     <description Cclass="Graphics">Graphical User Interface</description>
 236     <description Cclass="Network">Network Stack using Internet Protocols</description>
 237     <description Cclass="USB">Universal Serial Bus Stack</description>
 238     <description Cclass="Compiler">Compiler Software Extensions</description>
 239     <description Cclass="RTOS">Real-time Operating System</description>
 240   </taxonomy>
 241
 242   <devices>
 243     <!-- ******************************  Cortex-M0  ****************************** -->
 244     <family Dfamily="ARM Cortex M0" Dvendor="ARM:82">
 245       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/index.html" title="Cortex-M0 Device Generic Users Guide"/>
 246       <description>
 247 The Cortex-M0 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 248 - simple, easy-to-use programmers model
 249 - highly efficient ultra-low power operation
 250 - excellent code density
 251 - deterministic, high-performance interrupt handling
 252 - upward compatibility with the rest of the Cortex-M processor family.
 253       </description>
 254       <!-- debug svd="Device/ARM/SVD/ARMCM0.svd"/ SVD files do not contain any peripheral -->
 255       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 256       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 257       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 258
 259       <device Dname="ARMCM0">
 260         <processor Dcore="Cortex-M0" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
 261         <compile header="Device/ARM/ARMCM0/Include/ARMCM0.h" define="ARMCM0"/>
 262       </device>
 263     </family>
 264
 265     <!-- ******************************  Cortex-M0P  ****************************** -->
 266     <family Dfamily="ARM Cortex M0 plus" Dvendor="ARM:82">
 267       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0662b/index.html" title="Cortex-M0+ Device Generic Users Guide"/>
 268       <description>
 269 The Cortex-M0+ processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 270 - simple, easy-to-use programmers model
 271 - highly efficient ultra-low power operation
 272 - excellent code density
 273 - deterministic, high-performance interrupt handling
 274 - upward compatibility with the rest of the Cortex-M processor family.
 275       </description>
 276       <!-- debug svd="Device/ARM/SVD/ARMCM0P.svd"/ SVD files do not contain any peripheral -->
 277       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 278       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 279       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 280
 281       <device Dname="ARMCM0P">
 282         <processor Dcore="Cortex-M0+" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
 283         <compile header="Device/ARM/ARMCM0plus/Include/ARMCM0plus.h" define="ARMCM0P"/>
 284       </device>
 285
 286       <device Dname="ARMCM0P_MPU">
 287         <processor Dcore="Cortex-M0+" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 288         <compile header="Device/ARM/ARMCM0plus/Include/ARMCM0plus_MPU.h" define="ARMCM0P_MPU"/>
 289       </device>
 290     </family>
 291
 292     <!-- ******************************  Cortex-M1  ****************************** -->
 293     <family Dfamily="ARM Cortex M1" Dvendor="ARM:82">
 294       <!--book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/index.html" title="Cortex-M1 Device Generic Users Guide"/-->
 295       <description>
 296 The ARM Cortex-M1 FPGA processor is intended for deeply embedded applications that require a small processor integrated into an FPGA.
 297 The ARM Cortex-M1 processor implements the ARMv6-M architecture profile.
 298       </description>
 299       <!-- debug svd="Device/ARM/SVD/ARMCM0.svd"/ SVD files do not contain any peripheral -->
 300       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 301       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 302       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 303
 304       <device Dname="ARMCM1">
 305         <processor Dcore="Cortex-M1" DcoreVersion="r1p0" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
 306         <compile header="Device/ARM/ARMCM1/Include/ARMCM1.h" define="ARMCM1"/>
 307       </device>
 308     </family>
 309
 310     <!-- ******************************  Cortex-M3  ****************************** -->
 311     <family Dfamily="ARM Cortex M3" Dvendor="ARM:82">
 312       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/index.html" title="Cortex-M3 Device Generic Users Guide"/>
 313       <description>
 314 The Cortex-M3 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 315 - simple, easy-to-use programmers model
 316 - highly efficient ultra-low power operation
 317 - excellent code density
 318 - deterministic, high-performance interrupt handling
 319 - upward compatibility with the rest of the Cortex-M processor family.
 320       </description>
 321       <!-- debug svd="Device/ARM/SVD/ARMCM3.svd"/ SVD files do not contain any peripheral -->
 322       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 323       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 324       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 325
 326       <device Dname="ARMCM3">
 327         <processor Dcore="Cortex-M3" DcoreVersion="r2p1" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 328         <compile header="Device/ARM/ARMCM3/Include/ARMCM3.h" define="ARMCM3"/>
 329       </device>
 330     </family>
 331
 332     <!-- ******************************  Cortex-M4  ****************************** -->
 333     <family Dfamily="ARM Cortex M4" Dvendor="ARM:82">
 334       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/index.html" title="Cortex-M4 Device Generic Users Guide"/>
 335       <description>
 336 The Cortex-M4 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 337 - simple, easy-to-use programmers model
 338 - highly efficient ultra-low power operation
 339 - excellent code density
 340 - deterministic, high-performance interrupt handling
 341 - upward compatibility with the rest of the Cortex-M processor family.
 342       </description>
 343       <!-- debug svd="Device/ARM/SVD/ARMCM4.svd"/ SVD files do not contain any peripheral -->
 344       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 345       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 346       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 347
 348       <device Dname="ARMCM4">
 349         <processor Dcore="Cortex-M4" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 350         <compile header="Device/ARM/ARMCM4/Include/ARMCM4.h"    define="ARMCM4"/>
 351       </device>
 352
 353       <device Dname="ARMCM4_FP">
 354         <processor Dcore="Cortex-M4" DcoreVersion="r0p1" Dfpu="SP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 355         <compile header="Device/ARM/ARMCM4/Include/ARMCM4_FP.h" define="ARMCM4_FP"/>
 356       </device>
 357     </family>
 358
 359     <!-- ******************************  Cortex-M7  ****************************** -->
 360     <family Dfamily="ARM Cortex M7" Dvendor="ARM:82">
 361       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.dui0646b/index.html" title="Cortex-M7 Device Generic Users Guide"/>
 362       <description>
 363 The Cortex-M7 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:
 364 - simple, easy-to-use programmers model
 365 - highly efficient ultra-low power operation
 366 - excellent code density
 367 - deterministic, high-performance interrupt handling
 368 - upward compatibility with the rest of the Cortex-M processor family.
 369       </description>
 370       <!-- debug svd="Device/ARM/SVD/ARMCM7.svd"/ SVD files do not contain any peripheral -->
 371       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 372       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 373       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 374
 375       <device Dname="ARMCM7">
 376         <processor Dcore="Cortex-M7" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 377         <compile header="Device/ARM/ARMCM7/Include/ARMCM7.h" define="ARMCM7"/>
 378       </device>
 379
 380       <device Dname="ARMCM7_SP">
 381         <processor Dcore="Cortex-M7" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 382         <compile header="Device/ARM/ARMCM7/Include/ARMCM7_SP.h" define="ARMCM7_SP"/>
 383       </device>
 384
 385       <device Dname="ARMCM7_DP">
 386         <processor Dcore="Cortex-M7" DcoreVersion="r0p0" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
 387         <compile header="Device/ARM/ARMCM7/Include/ARMCM7_DP.h" define="ARMCM7_DP"/>
 388       </device>
 389     </family>
 390
 391     <!-- ******************************  Cortex-M23  ********************** -->
 392     <family Dfamily="ARM Cortex M23" Dvendor="ARM:82">
 393       <!--book name="Device/ARM/Documents/??_dgug.pdf"       title="?? Device Generic Users Guide"/-->
 394       <description>
 395 The Arm Cortex-M23 is based on the Armv8-M baseline architecture.
 396 It is the smallest and most energy efficient Arm processor with Arm TrustZone technology.
 397 Cortex-M23 is the ideal processor for constrained embedded applications requiring efficient security.
 398       </description>
 399       <!-- debug svd="Device/ARM/SVD/ARMCM23.svd"/ SVD files do not contain any peripheral -->
 400       <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
 401       <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
 402       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 403       <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
 404       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 405
 406       <device Dname="ARMCM23">
 407         <processor Dcore="Cortex-M23" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
 408         <compile header="Device/ARM/ARMCM23/Include/ARMCM23.h" define="ARMCM23"/>
 409       </device>
 410
 411       <device Dname="ARMCM23_TZ">
 412         <processor Dcore="Cortex-M23" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 413         <compile header="Device/ARM/ARMCM23/Include/ARMCM23_TZ.h" define="ARMCM23_TZ"/>
 414       </device>
 415     </family>
 416
 417     <!-- ******************************  Cortex-M33  ****************************** -->
 418     <family Dfamily="ARM Cortex M33" Dvendor="ARM:82">
 419       <!--book name="Device/ARM/Documents/??_dgug.pdf"       title="?? Device Generic Users Guide"/-->
 420       <description>
 421 The Arm Cortex-M33 is the most configurable of all Cortex-M processors. It is a full featured microcontroller
 422 class processor based on the Armv8-M mainline architecture with Arm TrustZone security.
 423       </description>
 424       <!-- debug svd="Device/ARM/SVD/ARMCM33.svd"/ SVD files do not contain any peripheral -->
 425       <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
 426       <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
 427       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 428       <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
 429       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"          default="1"/-->
 430
 431       <device Dname="ARMCM33">
 432         <processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
 433         <description>
 434           no DSP Instructions, no Floating Point Unit, no TrustZone
 435         </description>
 436         <compile header="Device/ARM/ARMCM33/Include/ARMCM33.h" define="ARMCM33"/>
 437       </device>
 438
 439       <device Dname="ARMCM33_TZ">
 440         <processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 441         <description>
 442           no DSP Instructions, no Floating Point Unit, TrustZone
 443         </description>
 444         <compile header="Device/ARM/ARMCM33/Include/ARMCM33_TZ.h" define="ARMCM33_TZ"/>
 445       </device>
 446
 447       <device Dname="ARMCM33_DSP_FP">
 448         <processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
 449         <description>
 450           DSP Instructions, Single Precision Floating Point Unit, no TrustZone
 451         </description>
 452         <compile header="Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP.h" define="ARMCM33_DSP_FP"/>
 453       </device>
 454
 455       <device Dname="ARMCM33_DSP_FP_TZ">
 456         <processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 457         <description>
 458           DSP Instructions, Single Precision Floating Point Unit, TrustZone
 459         </description>
 460         <compile header="Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h" define="ARMCM33_DSP_FP_TZ"/>
 461       </device>
 462     </family>
 463
 464     <!-- ******************************  Cortex-M35P  ****************************** -->
 465     <family Dfamily="ARM Cortex M35P" Dvendor="ARM:82">
 466       <!--book name="Device/ARM/Documents/??_dgug.pdf"       title="?? Device Generic Users Guide"/-->
 467       <description>
 468 The Arm Cortex-M35P is the most configurable of all Cortex-M processors. It is a full featured microcontroller
 469 class processor based on the Armv8-M mainline architecture with Arm TrustZone security designed for a broad range of secure embedded applications.
 470       </description>
 471
 472       <!-- debug svd="Device/ARM/SVD/ARMCM35P.svd"/ SVD files do not contain any peripheral -->
 473       <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
 474       <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
 475       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 476       <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
 477       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"          default="1"/-->
 478
 479       <device Dname="ARMCM35P">
 480         <processor Dcore="Cortex-M35P" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
 481         <description>
 482           no DSP Instructions, no Floating Point Unit, no TrustZone
 483         </description>
 484         <compile header="Device/ARM/ARMCM35P/Include/ARMCM35P.h" define="ARMCM35P"/>
 485       </device>
 486
 487       <device Dname="ARMCM35P_TZ">
 488         <processor Dcore="Cortex-M35P" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 489         <description>
 490           no DSP Instructions, no Floating Point Unit, TrustZone
 491         </description>
 492         <compile header="Device/ARM/ARMCM35P/Include/ARMCM35P_TZ.h" define="ARMCM35P_TZ"/>
 493       </device>
 494
 495       <device Dname="ARMCM35P_DSP_FP">
 496         <processor Dcore="Cortex-M35P" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
 497         <description>
 498           DSP Instructions, Single Precision Floating Point Unit, no TrustZone
 499         </description>
 500         <compile header="Device/ARM/ARMCM35P/Include/ARMCM35P_DSP_FP.h" define="ARMCM35P_DSP_FP"/>
 501       </device>
 502
 503       <device Dname="ARMCM35P_DSP_FP_TZ">
 504         <processor Dcore="Cortex-M35P" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 505         <description>
 506           DSP Instructions, Single Precision Floating Point Unit, TrustZone
 507         </description>
 508         <compile header="Device/ARM/ARMCM35P/Include/ARMCM35P_DSP_FP_TZ.h" define="ARMCM35P_DSP_FP_TZ"/>
 509       </device>
 510     </family>
 511
 512     <!-- ******************************  ARMSC000  ****************************** -->
 513     <family Dfamily="ARM SC000" Dvendor="ARM:82">
 514       <description>
 515 The Arm SC000 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including:
 516 - simple, easy-to-use programmers model
 517 - highly efficient ultra-low power operation
 518 - excellent code density
 519 - deterministic, high-performance interrupt handling
 520       </description>
 521       <!-- debug svd="Device/ARM/SVD/ARMSC000.svd"/ SVD files do not contain any peripheral -->
 522       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 523       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 524       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 525
 526       <device Dname="ARMSC000">
 527         <processor Dcore="SC000" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
 528         <compile header="Device/ARM/ARMSC000/Include/ARMSC000.h" define="ARMSC000"/>
 529       </device>
 530     </family>
 531
 532     <!-- ******************************  ARMSC300  ****************************** -->
 533     <family Dfamily="ARM SC300" Dvendor="ARM:82">
 534       <description>
 535 The ARM SC300 processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including:
 536 - simple, easy-to-use programmers model
 537 - highly efficient ultra-low power operation
 538 - excellent code density
 539 - deterministic, high-performance interrupt handling
 540       </description>
 541       <!-- debug svd="Device/ARM/SVD/ARMSC300.svd"/ SVD files do not contain any peripheral -->
 542       <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
 543       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 544       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 545
 546       <device Dname="ARMSC300">
 547         <processor Dcore="SC300" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
 548         <compile header="Device/ARM/ARMSC300/Include/ARMSC300.h" define="ARMSC300"/>
 549       </device>
 550     </family>
 551
 552     <!-- ******************************  ARMv8-M Baseline  ********************** -->
 553     <family Dfamily="ARMv8-M Baseline" Dvendor="ARM:82">
 554       <!--book name="Device/ARM/Documents/ARMv8MBL_dgug.pdf"       title="ARMv8MBL Device Generic Users Guide"/-->
 555       <description>
 556 Armv8-M Baseline based device with TrustZone
 557       </description>
 558       <!-- debug svd="Device/ARM/SVD/ARMv8MBL.svd"/ SVD files do not contain any peripheral -->
 559       <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
 560       <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
 561       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 562       <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
 563       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 564
 565       <device Dname="ARMv8MBL">
 566         <processor Dcore="ARMV8MBL" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 567         <compile header="Device/ARM/ARMv8MBL/Include/ARMv8MBL.h" define="ARMv8MBL"/>
 568       </device>
 569     </family>
 570
 571     <!-- ******************************  ARMv8-M Mainline  ****************************** -->
 572     <family Dfamily="ARMv8-M Mainline" Dvendor="ARM:82">
 573       <!--book name="Device/ARM/Documents/ARMv8MML_dgug.pdf"       title="ARMv8MML Device Generic Users Guide"/-->
 574       <description>
 575 Armv8-M Mainline based device with TrustZone
 576       </description>
 577       <!-- debug svd="Device/ARM/SVD/ARMv8MML.svd"/ SVD files do not contain any peripheral -->
 578       <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
 579       <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
 580       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
 581       <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
 582       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 583
 584       <device Dname="ARMv8MML">
 585         <processor Dcore="ARMV8MML" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 586         <description>
 587           no DSP Instructions, no Floating Point Unit, TrustZone
 588         </description>
 589         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML.h" define="ARMv8MML"/>
 590       </device>
 591
 592       <device Dname="ARMv8MML_DSP">
 593         <processor Dcore="ARMV8MML" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 594         <description>
 595           DSP Instructions, no Floating Point Unit, TrustZone
 596         </description>
 597         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DSP.h" define="ARMv8MML_DSP"/>
 598       </device>
 599
 600       <device Dname="ARMv8MML_SP">
 601         <processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 602         <description>
 603           no DSP Instructions, Single Precision Floating Point Unit, TrustZone
 604         </description>
 605         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_SP.h" define="ARMv8MML_SP"/>
 606       </device>
 607
 608       <device Dname="ARMv8MML_DSP_SP">
 609         <processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 610         <description>
 611           DSP Instructions, Single Precision Floating Point Unit, TrustZone
 612         </description>
 613         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_SP.h" define="ARMv8MML_DSP_SP"/>
 614       </device>
 615
 616       <device Dname="ARMv8MML_DP">
 617         <processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="DP_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 618         <description>
 619           no DSP Instructions, Double Precision Floating Point Unit, TrustZone
 620         </description>
 621         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DP.h" define="ARMv8MML_DP"/>
 622       </device>
 623
 624       <device Dname="ARMv8MML_DSP_DP">
 625         <processor Dcore="ARMV8MML" DcoreVersion="r0p1" Dfpu="DP_FPU" Dmpu="MPU" Ddsp="DSP" Dtz="TZ" Dendian="Configurable" Dclock="10000000"/>
 626         <description>
 627           DSP Instructions, Double Precision Floating Point Unit, TrustZone
 628         </description>
 629         <compile header="Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h" define="ARMv8MML_DSP_DP"/>
 630       </device>
 631     </family>
 632
 633     <!-- ******************************  Cortex-A5  ****************************** -->
 634     <family Dfamily="ARM Cortex A5" Dvendor="ARM:82">
 635       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0433c/index.html" title="Cortex-A5 Technical Reference Manual"/>
 636       <description>
 637 The Arm Cortex-A5 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full
 638 virtual memory capabilities. The Cortex-A5 processor implements the Armv7-A architecture profile and can execute 32-bit
 639 Arm instructions and 16-bit and 32-bit Thumb instructions. The Cortex-A5 is the smallest member of the Cortex-A processor family.
 640       </description>
 641
 642       <memory id="IROM1"                                start="0x80000000" size="0x00200000" startup="1" default="1"/>
 643       <memory id="IRAM1"                                start="0x80200000" size="0x00200000" init   ="0" default="1"/>
 644
 645       <device Dname="ARMCA5">
 646         <processor Dcore="Cortex-A5" DcoreVersion="r0p1" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable"/>
 647         <compile header="Device/ARM/ARMCA5/Include/ARMCA5.h" define="ARMCA5"/>
 648       </device>
 649     </family>
 650
 651     <!-- ******************************  Cortex-A7  ****************************** -->
 652     <family Dfamily="ARM Cortex A7" Dvendor="ARM:82">
 653       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/index.html" title="Cortex-A7 MPCore Technical Reference Manual"/>
 654       <description>
 655 The Cortex-A7 MPCore processor is a high-performance, low-power processor that implements the Armv7-A architecture.
 656 The Cortex-A7 MPCore processor has one to four processors in a single multiprocessor device with a L1 cache subsystem,
 657 an optional integrated GIC, and an optional L2 cache controller.
 658       </description>
 659
 660       <memory id="IROM1"                                start="0x80000000" size="0x00200000" startup="1" default="1"/>
 661       <memory id="IRAM1"                                start="0x80200000" size="0x00200000" init   ="0" default="1"/>
 662
 663       <device Dname="ARMCA7">
 664         <processor Dcore="Cortex-A7" DcoreVersion="r0p5" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable"/>
 665         <compile header="Device/ARM/ARMCA7/Include/ARMCA7.h" define="ARMCA7"/>
 666       </device>
 667     </family>
 668
 669     <!-- ******************************  Cortex-A9  ****************************** -->
 670     <family Dfamily="ARM Cortex A9" Dvendor="ARM:82">
 671       <book name="http://infocenter.arm.com/help/topic/com.arm.doc.100511_0401_10_en/index.html" title="Cortex-A9 Technical Reference Manual"/>
 672       <description>
 673 The Cortex-A9 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full virtual memory capabilities.
 674 The Cortex-A9 processor implements the Armv7-A architecture and runs 32-bit Arm instructions, 16-bit and 32-bit Thumb instructions,
 675 and 8-bit Java bytecodes in Jazelle state.
 676       </description>
 677
 678       <memory id="IROM1"                                start="0x80000000" size="0x00200000" startup="1" default="1"/>
 679       <memory id="IRAM1"                                start="0x80200000" size="0x00200000" init   ="0" default="1"/>
 680
 681       <device Dname="ARMCA9">
 682         <processor Dcore="Cortex-A9" DcoreVersion="r4p1" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable"/>
 683         <compile header="Device/ARM/ARMCA9/Include/ARMCA9.h" define="ARMCA9"/>
 684       </device>
 685     </family>
 686   </devices>
 687
 688
 689   <apis>
 690     <!-- CMSIS Device API -->
 691     <api Cclass="Device" Cgroup="IRQ Controller" Capiversion="1.0.0" exclusive="1">
 692       <description>Device interrupt controller interface</description>
 693       <files>
 694         <file category="header" name="CMSIS/Core_A/Include/irq_ctrl.h"/>
 695       </files>
 696     </api>
 697     <api Cclass="Device" Cgroup="OS Tick" Capiversion="1.0.1" exclusive="1">
 698       <description>RTOS Kernel system tick timer interface</description>
 699       <files>
 700         <file category="header" name="CMSIS/RTOS2/Include/os_tick.h"/>
 701       </files>
 702     </api>
 703     <!-- CMSIS-RTOS API -->
 704     <api Cclass="CMSIS" Cgroup="RTOS" Capiversion="1.0.0" exclusive="1">
 705       <description>CMSIS-RTOS API for Cortex-M, SC000, and SC300</description>
 706       <files>
 707         <file category="doc" name="CMSIS/Documentation/RTOS/html/index.html"/>
 708       </files>
 709     </api>
 710     <api Cclass="CMSIS" Cgroup="RTOS2" Capiversion="2.1.3" exclusive="1">
 711       <description>CMSIS-RTOS API for Cortex-M, SC000, and SC300</description>
 712       <files>
 713         <file category="doc" name="CMSIS/Documentation/RTOS2/html/index.html"/>
 714         <file category="header" name="CMSIS/RTOS2/Include/cmsis_os2.h"/>
 715       </files>
 716     </api>
 717     <!-- CMSIS Driver API -->
 718     <api Cclass="CMSIS Driver" Cgroup="USART" Capiversion="2.3.0" exclusive="0">
 719       <description>USART Driver API for Cortex-M</description>
 720       <files>
 721         <file category="doc" name="CMSIS/Documentation/Driver/html/group__usart__interface__gr.html" />
 722         <file category="header" name="CMSIS/Driver/Include/Driver_USART.h" />
 723       </files>
 724     </api>
 725     <api Cclass="CMSIS Driver" Cgroup="SPI" Capiversion="2.2.0" exclusive="0">
 726       <description>SPI Driver API for Cortex-M</description>
 727       <files>
 728         <file category="doc" name="CMSIS/Documentation/Driver/html/group__spi__interface__gr.html" />
 729         <file category="header" name="CMSIS/Driver/Include/Driver_SPI.h" />
 730       </files>
 731     </api>
 732     <api Cclass="CMSIS Driver" Cgroup="SAI" Capiversion="1.1.0" exclusive="0">
 733       <description>SAI Driver API for Cortex-M</description>
 734       <files>
 735         <file category="doc" name="CMSIS/Documentation/Driver/html/group__sai__interface__gr.html"/>
 736         <file category="header" name="CMSIS/Driver/Include/Driver_SAI.h" />
 737       </files>
 738     </api>
 739     <api Cclass="CMSIS Driver" Cgroup="I2C" Capiversion="2.3.0" exclusive="0">
 740       <description>I2C Driver API for Cortex-M</description>
 741       <files>
 742         <file category="doc" name="CMSIS/Documentation/Driver/html/group__i2c__interface__gr.html"/>
 743         <file category="header" name="CMSIS/Driver/Include/Driver_I2C.h" />
 744       </files>
 745     </api>
 746     <api Cclass="CMSIS Driver" Cgroup="CAN" Capiversion="1.2.0" exclusive="0">
 747       <description>CAN Driver API for Cortex-M</description>
 748       <files>
 749         <file category="doc" name="CMSIS/Documentation/Driver/html/group__can__interface__gr.html"/>
 750         <file category="header" name="CMSIS/Driver/Include/Driver_CAN.h" />
 751       </files>
 752     </api>
 753     <api Cclass="CMSIS Driver" Cgroup="Flash" Capiversion="2.2.0" exclusive="0">
 754       <description>Flash Driver API for Cortex-M</description>
 755       <files>
 756         <file category="doc" name="CMSIS/Documentation/Driver/html/group__flash__interface__gr.html" />
 757         <file category="header" name="CMSIS/Driver/Include/Driver_Flash.h" />
 758       </files>
 759     </api>
 760     <api Cclass="CMSIS Driver" Cgroup="MCI" Capiversion="2.3.0" exclusive="0">
 761       <description>MCI Driver API for Cortex-M</description>
 762       <files>
 763         <file category="doc" name="CMSIS/Documentation/Driver/html/group__mci__interface__gr.html" />
 764         <file category="header" name="CMSIS/Driver/Include/Driver_MCI.h" />
 765       </files>
 766     </api>
 767     <api Cclass="CMSIS Driver" Cgroup="NAND" Capiversion="2.3.0" exclusive="0">
 768       <description>NAND Flash Driver API for Cortex-M</description>
 769       <files>
 770         <file category="doc" name="CMSIS/Documentation/Driver/html/group__nand__interface__gr.html" />
 771         <file category="header" name="CMSIS/Driver/Include/Driver_NAND.h" />
 772       </files>
 773     </api>
 774     <api Cclass="CMSIS Driver" Cgroup="Ethernet" Capiversion="2.1.0" exclusive="0">
 775       <description>Ethernet MAC and PHY Driver API for Cortex-M</description>
 776       <files>
 777         <file category="doc" name="CMSIS/Documentation/Driver/html/group__eth__interface__gr.html" />
 778         <file category="header" name="CMSIS/Driver/Include/Driver_ETH_MAC.h" />
 779         <file category="header" name="CMSIS/Driver/Include/Driver_ETH_PHY.h" />
 780       </files>
 781     </api>
 782     <api Cclass="CMSIS Driver" Cgroup="Ethernet MAC" Capiversion="2.1.0" exclusive="0">
 783       <description>Ethernet MAC Driver API for Cortex-M</description>
 784       <files>
 785         <file category="doc" name="CMSIS/Documentation/Driver/html/group__eth__mac__interface__gr.html" />
 786         <file category="header" name="CMSIS/Driver/Include/Driver_ETH_MAC.h" />
 787       </files>
 788     </api>
 789     <api Cclass="CMSIS Driver" Cgroup="Ethernet PHY" Capiversion="2.1.0" exclusive="0">
 790       <description>Ethernet PHY Driver API for Cortex-M</description>
 791       <files>
 792         <file category="doc" name="CMSIS/Documentation/Driver/html/group__eth__phy__interface__gr.html" />
 793         <file category="header" name="CMSIS/Driver/Include/Driver_ETH_PHY.h" />
 794       </files>
 795     </api>
 796     <api Cclass="CMSIS Driver" Cgroup="USB Device" Capiversion="2.2.0" exclusive="0">
 797       <description>USB Device Driver API for Cortex-M</description>
 798       <files>
 799         <file category="doc" name="CMSIS/Documentation/Driver/html/group__usbd__interface__gr.html" />
 800         <file category="header" name="CMSIS/Driver/Include/Driver_USBD.h" />
 801       </files>
 802     </api>
 803     <api Cclass="CMSIS Driver" Cgroup="USB Host" Capiversion="2.2.0" exclusive="0">
 804       <description>USB Host Driver API for Cortex-M</description>
 805       <files>
 806         <file category="doc" name="CMSIS/Documentation/Driver/html/group__usbh__interface__gr.html" />
 807         <file category="header" name="CMSIS/Driver/Include/Driver_USBH.h" />
 808       </files>
 809     </api>
 810   </apis>
 811
 812   <!-- conditions are dependency rules that can apply to a component or an individual file -->
 813   <conditions>
 814     <!-- compiler -->
 815     <condition id="ARMCC6">
 816       <accept Tcompiler="ARMCC" Toptions="AC6"/>
 817       <accept Tcompiler="ARMCC" Toptions="AC6LTO"/>
 818     </condition>
 819     <condition id="ARMCC5">
 820       <require Tcompiler="ARMCC" Toptions="AC5"/>
 821     </condition>
 822     <condition id="ARMCC">
 823       <require Tcompiler="ARMCC"/>
 824     </condition>
 825     <condition id="GCC">
 826       <require Tcompiler="GCC"/>
 827     </condition>
 828     <condition id="IAR">
 829       <require Tcompiler="IAR"/>
 830     </condition>
 831     <condition id="ARMCC GCC">
 832       <accept Tcompiler="ARMCC"/>
 833       <accept Tcompiler="GCC"/>
 834     </condition>
 835     <condition id="ARMCC GCC IAR">
 836       <accept Tcompiler="ARMCC"/>
 837       <accept Tcompiler="GCC"/>
 838       <accept Tcompiler="IAR"/>
 839     </condition>
 840
 841     <!-- Arm architecture -->
 842     <condition id="ARMv6-M Device">
 843       <description>Armv6-M architecture based device</description>
 844       <accept Dcore="Cortex-M0"/>
 845       <accept Dcore="Cortex-M1"/>
 846       <accept Dcore="Cortex-M0+"/>
 847       <accept Dcore="SC000"/>
 848     </condition>
 849     <condition id="ARMv7-M Device">
 850       <description>Armv7-M architecture based device</description>
 851       <accept Dcore="Cortex-M3"/>
 852       <accept Dcore="Cortex-M4"/>
 853       <accept Dcore="Cortex-M7"/>
 854       <accept Dcore="SC300"/>
 855     </condition>
 856     <condition id="ARMv8-M Device">
 857       <description>Armv8-M architecture based device</description>
 858       <accept Dcore="ARMV8MBL"/>
 859       <accept Dcore="ARMV8MML"/>
 860       <accept Dcore="Cortex-M23"/>
 861       <accept Dcore="Cortex-M33"/>
 862       <accept Dcore="Cortex-M35P"/>
 863     </condition>
 864     <condition id="ARMv8-M TZ Device">
 865       <description>Armv8-M architecture based device with TrustZone</description>
 866       <require condition="ARMv8-M Device"/>
 867       <require Dtz="TZ"/>
 868     </condition>
 869     <condition id="ARMv6_7-M Device">
 870       <description>Armv6_7-M architecture based device</description>
 871       <accept condition="ARMv6-M Device"/>
 872       <accept condition="ARMv7-M Device"/>
 873     </condition>
 874     <condition id="ARMv6_7_8-M Device">
 875       <description>Armv6_7_8-M architecture based device</description>
 876       <accept condition="ARMv6-M Device"/>
 877       <accept condition="ARMv7-M Device"/>
 878       <accept condition="ARMv8-M Device"/>
 879     </condition>
 880     <condition id="ARMv7-A Device">
 881       <description>Armv7-A architecture based device</description>
 882       <accept Dcore="Cortex-A5"/>
 883       <accept Dcore="Cortex-A7"/>
 884       <accept Dcore="Cortex-A9"/>
 885     </condition>
 886
 887     <!-- ARM core -->
 888     <condition id="CM0">
 889       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device</description>
 890       <accept Dcore="Cortex-M0"/>
 891       <accept Dcore="Cortex-M0+"/>
 892       <accept Dcore="SC000"/>
 893     </condition>
 894     <condition id="CM1">
 895       <description>Cortex-M1</description>
 896       <require Dcore="Cortex-M1"/>
 897     </condition>
 898     <condition id="CM3">
 899       <description>Cortex-M3 or SC300 processor based device</description>
 900       <accept Dcore="Cortex-M3"/>
 901       <accept Dcore="SC300"/>
 902     </condition>
 903     <condition id="CM4">
 904       <description>Cortex-M4 processor based device</description>
 905       <require Dcore="Cortex-M4" Dfpu="NO_FPU"/>
 906     </condition>
 907     <condition id="CM4_FP">
 908       <description>Cortex-M4 processor based device using Floating Point Unit</description>
 909       <accept Dcore="Cortex-M4" Dfpu="FPU"/>
 910       <accept Dcore="Cortex-M4" Dfpu="SP_FPU"/>
 911       <accept Dcore="Cortex-M4" Dfpu="DP_FPU"/>
 912     </condition>
 913     <condition id="CM7">
 914       <description>Cortex-M7 processor based device</description>
 915       <require Dcore="Cortex-M7" Dfpu="NO_FPU"/>
 916     </condition>
 917     <condition id="CM7_FP">
 918       <description>Cortex-M7 processor based device using Floating Point Unit</description>
 919       <accept Dcore="Cortex-M7" Dfpu="SP_FPU"/>
 920       <accept Dcore="Cortex-M7" Dfpu="DP_FPU"/>
 921     </condition>
 922     <condition id="CM7_SP">
 923       <description>Cortex-M7 processor based device using Floating Point Unit (SP)</description>
 924       <require Dcore="Cortex-M7" Dfpu="SP_FPU"/>
 925     </condition>
 926     <condition id="CM7_DP">
 927       <description>Cortex-M7 processor based device using Floating Point Unit (DP)</description>
 928       <require Dcore="Cortex-M7" Dfpu="DP_FPU"/>
 929     </condition>
 930     <condition id="CM23">
 931       <description>Cortex-M23 processor based device</description>
 932       <require Dcore="Cortex-M23"/>
 933     </condition>
 934     <condition id="CM33">
 935       <description>Cortex-M33 processor based device</description>
 936       <require Dcore="Cortex-M33" Dfpu="NO_FPU"/>
 937     </condition>
 938     <condition id="CM33_FP">
 939       <description>Cortex-M33 processor based device using Floating Point Unit</description>
 940       <require Dcore="Cortex-M33" Dfpu="SP_FPU"/>
 941     </condition>
 942     <condition id="CM35P">
 943       <description>Cortex-M35P processor based device</description>
 944       <require Dcore="Cortex-M35P" Dfpu="NO_FPU"/>
 945     </condition>
 946     <condition id="CM35P_FP">
 947       <description>Cortex-M35P processor based device using Floating Point Unit</description>
 948       <require Dcore="Cortex-M35P" Dfpu="SP_FPU"/>
 949     </condition>
 950     <condition id="ARMv8MBL">
 951       <description>Armv8-M Baseline processor based device</description>
 952       <require Dcore="ARMV8MBL"/>
 953     </condition>
 954     <condition id="ARMv8MML">
 955       <description>Armv8-M Mainline processor based device</description>
 956       <require Dcore="ARMV8MML" Dfpu="NO_FPU"/>
 957     </condition>
 958     <condition id="ARMv8MML_FP">
 959       <description>Armv8-M Mainline processor based device using Floating Point Unit</description>
 960       <accept Dcore="ARMV8MML" Dfpu="SP_FPU"/>
 961       <accept Dcore="ARMV8MML" Dfpu="DP_FPU"/>
 962     </condition>
 963
 964     <condition id="CM33_NODSP_NOFPU">
 965       <description>CM33, no DSP, no FPU</description>
 966       <require Dcore="Cortex-M33" Ddsp="NO_DSP" Dfpu="NO_FPU"/>
 967     </condition>
 968     <condition id="CM33_DSP_NOFPU">
 969       <description>CM33, DSP, no FPU</description>
 970       <require Dcore="Cortex-M33" Ddsp="DSP" Dfpu="NO_FPU"/>
 971     </condition>
 972     <condition id="CM33_NODSP_SP">
 973       <description>CM33, no DSP, SP FPU</description>
 974       <require Dcore="Cortex-M33" Ddsp="NO_DSP" Dfpu="SP_FPU"/>
 975     </condition>
 976     <condition id="CM33_DSP_SP">
 977       <description>CM33, DSP, SP FPU</description>
 978       <require Dcore="Cortex-M33" Ddsp="DSP" Dfpu="SP_FPU"/>
 979     </condition>
 980
 981     <condition id="CM35P_NODSP_NOFPU">
 982       <description>CM35P, no DSP, no FPU</description>
 983       <require Dcore="Cortex-M35P" Ddsp="NO_DSP" Dfpu="NO_FPU"/>
 984     </condition>
 985     <condition id="CM35P_DSP_NOFPU">
 986       <description>CM35P, DSP, no FPU</description>
 987       <require Dcore="Cortex-M35P" Ddsp="DSP" Dfpu="NO_FPU"/>
 988     </condition>
 989     <condition id="CM35P_NODSP_SP">
 990       <description>CM35P, no DSP, SP FPU</description>
 991       <require Dcore="Cortex-M35P" Ddsp="NO_DSP" Dfpu="SP_FPU"/>
 992     </condition>
 993     <condition id="CM35P_DSP_SP">
 994       <description>CM35P, DSP, SP FPU</description>
 995       <require Dcore="Cortex-M35P" Ddsp="DSP" Dfpu="SP_FPU"/>
 996     </condition>
 997
 998     <condition id="ARMv8MML_NODSP_NOFPU">
 999       <description>Armv8-M Mainline, no DSP, no FPU</description>
1000       <require Dcore="ARMV8MML" Ddsp="NO_DSP" Dfpu="NO_FPU"/>
1001     </condition>
1002     <condition id="ARMv8MML_DSP_NOFPU">
1003       <description>Armv8-M Mainline, DSP, no FPU</description>
1004       <require Dcore="ARMV8MML" Ddsp="DSP" Dfpu="NO_FPU"/>
1005     </condition>
1006     <condition id="ARMv8MML_NODSP_SP">
1007       <description>Armv8-M Mainline, no DSP, SP FPU</description>
1008       <require Dcore="ARMV8MML" Ddsp="NO_DSP" Dfpu="SP_FPU"/>
1009     </condition>
1010     <condition id="ARMv8MML_DSP_SP">
1011       <description>Armv8-M Mainline, DSP, SP FPU</description>
1012       <require Dcore="ARMV8MML" Ddsp="DSP" Dfpu="SP_FPU"/>
1013     </condition>
1014
1015     <condition id="CA5_CA9">
1016       <description>Cortex-A5 or Cortex-A9 processor based device</description>
1017       <accept Dcore="Cortex-A5"/>
1018       <accept Dcore="Cortex-A9"/>
1019     </condition>
1020
1021     <condition id="CA7">
1022       <description>Cortex-A7 processor based device</description>
1023       <accept Dcore="Cortex-A7"/>
1024     </condition>
1025
1026     <!-- ARMCC compiler -->
1027     <condition id="CA_ARMCC5">
1028       <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the Arm Compiler 5</description>
1029       <require condition="ARMv7-A Device"/>
1030       <require condition="ARMCC5"/>
1031     </condition>
1032     <condition id="CA_ARMCC6">
1033       <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the Arm Compiler 6</description>
1034       <require condition="ARMv7-A Device"/>
1035       <require condition="ARMCC6"/>
1036     </condition>
1037
1038     <condition id="CM0_ARMCC">
1039       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device for the Arm Compiler</description>
1040       <require condition="CM0"/>
1041       <require Tcompiler="ARMCC"/>
1042     </condition>
1043     <condition id="CM0_LE_ARMCC">
1044       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the Arm Compiler</description>
1045       <require condition="CM0_ARMCC"/>
1046       <require Dendian="Little-endian"/>
1047     </condition>
1048     <condition id="CM0_BE_ARMCC">
1049       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the Arm Compiler</description>
1050       <require condition="CM0_ARMCC"/>
1051       <require Dendian="Big-endian"/>
1052     </condition>
1053
1054     <condition id="CM1_ARMCC">
1055       <description>Cortex-M1 based device for the Arm Compiler</description>
1056       <require condition="CM1"/>
1057       <require Tcompiler="ARMCC"/>
1058     </condition>
1059     <condition id="CM1_LE_ARMCC">
1060       <description>Cortex-M1 based device in little endian mode for the Arm Compiler</description>
1061       <require condition="CM1_ARMCC"/>
1062       <require Dendian="Little-endian"/>
1063     </condition>
1064     <condition id="CM1_BE_ARMCC">
1065       <description>Cortex-M1 based device in big endian mode for the Arm Compiler</description>
1066       <require condition="CM1_ARMCC"/>
1067       <require Dendian="Big-endian"/>
1068     </condition>
1069
1070     <condition id="CM3_ARMCC">
1071       <description>Cortex-M3 or SC300 processor based device for the Arm Compiler</description>
1072       <require condition="CM3"/>
1073       <require Tcompiler="ARMCC"/>
1074     </condition>
1075     <condition id="CM3_LE_ARMCC">
1076       <description>Cortex-M3 or SC300 processor based device in little endian mode for the Arm Compiler</description>
1077       <require condition="CM3_ARMCC"/>
1078       <require Dendian="Little-endian"/>
1079     </condition>
1080     <condition id="CM3_BE_ARMCC">
1081       <description>Cortex-M3 or SC300 processor based device in big endian mode for the Arm Compiler</description>
1082       <require condition="CM3_ARMCC"/>
1083       <require Dendian="Big-endian"/>
1084     </condition>
1085
1086     <condition id="CM4_ARMCC">
1087       <description>Cortex-M4 processor based device for the Arm Compiler</description>
1088       <require condition="CM4"/>
1089       <require Tcompiler="ARMCC"/>
1090     </condition>
1091     <condition id="CM4_LE_ARMCC">
1092       <description>Cortex-M4 processor based device in little endian mode for the Arm Compiler</description>
1093       <require condition="CM4_ARMCC"/>
1094       <require Dendian="Little-endian"/>
1095     </condition>
1096     <condition id="CM4_BE_ARMCC">
1097       <description>Cortex-M4 processor based device in big endian mode for the Arm Compiler</description>
1098       <require condition="CM4_ARMCC"/>
1099       <require Dendian="Big-endian"/>
1100     </condition>
1101
1102     <condition id="CM4_FP_ARMCC">
1103       <description>Cortex-M4 processor based device using Floating Point Unit for the Arm Compiler</description>
1104       <require condition="CM4_FP"/>
1105       <require Tcompiler="ARMCC"/>
1106     </condition>
1107     <condition id="CM4_FP_LE_ARMCC">
1108       <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
1109       <require condition="CM4_FP_ARMCC"/>
1110       <require Dendian="Little-endian"/>
1111     </condition>
1112     <condition id="CM4_FP_BE_ARMCC">
1113       <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
1114       <require condition="CM4_FP_ARMCC"/>
1115       <require Dendian="Big-endian"/>
1116     </condition>
1117
1118     <condition id="CM7_ARMCC">
1119       <description>Cortex-M7 processor based device for the Arm Compiler</description>
1120       <require condition="CM7"/>
1121       <require Tcompiler="ARMCC"/>
1122     </condition>
1123     <condition id="CM7_LE_ARMCC">
1124       <description>Cortex-M7 processor based device in little endian mode for the Arm Compiler</description>
1125       <require condition="CM7_ARMCC"/>
1126       <require Dendian="Little-endian"/>
1127     </condition>
1128     <condition id="CM7_BE_ARMCC">
1129       <description>Cortex-M7 processor based device in big endian mode for the Arm Compiler</description>
1130       <require condition="CM7_ARMCC"/>
1131       <require Dendian="Big-endian"/>
1132     </condition>
1133
1134     <condition id="CM7_FP_ARMCC">
1135       <description>Cortex-M7 processor based device using Floating Point Unit for the Arm Compiler</description>
1136       <require condition="CM7_FP"/>
1137       <require Tcompiler="ARMCC"/>
1138     </condition>
1139     <condition id="CM7_FP_LE_ARMCC">
1140       <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
1141       <require condition="CM7_FP_ARMCC"/>
1142       <require Dendian="Little-endian"/>
1143     </condition>
1144     <condition id="CM7_FP_BE_ARMCC">
1145       <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
1146       <require condition="CM7_FP_ARMCC"/>
1147       <require Dendian="Big-endian"/>
1148     </condition>
1149
1150     <condition id="CM7_SP_ARMCC">
1151       <description>Cortex-M7 processor based device using Floating Point Unit (SP) for the Arm Compiler</description>
1152       <require condition="CM7_SP"/>
1153       <require Tcompiler="ARMCC"/>
1154     </condition>
1155     <condition id="CM7_SP_LE_ARMCC">
1156       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the Arm Compiler</description>
1157       <require condition="CM7_SP_ARMCC"/>
1158       <require Dendian="Little-endian"/>
1159     </condition>
1160     <condition id="CM7_SP_BE_ARMCC">
1161       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the Arm Compiler</description>
1162       <require condition="CM7_SP_ARMCC"/>
1163       <require Dendian="Big-endian"/>
1164     </condition>
1165
1166     <condition id="CM7_DP_ARMCC">
1167       <description>Cortex-M7 processor based device using Floating Point Unit (DP) for the Arm Compiler</description>
1168       <require condition="CM7_DP"/>
1169       <require Tcompiler="ARMCC"/>
1170     </condition>
1171     <condition id="CM7_DP_LE_ARMCC">
1172       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the Arm Compiler</description>
1173       <require condition="CM7_DP_ARMCC"/>
1174       <require Dendian="Little-endian"/>
1175     </condition>
1176     <condition id="CM7_DP_BE_ARMCC">
1177       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the Arm Compiler</description>
1178       <require condition="CM7_DP_ARMCC"/>
1179       <require Dendian="Big-endian"/>
1180     </condition>
1181
1182     <condition id="CM23_ARMCC">
1183       <description>Cortex-M23 processor based device for the Arm Compiler</description>
1184       <require condition="CM23"/>
1185       <require Tcompiler="ARMCC"/>
1186     </condition>
1187     <condition id="CM23_LE_ARMCC">
1188       <description>Cortex-M23 processor based device in little endian mode for the Arm Compiler</description>
1189       <require condition="CM23_ARMCC"/>
1190       <require Dendian="Little-endian"/>
1191     </condition>
1192     <condition id="CM23_BE_ARMCC">
1193       <description>Cortex-M23 processor based device in big endian mode for the Arm Compiler</description>
1194       <require condition="CM23_ARMCC"/>
1195       <require Dendian="Big-endian"/>
1196     </condition>
1197
1198     <condition id="CM33_ARMCC">
1199       <description>Cortex-M33 processor based device for the Arm Compiler</description>
1200       <require condition="CM33"/>
1201       <require Tcompiler="ARMCC"/>
1202     </condition>
1203     <condition id="CM33_LE_ARMCC">
1204       <description>Cortex-M33 processor based device in little endian mode for the Arm Compiler</description>
1205       <require condition="CM33_ARMCC"/>
1206       <require Dendian="Little-endian"/>
1207     </condition>
1208     <condition id="CM33_BE_ARMCC">
1209       <description>Cortex-M33 processor based device in big endian mode for the Arm Compiler</description>
1210       <require condition="CM33_ARMCC"/>
1211       <require Dendian="Big-endian"/>
1212     </condition>
1213
1214     <condition id="CM33_FP_ARMCC">
1215       <description>Cortex-M33 processor based device using Floating Point Unit for the Arm Compiler</description>
1216       <require condition="CM33_FP"/>
1217       <require Tcompiler="ARMCC"/>
1218     </condition>
1219     <condition id="CM33_FP_LE_ARMCC">
1220       <description>Cortex-M33 processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
1221       <require condition="CM33_FP_ARMCC"/>
1222       <require Dendian="Little-endian"/>
1223     </condition>
1224     <condition id="CM33_FP_BE_ARMCC">
1225       <description>Cortex-M33 processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
1226       <require condition="CM33_FP_ARMCC"/>
1227       <require Dendian="Big-endian"/>
1228     </condition>
1229
1230     <condition id="CM33_NODSP_NOFPU_ARMCC">
1231       <description>Cortex-M33 processor, no DSP, no FPU, Arm Compiler</description>
1232       <require condition="CM33_NODSP_NOFPU"/>
1233       <require Tcompiler="ARMCC"/>
1234     </condition>
1235     <condition id="CM33_DSP_NOFPU_ARMCC">
1236       <description>Cortex-M33 processor, DSP, no FPU, Arm Compiler</description>
1237       <require condition="CM33_DSP_NOFPU"/>
1238       <require Tcompiler="ARMCC"/>
1239     </condition>
1240     <condition id="CM33_NODSP_SP_ARMCC">
1241       <description>Cortex-M33 processor, no DSP, SP FPU, Arm Compiler</description>
1242       <require condition="CM33_NODSP_SP"/>
1243       <require Tcompiler="ARMCC"/>
1244     </condition>
1245     <condition id="CM33_DSP_SP_ARMCC">
1246       <description>Cortex-M33 processor, DSP, SP FPU, Arm Compiler</description>
1247       <require condition="CM33_DSP_SP"/>
1248       <require Tcompiler="ARMCC"/>
1249     </condition>
1250     <condition id="CM33_NODSP_NOFPU_LE_ARMCC">
1251       <description>Cortex-M33 processor, little endian, no DSP, no FPU, Arm Compiler</description>
1252       <require condition="CM33_NODSP_NOFPU_ARMCC"/>
1253       <require Dendian="Little-endian"/>
1254     </condition>
1255     <condition id="CM33_DSP_NOFPU_LE_ARMCC">
1256       <description>Cortex-M33 processor, little endian, DSP, no FPU, Arm Compiler</description>
1257       <require condition="CM33_DSP_NOFPU_ARMCC"/>
1258       <require Dendian="Little-endian"/>
1259     </condition>
1260     <condition id="CM33_NODSP_SP_LE_ARMCC">
1261       <description>Cortex-M33 processor, little endian, no DSP, SP FPU, Arm Compiler</description>
1262       <require condition="CM33_NODSP_SP_ARMCC"/>
1263       <require Dendian="Little-endian"/>
1264     </condition>
1265     <condition id="CM33_DSP_SP_LE_ARMCC">
1266       <description>Cortex-M33 processor, little endian, DSP, SP FPU, Arm Compiler</description>
1267       <require condition="CM33_DSP_SP_ARMCC"/>
1268       <require Dendian="Little-endian"/>
1269     </condition>
1270
1271     <condition id="CM35P_ARMCC">
1272       <description>Cortex-M35P processor based device for the Arm Compiler</description>
1273       <require condition="CM35P"/>
1274       <require Tcompiler="ARMCC"/>
1275     </condition>
1276     <condition id="CM35P_LE_ARMCC">
1277       <description>Cortex-M35P processor based device in little endian mode for the Arm Compiler</description>
1278       <require condition="CM35P_ARMCC"/>
1279       <require Dendian="Little-endian"/>
1280     </condition>
1281     <condition id="CM35P_BE_ARMCC">
1282       <description>Cortex-M35P processor based device in big endian mode for the Arm Compiler</description>
1283       <require condition="CM35P_ARMCC"/>
1284       <require Dendian="Big-endian"/>
1285     </condition>
1286
1287     <condition id="CM35P_FP_ARMCC">
1288       <description>Cortex-M35P processor based device using Floating Point Unit for the Arm Compiler</description>
1289       <require condition="CM35P_FP"/>
1290       <require Tcompiler="ARMCC"/>
1291     </condition>
1292     <condition id="CM35P_FP_LE_ARMCC">
1293       <description>Cortex-M35P processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
1294       <require condition="CM35P_FP_ARMCC"/>
1295       <require Dendian="Little-endian"/>
1296     </condition>
1297     <condition id="CM35P_FP_BE_ARMCC">
1298       <description>Cortex-M35P processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
1299       <require condition="CM35P_FP_ARMCC"/>
1300       <require Dendian="Big-endian"/>
1301     </condition>
1302
1303     <condition id="CM35P_NODSP_NOFPU_ARMCC">
1304       <description>Cortex-M35P processor, no DSP, no FPU, Arm Compiler</description>
1305       <require condition="CM35P_NODSP_NOFPU"/>
1306       <require Tcompiler="ARMCC"/>
1307     </condition>
1308     <condition id="CM35P_DSP_NOFPU_ARMCC">
1309       <description>Cortex-M35P processor, DSP, no FPU, Arm Compiler</description>
1310       <require condition="CM35P_DSP_NOFPU"/>
1311       <require Tcompiler="ARMCC"/>
1312     </condition>
1313     <condition id="CM35P_NODSP_SP_ARMCC">
1314       <description>Cortex-M35P processor, no DSP, SP FPU, Arm Compiler</description>
1315       <require condition="CM35P_NODSP_SP"/>
1316       <require Tcompiler="ARMCC"/>
1317     </condition>
1318     <condition id="CM35P_DSP_SP_ARMCC">
1319       <description>Cortex-M35P processor, DSP, SP FPU, Arm Compiler</description>
1320       <require condition="CM35P_DSP_SP"/>
1321       <require Tcompiler="ARMCC"/>
1322     </condition>
1323     <condition id="CM35P_NODSP_NOFPU_LE_ARMCC">
1324       <description>Cortex-M35P processor, little endian, no DSP, no FPU, Arm Compiler</description>
1325       <require condition="CM35P_NODSP_NOFPU_ARMCC"/>
1326       <require Dendian="Little-endian"/>
1327     </condition>
1328     <condition id="CM35P_DSP_NOFPU_LE_ARMCC">
1329       <description>Cortex-M35P processor, little endian, DSP, no FPU, Arm Compiler</description>
1330       <require condition="CM35P_DSP_NOFPU_ARMCC"/>
1331       <require Dendian="Little-endian"/>
1332     </condition>
1333     <condition id="CM35P_NODSP_SP_LE_ARMCC">
1334       <description>Cortex-M35P processor, little endian, no DSP, SP FPU, Arm Compiler</description>
1335       <require condition="CM35P_NODSP_SP_ARMCC"/>
1336       <require Dendian="Little-endian"/>
1337     </condition>
1338     <condition id="CM35P_DSP_SP_LE_ARMCC">
1339       <description>Cortex-M35P processor, little endian, DSP, SP FPU, Arm Compiler</description>
1340       <require condition="CM35P_DSP_SP_ARMCC"/>
1341       <require Dendian="Little-endian"/>
1342     </condition>
1343
1344     <condition id="ARMv8MBL_ARMCC">
1345       <description>Armv8-M Baseline processor based device for the Arm Compiler</description>
1346       <require condition="ARMv8MBL"/>
1347       <require Tcompiler="ARMCC"/>
1348     </condition>
1349     <condition id="ARMv8MBL_LE_ARMCC">
1350       <description>Armv8-M Baseline processor based device in little endian mode for the Arm Compiler</description>
1351       <require condition="ARMv8MBL_ARMCC"/>
1352       <require Dendian="Little-endian"/>
1353     </condition>
1354     <condition id="ARMv8MBL_BE_ARMCC">
1355       <description>Armv8-M Baseline processor based device in big endian mode for the Arm Compiler</description>
1356       <require condition="ARMv8MBL_ARMCC"/>
1357       <require Dendian="Big-endian"/>
1358     </condition>
1359
1360     <condition id="ARMv8MML_ARMCC">
1361       <description>Armv8-M Mainline processor based device for the Arm Compiler</description>
1362       <require condition="ARMv8MML"/>
1363       <require Tcompiler="ARMCC"/>
1364     </condition>
1365     <condition id="ARMv8MML_LE_ARMCC">
1366       <description>Armv8-M Mainline processor based device in little endian mode for the Arm Compiler</description>
1367       <require condition="ARMv8MML_ARMCC"/>
1368       <require Dendian="Little-endian"/>
1369     </condition>
1370     <condition id="ARMv8MML_BE_ARMCC">
1371       <description>Armv8-M Mainline processor based device in big endian mode for the Arm Compiler</description>
1372       <require condition="ARMv8MML_ARMCC"/>
1373       <require Dendian="Big-endian"/>
1374     </condition>
1375
1376     <condition id="ARMv8MML_FP_ARMCC">
1377       <description>Armv8-M Mainline processor based device using Floating Point Unit for the Arm Compiler</description>
1378       <require condition="ARMv8MML_FP"/>
1379       <require Tcompiler="ARMCC"/>
1380     </condition>
1381     <condition id="ARMv8MML_FP_LE_ARMCC">
1382       <description>Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the Arm Compiler</description>
1383       <require condition="ARMv8MML_FP_ARMCC"/>
1384       <require Dendian="Little-endian"/>
1385     </condition>
1386     <condition id="ARMv8MML_FP_BE_ARMCC">
1387       <description>Armv8-M Mainline processor based device using Floating Point Unit in big endian mode for the Arm Compiler</description>
1388       <require condition="ARMv8MML_FP_ARMCC"/>
1389       <require Dendian="Big-endian"/>
1390     </condition>
1391
1392     <condition id="ARMv8MML_NODSP_NOFPU_ARMCC">
1393       <description>Armv8-M Mainline, no DSP, no FPU, Arm Compiler</description>
1394       <require condition="ARMv8MML_NODSP_NOFPU"/>
1395       <require Tcompiler="ARMCC"/>
1396     </condition>
1397     <condition id="ARMv8MML_DSP_NOFPU_ARMCC">
1398       <description>Armv8-M Mainline, DSP, no FPU, Arm Compiler</description>
1399       <require condition="ARMv8MML_DSP_NOFPU"/>
1400       <require Tcompiler="ARMCC"/>
1401     </condition>
1402     <condition id="ARMv8MML_NODSP_SP_ARMCC">
1403       <description>Armv8-M Mainline, no DSP, SP FPU, Arm Compiler</description>
1404       <require condition="ARMv8MML_NODSP_SP"/>
1405       <require Tcompiler="ARMCC"/>
1406     </condition>
1407     <condition id="ARMv8MML_DSP_SP_ARMCC">
1408       <description>Armv8-M Mainline, DSP, SP FPU, Arm Compiler</description>
1409       <require condition="ARMv8MML_DSP_SP"/>
1410       <require Tcompiler="ARMCC"/>
1411     </condition>
1412     <condition id="ARMv8MML_NODSP_NOFPU_LE_ARMCC">
1413       <description>Armv8-M Mainline, little endian, no DSP, no FPU, Arm Compiler</description>
1414       <require condition="ARMv8MML_NODSP_NOFPU_ARMCC"/>
1415       <require Dendian="Little-endian"/>
1416     </condition>
1417     <condition id="ARMv8MML_DSP_NOFPU_LE_ARMCC">
1418       <description>Armv8-M Mainline, little endian, DSP, no FPU, Arm Compiler</description>
1419       <require condition="ARMv8MML_DSP_NOFPU_ARMCC"/>
1420       <require Dendian="Little-endian"/>
1421     </condition>
1422     <condition id="ARMv8MML_NODSP_SP_LE_ARMCC">
1423       <description>Armv8-M Mainline, little endian, no DSP, SP FPU, Arm Compiler</description>
1424       <require condition="ARMv8MML_NODSP_SP_ARMCC"/>
1425       <require Dendian="Little-endian"/>
1426     </condition>
1427     <condition id="ARMv8MML_DSP_SP_LE_ARMCC">
1428       <description>Armv8-M Mainline, little endian, DSP, SP FPU, Arm Compiler</description>
1429       <require condition="ARMv8MML_DSP_SP_ARMCC"/>
1430       <require Dendian="Little-endian"/>
1431     </condition>
1432
1433     <!-- GCC compiler -->
1434     <condition id="CA_GCC">
1435       <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the GCC Compiler</description>
1436       <require condition="ARMv7-A Device"/>
1437       <require Tcompiler="GCC"/>
1438     </condition>
1439
1440     <condition id="CM0_GCC">
1441       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device for the GCC Compiler</description>
1442       <require condition="CM0"/>
1443       <require Tcompiler="GCC"/>
1444     </condition>
1445     <condition id="CM0_LE_GCC">
1446       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the GCC Compiler</description>
1447       <require condition="CM0_GCC"/>
1448       <require Dendian="Little-endian"/>
1449     </condition>
1450     <condition id="CM0_BE_GCC">
1451       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the GCC Compiler</description>
1452       <require condition="CM0_GCC"/>
1453       <require Dendian="Big-endian"/>
1454     </condition>
1455
1456     <condition id="CM1_GCC">
1457       <description>Cortex-M1 based device for the GCC Compiler</description>
1458       <require condition="CM1"/>
1459       <require Tcompiler="GCC"/>
1460     </condition>
1461     <condition id="CM1_LE_GCC">
1462       <description>Cortex-M1 based device in little endian mode for the GCC Compiler</description>
1463       <require condition="CM1_GCC"/>
1464       <require Dendian="Little-endian"/>
1465     </condition>
1466     <condition id="CM1_BE_GCC">
1467       <description>Cortex-M1 based device in big endian mode for the GCC Compiler</description>
1468       <require condition="CM1_GCC"/>
1469       <require Dendian="Big-endian"/>
1470     </condition>
1471
1472     <condition id="CM3_GCC">
1473       <description>Cortex-M3 or SC300 processor based device for the GCC Compiler</description>
1474       <require condition="CM3"/>
1475       <require Tcompiler="GCC"/>
1476     </condition>
1477     <condition id="CM3_LE_GCC">
1478       <description>Cortex-M3 or SC300 processor based device in little endian mode for the GCC Compiler</description>
1479       <require condition="CM3_GCC"/>
1480       <require Dendian="Little-endian"/>
1481     </condition>
1482     <condition id="CM3_BE_GCC">
1483       <description>Cortex-M3 or SC300 processor based device in big endian mode for the GCC Compiler</description>
1484       <require condition="CM3_GCC"/>
1485       <require Dendian="Big-endian"/>
1486     </condition>
1487
1488     <condition id="CM4_GCC">
1489       <description>Cortex-M4 processor based device for the GCC Compiler</description>
1490       <require condition="CM4"/>
1491       <require Tcompiler="GCC"/>
1492     </condition>
1493     <condition id="CM4_LE_GCC">
1494       <description>Cortex-M4 processor based device in little endian mode for the GCC Compiler</description>
1495       <require condition="CM4_GCC"/>
1496       <require Dendian="Little-endian"/>
1497     </condition>
1498     <condition id="CM4_BE_GCC">
1499       <description>Cortex-M4 processor based device in big endian mode for the GCC Compiler</description>
1500       <require condition="CM4_GCC"/>
1501       <require Dendian="Big-endian"/>
1502     </condition>
1503
1504     <condition id="CM4_FP_GCC">
1505       <description>Cortex-M4 processor based device using Floating Point Unit for the GCC Compiler</description>
1506       <require condition="CM4_FP"/>
1507       <require Tcompiler="GCC"/>
1508     </condition>
1509     <condition id="CM4_FP_LE_GCC">
1510       <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
1511       <require condition="CM4_FP_GCC"/>
1512       <require Dendian="Little-endian"/>
1513     </condition>
1514     <condition id="CM4_FP_BE_GCC">
1515       <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
1516       <require condition="CM4_FP_GCC"/>
1517       <require Dendian="Big-endian"/>
1518     </condition>
1519
1520     <condition id="CM7_GCC">
1521       <description>Cortex-M7 processor based device for the GCC Compiler</description>
1522       <require condition="CM7"/>
1523       <require Tcompiler="GCC"/>
1524     </condition>
1525     <condition id="CM7_LE_GCC">
1526       <description>Cortex-M7 processor based device in little endian mode for the GCC Compiler</description>
1527       <require condition="CM7_GCC"/>
1528       <require Dendian="Little-endian"/>
1529     </condition>
1530     <condition id="CM7_BE_GCC">
1531       <description>Cortex-M7 processor based device in big endian mode for the GCC Compiler</description>
1532       <require condition="CM7_GCC"/>
1533       <require Dendian="Big-endian"/>
1534     </condition>
1535
1536     <condition id="CM7_FP_GCC">
1537       <description>Cortex-M7 processor based device using Floating Point Unit for the GCC Compiler</description>
1538       <require condition="CM7_FP"/>
1539       <require Tcompiler="GCC"/>
1540     </condition>
1541     <condition id="CM7_FP_LE_GCC">
1542       <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
1543       <require condition="CM7_FP_GCC"/>
1544       <require Dendian="Little-endian"/>
1545     </condition>
1546     <condition id="CM7_FP_BE_GCC">
1547       <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
1548       <require condition="CM7_FP_GCC"/>
1549       <require Dendian="Big-endian"/>
1550     </condition>
1551
1552     <condition id="CM7_SP_GCC">
1553       <description>Cortex-M7 processor based device using Floating Point Unit (SP) for the GCC Compiler</description>
1554       <require condition="CM7_SP"/>
1555       <require Tcompiler="GCC"/>
1556     </condition>
1557     <condition id="CM7_SP_LE_GCC">
1558       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the GCC Compiler</description>
1559       <require condition="CM7_SP_GCC"/>
1560       <require Dendian="Little-endian"/>
1561     </condition>
1562     <condition id="CM7_SP_BE_GCC">
1563       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the GCC Compiler</description>
1564       <require condition="CM7_SP_GCC"/>
1565       <require Dendian="Big-endian"/>
1566     </condition>
1567
1568     <condition id="CM7_DP_GCC">
1569       <description>Cortex-M7 processor based device using Floating Point Unit (DP) for the GCC Compiler</description>
1570       <require condition="CM7_DP"/>
1571       <require Tcompiler="GCC"/>
1572     </condition>
1573     <condition id="CM7_DP_LE_GCC">
1574       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the GCC Compiler</description>
1575       <require condition="CM7_DP_GCC"/>
1576       <require Dendian="Little-endian"/>
1577     </condition>
1578     <condition id="CM7_DP_BE_GCC">
1579       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the GCC Compiler</description>
1580       <require condition="CM7_DP_GCC"/>
1581       <require Dendian="Big-endian"/>
1582     </condition>
1583
1584     <condition id="CM23_GCC">
1585       <description>Cortex-M23 processor based device for the GCC Compiler</description>
1586       <require condition="CM23"/>
1587       <require Tcompiler="GCC"/>
1588     </condition>
1589     <condition id="CM23_LE_GCC">
1590       <description>Cortex-M23 processor based device in little endian mode for the GCC Compiler</description>
1591       <require condition="CM23_GCC"/>
1592       <require Dendian="Little-endian"/>
1593     </condition>
1594     <condition id="CM23_BE_GCC">
1595       <description>Cortex-M23 processor based device in big endian mode for the GCC Compiler</description>
1596       <require condition="CM23_GCC"/>
1597       <require Dendian="Big-endian"/>
1598     </condition>
1599
1600     <condition id="CM33_GCC">
1601       <description>Cortex-M33 processor based device for the GCC Compiler</description>
1602       <require condition="CM33"/>
1603       <require Tcompiler="GCC"/>
1604     </condition>
1605     <condition id="CM33_LE_GCC">
1606       <description>Cortex-M33 processor based device in little endian mode for the GCC Compiler</description>
1607       <require condition="CM33_GCC"/>
1608       <require Dendian="Little-endian"/>
1609     </condition>
1610     <condition id="CM33_BE_GCC">
1611       <description>Cortex-M33 processor based device in big endian mode for the GCC Compiler</description>
1612       <require condition="CM33_GCC"/>
1613       <require Dendian="Big-endian"/>
1614     </condition>
1615
1616     <condition id="CM33_FP_GCC">
1617       <description>Cortex-M33 processor based device using Floating Point Unit for the GCC Compiler</description>
1618       <require condition="CM33_FP"/>
1619       <require Tcompiler="GCC"/>
1620     </condition>
1621     <condition id="CM33_FP_LE_GCC">
1622       <description>Cortex-M33 processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
1623       <require condition="CM33_FP_GCC"/>
1624       <require Dendian="Little-endian"/>
1625     </condition>
1626     <condition id="CM33_FP_BE_GCC">
1627       <description>Cortex-M33 processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
1628       <require condition="CM33_FP_GCC"/>
1629       <require Dendian="Big-endian"/>
1630     </condition>
1631
1632     <condition id="CM33_NODSP_NOFPU_GCC">
1633       <description>CM33, no DSP, no FPU, GCC Compiler</description>
1634       <require condition="CM33_NODSP_NOFPU"/>
1635       <require Tcompiler="GCC"/>
1636     </condition>
1637     <condition id="CM33_DSP_NOFPU_GCC">
1638       <description>CM33, DSP, no FPU, GCC Compiler</description>
1639       <require condition="CM33_DSP_NOFPU"/>
1640       <require Tcompiler="GCC"/>
1641     </condition>
1642     <condition id="CM33_NODSP_SP_GCC">
1643       <description>CM33, no DSP, SP FPU, GCC Compiler</description>
1644       <require condition="CM33_NODSP_SP"/>
1645       <require Tcompiler="GCC"/>
1646     </condition>
1647     <condition id="CM33_DSP_SP_GCC">
1648       <description>CM33, DSP, SP FPU, GCC Compiler</description>
1649       <require condition="CM33_DSP_SP"/>
1650       <require Tcompiler="GCC"/>
1651     </condition>
1652     <condition id="CM33_NODSP_NOFPU_LE_GCC">
1653       <description>CM33, little endian, no DSP, no FPU, GCC Compiler</description>
1654       <require condition="CM33_NODSP_NOFPU_GCC"/>
1655       <require Dendian="Little-endian"/>
1656     </condition>
1657     <condition id="CM33_DSP_NOFPU_LE_GCC">
1658       <description>CM33, little endian, DSP, no FPU, GCC Compiler</description>
1659       <require condition="CM33_DSP_NOFPU_GCC"/>
1660       <require Dendian="Little-endian"/>
1661     </condition>
1662     <condition id="CM33_NODSP_SP_LE_GCC">
1663       <description>CM33, little endian, no DSP, SP FPU, GCC Compiler</description>
1664       <require condition="CM33_NODSP_SP_GCC"/>
1665       <require Dendian="Little-endian"/>
1666     </condition>
1667     <condition id="CM33_DSP_SP_LE_GCC">
1668       <description>CM33, little endian, DSP, SP FPU, GCC Compiler</description>
1669       <require condition="CM33_DSP_SP_GCC"/>
1670       <require Dendian="Little-endian"/>
1671     </condition>
1672
1673     <condition id="CM35P_GCC">
1674       <description>Cortex-M35P processor based device for the GCC Compiler</description>
1675       <require condition="CM35P"/>
1676       <require Tcompiler="GCC"/>
1677     </condition>
1678     <condition id="CM35P_LE_GCC">
1679       <description>Cortex-M35P processor based device in little endian mode for the GCC Compiler</description>
1680       <require condition="CM35P_GCC"/>
1681       <require Dendian="Little-endian"/>
1682     </condition>
1683     <condition id="CM35P_BE_GCC">
1684       <description>Cortex-M35P processor based device in big endian mode for the GCC Compiler</description>
1685       <require condition="CM35P_GCC"/>
1686       <require Dendian="Big-endian"/>
1687     </condition>
1688
1689     <condition id="CM35P_FP_GCC">
1690       <description>Cortex-M35P processor based device using Floating Point Unit for the GCC Compiler</description>
1691       <require condition="CM35P_FP"/>
1692       <require Tcompiler="GCC"/>
1693     </condition>
1694     <condition id="CM35P_FP_LE_GCC">
1695       <description>Cortex-M35P processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
1696       <require condition="CM35P_FP_GCC"/>
1697       <require Dendian="Little-endian"/>
1698     </condition>
1699     <condition id="CM35P_FP_BE_GCC">
1700       <description>Cortex-M35P processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
1701       <require condition="CM35P_FP_GCC"/>
1702       <require Dendian="Big-endian"/>
1703     </condition>
1704
1705     <condition id="CM35P_NODSP_NOFPU_GCC">
1706       <description>CM35P, no DSP, no FPU, GCC Compiler</description>
1707       <require condition="CM35P_NODSP_NOFPU"/>
1708       <require Tcompiler="GCC"/>
1709     </condition>
1710     <condition id="CM35P_DSP_NOFPU_GCC">
1711       <description>CM35P, DSP, no FPU, GCC Compiler</description>
1712       <require condition="CM35P_DSP_NOFPU"/>
1713       <require Tcompiler="GCC"/>
1714     </condition>
1715     <condition id="CM35P_NODSP_SP_GCC">
1716       <description>CM35P, no DSP, SP FPU, GCC Compiler</description>
1717       <require condition="CM35P_NODSP_SP"/>
1718       <require Tcompiler="GCC"/>
1719     </condition>
1720     <condition id="CM35P_DSP_SP_GCC">
1721       <description>CM35P, DSP, SP FPU, GCC Compiler</description>
1722       <require condition="CM35P_DSP_SP"/>
1723       <require Tcompiler="GCC"/>
1724     </condition>
1725     <condition id="CM35P_NODSP_NOFPU_LE_GCC">
1726       <description>CM35P, little endian, no DSP, no FPU, GCC Compiler</description>
1727       <require condition="CM35P_NODSP_NOFPU_GCC"/>
1728       <require Dendian="Little-endian"/>
1729     </condition>
1730     <condition id="CM35P_DSP_NOFPU_LE_GCC">
1731       <description>CM35P, little endian, DSP, no FPU, GCC Compiler</description>
1732       <require condition="CM35P_DSP_NOFPU_GCC"/>
1733       <require Dendian="Little-endian"/>
1734     </condition>
1735     <condition id="CM35P_NODSP_SP_LE_GCC">
1736       <description>CM35P, little endian, no DSP, SP FPU, GCC Compiler</description>
1737       <require condition="CM35P_NODSP_SP_GCC"/>
1738       <require Dendian="Little-endian"/>
1739     </condition>
1740     <condition id="CM35P_DSP_SP_LE_GCC">
1741       <description>CM35P, little endian, DSP, SP FPU, GCC Compiler</description>
1742       <require condition="CM35P_DSP_SP_GCC"/>
1743       <require Dendian="Little-endian"/>
1744     </condition>
1745
1746     <condition id="ARMv8MBL_GCC">
1747       <description>Armv8-M Baseline processor based device for the GCC Compiler</description>
1748       <require condition="ARMv8MBL"/>
1749       <require Tcompiler="GCC"/>
1750     </condition>
1751     <condition id="ARMv8MBL_LE_GCC">
1752       <description>Armv8-M Baseline processor based device in little endian mode for the GCC Compiler</description>
1753       <require condition="ARMv8MBL_GCC"/>
1754       <require Dendian="Little-endian"/>
1755     </condition>
1756     <condition id="ARMv8MBL_BE_GCC">
1757       <description>Armv8-M Baseline processor based device in big endian mode for the GCC Compiler</description>
1758       <require condition="ARMv8MBL_GCC"/>
1759       <require Dendian="Big-endian"/>
1760     </condition>
1761
1762     <condition id="ARMv8MML_GCC">
1763       <description>Armv8-M Mainline processor based device for the GCC Compiler</description>
1764       <require condition="ARMv8MML"/>
1765       <require Tcompiler="GCC"/>
1766     </condition>
1767     <condition id="ARMv8MML_LE_GCC">
1768       <description>Armv8-M Mainline processor based device in little endian mode for the GCC Compiler</description>
1769       <require condition="ARMv8MML_GCC"/>
1770       <require Dendian="Little-endian"/>
1771     </condition>
1772     <condition id="ARMv8MML_BE_GCC">
1773       <description>Armv8-M Mainline processor based device in big endian mode for the GCC Compiler</description>
1774       <require condition="ARMv8MML_GCC"/>
1775       <require Dendian="Big-endian"/>
1776     </condition>
1777
1778     <condition id="ARMv8MML_FP_GCC">
1779       <description>Armv8-M Mainline processor based device using Floating Point Unit for the GCC Compiler</description>
1780       <require condition="ARMv8MML_FP"/>
1781       <require Tcompiler="GCC"/>
1782     </condition>
1783     <condition id="ARMv8MML_FP_LE_GCC">
1784       <description>Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the GCC Compiler</description>
1785       <require condition="ARMv8MML_FP_GCC"/>
1786       <require Dendian="Little-endian"/>
1787     </condition>
1788     <condition id="ARMv8MML_FP_BE_GCC">
1789       <description>Armv8-M Mainline processor based device using Floating Point Unit in big endian mode for the GCC Compiler</description>
1790       <require condition="ARMv8MML_FP_GCC"/>
1791       <require Dendian="Big-endian"/>
1792     </condition>
1793
1794     <condition id="ARMv8MML_NODSP_NOFPU_GCC">
1795       <description>Armv8-M Mainline, no DSP, no FPU, GCC Compiler</description>
1796       <require condition="ARMv8MML_NODSP_NOFPU"/>
1797       <require Tcompiler="GCC"/>
1798     </condition>
1799     <condition id="ARMv8MML_DSP_NOFPU_GCC">
1800       <description>Armv8-M Mainline, DSP, no FPU, GCC Compiler</description>
1801       <require condition="ARMv8MML_DSP_NOFPU"/>
1802       <require Tcompiler="GCC"/>
1803     </condition>
1804     <condition id="ARMv8MML_NODSP_SP_GCC">
1805       <description>Armv8-M Mainline, no DSP, SP FPU, GCC Compiler</description>
1806       <require condition="ARMv8MML_NODSP_SP"/>
1807       <require Tcompiler="GCC"/>
1808     </condition>
1809     <condition id="ARMv8MML_DSP_SP_GCC">
1810       <description>Armv8-M Mainline, DSP, SP FPU, GCC Compiler</description>
1811       <require condition="ARMv8MML_DSP_SP"/>
1812       <require Tcompiler="GCC"/>
1813     </condition>
1814     <condition id="ARMv8MML_NODSP_NOFPU_LE_GCC">
1815       <description>Armv8-M Mainline, little endian, no DSP, no FPU, GCC Compiler</description>
1816       <require condition="ARMv8MML_NODSP_NOFPU_GCC"/>
1817       <require Dendian="Little-endian"/>
1818     </condition>
1819     <condition id="ARMv8MML_DSP_NOFPU_LE_GCC">
1820       <description>Armv8-M Mainline, little endian, DSP, no FPU, GCC Compiler</description>
1821       <require condition="ARMv8MML_DSP_NOFPU_GCC"/>
1822       <require Dendian="Little-endian"/>
1823     </condition>
1824     <condition id="ARMv8MML_NODSP_SP_LE_GCC">
1825       <description>Armv8-M Mainline, little endian, no DSP, SP FPU, GCC Compiler</description>
1826       <require condition="ARMv8MML_NODSP_SP_GCC"/>
1827       <require Dendian="Little-endian"/>
1828     </condition>
1829     <condition id="ARMv8MML_DSP_SP_LE_GCC">
1830       <description>Armv8-M Mainline, little endian, DSP, SP FPU, GCC Compiler</description>
1831       <require condition="ARMv8MML_DSP_SP_GCC"/>
1832       <require Dendian="Little-endian"/>
1833     </condition>
1834
1835     <!-- IAR compiler -->
1836     <condition id="CA_IAR">
1837       <description>Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the IAR Compiler</description>
1838       <require condition="ARMv7-A Device"/>
1839       <require Tcompiler="IAR"/>
1840     </condition>
1841
1842     <condition id="CM0_IAR">
1843       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device for the IAR Compiler</description>
1844       <require condition="CM0"/>
1845       <require Tcompiler="IAR"/>
1846     </condition>
1847     <condition id="CM0_LE_IAR">
1848       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in little endian mode for the IAR Compiler</description>
1849       <require condition="CM0_IAR"/>
1850       <require Dendian="Little-endian"/>
1851     </condition>
1852     <condition id="CM0_BE_IAR">
1853       <description>Cortex-M0 or Cortex-M0+ or SC000 processor based device in big endian mode for the IAR Compiler</description>
1854       <require condition="CM0_IAR"/>
1855       <require Dendian="Big-endian"/>
1856     </condition>
1857
1858     <condition id="CM1_IAR">
1859       <description>Cortex-M1 based device for the IAR Compiler</description>
1860       <require condition="CM1"/>
1861       <require Tcompiler="IAR"/>
1862     </condition>
1863     <condition id="CM1_LE_IAR">
1864       <description>Cortex-M1 based device in little endian mode for the IAR Compiler</description>
1865       <require condition="CM1_IAR"/>
1866       <require Dendian="Little-endian"/>
1867     </condition>
1868     <condition id="CM1_BE_IAR">
1869       <description>Cortex-M1 based device in big endian mode for the IAR Compiler</description>
1870       <require condition="CM1_IAR"/>
1871       <require Dendian="Big-endian"/>
1872     </condition>
1873
1874     <condition id="CM3_IAR">
1875       <description>Cortex-M3 or SC300 processor based device for the IAR Compiler</description>
1876       <require condition="CM3"/>
1877       <require Tcompiler="IAR"/>
1878     </condition>
1879     <condition id="CM3_LE_IAR">
1880       <description>Cortex-M3 or SC300 processor based device in little endian mode for the IAR Compiler</description>
1881       <require condition="CM3_IAR"/>
1882       <require Dendian="Little-endian"/>
1883     </condition>
1884     <condition id="CM3_BE_IAR">
1885       <description>Cortex-M3 or SC300 processor based device in big endian mode for the IAR Compiler</description>
1886       <require condition="CM3_IAR"/>
1887       <require Dendian="Big-endian"/>
1888     </condition>
1889
1890     <condition id="CM4_IAR">
1891       <description>Cortex-M4 processor based device for the IAR Compiler</description>
1892       <require condition="CM4"/>
1893       <require Tcompiler="IAR"/>
1894     </condition>
1895     <condition id="CM4_LE_IAR">
1896       <description>Cortex-M4 processor based device in little endian mode for the IAR Compiler</description>
1897       <require condition="CM4_IAR"/>
1898       <require Dendian="Little-endian"/>
1899     </condition>
1900     <condition id="CM4_BE_IAR">
1901       <description>Cortex-M4 processor based device in big endian mode for the IAR Compiler</description>
1902       <require condition="CM4_IAR"/>
1903       <require Dendian="Big-endian"/>
1904     </condition>
1905
1906     <condition id="CM4_FP_IAR">
1907       <description>Cortex-M4 processor based device using Floating Point Unit for the IAR Compiler</description>
1908       <require condition="CM4_FP"/>
1909       <require Tcompiler="IAR"/>
1910     </condition>
1911     <condition id="CM4_FP_LE_IAR">
1912       <description>Cortex-M4 processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
1913       <require condition="CM4_FP_IAR"/>
1914       <require Dendian="Little-endian"/>
1915     </condition>
1916     <condition id="CM4_FP_BE_IAR">
1917       <description>Cortex-M4 processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
1918       <require condition="CM4_FP_IAR"/>
1919       <require Dendian="Big-endian"/>
1920     </condition>
1921
1922     <condition id="CM7_IAR">
1923       <description>Cortex-M7 processor based device for the IAR Compiler</description>
1924       <require condition="CM7"/>
1925       <require Tcompiler="IAR"/>
1926     </condition>
1927     <condition id="CM7_LE_IAR">
1928       <description>Cortex-M7 processor based device in little endian mode for the IAR Compiler</description>
1929       <require condition="CM7_IAR"/>
1930       <require Dendian="Little-endian"/>
1931     </condition>
1932     <condition id="CM7_BE_IAR">
1933       <description>Cortex-M7 processor based device in big endian mode for the IAR Compiler</description>
1934       <require condition="CM7_IAR"/>
1935       <require Dendian="Big-endian"/>
1936     </condition>
1937
1938     <condition id="CM7_FP_IAR">
1939       <description>Cortex-M7 processor based device using Floating Point Unit for the IAR Compiler</description>
1940       <require condition="CM7_FP"/>
1941       <require Tcompiler="IAR"/>
1942     </condition>
1943     <condition id="CM7_FP_LE_IAR">
1944       <description>Cortex-M7 processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
1945       <require condition="CM7_FP_IAR"/>
1946       <require Dendian="Little-endian"/>
1947     </condition>
1948     <condition id="CM7_FP_BE_IAR">
1949       <description>Cortex-M7 processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
1950       <require condition="CM7_FP_IAR"/>
1951       <require Dendian="Big-endian"/>
1952     </condition>
1953
1954     <condition id="CM7_SP_IAR">
1955       <description>Cortex-M7 processor based device using Floating Point Unit (SP) for the IAR Compiler</description>
1956       <require condition="CM7_SP"/>
1957       <require Tcompiler="IAR"/>
1958     </condition>
1959     <condition id="CM7_SP_LE_IAR">
1960       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in little endian mode for the IAR Compiler</description>
1961       <require condition="CM7_SP_IAR"/>
1962       <require Dendian="Little-endian"/>
1963     </condition>
1964     <condition id="CM7_SP_BE_IAR">
1965       <description>Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the IAR Compiler</description>
1966       <require condition="CM7_SP_IAR"/>
1967       <require Dendian="Big-endian"/>
1968     </condition>
1969
1970     <condition id="CM7_DP_IAR">
1971       <description>Cortex-M7 processor based device using Floating Point Unit (DP) for the IAR Compiler</description>
1972       <require condition="CM7_DP"/>
1973       <require Tcompiler="IAR"/>
1974     </condition>
1975     <condition id="CM7_DP_LE_IAR">
1976       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in little endian mode for the IAR Compiler</description>
1977       <require condition="CM7_DP_IAR"/>
1978       <require Dendian="Little-endian"/>
1979     </condition>
1980     <condition id="CM7_DP_BE_IAR">
1981       <description>Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the IAR Compiler</description>
1982       <require condition="CM7_DP_IAR"/>
1983       <require Dendian="Big-endian"/>
1984     </condition>
1985
1986     <condition id="CM23_IAR">
1987       <description>Cortex-M23 processor based device for the IAR Compiler</description>
1988       <require condition="CM23"/>
1989       <require Tcompiler="IAR"/>
1990     </condition>
1991     <condition id="CM23_LE_IAR">
1992       <description>Cortex-M23 processor based device in little endian mode for the IAR Compiler</description>
1993       <require condition="CM23_IAR"/>
1994       <require Dendian="Little-endian"/>
1995     </condition>
1996     <condition id="CM23_BE_IAR">
1997       <description>Cortex-M23 processor based device in big endian mode for the IAR Compiler</description>
1998       <require condition="CM23_IAR"/>
1999       <require Dendian="Big-endian"/>
2000     </condition>
2001
2002     <condition id="CM33_IAR">
2003       <description>Cortex-M33 processor based device for the IAR Compiler</description>
2004       <require condition="CM33"/>
2005       <require Tcompiler="IAR"/>
2006     </condition>
2007     <condition id="CM33_LE_IAR">
2008       <description>Cortex-M33 processor based device in little endian mode for the IAR Compiler</description>
2009       <require condition="CM33_IAR"/>
2010       <require Dendian="Little-endian"/>
2011     </condition>
2012     <condition id="CM33_BE_IAR">
2013       <description>Cortex-M33 processor based device in big endian mode for the IAR Compiler</description>
2014       <require condition="CM33_IAR"/>
2015       <require Dendian="Big-endian"/>
2016     </condition>
2017
2018     <condition id="CM33_FP_IAR">
2019       <description>Cortex-M33 processor based device using Floating Point Unit for the IAR Compiler</description>
2020       <require condition="CM33_FP"/>
2021       <require Tcompiler="IAR"/>
2022     </condition>
2023     <condition id="CM33_FP_LE_IAR">
2024       <description>Cortex-M33 processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
2025       <require condition="CM33_FP_IAR"/>
2026       <require Dendian="Little-endian"/>
2027     </condition>
2028     <condition id="CM33_FP_BE_IAR">
2029       <description>Cortex-M33 processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
2030       <require condition="CM33_FP_IAR"/>
2031       <require Dendian="Big-endian"/>
2032     </condition>
2033
2034     <condition id="CM33_NODSP_NOFPU_IAR">
2035       <description>CM33, no DSP, no FPU, IAR Compiler</description>
2036       <require condition="CM33_NODSP_NOFPU"/>
2037       <require Tcompiler="IAR"/>
2038     </condition>
2039     <condition id="CM33_DSP_NOFPU_IAR">
2040       <description>CM33, DSP, no FPU, IAR Compiler</description>
2041       <require condition="CM33_DSP_NOFPU"/>
2042       <require Tcompiler="IAR"/>
2043     </condition>
2044     <condition id="CM33_NODSP_SP_IAR">
2045       <description>CM33, no DSP, SP FPU, IAR Compiler</description>
2046       <require condition="CM33_NODSP_SP"/>
2047       <require Tcompiler="IAR"/>
2048     </condition>
2049     <condition id="CM33_DSP_SP_IAR">
2050       <description>CM33, DSP, SP FPU, IAR Compiler</description>
2051       <require condition="CM33_DSP_SP"/>
2052       <require Tcompiler="IAR"/>
2053     </condition>
2054     <condition id="CM33_NODSP_NOFPU_LE_IAR">
2055       <description>CM33, little endian, no DSP, no FPU, IAR Compiler</description>
2056       <require condition="CM33_NODSP_NOFPU_IAR"/>
2057       <require Dendian="Little-endian"/>
2058     </condition>
2059     <condition id="CM33_DSP_NOFPU_LE_IAR">
2060       <description>CM33, little endian, DSP, no FPU, IAR Compiler</description>
2061       <require condition="CM33_DSP_NOFPU_IAR"/>
2062       <require Dendian="Little-endian"/>
2063     </condition>
2064     <condition id="CM33_NODSP_SP_LE_IAR">
2065       <description>CM33, little endian, no DSP, SP FPU, IAR Compiler</description>
2066       <require condition="CM33_NODSP_SP_IAR"/>
2067       <require Dendian="Little-endian"/>
2068     </condition>
2069     <condition id="CM33_DSP_SP_LE_IAR">
2070       <description>CM33, little endian, DSP, SP FPU, IAR Compiler</description>
2071       <require condition="CM33_DSP_SP_IAR"/>
2072       <require Dendian="Little-endian"/>
2073     </condition>
2074
2075     <condition id="CM35P_IAR">
2076       <description>Cortex-M35P processor based device for the IAR Compiler</description>
2077       <require condition="CM35P"/>
2078       <require Tcompiler="IAR"/>
2079     </condition>
2080     <condition id="CM35P_LE_IAR">
2081       <description>Cortex-M35P processor based device in little endian mode for the IAR Compiler</description>
2082       <require condition="CM35P_IAR"/>
2083       <require Dendian="Little-endian"/>
2084     </condition>
2085     <condition id="CM35P_BE_IAR">
2086       <description>Cortex-M35P processor based device in big endian mode for the IAR Compiler</description>
2087       <require condition="CM35P_IAR"/>
2088       <require Dendian="Big-endian"/>
2089     </condition>
2090
2091     <condition id="CM35P_FP_IAR">
2092       <description>Cortex-M35P processor based device using Floating Point Unit for the IAR Compiler</description>
2093       <require condition="CM35P_FP"/>
2094       <require Tcompiler="IAR"/>
2095     </condition>
2096     <condition id="CM35P_FP_LE_IAR">
2097       <description>Cortex-M35P processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
2098       <require condition="CM35P_FP_IAR"/>
2099       <require Dendian="Little-endian"/>
2100     </condition>
2101     <condition id="CM35P_FP_BE_IAR">
2102       <description>Cortex-M35P processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
2103       <require condition="CM35P_FP_IAR"/>
2104       <require Dendian="Big-endian"/>
2105     </condition>
2106
2107     <condition id="CM35P_NODSP_NOFPU_IAR">
2108       <description>CM35P, no DSP, no FPU, IAR Compiler</description>
2109       <require condition="CM35P_NODSP_NOFPU"/>
2110       <require Tcompiler="IAR"/>
2111     </condition>
2112     <condition id="CM35P_DSP_NOFPU_IAR">
2113       <description>CM35P, DSP, no FPU, IAR Compiler</description>
2114       <require condition="CM35P_DSP_NOFPU"/>
2115       <require Tcompiler="IAR"/>
2116     </condition>
2117     <condition id="CM35P_NODSP_SP_IAR">
2118       <description>CM35P, no DSP, SP FPU, IAR Compiler</description>
2119       <require condition="CM35P_NODSP_SP"/>
2120       <require Tcompiler="IAR"/>
2121     </condition>
2122     <condition id="CM35P_DSP_SP_IAR">
2123       <description>CM35P, DSP, SP FPU, IAR Compiler</description>
2124       <require condition="CM35P_DSP_SP"/>
2125       <require Tcompiler="IAR"/>
2126     </condition>
2127     <condition id="CM35P_NODSP_NOFPU_LE_IAR">
2128       <description>CM35P, little endian, no DSP, no FPU, IAR Compiler</description>
2129       <require condition="CM35P_NODSP_NOFPU_IAR"/>
2130       <require Dendian="Little-endian"/>
2131     </condition>
2132     <condition id="CM35P_DSP_NOFPU_LE_IAR">
2133       <description>CM35P, little endian, DSP, no FPU, IAR Compiler</description>
2134       <require condition="CM35P_DSP_NOFPU_IAR"/>
2135       <require Dendian="Little-endian"/>
2136     </condition>
2137     <condition id="CM35P_NODSP_SP_LE_IAR">
2138       <description>CM35P, little endian, no DSP, SP FPU, IAR Compiler</description>
2139       <require condition="CM35P_NODSP_SP_IAR"/>
2140       <require Dendian="Little-endian"/>
2141     </condition>
2142     <condition id="CM35P_DSP_SP_LE_IAR">
2143       <description>CM35P, little endian, DSP, SP FPU, IAR Compiler</description>
2144       <require condition="CM35P_DSP_SP_IAR"/>
2145       <require Dendian="Little-endian"/>
2146     </condition>
2147
2148     <condition id="ARMv8MBL_IAR">
2149       <description>Armv8-M Baseline processor based device for the IAR Compiler</description>
2150       <require condition="ARMv8MBL"/>
2151       <require Tcompiler="IAR"/>
2152     </condition>
2153     <condition id="ARMv8MBL_LE_IAR">
2154       <description>Armv8-M Baseline processor based device in little endian mode for the IAR Compiler</description>
2155       <require condition="ARMv8MBL_IAR"/>
2156       <require Dendian="Little-endian"/>
2157     </condition>
2158     <condition id="ARMv8MBL_BE_IAR">
2159       <description>Armv8-M Baseline processor based device in big endian mode for the IAR Compiler</description>
2160       <require condition="ARMv8MBL_IAR"/>
2161       <require Dendian="Big-endian"/>
2162     </condition>
2163
2164     <condition id="ARMv8MML_IAR">
2165       <description>Armv8-M Mainline processor based device for the IAR Compiler</description>
2166       <require condition="ARMv8MML"/>
2167       <require Tcompiler="IAR"/>
2168     </condition>
2169     <condition id="ARMv8MML_LE_IAR">
2170       <description>Armv8-M Mainline processor based device in little endian mode for the IAR Compiler</description>
2171       <require condition="ARMv8MML_IAR"/>
2172       <require Dendian="Little-endian"/>
2173     </condition>
2174     <condition id="ARMv8MML_BE_IAR">
2175       <description>Armv8-M Mainline processor based device in big endian mode for the IAR Compiler</description>
2176       <require condition="ARMv8MML_IAR"/>
2177       <require Dendian="Big-endian"/>
2178     </condition>
2179
2180     <condition id="ARMv8MML_FP_IAR">
2181       <description>Armv8-M Mainline processor based device using Floating Point Unit for the IAR Compiler</description>
2182       <require condition="ARMv8MML_FP"/>
2183       <require Tcompiler="IAR"/>
2184     </condition>
2185     <condition id="ARMv8MML_FP_LE_IAR">
2186       <description>Armv8-M Mainline processor based device using Floating Point Unit in little endian mode for the IAR Compiler</description>
2187       <require condition="ARMv8MML_FP_IAR"/>
2188       <require Dendian="Little-endian"/>
2189     </condition>
2190     <condition id="ARMv8MML_FP_BE_IAR">
2191       <description>Armv8-M Mainline processor based device using Floating Point Unit in big endian mode for the IAR Compiler</description>
2192       <require condition="ARMv8MML_FP_IAR"/>
2193       <require Dendian="Big-endian"/>
2194     </condition>
2195
2196     <condition id="ARMv8MML_NODSP_NOFPU_IAR">
2197       <description>Armv8-M Mainline, no DSP, no FPU, IAR Compiler</description>
2198       <require condition="ARMv8MML_NODSP_NOFPU"/>
2199       <require Tcompiler="IAR"/>
2200     </condition>
2201     <condition id="ARMv8MML_DSP_NOFPU_IAR">
2202       <description>Armv8-M Mainline, DSP, no FPU, IAR Compiler</description>
2203       <require condition="ARMv8MML_DSP_NOFPU"/>
2204       <require Tcompiler="IAR"/>
2205     </condition>
2206     <condition id="ARMv8MML_NODSP_SP_IAR">
2207       <description>Armv8-M Mainline, no DSP, SP FPU, IAR Compiler</description>
2208       <require condition="ARMv8MML_NODSP_SP"/>
2209       <require Tcompiler="IAR"/>
2210     </condition>
2211     <condition id="ARMv8MML_DSP_SP_IAR">
2212       <description>Armv8-M Mainline, DSP, SP FPU, IAR Compiler</description>
2213       <require condition="ARMv8MML_DSP_SP"/>
2214       <require Tcompiler="IAR"/>
2215     </condition>
2216     <condition id="ARMv8MML_NODSP_NOFPU_LE_IAR">
2217       <description>Armv8-M Mainline, little endian, no DSP, no FPU, IAR Compiler</description>
2218       <require condition="ARMv8MML_NODSP_NOFPU_IAR"/>
2219       <require Dendian="Little-endian"/>
2220     </condition>
2221     <condition id="ARMv8MML_DSP_NOFPU_LE_IAR">
2222       <description>Armv8-M Mainline, little endian, DSP, no FPU, IAR Compiler</description>
2223       <require condition="ARMv8MML_DSP_NOFPU_IAR"/>
2224       <require Dendian="Little-endian"/>
2225     </condition>
2226     <condition id="ARMv8MML_NODSP_SP_LE_IAR">
2227       <description>Armv8-M Mainline, little endian, no DSP, SP FPU, IAR Compiler</description>
2228       <require condition="ARMv8MML_NODSP_SP_IAR"/>
2229       <require Dendian="Little-endian"/>
2230     </condition>
2231     <condition id="ARMv8MML_DSP_SP_LE_IAR">
2232       <description>Armv8-M Mainline, little endian, DSP, SP FPU, IAR Compiler</description>
2233       <require condition="ARMv8MML_DSP_SP_IAR"/>
2234       <require Dendian="Little-endian"/>
2235     </condition>
2236
2237     <!-- conditions selecting single devices and CMSIS Core -->
2238     <!-- used for component startup, GCC version is used for C-Startup -->
2239     <condition id="ARMCM0 CMSIS">
2240       <description>Generic Arm Cortex-M0 device startup and depends on CMSIS Core</description>
2241       <require Dvendor="ARM:82" Dname="ARMCM0"/>
2242       <require Cclass="CMSIS" Cgroup="CORE"/>
2243     </condition>
2244     <condition id="ARMCM0 CMSIS GCC">
2245       <description>Generic ARM Cortex-M0 device startup and depends on CMSIS Core requiring GCC</description>
2246       <require condition="ARMCM0 CMSIS"/>
2247       <require condition="GCC"/>
2248     </condition>
2249
2250     <condition id="ARMCM0+ CMSIS">
2251       <description>Generic Arm Cortex-M0+ device startup and depends on CMSIS Core</description>
2252       <require Dvendor="ARM:82" Dname="ARMCM0P*"/>
2253       <require Cclass="CMSIS" Cgroup="CORE"/>
2254     </condition>
2255     <condition id="ARMCM0+ CMSIS GCC">
2256       <description>Generic Arm Cortex-M0+ device startup and depends CMSIS Core requiring GCC</description>
2257       <require condition="ARMCM0+ CMSIS"/>
2258       <require condition="GCC"/>
2259     </condition>
2260
2261     <condition id="ARMCM1 CMSIS">
2262       <description>Generic Arm Cortex-M1 device startup and depends on CMSIS Core</description>
2263       <require Dvendor="ARM:82" Dname="ARMCM1"/>
2264       <require Cclass="CMSIS" Cgroup="CORE"/>
2265     </condition>
2266     <condition id="ARMCM1 CMSIS GCC">
2267       <description>Generic ARM Cortex-M1 device startup and depends on CMSIS Core requiring GCC</description>
2268       <require condition="ARMCM1 CMSIS"/>
2269       <require condition="GCC"/>
2270     </condition>
2271
2272     <condition id="ARMCM3 CMSIS">
2273       <description>Generic Arm Cortex-M3 device startup and depends on CMSIS Core</description>
2274       <require Dvendor="ARM:82" Dname="ARMCM3"/>
2275       <require Cclass="CMSIS" Cgroup="CORE"/>
2276     </condition>
2277     <condition id="ARMCM3 CMSIS GCC">
2278       <description>Generic Arm Cortex-M3 device startup and depends on CMSIS Core requiring GCC</description>
2279       <require condition="ARMCM3 CMSIS"/>
2280       <require condition="GCC"/>
2281     </condition>
2282
2283     <condition id="ARMCM4 CMSIS">
2284       <description>Generic Arm Cortex-M4 device startup and depends on CMSIS Core</description>
2285       <require Dvendor="ARM:82" Dname="ARMCM4*"/>
2286       <require Cclass="CMSIS" Cgroup="CORE"/>
2287     </condition>
2288     <condition id="ARMCM4 CMSIS GCC">
2289       <description>Generic Arm Cortex-M4 device startup and depends on CMSIS Core requiring GCC</description>
2290       <require condition="ARMCM4 CMSIS"/>
2291       <require condition="GCC"/>
2292     </condition>
2293
2294     <condition id="ARMCM7 CMSIS">
2295       <description>Generic Arm Cortex-M7 device startup and depends on CMSIS Core</description>
2296       <require Dvendor="ARM:82" Dname="ARMCM7*"/>
2297       <require Cclass="CMSIS" Cgroup="CORE"/>
2298     </condition>
2299     <condition id="ARMCM7 CMSIS GCC">
2300       <description>Generic Arm Cortex-M7 device startup and depends on CMSIS Core requiring GCC</description>
2301       <require condition="ARMCM7 CMSIS"/>
2302       <require condition="GCC"/>
2303     </condition>
2304
2305     <condition id="ARMCM23 CMSIS">
2306       <description>Generic Arm Cortex-M23 device startup and depends on CMSIS Core</description>
2307       <require Dvendor="ARM:82" Dname="ARMCM23*"/>
2308       <require Cclass="CMSIS" Cgroup="CORE"/>
2309     </condition>
2310     <condition id="ARMCM23 CMSIS GCC">
2311       <description>Generic Arm Cortex-M23 device startup and depends on CMSIS Core requiring GCC</description>
2312       <require condition="ARMCM23 CMSIS"/>
2313       <require condition="GCC"/>
2314     </condition>
2315
2316     <condition id="ARMCM33 CMSIS">
2317       <description>Generic Arm Cortex-M33 device startup and depends on CMSIS Core</description>
2318       <require Dvendor="ARM:82" Dname="ARMCM33*"/>
2319       <require Cclass="CMSIS" Cgroup="CORE"/>
2320     </condition>
2321     <condition id="ARMCM33 CMSIS GCC">
2322       <description>Generic Arm Cortex-M33 device startup and depends on CMSIS Core requiring GCC</description>
2323       <require condition="ARMCM33 CMSIS"/>
2324       <require condition="GCC"/>
2325     </condition>
2326
2327     <condition id="ARMCM35P CMSIS">
2328       <description>Generic Arm Cortex-M35P device startup and depends on CMSIS Core</description>
2329       <require Dvendor="ARM:82" Dname="ARMCM35P*"/>
2330       <require Cclass="CMSIS" Cgroup="CORE"/>
2331     </condition>
2332     <condition id="ARMCM35P CMSIS GCC">
2333       <description>Generic Arm Cortex-M35P device startup and depends on CMSIS Core requiring GCC</description>
2334       <require condition="ARMCM35P CMSIS"/>
2335       <require condition="GCC"/>
2336     </condition>
2337
2338     <condition id="ARMSC000 CMSIS">
2339       <description>Generic Arm SC000 device startup and depends on CMSIS Core</description>
2340       <require Dvendor="ARM:82" Dname="ARMSC000"/>
2341       <require Cclass="CMSIS" Cgroup="CORE"/>
2342     </condition>
2343     <condition id="ARMSC000 CMSIS GCC">
2344       <description>Generic Arm SC000 device startup and depends on CMSIS Core requiring GCC</description>
2345       <require condition="ARMSC000 CMSIS"/>
2346       <require condition="GCC"/>
2347     </condition>
2348
2349     <condition id="ARMSC300 CMSIS">
2350       <description>Generic Arm SC300 device startup and depends on CMSIS Core</description>
2351       <require Dvendor="ARM:82" Dname="ARMSC300"/>
2352       <require Cclass="CMSIS" Cgroup="CORE"/>
2353     </condition>
2354     <condition id="ARMSC300 CMSIS GCC">
2355       <description>Generic Arm SC300 device startup and dependson CMSIS Core requiring GCC</description>
2356       <require condition="ARMSC300 CMSIS"/>
2357       <require condition="GCC"/>
2358     </condition>
2359
2360     <condition id="ARMv8MBL CMSIS">
2361       <description>Generic Armv8-M Baseline device startup and depends on CMSIS Core</description>
2362       <require Dvendor="ARM:82" Dname="ARMv8MBL"/>
2363       <require Cclass="CMSIS" Cgroup="CORE"/>
2364     </condition>
2365     <condition id="ARMv8MBL CMSIS GCC">
2366       <description>Generic Armv8-M Baseline device startup and depends on CMSIS Core requiring GCC</description>
2367       <require condition="ARMv8MBL CMSIS"/>
2368       <require condition="GCC"/>
2369     </condition>
2370
2371     <condition id="ARMv8MML CMSIS">
2372       <description>Generic Armv8-M Mainline device startup and depends on CMSIS Core</description>
2373       <require Dvendor="ARM:82" Dname="ARMv8MML*"/>
2374       <require Cclass="CMSIS" Cgroup="CORE"/>
2375     </condition>
2376     <condition id="ARMv8MML CMSIS GCC">
2377       <description>Generic Armv8-M Mainline device startup and depends on CMSIS Core requiring GCC</description>
2378       <require condition="ARMv8MML CMSIS"/>
2379       <require condition="GCC"/>
2380     </condition>
2381
2382     <condition id="ARMCA5 CMSIS">
2383       <description>Generic Arm Cortex-A5 device startup and depends on CMSIS Core</description>
2384       <require Dvendor="ARM:82" Dname="ARMCA5"/>
2385       <require Cclass="CMSIS" Cgroup="CORE"/>
2386     </condition>
2387
2388     <condition id="ARMCA7 CMSIS">
2389       <description>Generic Arm Cortex-A7 device startup and depends on CMSIS Core</description>
2390       <require Dvendor="ARM:82" Dname="ARMCA7"/>
2391       <require Cclass="CMSIS" Cgroup="CORE"/>
2392     </condition>
2393
2394     <condition id="ARMCA9 CMSIS">
2395       <description>Generic Arm Cortex-A9 device startup and depends on CMSIS Core</description>
2396       <require Dvendor="ARM:82" Dname="ARMCA9"/>
2397       <require Cclass="CMSIS" Cgroup="CORE"/>
2398     </condition>
2399
2400     <!-- CMSIS DSP -->
2401     <condition id="CMSIS DSP">
2402       <description>Components required for DSP</description>
2403       <require condition="ARMv6_7_8-M Device"/>
2404       <require condition="ARMCC GCC IAR"/>
2405       <require Cclass="CMSIS" Cgroup="CORE"/>
2406     </condition>
2407
2408     <!-- CMSIS NN -->
2409     <condition id="CMSIS NN">
2410       <description>Components required for NN</description>
2411       <require condition="CMSIS DSP"/>
2412     </condition>
2413
2414     <!-- RTOS RTX -->
2415     <condition id="RTOS RTX">
2416       <description>Components required for RTOS RTX</description>
2417       <require condition="ARMv6_7-M Device"/>
2418       <require condition="ARMCC GCC IAR"/>
2419       <require Cclass="Device" Cgroup="Startup"/>
2420       <deny    Cclass="CMSIS"  Cgroup="RTOS2" Csub="Keil RTX5"/>
2421     </condition>
2422     <condition id="RTOS RTX IFX">
2423       <description>Components required for RTOS RTX IFX</description>
2424       <require condition="ARMv6_7-M Device"/>
2425       <require condition="ARMCC GCC IAR"/>
2426       <require Dvendor="Infineon:7" Dname="XMC4*"/>
2427       <require Cclass="Device" Cgroup="Startup"/>
2428       <deny    Cclass="CMSIS"  Cgroup="RTOS2" Csub="Keil RTX5"/>
2429     </condition>
2430     <condition id="RTOS RTX5">
2431       <description>Components required for RTOS RTX5</description>
2432       <require condition="ARMv6_7_8-M Device"/>
2433       <require condition="ARMCC GCC IAR"/>
2434       <require Cclass="CMSIS"  Cgroup="RTOS2" Csub="Keil RTX5"/>
2435     </condition>
2436     <condition id="RTOS2 RTX5">
2437       <description>Components required for RTOS2 RTX5</description>
2438       <require condition="ARMv6_7_8-M Device"/>
2439       <require condition="ARMCC GCC IAR"/>
2440       <require Cclass="CMSIS"  Cgroup="CORE"/>
2441       <require Cclass="Device" Cgroup="Startup"/>
2442     </condition>
2443     <condition id="RTOS2 RTX5 v7-A">
2444       <description>Components required for RTOS2 RTX5 on Armv7-A</description>
2445       <require condition="ARMv7-A Device"/>
2446       <require condition="ARMCC GCC IAR"/>
2447       <require Cclass="CMSIS"  Cgroup="CORE"/>
2448       <require Cclass="Device" Cgroup="Startup"/>
2449       <require Cclass="Device" Cgroup="OS Tick"/>
2450       <require Cclass="Device" Cgroup="IRQ Controller"/>
2451     </condition>
2452     <condition id="RTOS2 RTX5 Lib">
2453       <description>Components required for RTOS2 RTX5 Library</description>
2454       <require condition="ARMv6_7_8-M Device"/>
2455       <require condition="ARMCC GCC IAR"/>
2456       <require Cclass="CMSIS"  Cgroup="CORE"/>
2457       <require Cclass="Device" Cgroup="Startup"/>
2458     </condition>
2459     <condition id="RTOS2 RTX5 NS">
2460       <description>Components required for RTOS2 RTX5 in Non-Secure Domain</description>
2461       <require condition="ARMv8-M TZ Device"/>
2462       <require condition="ARMCC GCC IAR"/>
2463       <require Cclass="CMSIS"  Cgroup="CORE"/>
2464       <require Cclass="Device" Cgroup="Startup"/>
2465     </condition>
2466
2467     <!-- OS Tick -->
2468     <condition id="OS Tick PTIM">
2469       <description>Components required for OS Tick Private Timer</description>
2470       <require condition="CA5_CA9"/>
2471       <require Cclass="Device" Cgroup="IRQ Controller"/>
2472     </condition>
2473
2474     <condition id="OS Tick GTIM">
2475       <description>Components required for OS Tick Generic Physical Timer</description>
2476       <require condition="CA7"/>
2477       <require Cclass="Device" Cgroup="IRQ Controller"/>
2478     </condition>
2479
2480   </conditions>
2481
2482   <components>
2483     <!-- CMSIS-Core component -->
2484     <component Cclass="CMSIS" Cgroup="CORE" Cversion="5.1.2"  condition="ARMv6_7_8-M Device" >
2485       <description>CMSIS-CORE for Cortex-M, SC000, SC300, ARMv8-M</description>
2486       <files>
2487         <!-- CPU independent -->
2488         <file category="doc"     name="CMSIS/Documentation/Core/html/index.html"/>
2489         <file category="include" name="CMSIS/Core/Include/"/>
2490         <file category="header"  name="CMSIS/Core/Include/tz_context.h" condition="ARMv8-M TZ Device"/>
2491         <!-- Code template -->
2492         <file category="sourceC" attr="template" condition="ARMv8-M TZ Device" name="CMSIS/Core/Template/ARMv8-M/main_s.c"     version="1.1.0" select="Secure mode 'main' module for ARMv8-M"/>
2493         <file category="sourceC" attr="template" condition="ARMv8-M TZ Device" name="CMSIS/Core/Template/ARMv8-M/tz_context.c" version="1.1.0" select="RTOS Context Management (TrustZone for ARMv8-M)" />
2494       </files>
2495     </component>
2496
2497     <component Cclass="CMSIS" Cgroup="CORE" Cversion="1.1.2"  condition="ARMv7-A Device" >
2498       <description>CMSIS-CORE for Cortex-A</description>
2499       <files>
2500         <!-- CPU independent -->
2501         <file category="doc"     name="CMSIS/Documentation/Core_A/html/index.html"/>
2502         <file category="include" name="CMSIS/Core_A/Include/"/>
2503       </files>
2504     </component>
2505
2506     <!-- CMSIS-Startup components -->
2507     <!-- Cortex-M0 -->
2508     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM0 CMSIS">
2509       <description>System and Startup for Generic Arm Cortex-M0 device</description>
2510       <files>
2511         <!-- include folder / device header file -->
2512         <file category="header"  name="Device/ARM/ARMCM0/Include/ARMCM0.h"/>
2513         <!-- startup / system file -->
2514         <file category="sourceAsm"    name="Device/ARM/ARMCM0/Source/ARM/startup_ARMCM0.s" version="1.0.0" attr="config" condition="ARMCC"/>
2515         <file category="sourceAsm"    name="Device/ARM/ARMCM0/Source/GCC/startup_ARMCM0.S" version="1.0.0" attr="config" condition="GCC"/>
2516         <file category="linkerScript" name="Device/ARM/ARMCM0/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2517         <file category="sourceAsm"    name="Device/ARM/ARMCM0/Source/IAR/startup_ARMCM0.s" version="1.0.0" attr="config" condition="IAR"/>
2518         <file category="sourceC"      name="Device/ARM/ARMCM0/Source/system_ARMCM0.c"      version="1.0.0" attr="config"/>
2519       </files>
2520     </component>
2521     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM0 CMSIS GCC">
2522       <description>System and Startup for Generic Arm Cortex-M0 device</description>
2523       <files>
2524         <!-- include folder / device header file -->
2525         <file category="header"  name="Device/ARM/ARMCM0/Include/ARMCM0.h"/>
2526         <!-- startup / system file -->
2527         <file category="sourceC"      name="Device/ARM/ARMCM0/Source/GCC/startup_ARMCM0.c" version="1.0.0" attr="config" condition="GCC"/>
2528         <file category="linkerScript" name="Device/ARM/ARMCM0/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2529         <file category="sourceC"      name="Device/ARM/ARMCM0/Source/system_ARMCM0.c"      version="1.0.0" attr="config"/>
2530       </files>
2531     </component>
2532
2533     <!-- Cortex-M0+ -->
2534     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM0+ CMSIS">
2535       <description>System and Startup for Generic Arm Cortex-M0+ device</description>
2536       <files>
2537         <!-- include folder / device header file -->
2538         <file category="header"  name="Device/ARM/ARMCM0plus/Include/ARMCM0plus.h"/>
2539         <!-- startup / system file -->
2540         <file category="sourceAsm"    name="Device/ARM/ARMCM0plus/Source/ARM/startup_ARMCM0plus.s" version="1.0.0" attr="config" condition="ARMCC"/>
2541         <file category="sourceAsm"    name="Device/ARM/ARMCM0plus/Source/GCC/startup_ARMCM0plus.S" version="1.0.0" attr="config" condition="GCC"/>
2542         <file category="linkerScript" name="Device/ARM/ARMCM0plus/Source/GCC/gcc_arm.ld"           version="1.0.0" attr="config" condition="GCC"/>
2543         <file category="sourceAsm"    name="Device/ARM/ARMCM0plus/Source/IAR/startup_ARMCM0plus.s" version="1.0.0" attr="config" condition="IAR"/>
2544         <file category="sourceC"      name="Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c"      version="1.0.0" attr="config"/>
2545       </files>
2546     </component>
2547     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM0+ CMSIS GCC">
2548       <description>System and Startup for Generic Arm Cortex-M0+ device</description>
2549       <files>
2550         <!-- include folder / device header file -->
2551         <file category="header"  name="Device/ARM/ARMCM0plus/Include/ARMCM0plus.h"/>
2552         <!-- startup / system file -->
2553         <file category="sourceC"      name="Device/ARM/ARMCM0plus/Source/GCC/startup_ARMCM0plus.c" version="1.0.0" attr="config" condition="GCC"/>
2554         <file category="linkerScript" name="Device/ARM/ARMCM0plus/Source/GCC/gcc_arm.ld"           version="1.0.0" attr="config" condition="GCC"/>
2555         <file category="sourceC"      name="Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c"      version="1.0.0" attr="config"/>
2556       </files>
2557     </component>
2558
2559     <!-- Cortex-M1 -->
2560     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM1 CMSIS">
2561       <description>System and Startup for Generic Arm Cortex-M1 device</description>
2562       <files>
2563         <!-- include folder / device header file -->
2564         <file category="header"  name="Device/ARM/ARMCM1/Include/ARMCM1.h"/>
2565         <!-- startup / system file -->
2566         <file category="sourceAsm"    name="Device/ARM/ARMCM1/Source/ARM/startup_ARMCM1.s" version="1.0.0" attr="config" condition="ARMCC"/>
2567         <file category="sourceAsm"    name="Device/ARM/ARMCM1/Source/GCC/startup_ARMCM1.S" version="1.0.0" attr="config" condition="GCC"/>
2568         <file category="linkerScript" name="Device/ARM/ARMCM1/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2569         <file category="sourceAsm"    name="Device/ARM/ARMCM1/Source/IAR/startup_ARMCM1.s" version="1.0.0" attr="config" condition="IAR"/>
2570         <file category="sourceC"      name="Device/ARM/ARMCM1/Source/system_ARMCM1.c"      version="1.0.0" attr="config"/>
2571       </files>
2572     </component>
2573     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM1 CMSIS GCC">
2574       <description>System and Startup for Generic Arm Cortex-M1 device</description>
2575       <files>
2576         <!-- include folder / device header file -->
2577         <file category="header"  name="Device/ARM/ARMCM1/Include/ARMCM1.h"/>
2578         <!-- startup / system file -->
2579         <file category="sourceC"      name="Device/ARM/ARMCM1/Source/GCC/startup_ARMCM1.c" version="1.0.0" attr="config" condition="GCC"/>
2580         <file category="linkerScript" name="Device/ARM/ARMCM1/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2581         <file category="sourceC"      name="Device/ARM/ARMCM1/Source/system_ARMCM1.c"      version="1.0.0" attr="config"/>
2582       </files>
2583     </component>
2584
2585     <!-- Cortex-M3 -->
2586     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM3 CMSIS">
2587       <description>System and Startup for Generic Arm Cortex-M3 device</description>
2588       <files>
2589         <!-- include folder / device header file -->
2590         <file category="header"  name="Device/ARM/ARMCM3/Include/ARMCM3.h"/>
2591         <!-- startup / system file -->
2592         <file category="sourceAsm"    name="Device/ARM/ARMCM3/Source/ARM/startup_ARMCM3.s" version="1.0.0" attr="config" condition="ARMCC"/>
2593         <file category="sourceAsm"    name="Device/ARM/ARMCM3/Source/GCC/startup_ARMCM3.S" version="1.0.0" attr="config" condition="GCC"/>
2594         <file category="linkerScript" name="Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2595         <file category="sourceAsm"    name="Device/ARM/ARMCM3/Source/IAR/startup_ARMCM3.s" version="1.0.0" attr="config" condition="IAR"/>
2596         <file category="sourceC"      name="Device/ARM/ARMCM3/Source/system_ARMCM3.c"      version="1.0.0" attr="config"/>
2597       </files>
2598     </component>
2599     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM3 CMSIS GCC">
2600       <description>System and Startup for Generic Arm Cortex-M3 device</description>
2601       <files>
2602         <!-- include folder / device header file -->
2603         <file category="header"  name="Device/ARM/ARMCM3/Include/ARMCM3.h"/>
2604         <!-- startup / system file -->
2605         <file category="sourceC"      name="Device/ARM/ARMCM3/Source/GCC/startup_ARMCM3.c" version="1.0.0" attr="config" condition="GCC"/>
2606         <file category="linkerScript" name="Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2607         <file category="sourceC"      name="Device/ARM/ARMCM3/Source/system_ARMCM3.c"      version="1.0.0" attr="config"/>
2608       </files>
2609     </component>
2610
2611     <!-- Cortex-M4 -->
2612     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM4 CMSIS">
2613       <description>System and Startup for Generic Arm Cortex-M4 device</description>
2614       <files>
2615         <!-- include folder / device header file -->
2616         <file category="include" name="Device/ARM/ARMCM4/Include/"/>
2617         <!-- startup / system file -->
2618         <file category="sourceAsm"    name="Device/ARM/ARMCM4/Source/ARM/startup_ARMCM4.s" version="1.0.0" attr="config" condition="ARMCC"/>
2619         <file category="sourceAsm"    name="Device/ARM/ARMCM4/Source/GCC/startup_ARMCM4.S" version="1.0.0" attr="config" condition="GCC"/>
2620         <file category="linkerScript" name="Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2621         <file category="sourceAsm"    name="Device/ARM/ARMCM4/Source/IAR/startup_ARMCM4.s" version="1.0.0" attr="config" condition="IAR"/>
2622         <file category="sourceC"      name="Device/ARM/ARMCM4/Source/system_ARMCM4.c"      version="1.0.0" attr="config"/>
2623       </files>
2624     </component>
2625     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM4 CMSIS GCC">
2626       <description>System and Startup for Generic Arm Cortex-M4 device</description>
2627       <files>
2628         <!-- include folder / device header file -->
2629         <file category="include" name="Device/ARM/ARMCM4/Include/"/>
2630         <!-- startup / system file -->
2631         <file category="sourceC"      name="Device/ARM/ARMCM4/Source/GCC/startup_ARMCM4.c" version="1.0.0" attr="config" condition="GCC"/>
2632         <file category="linkerScript" name="Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2633         <file category="sourceC"      name="Device/ARM/ARMCM4/Source/system_ARMCM4.c"      version="1.0.0" attr="config"/>
2634       </files>
2635     </component>
2636
2637     <!-- Cortex-M7 -->
2638     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCM7 CMSIS">
2639       <description>System and Startup for Generic Arm Cortex-M7 device</description>
2640       <files>
2641         <!-- include folder / device header file -->
2642         <file category="include"  name="Device/ARM/ARMCM7/Include/"/>
2643         <!-- startup / system file -->
2644         <file category="sourceAsm"    name="Device/ARM/ARMCM7/Source/ARM/startup_ARMCM7.s" version="1.0.0" attr="config" condition="ARMCC"/>
2645         <file category="sourceAsm"    name="Device/ARM/ARMCM7/Source/GCC/startup_ARMCM7.S" version="1.0.0" attr="config" condition="GCC"/>
2646         <file category="linkerScript" name="Device/ARM/ARMCM7/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2647         <file category="sourceAsm"    name="Device/ARM/ARMCM7/Source/IAR/startup_ARMCM7.s" version="1.0.0" attr="config" condition="IAR"/>
2648         <file category="sourceC"      name="Device/ARM/ARMCM7/Source/system_ARMCM7.c"      version="1.0.0" attr="config"/>
2649       </files>
2650     </component>
2651     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMCM7 CMSIS GCC">
2652       <description>System and Startup for Generic Arm Cortex-M7 device</description>
2653       <files>
2654         <!-- include folder / device header file -->
2655         <file category="include"  name="Device/ARM/ARMCM7/Include/"/>
2656         <!-- startup / system file -->
2657         <file category="sourceC"      name="Device/ARM/ARMCM7/Source/GCC/startup_ARMCM7.c" version="1.0.0" attr="config" condition="GCC"/>
2658         <file category="linkerScript" name="Device/ARM/ARMCM7/Source/GCC/gcc_arm.ld"       version="1.0.0" attr="config" condition="GCC"/>
2659         <file category="sourceC"      name="Device/ARM/ARMCM7/Source/system_ARMCM7.c"      version="1.0.0" attr="config"/>
2660       </files>
2661     </component>
2662
2663     <!-- Cortex-M23 -->
2664     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.0" condition="ARMCM23 CMSIS">
2665       <description>System and Startup for Generic Arm Cortex-M23 device</description>
2666       <files>
2667         <!-- include folder / device header file -->
2668         <file category="include"      name="Device/ARM/ARMCM23/Include/"/>
2669         <!-- startup / system file -->
2670         <file category="sourceAsm"    name="Device/ARM/ARMCM23/Source/ARM/startup_ARMCM23.s" version="1.0.0" attr="config" condition="ARMCC"/>
2671         <file category="sourceAsm"    name="Device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.S" version="1.0.0" attr="config" condition="GCC"/>
2672         <file category="linkerScript" name="Device/ARM/ARMCM23/Source/GCC/gcc_arm.ld"        version="1.0.0" attr="config" condition="GCC"/>
2673         <file category="sourceAsm"    name="Device/ARM/ARMCM23/Source/IAR/startup_ARMCM23.s" version="1.0.0" attr="config" condition="IAR"/>
2674         <file category="sourceC"      name="Device/ARM/ARMCM23/Source/system_ARMCM23.c"      version="1.0.0" attr="config"/>
2675         <!-- SAU configuration -->
2676         <file category="header"       name="Device/ARM/ARMCM23/Include/Template/partition_ARMCM23.h" version="1.0.0" attr="config" condition="ARMv8-M TZ Device"/>
2677       </files>
2678     </component>
2679     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.0" condition="ARMCM23 CMSIS GCC">
2680       <description>System and Startup for Generic Arm Cortex-M23 device</description>
2681       <files>
2682         <!-- include folder / device header file -->
2683         <file category="include"  name="Device/ARM/ARMCM23/Include/"/>
2684         <!-- startup / system file -->
2685         <file category="sourceC"      name="Device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.c" version="1.0.0" attr="config" condition="GCC"/>
2686         <file category="linkerScript" name="Device/ARM/ARMCM23/Source/GCC/gcc_arm.ld"        version="1.0.0" attr="config" condition="GCC"/>
2687         <file category="sourceC"      name="Device/ARM/ARMCM23/Source/system_ARMCM23.c"      version="1.0.0" attr="config"/>
2688         <!-- SAU configuration -->
2689         <file category="header"       name="Device/ARM/ARMCM23/Include/Template/partition_ARMCM23.h" version="1.0.0" attr="config" condition="ARMv8-M TZ Device"/>
2690       </files>
2691     </component>
2692
2693     <!-- Cortex-M33 -->
2694     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.1.0" condition="ARMCM33 CMSIS">
2695       <description>System and Startup for Generic Arm Cortex-M33 device</description>
2696       <files>
2697         <!-- include folder / device header file -->
2698         <file category="include"      name="Device/ARM/ARMCM33/Include/"/>
2699         <!-- startup / system file -->
2700         <file category="sourceAsm"    name="Device/ARM/ARMCM33/Source/ARM/startup_ARMCM33.s"         version="1.0.0" attr="config" condition="ARMCC"/>
2701         <file category="sourceAsm"    name="Device/ARM/ARMCM33/Source/GCC/startup_ARMCM33.S"         version="1.0.0" attr="config" condition="GCC"/>
2702         <file category="linkerScript" name="Device/ARM/ARMCM33/Source/GCC/gcc_arm.ld"                version="1.0.0" attr="config" condition="GCC"/>
2703         <file category="sourceAsm"    name="Device/ARM/ARMCM33/Source/IAR/startup_ARMCM33.s"         version="1.0.0" attr="config" condition="IAR"/>
2704         <file category="sourceC"      name="Device/ARM/ARMCM33/Source/system_ARMCM33.c"              version="1.0.0" attr="config"/>
2705         <!-- SAU configuration -->
2706         <file category="header"       name="Device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2707       </files>
2708     </component>
2709     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.1.0" condition="ARMCM33 CMSIS GCC">
2710       <description>System and Startup for Generic Arm Cortex-M33 device</description>
2711       <files>
2712         <!-- include folder / device header file -->
2713         <file category="include"  name="Device/ARM/ARMCM33/Include/"/>
2714         <!-- startup / system file -->
2715         <file category="sourceC"      name="Device/ARM/ARMCM33/Source/GCC/startup_ARMCM33.c"         version="1.0.0" attr="config" condition="GCC"/>
2716         <file category="linkerScript" name="Device/ARM/ARMCM33/Source/GCC/gcc_arm.ld"                version="1.0.0" attr="config" condition="GCC"/>
2717         <file category="sourceC"      name="Device/ARM/ARMCM33/Source/system_ARMCM33.c"              version="1.0.0" attr="config"/>
2718         <!-- SAU configuration -->
2719         <file category="header"       name="Device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2720       </files>
2721     </component>
2722
2723     <!-- Cortex-M35P -->
2724     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.1.0" condition="ARMCM35P CMSIS">
2725       <description>System and Startup for Generic Arm Cortex-M35P device</description>
2726       <files>
2727         <!-- include folder / device header file -->
2728         <file category="include"      name="Device/ARM/ARMCM35P/Include/"/>
2729         <!-- startup / system file -->
2730         <file category="sourceAsm"    name="Device/ARM/ARMCM35P/Source/ARM/startup_ARMCM35P.s"         version="1.0.0" attr="config" condition="ARMCC"/>
2731         <file category="sourceAsm"    name="Device/ARM/ARMCM35P/Source/GCC/startup_ARMCM35P.S"         version="1.0.0" attr="config" condition="GCC"/>
2732         <file category="linkerScript" name="Device/ARM/ARMCM35P/Source/GCC/gcc_arm.ld"                 version="1.0.0" attr="config" condition="GCC"/>
2733         <file category="sourceAsm"    name="Device/ARM/ARMCM35P/Source/IAR/startup_ARMCM35P.s"         version="1.0.0" attr="config" condition="IAR"/>
2734         <file category="sourceC"      name="Device/ARM/ARMCM35P/Source/system_ARMCM35P.c"              version="1.0.0" attr="config"/>
2735         <!-- SAU configuration -->
2736         <file category="header"       name="Device/ARM/ARMCM35P/Include/Template/partition_ARMCM35P.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2737       </files>
2738     </component>
2739     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.1.0" condition="ARMCM35P CMSIS GCC">
2740       <description>System and Startup for Generic Arm Cortex-M35P device</description>
2741       <files>
2742         <!-- include folder / device header file -->
2743         <file category="include"  name="Device/ARM/ARMCM35P/Include/"/>
2744         <!-- startup / system file -->
2745         <file category="sourceC"      name="Device/ARM/ARMCM35P/Source/GCC/startup_ARMCM35P.c"         version="1.0.0" attr="config" condition="GCC"/>
2746         <file category="linkerScript" name="Device/ARM/ARMCM35P/Source/GCC/gcc_arm.ld"                 version="1.0.0" attr="config" condition="GCC"/>
2747         <file category="sourceC"      name="Device/ARM/ARMCM35P/Source/system_ARMCM35P.c"              version="1.0.0" attr="config"/>
2748         <!-- SAU configuration -->
2749         <file category="header"       name="Device/ARM/ARMCM35P/Include/Template/partition_ARMCM35P.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2750       </files>
2751     </component>
2752
2753     <!-- Cortex-SC000 -->
2754     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMSC000 CMSIS">
2755       <description>System and Startup for Generic Arm SC000 device</description>
2756       <files>
2757         <!-- include folder / device header file -->
2758         <file category="header"  name="Device/ARM/ARMSC000/Include/ARMSC000.h"/>
2759         <!-- startup / system file -->
2760         <file category="sourceAsm"    name="Device/ARM/ARMSC000/Source/ARM/startup_ARMSC000.s" version="1.0.0" attr="config" condition="ARMCC"/>
2761         <file category="sourceAsm"    name="Device/ARM/ARMSC000/Source/GCC/startup_ARMSC000.S" version="1.0.0" attr="config" condition="GCC"/>
2762         <file category="linkerScript" name="Device/ARM/ARMSC000/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2763         <file category="sourceAsm"    name="Device/ARM/ARMSC000/Source/IAR/startup_ARMSC000.s" version="1.0.0" attr="config" condition="IAR"/>
2764         <file category="sourceC"      name="Device/ARM/ARMSC000/Source/system_ARMSC000.c"      version="1.0.0" attr="config"/>
2765       </files>
2766     </component>
2767     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMSC000 CMSIS GCC">
2768       <description>System and Startup for Generic Arm SC000 device</description>
2769       <files>
2770         <!-- include folder / device header file -->
2771         <file category="header"  name="Device/ARM/ARMSC000/Include/ARMSC000.h"/>
2772         <!-- startup / system file -->
2773         <file category="sourceC"      name="Device/ARM/ARMSC000/Source/GCC/startup_ARMSC000.c" version="1.0.0" attr="config" condition="GCC"/>
2774         <file category="linkerScript" name="Device/ARM/ARMSC000/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2775         <file category="sourceC"      name="Device/ARM/ARMSC000/Source/system_ARMSC000.c"      version="1.0.0" attr="config"/>
2776       </files>
2777     </component>
2778
2779     <!-- Cortex-SC300 -->
2780     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMSC300 CMSIS">
2781       <description>System and Startup for Generic Arm SC300 device</description>
2782       <files>
2783         <!-- include folder / device header file -->
2784         <file category="header"  name="Device/ARM/ARMSC300/Include/ARMSC300.h"/>
2785         <!-- startup / system file -->
2786         <file category="sourceAsm"    name="Device/ARM/ARMSC300/Source/ARM/startup_ARMSC300.s" version="1.0.0" attr="config" condition="ARMCC"/>
2787         <file category="sourceAsm"    name="Device/ARM/ARMSC300/Source/GCC/startup_ARMSC300.S" version="1.0.0" attr="config" condition="GCC"/>
2788         <file category="linkerScript" name="Device/ARM/ARMSC300/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2789         <file category="sourceAsm"    name="Device/ARM/ARMSC300/Source/IAR/startup_ARMSC300.s" version="1.0.0" attr="config" condition="IAR"/>
2790         <file category="sourceC"      name="Device/ARM/ARMSC300/Source/system_ARMSC300.c"      version="1.0.0" attr="config"/>
2791       </files>
2792     </component>
2793     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.1" condition="ARMSC300 CMSIS GCC">
2794       <description>System and Startup for Generic Arm SC300 device</description>
2795       <files>
2796         <!-- include folder / device header file -->
2797         <file category="header"  name="Device/ARM/ARMSC300/Include/ARMSC300.h"/>
2798         <!-- startup / system file -->
2799         <file category="sourceC"      name="Device/ARM/ARMSC300/Source/GCC/startup_ARMSC300.c" version="1.0.0" attr="config" condition="GCC"/>
2800         <file category="linkerScript" name="Device/ARM/ARMSC300/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2801         <file category="sourceC"      name="Device/ARM/ARMSC300/Source/system_ARMSC300.c"      version="1.0.0" attr="config"/>
2802       </files>
2803     </component>
2804
2805     <!-- ARMv8MBL -->
2806     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.0" condition="ARMv8MBL CMSIS">
2807       <description>System and Startup for Generic Armv8-M Baseline device</description>
2808       <files>
2809         <!-- include folder / device header file -->
2810         <file category="include"      name="Device/ARM/ARMv8MBL/Include/"/>
2811         <!-- startup / system file -->
2812         <file category="sourceAsm"    name="Device/ARM/ARMv8MBL/Source/ARM/startup_ARMv8MBL.s" version="1.0.0" attr="config" condition="ARMCC"/>
2813         <file category="sourceAsm"    name="Device/ARM/ARMv8MBL/Source/GCC/startup_ARMv8MBL.S" version="1.0.0" attr="config" condition="GCC"/>
2814         <file category="linkerScript" name="Device/ARM/ARMv8MBL/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2815         <file category="sourceC"      name="Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c"      version="1.0.0" attr="config" condition="ARMCC GCC"/>
2816         <!-- SAU configuration -->
2817         <file category="header"       name="Device/ARM/ARMv8MBL/Include/Template/partition_ARMv8MBL.h" version="1.0.0" attr="config"/>
2818       </files>
2819     </component>
2820     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.0.0" condition="ARMv8MBL CMSIS GCC">
2821       <description>System and Startup for Generic Armv8-M Baseline device</description>
2822       <files>
2823         <!-- include folder / device header file -->
2824         <file category="include"  name="Device/ARM/ARMv8MBL/Include/"/>
2825         <!-- startup / system file -->
2826         <file category="sourceC"      name="Device/ARM/ARMv8MBL/Source/GCC/startup_ARMv8MBL.c" version="1.0.0" attr="config" condition="GCC"/>
2827         <file category="linkerScript" name="Device/ARM/ARMv8MBL/Source/GCC/gcc_arm.ld"         version="1.0.0" attr="config" condition="GCC"/>
2828         <file category="sourceC"      name="Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c"      version="1.0.0" attr="config"/>
2829         <!-- SAU configuration -->
2830         <file category="header"       name="Device/ARM/ARMv8MBL/Include/Template/partition_ARMv8MBL.h" version="1.0.0" attr="config" condition="ARMv8-M TZ Device"/>
2831       </files>
2832     </component>
2833
2834     <!-- ARMv8MML -->
2835     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.1.0" condition="ARMv8MML CMSIS">
2836       <description>System and Startup for Generic Armv8-M Mainline device</description>
2837       <files>
2838         <!-- include folder / device header file -->
2839         <file category="include"      name="Device/ARM/ARMv8MML/Include/"/>
2840         <!-- startup / system file -->
2841         <file category="sourceAsm"    name="Device/ARM/ARMv8MML/Source/ARM/startup_ARMv8MML.s"         version="1.0.0" attr="config" condition="ARMCC"/>
2842         <file category="sourceAsm"    name="Device/ARM/ARMv8MML/Source/GCC/startup_ARMv8MML.S"         version="1.0.0" attr="config" condition="GCC"/>
2843         <file category="linkerScript" name="Device/ARM/ARMv8MML/Source/GCC/gcc_arm.ld"                 version="1.0.0" attr="config" condition="GCC"/>
2844         <file category="sourceC"      name="Device/ARM/ARMv8MML/Source/system_ARMv8MML.c"              version="1.0.0" attr="config" condition="ARMCC GCC"/>
2845         <!-- SAU configuration -->
2846         <file category="header"       name="Device/ARM/ARMv8MML/Include/Template/partition_ARMv8MML.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2847       </files>
2848     </component>
2849     <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cversion="1.1.0" condition="ARMv8MML CMSIS GCC">
2850       <description>System and Startup for Generic Armv8-M Mainline device</description>
2851       <files>
2852         <!-- include folder / device header file -->
2853         <file category="include"      name="Device/ARM/ARMv8MML/Include/"/>
2854         <!-- startup / system file -->
2855         <file category="sourceC"      name="Device/ARM/ARMv8MML/Source/GCC/startup_ARMv8MML.c"         version="1.0.0" attr="config" condition="GCC"/>
2856         <file category="linkerScript" name="Device/ARM/ARMv8MML/Source/GCC/gcc_arm.ld"                 version="1.0.0" attr="config" condition="GCC"/>
2857         <file category="sourceC"      name="Device/ARM/ARMv8MML/Source/system_ARMv8MML.c"              version="1.0.0" attr="config"/>
2858         <!-- SAU configuration -->
2859         <file category="header"       name="Device/ARM/ARMv8MML/Include/Template/partition_ARMv8MML.h" version="1.1.0" attr="config" condition="ARMv8-M TZ Device"/>
2860       </files>
2861     </component>
2862
2863     <!-- Cortex-A5 -->
2864     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.0" condition="ARMCA5 CMSIS">
2865       <description>System and Startup for Generic Arm Cortex-A5 device</description>
2866       <files>
2867         <!-- include folder / device header file -->
2868         <file category="include"      name="Device/ARM/ARMCA5/Include/"/>
2869         <!-- startup / system / mmu files -->
2870         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/AC5/startup_ARMCA5.c" version="1.0.0" attr="config" condition="ARMCC5"/>
2871         <file category="linkerScript" name="Device/ARM/ARMCA5/Source/AC5/ARMCA5.sct"       version="1.0.0" attr="config" condition="ARMCC5"/>
2872         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/AC6/startup_ARMCA5.c" version="1.0.0" attr="config" condition="ARMCC6"/>
2873         <file category="linkerScript" name="Device/ARM/ARMCA5/Source/AC6/ARMCA5.sct"       version="1.0.0" attr="config" condition="ARMCC6"/>
2874         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/GCC/startup_ARMCA5.c" version="1.0.0" attr="config" condition="GCC"/>
2875         <file category="other"        name="Device/ARM/ARMCA5/Source/GCC/ARMCA5.ld"        version="1.0.0" attr="config" condition="GCC"/>
2876         <file category="sourceAsm"    name="Device/ARM/ARMCA5/Source/IAR/startup_ARMCA5.s" version="1.0.0" attr="config" condition="IAR"/>
2877         <file category="linkerScript" name="Device/ARM/ARMCA5/Source/IAR/ARMCA5.icf"       version="1.0.0" attr="config" condition="IAR"/>
2878         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/system_ARMCA5.c"      version="1.0.0" attr="config"/>
2879         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/mmu_ARMCA5.c"         version="1.0.0" attr="config"/>
2880         <file category="header"       name="Device/ARM/ARMCA5/Include/system_ARMCA5.h"     version="1.0.0" attr="config"/>
2881         <file category="header"       name="Device/ARM/ARMCA5/Include/mem_ARMCA5.h"        version="1.0.0" attr="config"/>
2882
2883       </files>
2884     </component>
2885
2886     <!-- Cortex-A7 -->
2887     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.0" condition="ARMCA7 CMSIS">
2888       <description>System and Startup for Generic Arm Cortex-A7 device</description>
2889       <files>
2890         <!-- include folder / device header file -->
2891         <file category="include"      name="Device/ARM/ARMCA7/Include/"/>
2892         <!-- startup / system / mmu files -->
2893         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/AC5/startup_ARMCA7.c" version="1.0.0" attr="config" condition="ARMCC5"/>
2894         <file category="linkerScript" name="Device/ARM/ARMCA7/Source/AC5/ARMCA7.sct"       version="1.0.0" attr="config" condition="ARMCC5"/>
2895         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/AC6/startup_ARMCA7.c" version="1.0.0" attr="config" condition="ARMCC6"/>
2896         <file category="linkerScript" name="Device/ARM/ARMCA7/Source/AC6/ARMCA7.sct"       version="1.0.0" attr="config" condition="ARMCC6"/>
2897         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/GCC/startup_ARMCA7.c" version="1.0.0" attr="config" condition="GCC"/>
2898         <file category="other"        name="Device/ARM/ARMCA7/Source/GCC/ARMCA7.ld"        version="1.0.0" attr="config" condition="GCC"/>
2899         <file category="sourceAsm"    name="Device/ARM/ARMCA7/Source/IAR/startup_ARMCA7.s" version="1.0.0" attr="config" condition="IAR"/>
2900         <file category="linkerScript" name="Device/ARM/ARMCA7/Source/IAR/ARMCA7.icf"       version="1.0.0" attr="config" condition="IAR"/>
2901         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/system_ARMCA7.c"      version="1.0.0" attr="config"/>
2902         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/mmu_ARMCA7.c"         version="1.0.0" attr="config"/>
2903         <file category="header"       name="Device/ARM/ARMCA7/Include/system_ARMCA7.h"     version="1.0.0" attr="config"/>
2904         <file category="header"       name="Device/ARM/ARMCA7/Include/mem_ARMCA7.h"        version="1.0.0" attr="config"/>
2905       </files>
2906     </component>
2907
2908     <!-- Cortex-A9 -->
2909     <component Cclass="Device" Cgroup="Startup"                      Cversion="1.0.1" condition="ARMCA9 CMSIS">
2910       <description>System and Startup for Generic Arm Cortex-A9 device</description>
2911       <files>
2912         <!-- include folder / device header file -->
2913         <file category="include"  name="Device/ARM/ARMCA9/Include/"/>
2914         <!-- startup / system / mmu files -->
2915         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/AC5/startup_ARMCA9.c" version="1.0.0" attr="config" condition="ARMCC5"/>
2916         <file category="linkerScript" name="Device/ARM/ARMCA9/Source/AC5/ARMCA9.sct"       version="1.0.0" attr="config" condition="ARMCC5"/>
2917         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/AC6/startup_ARMCA9.c" version="1.0.0" attr="config" condition="ARMCC6"/>
2918         <file category="linkerScript" name="Device/ARM/ARMCA9/Source/AC6/ARMCA9.sct"       version="1.0.0" attr="config" condition="ARMCC6"/>
2919         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/GCC/startup_ARMCA9.c" version="1.0.0" attr="config" condition="GCC"/>
2920         <file category="other"        name="Device/ARM/ARMCA9/Source/GCC/ARMCA9.ld"        version="1.0.0" attr="config" condition="GCC"/>
2921         <file category="sourceAsm"    name="Device/ARM/ARMCA9/Source/IAR/startup_ARMCA9.s" version="1.0.0" attr="config" condition="IAR"/>
2922         <file category="linkerScript" name="Device/ARM/ARMCA9/Source/IAR/ARMCA9.icf"       version="1.0.0" attr="config" condition="IAR"/>
2923         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/system_ARMCA9.c"      version="1.0.0" attr="config"/>
2924         <file category="sourceC"      name="Device/ARM/ARMCA9/Source/mmu_ARMCA9.c"         version="1.0.0" attr="config"/>
2925         <file category="header"       name="Device/ARM/ARMCA9/Include/system_ARMCA9.h"     version="1.0.0" attr="config"/>
2926         <file category="header"       name="Device/ARM/ARMCA9/Include/mem_ARMCA9.h"        version="1.0.0" attr="config"/>
2927       </files>
2928     </component>
2929
2930     <!-- IRQ Controller -->
2931     <component Cclass="Device" Cgroup="IRQ Controller" Csub="GIC" Capiversion="1.0.0" Cversion="1.0.1" condition="ARMv7-A Device">
2932       <description>IRQ Controller implementation using GIC</description>
2933       <files>
2934         <file category="sourceC" name="CMSIS/Core_A/Source/irq_ctrl_gic.c"/>
2935       </files>
2936     </component>
2937
2938     <!-- OS Tick -->
2939     <component Cclass="Device" Cgroup="OS Tick" Csub="Private Timer" Capiversion="1.0.1" Cversion="1.0.2" condition="OS Tick PTIM">
2940       <description>OS Tick implementation using Private Timer</description>
2941       <files>
2942         <file category="sourceC" name="CMSIS/RTOS2/Source/os_tick_ptim.c"/>
2943       </files>
2944     </component>
2945
2946     <component Cclass="Device" Cgroup="OS Tick" Csub="Generic Physical Timer" Capiversion="1.0.1" Cversion="1.0.1" condition="OS Tick GTIM">
2947       <description>OS Tick implementation using Generic Physical Timer</description>
2948       <files>
2949         <file category="sourceC" name="CMSIS/RTOS2/Source/os_tick_gtim.c"/>
2950       </files>
2951     </component>
2952
2953     <!-- CMSIS-DSP component -->
2954     <component Cclass="CMSIS" Cgroup="DSP" Cversion="1.5.2" condition="CMSIS DSP">
2955       <description>CMSIS-DSP Library for Cortex-M, SC000, and SC300</description>
2956       <files>
2957         <!-- CPU independent -->
2958         <file category="doc" name="CMSIS/Documentation/DSP/html/index.html"/>
2959         <file category="header" name="CMSIS/DSP/Include/arm_math.h"/>
2960
2961         <!-- CPU and Compiler dependent -->
2962         <!-- ARMCC -->
2963         <file category="library" condition="CM0_LE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM0l_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2964         <file category="library" condition="CM0_BE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM0b_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2965         <file category="library" condition="CM1_LE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM0l_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2966         <file category="library" condition="CM1_BE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM0b_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2967         <file category="library" condition="CM3_LE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM3l_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2968         <file category="library" condition="CM3_BE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM3b_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2969         <file category="library" condition="CM4_LE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM4l_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2970         <file category="library" condition="CM4_BE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM4b_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2971         <file category="library" condition="CM4_FP_LE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM4lf_math.lib"     src="CMSIS/DSP/Source/ARM"/>
2972         <file category="library" condition="CM4_FP_BE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM4bf_math.lib"     src="CMSIS/DSP/Source/ARM"/>
2973         <file category="library" condition="CM7_LE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM7l_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2974         <file category="library" condition="CM7_BE_ARMCC"             name="CMSIS/Lib/ARM/arm_cortexM7b_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2975         <file category="library" condition="CM7_SP_LE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM7lfsp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
2976         <file category="library" condition="CM7_SP_BE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM7bfsp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
2977         <file category="library" condition="CM7_DP_LE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM7lfdp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
2978         <file category="library" condition="CM7_DP_BE_ARMCC"          name="CMSIS/Lib/ARM/arm_cortexM7bfdp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
2979
2980         <file category="library" condition="CM23_LE_ARMCC"                  name="CMSIS/Lib/ARM/arm_ARMv8MBLl_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2981         <file category="library" condition="CM33_NODSP_NOFPU_LE_ARMCC"      name="CMSIS/Lib/ARM/arm_ARMv8MMLl_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2982         <file category="library" condition="CM33_DSP_NOFPU_LE_ARMCC"        name="CMSIS/Lib/ARM/arm_ARMv8MMLld_math.lib"     src="CMSIS/DSP/Source/ARM"/>
2983         <file category="library" condition="CM33_NODSP_SP_LE_ARMCC"         name="CMSIS/Lib/ARM/arm_ARMv8MMLlfsp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
2984         <file category="library" condition="CM33_DSP_SP_LE_ARMCC"           name="CMSIS/Lib/ARM/arm_ARMv8MMLldfsp_math.lib"  src="CMSIS/DSP/Source/ARM"/>
2985         <file category="library" condition="CM35P_NODSP_NOFPU_LE_ARMCC"     name="CMSIS/Lib/ARM/arm_ARMv8MMLl_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2986         <file category="library" condition="CM35P_DSP_NOFPU_LE_ARMCC"       name="CMSIS/Lib/ARM/arm_ARMv8MMLld_math.lib"     src="CMSIS/DSP/Source/ARM"/>
2987         <file category="library" condition="CM35P_NODSP_SP_LE_ARMCC"        name="CMSIS/Lib/ARM/arm_ARMv8MMLlfsp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
2988         <file category="library" condition="CM35P_DSP_SP_LE_ARMCC"          name="CMSIS/Lib/ARM/arm_ARMv8MMLldfsp_math.lib"  src="CMSIS/DSP/Source/ARM"/>
2989         <file category="library" condition="ARMv8MBL_LE_ARMCC"              name="CMSIS/Lib/ARM/arm_ARMv8MBLl_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2990         <file category="library" condition="ARMv8MML_NODSP_NOFPU_LE_ARMCC"  name="CMSIS/Lib/ARM/arm_ARMv8MMLl_math.lib"      src="CMSIS/DSP/Source/ARM"/>
2991         <file category="library" condition="ARMv8MML_DSP_NOFPU_LE_ARMCC"    name="CMSIS/Lib/ARM/arm_ARMv8MMLld_math.lib"     src="CMSIS/DSP/Source/ARM"/>
2992         <file category="library" condition="ARMv8MML_NODSP_SP_LE_ARMCC"     name="CMSIS/Lib/ARM/arm_ARMv8MMLlfsp_math.lib"   src="CMSIS/DSP/Source/ARM"/>
2993         <file category="library" condition="ARMv8MML_DSP_SP_LE_ARMCC"       name="CMSIS/Lib/ARM/arm_ARMv8MMLldfsp_math.lib"  src="CMSIS/DSP/Source/ARM"/>
2994         <!--file category="library" condition="ARMv8MML_DP_NOFPU_LE_ARMCC"     name="CMSIS/Lib/ARM/arm_ARMv8MMLlfdp_math.lib"   src="CMSIS/DSP/Source/ARM"/-->
2995         <!--file category="library" condition="ARMv8MML_DSP_DP_LE_ARMCC"       name="CMSIS/Lib/ARM/arm_ARMv8MMLldfdp_math.lib"  src="CMSIS/DSP/Source/ARM"/-->
2996
2997         <!-- GCC -->
2998         <file category="library" condition="CM0_LE_GCC"               name="CMSIS/Lib/GCC/libarm_cortexM0l_math.a"     src="CMSIS/DSP/Source/GCC"/>
2999         <file category="library" condition="CM1_LE_GCC"               name="CMSIS/Lib/GCC/libarm_cortexM0l_math.a"     src="CMSIS/DSP/Source/GCC"/>
3000         <file category="library" condition="CM3_LE_GCC"               name="CMSIS/Lib/GCC/libarm_cortexM3l_math.a"     src="CMSIS/DSP/Source/GCC"/>
3001         <file category="library" condition="CM4_LE_GCC"               name="CMSIS/Lib/GCC/libarm_cortexM4l_math.a"     src="CMSIS/DSP/Source/GCC"/>
3002         <file category="library" condition="CM4_FP_LE_GCC"            name="CMSIS/Lib/GCC/libarm_cortexM4lf_math.a"    src="CMSIS/DSP/Source/GCC"/>
3003         <file category="library" condition="CM7_LE_GCC"               name="CMSIS/Lib/GCC/libarm_cortexM7l_math.a"     src="CMSIS/DSP/Source/GCC"/>
3004         <file category="library" condition="CM7_SP_LE_GCC"            name="CMSIS/Lib/GCC/libarm_cortexM7lfsp_math.a"  src="CMSIS/DSP/Source/GCC"/>
3005         <file category="library" condition="CM7_DP_LE_GCC"            name="CMSIS/Lib/GCC/libarm_cortexM7lfdp_math.a"  src="CMSIS/DSP/Source/GCC"/>
3006
3007         <file category="library" condition="CM23_LE_GCC"                    name="CMSIS/Lib/GCC/libarm_ARMv8MBLl_math.a"     src="CMSIS/DSP/Source/GCC"/>
3008         <file category="library" condition="CM33_NODSP_NOFPU_LE_GCC"        name="CMSIS/Lib/GCC/libarm_ARMv8MMLl_math.a"     src="CMSIS/DSP/Source/GCC"/>
3009         <file category="library" condition="CM33_DSP_NOFPU_LE_GCC"          name="CMSIS/Lib/GCC/libarm_ARMv8MMLld_math.a"    src="CMSIS/DSP/Source/GCC"/>
3010         <file category="library" condition="CM33_NODSP_SP_LE_GCC"           name="CMSIS/Lib/GCC/libarm_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP/Source/GCC"/>
3011         <file category="library" condition="CM33_DSP_SP_LE_GCC"             name="CMSIS/Lib/GCC/libarm_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
3012         <file category="library" condition="CM35P_NODSP_NOFPU_LE_GCC"       name="CMSIS/Lib/GCC/libarm_ARMv8MMLl_math.a"     src="CMSIS/DSP/Source/GCC"/>
3013         <file category="library" condition="CM35P_DSP_NOFPU_LE_GCC"         name="CMSIS/Lib/GCC/libarm_ARMv8MMLld_math.a"    src="CMSIS/DSP/Source/GCC"/>
3014         <file category="library" condition="CM35P_NODSP_SP_LE_GCC"          name="CMSIS/Lib/GCC/libarm_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP/Source/GCC"/>
3015         <file category="library" condition="CM35P_DSP_SP_LE_GCC"            name="CMSIS/Lib/GCC/libarm_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
3016         <file category="library" condition="ARMv8MBL_LE_GCC"                name="CMSIS/Lib/GCC/libarm_ARMv8MBLl_math.a"     src="CMSIS/DSP/Source/GCC"/>
3017         <file category="library" condition="ARMv8MML_NODSP_NOFPU_LE_GCC"    name="CMSIS/Lib/GCC/libarm_ARMv8MMLl_math.a"     src="CMSIS/DSP/Source/GCC"/>
3018         <file category="library" condition="ARMv8MML_DSP_NOFPU_LE_GCC"      name="CMSIS/Lib/GCC/libarm_ARMv8MMLld_math.a"    src="CMSIS/DSP/Source/GCC"/>
3019         <file category="library" condition="ARMv8MML_NODSP_SP_LE_GCC"       name="CMSIS/Lib/GCC/libarm_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP/Source/GCC"/>
3020         <file category="library" condition="ARMv8MML_DSP_SP_LE_GCC"         name="CMSIS/Lib/GCC/libarm_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/GCC"/>
3021         <!--file category="library" condition="ARMv8MML_DP_NOFPU_LE_GCC"       name="CMSIS/Lib/GCC/libarm_ARMv8MMLlfdp_math.a"  src="CMSIS/DSP/Source/GCC"/-->
3022         <!--file category="library" condition="ARMv8MML_DSP_DP_LE_GCC"         name="CMSIS/Lib/GCC/libarm_ARMv8MMLldfdp_math.a" src="CMSIS/DSP/Source/GCC"/-->
3023
3024         <!-- IAR -->
3025         <file category="library" condition="CM0_LE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM0l_math.a"     src="CMSIS/DSP/Source/IAR"/>
3026         <file category="library" condition="CM0_BE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM0b_math.a"     src="CMSIS/DSP/Source/IAR"/>
3027         <file category="library" condition="CM1_LE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM0l_math.a"     src="CMSIS/DSP/Source/IAR"/>
3028         <file category="library" condition="CM1_BE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM0b_math.a"     src="CMSIS/DSP/Source/IAR"/>
3029         <file category="library" condition="CM3_LE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM3l_math.a"     src="CMSIS/DSP/Source/IAR"/>
3030         <file category="library" condition="CM3_BE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM3b_math.a"     src="CMSIS/DSP/Source/IAR"/>
3031         <file category="library" condition="CM4_LE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM4l_math.a"     src="CMSIS/DSP/Source/IAR"/>
3032         <file category="library" condition="CM4_BE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM4b_math.a"     src="CMSIS/DSP/Source/IAR"/>
3033         <file category="library" condition="CM4_FP_LE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM4lf_math.a"    src="CMSIS/DSP/Source/IAR"/>
3034         <file category="library" condition="CM4_FP_BE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM4bf_math.a"    src="CMSIS/DSP/Source/IAR"/>
3035         <file category="library" condition="CM7_LE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM7l_math.a"     src="CMSIS/DSP/Source/IAR"/>
3036         <file category="library" condition="CM7_BE_IAR"               name="CMSIS/Lib/IAR/iar_cortexM7b_math.a"     src="CMSIS/DSP/Source/IAR"/>
3037         <file category="library" condition="CM7_DP_LE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM7lf_math.a"    src="CMSIS/DSP/Source/IAR"/>
3038         <file category="library" condition="CM7_DP_BE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM7bf_math.a"    src="CMSIS/DSP/Source/IAR"/>
3039         <file category="library" condition="CM7_SP_LE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM7ls_math.a"    src="CMSIS/DSP/Source/IAR"/>
3040         <file category="library" condition="CM7_SP_BE_IAR"            name="CMSIS/Lib/IAR/iar_cortexM7bs_math.a"    src="CMSIS/DSP/Source/IAR"/>
3041
3042         <file category="library" condition="CM23_LE_IAR"              name="CMSIS/Lib/IAR/iar_ARMv8MBLl_math.a"     src="CMSIS/DSP/Source/IAR"/>
3043         <file category="library" condition="CM33_NODSP_NOFPU_LE_IAR"        name="CMSIS/Lib/IAR/iar_ARMv8MMLl_math.a"     src="CMSIS/DSP/Source/IAR"/>
3044         <file category="library" condition="CM33_DSP_NOFPU_LE_IAR"    name="CMSIS/Lib/IAR/iar_ARMv8MMLld_math.a"    src="CMSIS/DSP/Source/IAR"/>
3045         <file category="library" condition="CM33_NODSP_SP_LE_IAR"           name="CMSIS/Lib/IAR/iar_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP/Source/IAR"/>
3046         <file category="library" condition="CM33_DSP_SP_LE_IAR"       name="CMSIS/Lib/IAR/iar_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
3047         <file category="library" condition="CM35P_NODSP_NOFPU_LE_IAR"       name="CMSIS/Lib/IAR/iar_ARMv8MMLl_math.a"     src="CMSIS/DSP/Source/IAR"/>
3048         <file category="library" condition="CM35P_DSP_NOFPU_LE_IAR"         name="CMSIS/Lib/IAR/iar_ARMv8MMLld_math.a"    src="CMSIS/DSP/Source/IAR"/>
3049         <file category="library" condition="CM35P_NODSP_SP_LE_IAR"          name="CMSIS/Lib/IAR/iar_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP/Source/IAR"/>
3050         <file category="library" condition="CM35P_DSP_SP_LE_IAR"            name="CMSIS/Lib/IAR/iar_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
3051         <file category="library" condition="ARMv8MBL_LE_IAR"          name="CMSIS/Lib/IAR/iar_ARMv8MBLl_math.a"     src="CMSIS/DSP/Source/IAR"/>
3052         <file category="library" condition="ARMv8MML_NODSP_NOFPU_LE_IAR"    name="CMSIS/Lib/IAR/iar_ARMv8MMLl_math.a"     src="CMSIS/DSP/Source/IAR"/>
3053         <file category="library" condition="ARMv8MML_DSP_NOFPU_LE_IAR" name="CMSIS/Lib/IAR/iar_ARMv8MMLld_math.a"    src="CMSIS/DSP/Source/IAR"/>
3054         <file category="library" condition="ARMv8MML_NODSP_SP_LE_IAR"       name="CMSIS/Lib/IAR/iar_ARMv8MMLlfsp_math.a"  src="CMSIS/DSP/Source/IAR"/>
3055         <file category="library" condition="ARMv8MML_DSP_SP_LE_IAR"   name="CMSIS/Lib/IAR/iar_ARMv8MMLldfsp_math.a" src="CMSIS/DSP/Source/IAR"/>
3056      <!--file category="library" condition="ARMv8MML_DP_NOFPU_LE_IAR"       name="CMSIS/Lib/IAR/iar_ARMv8MMLlfdp_math.a"  src="CMSIS/DSP/Source/IAR"/-->
3057         <!--file category="library" condition="ARMv8MML_DSP_DP_LE_IAR"   name="CMSIS/Lib/IAR/iar_ARMv8MMLldfdp_math.a" src="CMSIS/DSP/Source/IAR"/-->
3058
3059       </files>
3060     </component>
3061
3062     <!-- CMSIS-NN component -->
3063     <component Cclass="CMSIS" Cgroup="NN Lib" Cversion="1.1.0" condition="CMSIS NN">
3064       <description>CMSIS-NN Neural Network Library</description>
3065       <files>
3066         <file category="doc" name="CMSIS/Documentation/NN/html/index.html"/>
3067         <file category="header" name="CMSIS/NN/Include/arm_nnfunctions.h"/>
3068
3069         <file category="source" name="CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c"/>
3070         <file category="source" name="CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c"/>
3071         <file category="source" name="CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c"/>
3072         <file category="source" name="CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c"/>
3073
3074         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c"/>
3075         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c"/>
3076         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c"/>
3077         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c"/>
3078         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c"/>
3079         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c"/>
3080         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c"/>
3081         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c"/>
3082         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c"/>
3083         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c"/>
3084         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c"/>
3085         <file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c"/>
3086
3087         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c"/>
3088         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c"/>
3089         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c"/>
3090         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c"/>
3091         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c"/>
3092         <file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c"/>
3093
3094         <file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c"/>
3095         <file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c"/>
3096         <file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c"/>
3097         <file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.c"/>
3098         <file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.c"/>
3099
3100         <file category="source" name="CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c"/>
3101
3102         <file category="source" name="CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.c"/>
3103         <file category="source" name="CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.c"/>
3104       </files>
3105     </component>
3106
3107     <!-- CMSIS-RTOS Keil RTX component -->
3108     <component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX" Cversion="4.81.1" Capiversion="1.0.0" isDefaultVariant="1" condition="RTOS RTX">
3109       <description>CMSIS-RTOS RTX implementation for Cortex-M, SC000, and SC300</description>
3110       <RTE_Components_h>
3111         <!-- the following content goes into file 'RTE_Components.h' -->
3112         #define RTE_CMSIS_RTOS                  /* CMSIS-RTOS */
3113         #define RTE_CMSIS_RTOS_RTX              /* CMSIS-RTOS Keil RTX */
3114       </RTE_Components_h>
3115       <files>
3116         <!-- CPU independent -->
3117         <file category="doc" name="CMSIS/Documentation/RTOS/html/rtxImplementation.html"/>
3118         <file category="header" name="CMSIS/RTOS/RTX/INC/cmsis_os.h"/>
3119         <file category="source" attr="config"   name="CMSIS/RTOS/RTX/Templates/RTX_Conf_CM.c" version="4.70.1"/>
3120
3121         <!-- RTX templates -->
3122         <file category="header" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/osObjects.h" select="CMSIS-RTOS 'main' function"/>
3123         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/main.c"      select="CMSIS-RTOS 'main' function"/>
3124         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MailQueue.c" select="CMSIS-RTOS Mail Queue"/>
3125         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MemPool.c"   select="CMSIS-RTOS Memory Pool"/>
3126         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MsgQueue.c"  select="CMSIS-RTOS Message Queue"/>
3127         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Mutex.c"     select="CMSIS-RTOS Mutex"/>
3128         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Semaphore.c" select="CMSIS-RTOS Semaphore"/>
3129         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Thread.c"    select="CMSIS-RTOS Thread"/>
3130         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Timer.c"     select="CMSIS-RTOS Timer"/>
3131         <!-- tool-chain specific template file -->
3132         <file category="source" attr="template" condition="ARMCC" name="CMSIS/RTOS/RTX/SRC/ARM/SVC_Table.s" select="CMSIS-RTOS User SVC"/>
3133         <file category="source" attr="template" condition="GCC"   name="CMSIS/RTOS/RTX/SRC/GCC/SVC_Table.S" select="CMSIS-RTOS User SVC"/>
3134         <file category="source" attr="template" condition="IAR"   name="CMSIS/RTOS/RTX/SRC/IAR/SVC_Table.s" select="CMSIS-RTOS User SVC"/>
3135
3136         <!-- CPU and Compiler dependent -->
3137         <!-- ARMCC -->
3138         <file category="library" condition="CM0_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
3139         <file category="library" condition="CM0_BE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3140         <file category="library" condition="CM1_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
3141         <file category="library" condition="CM1_BE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3142         <file category="library" condition="CM3_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
3143         <file category="library" condition="CM3_BE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3144         <file category="library" condition="CM4_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
3145         <file category="library" condition="CM4_BE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3146         <file category="library" condition="CM4_FP_LE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
3147         <file category="library" condition="CM4_FP_BE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3148         <file category="library" condition="CM7_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
3149         <file category="library" condition="CM7_BE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3150         <file category="library" condition="CM7_FP_LE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4.lib"    src="CMSIS/RTOS/RTX/SRC/ARM"/>
3151         <file category="library" condition="CM7_FP_BE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_B.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3152         <!-- GCC -->
3153         <file category="library" condition="CM0_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
3154         <file category="library" condition="CM0_BE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3155         <file category="library" condition="CM1_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
3156         <file category="library" condition="CM1_BE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3157         <file category="library" condition="CM3_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
3158         <file category="library" condition="CM3_BE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3159         <file category="library" condition="CM4_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
3160         <file category="library" condition="CM4_BE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3161         <file category="library" condition="CM4_FP_LE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
3162         <file category="library" condition="CM4_FP_BE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3163         <file category="library" condition="CM7_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
3164         <file category="library" condition="CM7_BE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3165         <file category="library" condition="CM7_FP_LE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4.a"   src="CMSIS/RTOS/RTX/SRC/GCC"/>
3166         <file category="library" condition="CM7_FP_BE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_B.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3167         <!-- IAR -->
3168         <file category="library" condition="CM0_LE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
3169         <file category="library" condition="CM0_BE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
3170         <file category="library" condition="CM1_LE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
3171         <file category="library" condition="CM1_BE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
3172         <file category="library" condition="CM3_LE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
3173         <file category="library" condition="CM3_BE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
3174         <file category="library" condition="CM4_LE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
3175         <file category="library" condition="CM4_BE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
3176         <file category="library" condition="CM4_FP_LE_IAR"   name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
3177         <file category="library" condition="CM4_FP_BE_IAR"   name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
3178         <file category="library" condition="CM7_LE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
3179         <file category="library" condition="CM7_BE_IAR"      name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
3180         <file category="library" condition="CM7_FP_LE_IAR"   name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4.a"      src="CMSIS/RTOS/RTX/SRC/IAR"/>
3181         <file category="library" condition="CM7_FP_BE_IAR"   name="CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4_B.a"    src="CMSIS/RTOS/RTX/SRC/IAR"/>
3182       </files>
3183     </component>
3184     <!-- CMSIS-RTOS Keil RTX component (IFX variant) -->
3185     <component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX" Cvariant="IFX" Cversion="4.81.1" Capiversion="1.0.0" condition="RTOS RTX IFX">
3186       <description>CMSIS-RTOS RTX implementation for Infineon XMC4 series affected by PMU_CM.001 errata</description>
3187       <RTE_Components_h>
3188         <!-- the following content goes into file 'RTE_Components.h' -->
3189         #define RTE_CMSIS_RTOS                  /* CMSIS-RTOS */
3190         #define RTE_CMSIS_RTOS_RTX              /* CMSIS-RTOS Keil RTX */
3191       </RTE_Components_h>
3192       <files>
3193         <!-- CPU independent -->
3194         <file category="doc" name="CMSIS/Documentation/RTOS/html/rtxImplementation.html"/>
3195         <file category="header" name="CMSIS/RTOS/RTX/INC/cmsis_os.h"/>
3196         <file category="source" attr="config"   name="CMSIS/RTOS/RTX/Templates/RTX_Conf_CM.c" version="4.70.1"/>
3197
3198         <!-- RTX templates -->
3199         <file category="header" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/osObjects.h" select="CMSIS-RTOS 'main' function"/>
3200         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/main.c"      select="CMSIS-RTOS 'main' function"/>
3201         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MailQueue.c" select="CMSIS-RTOS Mail Queue"/>
3202         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MemPool.c"   select="CMSIS-RTOS Memory Pool"/>
3203         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/MsgQueue.c"  select="CMSIS-RTOS Message Queue"/>
3204         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Mutex.c"     select="CMSIS-RTOS Mutex"/>
3205         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Semaphore.c" select="CMSIS-RTOS Semaphore"/>
3206         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Thread.c"    select="CMSIS-RTOS Thread"/>
3207         <file category="source" attr="template" name="CMSIS/RTOS/RTX/UserCodeTemplates/Timer.c"     select="CMSIS-RTOS Timer"/>
3208         <!-- tool-chain specific template file -->
3209         <file category="source" attr="template" condition="ARMCC" name="CMSIS/RTOS/RTX/SRC/ARM/SVC_Table.s" select="CMSIS-RTOS User SVC"/>
3210         <file category="source" attr="template" condition="GCC"   name="CMSIS/RTOS/RTX/SRC/GCC/SVC_Table.S" select="CMSIS-RTOS User SVC"/>
3211         <file category="source" attr="template" condition="IAR"   name="CMSIS/RTOS/RTX/SRC/IAR/SVC_Table.s" select="CMSIS-RTOS User SVC"/>
3212
3213         <!-- CPU and Compiler dependent -->
3214         <!-- ARMCC -->
3215         <file category="library" condition="CM4_LE_ARMCC"    name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_IFX.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3216         <file category="library" condition="CM4_FP_LE_ARMCC" name="CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_IFX.lib"  src="CMSIS/RTOS/RTX/SRC/ARM"/>
3217         <!-- GCC -->
3218         <file category="library" condition="CM4_LE_GCC"      name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_IFX.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3219         <file category="library" condition="CM4_FP_LE_GCC"   name="CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_IFX.a" src="CMSIS/RTOS/RTX/SRC/GCC"/>
3220         <!-- IAR -->
3221       </files>
3222     </component>
3223
3224     <!-- CMSIS-RTOS Keil RTX5 component -->
3225     <component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX5" Cversion="5.5.0" Capiversion="1.0.0" condition="RTOS RTX5">
3226       <description>CMSIS-RTOS RTX5 implementation for Cortex-M, SC000, and SC300</description>
3227       <RTE_Components_h>
3228         <!-- the following content goes into file 'RTE_Components.h' -->
3229         #define RTE_CMSIS_RTOS                  /* CMSIS-RTOS */
3230         #define RTE_CMSIS_RTOS_RTX5             /* CMSIS-RTOS Keil RTX5 */
3231       </RTE_Components_h>
3232       <files>
3233         <!-- RTX header file -->
3234         <file category="header" name="CMSIS/RTOS2/RTX/Include1/cmsis_os.h"/>
3235         <!-- RTX compatibility module for API V1 -->
3236         <file category="source" name="CMSIS/RTOS2/RTX/Library/cmsis_os1.c"/>
3237       </files>
3238     </component>
3239
3240     <!-- CMSIS-RTOS2 Keil RTX5 component -->
3241     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cversion="5.5.0" Capiversion="2.1.3" condition="RTOS2 RTX5 Lib">
3242       <description>CMSIS-RTOS2 RTX5 for Cortex-M, SC000, C300 and Armv8-M (Library)</description>
3243       <RTE_Components_h>
3244         <!-- the following content goes into file 'RTE_Components.h' -->
3245         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
3246         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
3247       </RTE_Components_h>
3248       <files>
3249         <!-- RTX documentation -->
3250         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
3251
3252         <!-- RTX header files -->
3253         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
3254
3255         <!-- RTX configuration -->
3256         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.5.0"/>
3257         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
3258
3259         <!-- RTX templates -->
3260         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.1.0" select="CMSIS-RTOS2 'main' function"/>
3261         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
3262         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
3263         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
3264         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
3265         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
3266         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
3267         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
3268         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
3269         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
3270
3271         <!-- RTX library configuration -->
3272         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
3273
3274         <!-- RTX libraries (CPU and Compiler dependent) -->
3275         <!-- ARMCC -->
3276         <file category="library" condition="CM0_LE_ARMCC"         name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM0.lib"    src="CMSIS/RTOS2/RTX/Source"/>
3277         <file category="library" condition="CM1_LE_ARMCC"         name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM0.lib"    src="CMSIS/RTOS2/RTX/Source"/>
3278         <file category="library" condition="CM3_LE_ARMCC"         name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM3.lib"    src="CMSIS/RTOS2/RTX/Source"/>
3279         <file category="library" condition="CM4_LE_ARMCC"         name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM3.lib"    src="CMSIS/RTOS2/RTX/Source"/>
3280         <file category="library" condition="CM4_FP_LE_ARMCC"      name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM4F.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3281         <file category="library" condition="CM7_LE_ARMCC"         name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM3.lib"    src="CMSIS/RTOS2/RTX/Source"/>
3282         <file category="library" condition="CM7_FP_LE_ARMCC"      name="CMSIS/RTOS2/RTX/Library/ARM/RTX_CM4F.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3283         <file category="library" condition="CM23_LE_ARMCC"        name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MB.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3284         <file category="library" condition="CM33_LE_ARMCC"        name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3285         <file category="library" condition="CM33_FP_LE_ARMCC"     name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib"  src="CMSIS/RTOS2/RTX/Source"/>
3286         <file category="library" condition="CM35P_LE_ARMCC"       name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3287         <file category="library" condition="CM35P_FP_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib"  src="CMSIS/RTOS2/RTX/Source"/>
3288         <file category="library" condition="ARMv8MBL_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MB.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3289         <file category="library" condition="ARMv8MML_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3290         <file category="library" condition="ARMv8MML_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib"  src="CMSIS/RTOS2/RTX/Source"/>
3291         <!-- GCC -->
3292         <file category="library" condition="CM0_LE_GCC"           name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM0.a"   src="CMSIS/RTOS2/RTX/Source"/>
3293         <file category="library" condition="CM1_LE_GCC"           name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM0.a"   src="CMSIS/RTOS2/RTX/Source"/>
3294         <file category="library" condition="CM3_LE_GCC"           name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a"   src="CMSIS/RTOS2/RTX/Source"/>
3295         <file category="library" condition="CM4_LE_GCC"           name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a"   src="CMSIS/RTOS2/RTX/Source"/>
3296         <file category="library" condition="CM4_FP_LE_GCC"        name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM4F.a"  src="CMSIS/RTOS2/RTX/Source"/>
3297         <file category="library" condition="CM7_LE_GCC"           name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a"   src="CMSIS/RTOS2/RTX/Source"/>
3298         <file category="library" condition="CM7_FP_LE_GCC"        name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM4F.a"  src="CMSIS/RTOS2/RTX/Source"/>
3299         <file category="library" condition="CM23_LE_GCC"          name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MB.a"  src="CMSIS/RTOS2/RTX/Source"/>
3300         <file category="library" condition="CM33_LE_GCC"          name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a"  src="CMSIS/RTOS2/RTX/Source"/>
3301         <file category="library" condition="CM33_FP_LE_GCC"       name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
3302         <file category="library" condition="CM35P_LE_GCC"         name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a"  src="CMSIS/RTOS2/RTX/Source"/>
3303         <file category="library" condition="CM35P_FP_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
3304         <file category="library" condition="ARMv8MBL_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MB.a"  src="CMSIS/RTOS2/RTX/Source"/>
3305         <file category="library" condition="ARMv8MML_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a"  src="CMSIS/RTOS2/RTX/Source"/>
3306         <file category="library" condition="ARMv8MML_FP_LE_GCC"   name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a" src="CMSIS/RTOS2/RTX/Source"/>
3307         <!-- IAR -->
3308         <file category="library" condition="CM0_LE_IAR"           name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM0.a"      src="CMSIS/RTOS2/RTX/Source"/>
3309         <file category="library" condition="CM1_LE_IAR"           name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM0.a"      src="CMSIS/RTOS2/RTX/Source"/>
3310         <file category="library" condition="CM3_LE_IAR"           name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM3.a"      src="CMSIS/RTOS2/RTX/Source"/>
3311         <file category="library" condition="CM4_LE_IAR"           name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM3.a"      src="CMSIS/RTOS2/RTX/Source"/>
3312         <file category="library" condition="CM4_FP_LE_IAR"        name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM4F.a"     src="CMSIS/RTOS2/RTX/Source"/>
3313         <file category="library" condition="CM7_LE_IAR"           name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM3.a"      src="CMSIS/RTOS2/RTX/Source"/>
3314         <file category="library" condition="CM7_FP_LE_IAR"        name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM4F.a"     src="CMSIS/RTOS2/RTX/Source"/>
3315       </files>
3316     </component>
3317     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library_NS" Cversion="5.5.0" Capiversion="2.1.3" condition="RTOS2 RTX5 NS">
3318       <description>CMSIS-RTOS2 RTX5 for Armv8-M Non-Secure Domain (Library)</description>
3319       <RTE_Components_h>
3320         <!-- the following content goes into file 'RTE_Components.h' -->
3321         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
3322         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
3323         #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS  /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */
3324       </RTE_Components_h>
3325       <files>
3326         <!-- RTX documentation -->
3327         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
3328
3329         <!-- RTX header files -->
3330         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
3331
3332         <!-- RTX configuration -->
3333         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.5.0"/>
3334         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
3335
3336         <!-- RTX templates -->
3337         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.1.0" select="CMSIS-RTOS2 'main' function"/>
3338         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
3339         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
3340         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
3341         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
3342         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
3343         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
3344         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
3345         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
3346         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
3347
3348         <!-- RTX library configuration -->
3349         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
3350
3351         <!-- RTX libraries (CPU and Compiler dependent) -->
3352         <!-- ARMCC -->
3353         <file category="library" condition="CM23_LE_ARMCC"        name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MBN.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3354         <file category="library" condition="CM33_LE_ARMCC"        name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3355         <file category="library" condition="CM33_FP_LE_ARMCC"     name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib"  src="CMSIS/RTOS2/RTX/Source"/>
3356         <file category="library" condition="CM35P_LE_ARMCC"       name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3357         <file category="library" condition="CM35P_FP_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib"  src="CMSIS/RTOS2/RTX/Source"/>
3358         <file category="library" condition="ARMv8MBL_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MBN.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3359         <file category="library" condition="ARMv8MML_LE_ARMCC"    name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib"   src="CMSIS/RTOS2/RTX/Source"/>
3360         <file category="library" condition="ARMv8MML_FP_LE_ARMCC" name="CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib"  src="CMSIS/RTOS2/RTX/Source"/>
3361         <!-- GCC -->
3362         <file category="library" condition="CM23_LE_GCC"          name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MBN.a"  src="CMSIS/RTOS2/RTX/Source"/>
3363         <file category="library" condition="CM33_LE_GCC"          name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a"  src="CMSIS/RTOS2/RTX/Source"/>
3364         <file category="library" condition="CM33_FP_LE_GCC"       name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
3365         <file category="library" condition="CM35P_LE_GCC"         name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a"  src="CMSIS/RTOS2/RTX/Source"/>
3366         <file category="library" condition="CM35P_FP_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
3367         <file category="library" condition="ARMv8MBL_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MBN.a"  src="CMSIS/RTOS2/RTX/Source"/>
3368         <file category="library" condition="ARMv8MML_LE_GCC"      name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a"  src="CMSIS/RTOS2/RTX/Source"/>
3369         <file category="library" condition="ARMv8MML_FP_LE_GCC"   name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
3370       </files>
3371     </component>
3372     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cversion="5.5.0" Capiversion="2.1.3" condition="RTOS2 RTX5">
3373       <description>CMSIS-RTOS2 RTX5 for Cortex-M, SC000, C300 and Armv8-M (Source)</description>
3374       <RTE_Components_h>
3375         <!-- the following content goes into file 'RTE_Components.h' -->
3376         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
3377         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
3378         #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
3379       </RTE_Components_h>
3380       <files>
3381         <!-- RTX documentation -->
3382         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
3383
3384         <!-- RTX header files -->
3385         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
3386
3387         <!-- RTX configuration -->
3388         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.5.0"/>
3389         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
3390
3391         <!-- RTX templates -->
3392         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.1.0" select="CMSIS-RTOS2 'main' function"/>
3393         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
3394         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
3395         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
3396         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
3397         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
3398         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
3399         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
3400         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
3401         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
3402
3403         <!-- RTX sources (core) -->
3404         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_kernel.c"/>
3405         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_thread.c"/>
3406         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_delay.c"/>
3407         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_timer.c"/>
3408         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evflags.c"/>
3409         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mutex.c"/>
3410         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_semaphore.c"/>
3411         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_memory.c"/>
3412         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mempool.c"/>
3413         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c"/>
3414         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_system.c"/>
3415         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evr.c"/>
3416         <!-- RTX sources (library configuration) -->
3417         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
3418         <!-- RTX sources (handlers ARMCC) -->
3419         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm0.s"         condition="CM0_ARMCC"/>
3420         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm0.s"         condition="CM1_ARMCC"/>
3421         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm3.s"         condition="CM3_ARMCC"/>
3422         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm3.s"         condition="CM4_ARMCC"/>
3423         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm4f.s"        condition="CM4_FP_ARMCC"/>
3424         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm3.s"         condition="CM7_ARMCC"/>
3425         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_cm4f.s"        condition="CM7_FP_ARMCC"/>
3426         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl.s"    condition="CM23_ARMCC"/>
3427         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="CM33_ARMCC"/>
3428         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="CM33_FP_ARMCC"/>
3429         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="CM35P_ARMCC"/>
3430         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="CM35P_FP_ARMCC"/>
3431         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl.s"    condition="ARMv8MBL_ARMCC"/>
3432         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="ARMv8MML_ARMCC"/>
3433         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s"    condition="ARMv8MML_FP_ARMCC"/>
3434         <!-- RTX sources (handlers GCC) -->
3435         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm0.S"         condition="CM0_GCC"/>
3436         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm0.S"         condition="CM1_GCC"/>
3437         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm3.S"         condition="CM3_GCC"/>
3438         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm3.S"         condition="CM4_GCC"/>
3439         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm4f.S"        condition="CM4_FP_GCC"/>
3440         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm3.S"         condition="CM7_GCC"/>
3441         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_cm4f.S"        condition="CM7_FP_GCC"/>
3442         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S"    condition="CM23_GCC"/>
3443         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S"    condition="CM33_GCC"/>
3444         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp.S" condition="CM33_FP_GCC"/>
3445         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S"    condition="CM35P_GCC"/>
3446         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp.S" condition="CM35P_FP_GCC"/>
3447         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S"    condition="ARMv8MBL_GCC"/>
3448         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S"    condition="ARMv8MML_GCC"/>
3449         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp.S" condition="ARMv8MML_FP_GCC"/>
3450         <!-- RTX sources (handlers IAR) -->
3451         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm0.s"         condition="CM0_IAR"/>
3452         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm0.s"         condition="CM1_IAR"/>
3453         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm3.s"         condition="CM3_IAR"/>
3454         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm3.s"         condition="CM4_IAR"/>
3455         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm4f.s"        condition="CM4_FP_IAR"/>
3456         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm3.s"         condition="CM7_IAR"/>
3457         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_cm4f.s"        condition="CM7_FP_IAR"/>
3458         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s"    condition="CM23_IAR"/>
3459         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="CM33_IAR"/>
3460         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="CM33_FP_IAR"/>
3461         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="CM35P_IAR"/>
3462         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="CM35P_FP_IAR"/>
3463         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s"    condition="ARMv8MBL_IAR"/>
3464         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="ARMv8MML_IAR"/>
3465         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s"    condition="ARMv8MML_FP_IAR"/>
3466         <!-- OS Tick (SysTick) -->
3467         <file category="source" name="CMSIS/RTOS2/Source/os_systick.c"/>
3468       </files>
3469     </component>
3470     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cversion="5.5.0" Capiversion="2.1.3" condition="RTOS2 RTX5 v7-A">
3471       <description>CMSIS-RTOS2 RTX5 for Armv7-A (Source)</description>
3472       <RTE_Components_h>
3473         <!-- the following content goes into file 'RTE_Components.h' -->
3474         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
3475         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
3476         #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
3477       </RTE_Components_h>
3478       <files>
3479         <!-- RTX documentation -->
3480         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
3481
3482         <!-- RTX header files -->
3483         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
3484
3485         <!-- RTX configuration -->
3486         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.5.0"/>
3487         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
3488
3489         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/handlers.c"    version="5.1.0"/>
3490
3491         <!-- RTX templates -->
3492         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.1.0" select="CMSIS-RTOS2 'main' function"/>
3493         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
3494         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
3495         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
3496         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
3497         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
3498         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
3499         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
3500         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
3501         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
3502
3503         <!-- RTX sources (core) -->
3504         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_kernel.c"/>
3505         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_thread.c"/>
3506         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_delay.c"/>
3507         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_timer.c"/>
3508         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evflags.c"/>
3509         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mutex.c"/>
3510         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_semaphore.c"/>
3511         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_memory.c"/>
3512         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mempool.c"/>
3513         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c"/>
3514         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_system.c"/>
3515         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evr.c"/>
3516         <!-- RTX sources (library configuration) -->
3517         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
3518         <!-- RTX sources (handlers ARMCC) -->
3519         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_ca.s"          condition="CA_ARMCC5"/>
3520         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_ca.S"          condition="CA_ARMCC6"/>
3521         <!-- RTX sources (handlers GCC) -->
3522         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_ca.S"          condition="CA_GCC"/>
3523         <!-- RTX sources (handlers IAR) -->
3524         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_ca.s"          condition="CA_IAR"/>
3525       </files>
3526     </component>
3527     <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source_NS" Cversion="5.5.0" Capiversion="2.1.3" condition="RTOS2 RTX5 NS">
3528       <description>CMSIS-RTOS2 RTX5 for Armv8-M Non-Secure Domain (Source)</description>
3529       <RTE_Components_h>
3530         <!-- the following content goes into file 'RTE_Components.h' -->
3531         #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
3532         #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
3533         #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */
3534         #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS  /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */
3535       </RTE_Components_h>
3536       <files>
3537         <!-- RTX documentation -->
3538         <file category="doc"    name="CMSIS/Documentation/RTOS2/html/rtx5_impl.html"/>
3539
3540         <!-- RTX header files -->
3541         <file category="header" name="CMSIS/RTOS2/RTX/Include/rtx_os.h"/>
3542
3543         <!-- RTX configuration -->
3544         <file category="header" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.h"  version="5.5.0"/>
3545         <file category="source" attr="config"   name="CMSIS/RTOS2/RTX/Config/RTX_Config.c"  version="5.1.0"/>
3546
3547         <!-- RTX templates -->
3548         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/main.c"      version="2.1.0" select="CMSIS-RTOS2 'main' function"/>
3549         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Events.c"    version="2.0.0" select="CMSIS-RTOS2 Events"/>
3550         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MemPool.c"   version="2.0.0" select="CMSIS-RTOS2 Memory Pool"/>
3551         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/MsgQueue.c"  version="2.0.0" select="CMSIS-RTOS2 Message Queue"/>
3552         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Mutex.c"     version="2.0.0" select="CMSIS-RTOS2 Mutex"/>
3553         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Semaphore.c" version="2.0.0" select="CMSIS-RTOS2 Semaphore"/>
3554         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Thread.c"    version="2.0.0" select="CMSIS-RTOS2 Thread"/>
3555         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/Timer.c"     version="2.0.1" select="CMSIS-RTOS2 Timer"/>
3556         <file category="source" attr="template" name="CMSIS/RTOS2/RTX/Template/svc_user.c"  version="1.0.0" select="CMSIS-RTOS2 SVC User Table"/>
3557         <file category="other"  name="CMSIS/RTOS2/RTX/RTX5.scvd"/>
3558
3559         <!-- RTX sources (core) -->
3560         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_kernel.c"/>
3561         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_thread.c"/>
3562         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_delay.c"/>
3563         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_timer.c"/>
3564         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evflags.c"/>
3565         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mutex.c"/>
3566         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_semaphore.c"/>
3567         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_memory.c"/>
3568         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_mempool.c"/>
3569         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c"/>
3570         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_system.c"/>
3571         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_evr.c"/>
3572         <!-- RTX sources (library configuration) -->
3573         <file category="source" name="CMSIS/RTOS2/RTX/Source/rtx_lib.c"/>
3574         <!-- RTX sources (ARMCC handlers) -->
3575         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl_ns.s"    condition="CM23_ARMCC"/>
3576         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="CM33_ARMCC"/>
3577         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="CM33_FP_ARMCC"/>
3578         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="CM35P_ARMCC"/>
3579         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="CM35P_FP_ARMCC"/>
3580         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl_ns.s"    condition="ARMv8MBL_ARMCC"/>
3581         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="ARMv8MML_ARMCC"/>
3582         <file category="source" name="CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s"    condition="ARMv8MML_FP_ARMCC"/>
3583         <!-- RTX sources (GCC handlers) -->
3584         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl_ns.S"    condition="CM23_GCC"/>
3585         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_ns.S"    condition="CM33_GCC"/>
3586         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp_ns.S" condition="CM33_FP_GCC"/>
3587         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_ns.S"    condition="CM35P_GCC"/>
3588         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp_ns.S" condition="CM35P_FP_GCC"/>
3589         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl_ns.S"    condition="ARMv8MBL_GCC"/>
3590         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_ns.S"    condition="ARMv8MML_GCC"/>
3591         <file category="source" name="CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp_ns.S" condition="ARMv8MML_FP_GCC"/>
3592         <!-- RTX sources (IAR handlers) -->
3593         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl_ns.s"    condition="CM23_IAR"/>
3594         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="CM33_IAR"/>
3595         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="CM33_FP_IAR"/>
3596         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="CM35P_IAR"/>
3597         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="CM35P_FP_IAR"/>
3598         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl_ns.s"    condition="ARMv8MBL_IAR"/>
3599         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="ARMv8MML_IAR"/>
3600         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s"    condition="ARMv8MML_FP_IAR"/>
3601         <!-- OS Tick (SysTick) -->
3602         <file category="source" name="CMSIS/RTOS2/Source/os_systick.c"/>
3603       </files>
3604     </component>
3605
3606   </components>
3607
3608   <boards>
3609     <board name="uVision Simulator" vendor="Keil">
3610       <description>uVision Simulator</description>
3611       <mountedDevice    deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0"/>
3612       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0P"/>
3613       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0P_MPU"/>
3614       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM1"/>
3615       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM3"/>
3616       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM4"/>
3617       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM4_FP"/>
3618       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7"/>
3619       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7_SP"/>
3620       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7_DP"/>
3621       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MBL"/>
3622       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML"/>
3623       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML_SP"/>
3624       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML_DP"/>
3625       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM23"/>
3626       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM23_TZ"/>
3627       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33"/>
3628       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_TZ"/>
3629       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_DSP_FP"/>
3630       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_DSP_FP_TZ"/>
3631       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P"/>
3632       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P_TZ"/>
3633       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P_DSP_FP"/>
3634       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P_DSP_FP_TZ"/>
3635     </board>
3636
3637     <board name="EWARM Simulator" vendor="IAR">
3638       <description>EWARM Simulator</description>
3639       <mountedDevice    deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0"/>
3640       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0P"/>
3641       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0P_MPU"/>
3642       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM1"/>
3643       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM3"/>
3644       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM4"/>
3645       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM4_FP"/>
3646       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7"/>
3647       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7_SP"/>
3648       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM7_DP"/>
3649       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MBL"/>
3650       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML"/>
3651       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML_SP"/>
3652       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMv8MML_DP"/>
3653       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM23"/>
3654       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM23_TZ"/>
3655       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33"/>
3656       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_TZ"/>
3657       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_DSP_FP"/>
3658       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM33_DSP_FP_TZ"/>
3659       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P"/>
3660       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P_TZ"/>
3661       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P_DSP_FP"/>
3662       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM35P_DSP_FP_TZ"/>
3663     </board>
3664
3665     <board name="Fixed Virtual Platform" vendor="ARM">
3666       <description>Fixed Virtual Platform</description>
3667       <mountedDevice    deviceIndex="0" Dvendor="ARM:82" Dname="ARMCA5"/>
3668       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCA7"/>
3669       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCA9"/>
3670     </board>
3671   </boards>
3672
3673   <examples>
3674     <example name="DSP_Lib Class Marks example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_class_marks_example">
3675       <description>DSP_Lib Class Marks example</description>
3676       <board name="uVision Simulator" vendor="Keil"/>
3677       <project>
3678         <environment name="uv" load="arm_class_marks_example.uvprojx"/>
3679       </project>
3680       <attributes>
3681         <component Cclass="CMSIS" Cgroup="CORE"/>
3682         <component Cclass="CMSIS" Cgroup="DSP"/>
3683         <component Cclass="Device" Cgroup="Startup"/>
3684         <category>Getting Started</category>
3685       </attributes>
3686     </example>
3687
3688     <example name="DSP_Lib Convolution example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_convolution_example">
3689       <description>DSP_Lib Convolution example</description>
3690       <board name="uVision Simulator" vendor="Keil"/>
3691       <project>
3692         <environment name="uv" load="arm_convolution_example.uvprojx"/>
3693       </project>
3694       <attributes>
3695         <component Cclass="CMSIS" Cgroup="CORE"/>
3696         <component Cclass="CMSIS" Cgroup="DSP"/>
3697         <component Cclass="Device" Cgroup="Startup"/>
3698         <category>Getting Started</category>
3699       </attributes>
3700     </example>
3701
3702     <example name="DSP_Lib Dotproduct example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_dotproduct_example">
3703       <description>DSP_Lib Dotproduct example</description>
3704       <board name="uVision Simulator" vendor="Keil"/>
3705       <project>
3706         <environment name="uv" load="arm_dotproduct_example.uvprojx"/>
3707       </project>
3708       <attributes>
3709         <component Cclass="CMSIS" Cgroup="CORE"/>
3710         <component Cclass="CMSIS" Cgroup="DSP"/>
3711         <component Cclass="Device" Cgroup="Startup"/>
3712         <category>Getting Started</category>
3713       </attributes>
3714     </example>
3715
3716     <example name="DSP_Lib FFT Bin example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_fft_bin_example">
3717       <description>DSP_Lib FFT Bin example</description>
3718       <board name="uVision Simulator" vendor="Keil"/>
3719       <project>
3720         <environment name="uv" load="arm_fft_bin_example.uvprojx"/>
3721       </project>
3722       <attributes>
3723         <component Cclass="CMSIS" Cgroup="CORE"/>
3724         <component Cclass="CMSIS" Cgroup="DSP"/>
3725         <component Cclass="Device" Cgroup="Startup"/>
3726         <category>Getting Started</category>
3727       </attributes>
3728     </example>
3729
3730     <example name="DSP_Lib FIR example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_fir_example">
3731       <description>DSP_Lib FIR example</description>
3732       <board name="uVision Simulator" vendor="Keil"/>
3733       <project>
3734         <environment name="uv" load="arm_fir_example.uvprojx"/>
3735       </project>
3736       <attributes>
3737         <component Cclass="CMSIS" Cgroup="CORE"/>
3738         <component Cclass="CMSIS" Cgroup="DSP"/>
3739         <component Cclass="Device" Cgroup="Startup"/>
3740         <category>Getting Started</category>
3741       </attributes>
3742     </example>
3743
3744     <example name="DSP_Lib Graphic Equalizer example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example">
3745       <description>DSP_Lib Graphic Equalizer example</description>
3746       <board name="uVision Simulator" vendor="Keil"/>
3747       <project>
3748         <environment name="uv" load="arm_graphic_equalizer_example.uvprojx"/>
3749       </project>
3750       <attributes>
3751         <component Cclass="CMSIS" Cgroup="CORE"/>
3752         <component Cclass="CMSIS" Cgroup="DSP"/>
3753         <component Cclass="Device" Cgroup="Startup"/>
3754         <category>Getting Started</category>
3755       </attributes>
3756     </example>
3757
3758     <example name="DSP_Lib Linear Interpolation example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_linear_interp_example">
3759       <description>DSP_Lib Linear Interpolation example</description>
3760       <board name="uVision Simulator" vendor="Keil"/>
3761       <project>
3762         <environment name="uv" load="arm_linear_interp_example.uvprojx"/>
3763       </project>
3764       <attributes>
3765         <component Cclass="CMSIS" Cgroup="CORE"/>
3766         <component Cclass="CMSIS" Cgroup="DSP"/>
3767         <component Cclass="Device" Cgroup="Startup"/>
3768         <category>Getting Started</category>
3769       </attributes>
3770     </example>
3771
3772     <example name="DSP_Lib Matrix example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_matrix_example">
3773       <description>DSP_Lib Matrix example</description>
3774       <board name="uVision Simulator" vendor="Keil"/>
3775       <project>
3776         <environment name="uv" load="arm_matrix_example.uvprojx"/>
3777       </project>
3778       <attributes>
3779         <component Cclass="CMSIS" Cgroup="CORE"/>
3780         <component Cclass="CMSIS" Cgroup="DSP"/>
3781         <component Cclass="Device" Cgroup="Startup"/>
3782         <category>Getting Started</category>
3783       </attributes>
3784     </example>
3785
3786     <example name="DSP_Lib Signal Convergence example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_signal_converge_example">
3787       <description>DSP_Lib Signal Convergence example</description>
3788       <board name="uVision Simulator" vendor="Keil"/>
3789       <project>
3790         <environment name="uv" load="arm_signal_converge_example.uvprojx"/>
3791       </project>
3792       <attributes>
3793         <component Cclass="CMSIS" Cgroup="CORE"/>
3794         <component Cclass="CMSIS" Cgroup="DSP"/>
3795         <component Cclass="Device" Cgroup="Startup"/>
3796         <category>Getting Started</category>
3797       </attributes>
3798     </example>
3799
3800     <example name="DSP_Lib Sinus/Cosinus example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_sin_cos_example">
3801       <description>DSP_Lib Sinus/Cosinus example</description>
3802       <board name="uVision Simulator" vendor="Keil"/>
3803       <project>
3804         <environment name="uv" load="arm_sin_cos_example.uvprojx"/>
3805       </project>
3806       <attributes>
3807         <component Cclass="CMSIS" Cgroup="CORE"/>
3808         <component Cclass="CMSIS" Cgroup="DSP"/>
3809         <component Cclass="Device" Cgroup="Startup"/>
3810         <category>Getting Started</category>
3811       </attributes>
3812     </example>
3813
3814     <example name="DSP_Lib Variance example" doc="Abstract.txt" folder="CMSIS/DSP/Examples/ARM/arm_variance_example">
3815       <description>DSP_Lib Variance example</description>
3816       <board name="uVision Simulator" vendor="Keil"/>
3817       <project>
3818         <environment name="uv" load="arm_variance_example.uvprojx"/>
3819       </project>
3820       <attributes>
3821         <component Cclass="CMSIS" Cgroup="CORE"/>
3822         <component Cclass="CMSIS" Cgroup="DSP"/>
3823         <component Cclass="Device" Cgroup="Startup"/>
3824         <category>Getting Started</category>
3825       </attributes>
3826     </example>
3827
3828     <example name="NN Library CIFAR10" doc="readme.txt" folder="CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10">
3829       <description>Neural Network CIFAR10 example</description>
3830       <board name="uVision Simulator" vendor="Keil"/>
3831       <project>
3832         <environment name="uv" load="arm_nnexamples_cifar10.uvprojx"/>
3833       </project>
3834       <attributes>
3835         <component Cclass="CMSIS" Cgroup="CORE"/>
3836         <component Cclass="CMSIS" Cgroup="DSP"/>
3837         <component Cclass="CMSIS" Cgroup="NN Lib"/>
3838         <component Cclass="Device" Cgroup="Startup"/>
3839         <category>Getting Started</category>
3840       </attributes>
3841     </example>
3842
3843     <example name="NN-example-cifar10" doc="readme_iar.txt" folder="CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10">
3844       <description>Neural Network CIFAR10 example</description>
3845       <board name="EWARM Simulator" vendor="IAR"/>
3846       <project>
3847         <environment name="iar" load="NN-example-cifar10.ewp"/>
3848       </project>
3849       <attributes>
3850         <component Cclass="CMSIS" Cgroup="CORE"/>
3851         <component Cclass="CMSIS" Cgroup="DSP"/>
3852         <component Cclass="CMSIS" Cgroup="NN Lib"/>
3853         <component Cclass="Device" Cgroup="Startup"/>
3854         <category>Getting Started</category>
3855       </attributes>
3856     </example>
3857
3858     <example name="NN Library GRU" doc="readme.txt" folder="CMSIS/NN/Examples/ARM/arm_nn_examples/gru">
3859       <description>Neural Network GRU example</description>
3860       <board name="uVision Simulator" vendor="Keil"/>
3861       <project>
3862         <environment name="uv" load="arm_nnexamples_gru.uvprojx"/>
3863       </project>
3864       <attributes>
3865         <component Cclass="CMSIS" Cgroup="CORE"/>
3866         <component Cclass="CMSIS" Cgroup="DSP"/>
3867         <component Cclass="CMSIS" Cgroup="NN Lib"/>
3868         <component Cclass="Device" Cgroup="Startup"/>
3869         <category>Getting Started</category>
3870       </attributes>
3871     </example>
3872
3873     <example name="NN-example-gru" doc="readme_iar.txt" folder="CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-gru">
3874       <description>Neural Network GRU example</description>
3875       <board name="EWARM Simulator" vendor="IAR"/>
3876       <project>
3877         <environment name="iar" load="NN-example-gru.ewp"/>
3878       </project>
3879       <attributes>
3880         <component Cclass="CMSIS" Cgroup="CORE"/>
3881         <component Cclass="CMSIS" Cgroup="DSP"/>
3882         <component Cclass="CMSIS" Cgroup="NN Lib"/>
3883         <component Cclass="Device" Cgroup="Startup"/>
3884         <category>Getting Started</category>
3885       </attributes>
3886     </example>
3887
3888     <example name="CMSIS-RTOS2 Blinky" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/Blinky">
3889       <description>CMSIS-RTOS2 Blinky example</description>
3890       <board name="uVision Simulator" vendor="Keil"/>
3891       <project>
3892         <environment name="uv" load="Blinky.uvprojx"/>
3893       </project>
3894       <attributes>
3895         <component Cclass="CMSIS" Cgroup="CORE"/>
3896         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3897         <component Cclass="Device" Cgroup="Startup"/>
3898         <category>Getting Started</category>
3899       </attributes>
3900     </example>
3901
3902     <example name="CMSIS-RTOS2 RTX5 Migration" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/Migration">
3903       <description>CMSIS-RTOS2 mixed API v1 and v2</description>
3904       <board name="uVision Simulator" vendor="Keil"/>
3905       <project>
3906         <environment name="uv" load="Blinky.uvprojx"/>
3907       </project>
3908       <attributes>
3909         <component Cclass="CMSIS" Cgroup="CORE"/>
3910         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3911         <component Cclass="Device" Cgroup="Startup"/>
3912         <category>Getting Started</category>
3913       </attributes>
3914     </example>
3915
3916     <example name="CMSIS-RTOS2 RTX5 Message Queue" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/MsgQueue">
3917       <description>CMSIS-RTOS2 Message Queue Example</description>
3918       <board name="uVision Simulator" vendor="Keil"/>
3919       <project>
3920         <environment name="uv" load="MsqQueue.uvprojx"/>
3921       </project>
3922       <attributes>
3923         <component Cclass="CMSIS" Cgroup="CORE"/>
3924         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3925         <component Cclass="Compiler" Cgroup="EventRecorder"/>
3926         <component Cclass="Device" Cgroup="Startup"/>
3927         <category>Getting Started</category>
3928       </attributes>
3929     </example>
3930
3931     <example name="CMSIS-RTOS2 RTX5 Memory Pool" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/MemPool">
3932       <description>CMSIS-RTOS2 Memory Pool Example</description>
3933       <board name="Fixed Virtual Platform" vendor="ARM"/>
3934       <project>
3935         <environment name="uv" load="MemPool.uvprojx"/>
3936       </project>
3937       <attributes>
3938         <component Cclass="CMSIS" Cgroup="CORE"/>
3939         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3940         <component Cclass="Compiler" Cgroup="EventRecorder"/>
3941         <component Cclass="Device" Cgroup="Startup"/>
3942         <category>Getting Started</category>
3943       </attributes>
3944     </example>
3945
3946     <example name="TrustZone for ARMv8-M No RTOS" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/NoRTOS">
3947       <description>Bare-metal secure/non-secure example without RTOS</description>
3948       <board name="uVision Simulator" vendor="Keil"/>
3949       <project>
3950         <environment name="uv" load="NoRTOS.uvmpw"/>
3951       </project>
3952       <attributes>
3953         <component Cclass="CMSIS" Cgroup="CORE"/>
3954         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3955         <component Cclass="Device" Cgroup="Startup"/>
3956         <category>Getting Started</category>
3957       </attributes>
3958     </example>
3959
3960     <example name="TrustZone for ARMv8-M RTOS"  doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS">
3961       <description>Secure/non-secure RTOS example with thread context management</description>
3962       <board name="uVision Simulator" vendor="Keil"/>
3963       <project>
3964         <environment name="uv" load="RTOS.uvmpw"/>
3965       </project>
3966       <attributes>
3967         <component Cclass="CMSIS" Cgroup="CORE"/>
3968         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3969         <component Cclass="Device" Cgroup="Startup"/>
3970         <category>Getting Started</category>
3971       </attributes>
3972     </example>
3973
3974     <example name="TrustZone for ARMv8-M RTOS Security Tests"  doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults">
3975       <description>Secure/non-secure RTOS example with security test cases and system recovery</description>
3976       <board name="uVision Simulator" vendor="Keil"/>
3977       <project>
3978         <environment name="uv" load="RTOS_Faults.uvmpw"/>
3979       </project>
3980       <attributes>
3981         <component Cclass="CMSIS" Cgroup="CORE"/>
3982         <component Cclass="CMSIS" Cgroup="RTOS2"/>
3983         <component Cclass="Device" Cgroup="Startup"/>
3984         <category>Getting Started</category>
3985       </attributes>
3986     </example>
3987
3988   </examples>
3989
3990 </package>