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55 <div id="projectbrief">CMSIS-Core support for Cortex-A processor-based devices</div>
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130 <div class="summary">
131 <a href="#define-members">Macros</a> </div>
132 <div class="headertitle"><div class="title">ACTLR Bits<div class="ingroups"><a class="el" href="group__CMSIS__core__register.html">Core Register Access</a> » <a class="el" href="group__CMSIS__ACTLR.html">Auxiliary Control Register (ACTLR)</a></div></div></div>
134 <div class="contents">
136 <p>Bit position and mask macros.
137 <a href="#details">More...</a></p>
138 <table class="memberdecls">
139 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a>
140 Macros</h2></td></tr>
141 <tr class="memitem:ga5468e93550ce28af7114cbc1e19474c0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga5468e93550ce28af7114cbc1e19474c0">ACTLR_DDI_Pos</a>   28U</td></tr>
142 <tr class="memdesc:ga5468e93550ce28af7114cbc1e19474c0"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: DDI Position. <br /></td></tr>
143 <tr class="separator:ga5468e93550ce28af7114cbc1e19474c0"><td class="memSeparator" colspan="2"> </td></tr>
144 <tr class="memitem:gaeee8e0fc7b28f2a405b234e7d2c7486e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gaeee8e0fc7b28f2a405b234e7d2c7486e">ACTLR_DDI_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga5468e93550ce28af7114cbc1e19474c0">ACTLR_DDI_Pos</a>)</td></tr>
145 <tr class="memdesc:gaeee8e0fc7b28f2a405b234e7d2c7486e"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: DDI Mask. <br /></td></tr>
146 <tr class="separator:gaeee8e0fc7b28f2a405b234e7d2c7486e"><td class="memSeparator" colspan="2"> </td></tr>
147 <tr class="memitem:ga0367a8413c0a37d6c1de7b90f3a56aee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga0367a8413c0a37d6c1de7b90f3a56aee">ACTLR_DBDI_Pos</a>   28U</td></tr>
148 <tr class="memdesc:ga0367a8413c0a37d6c1de7b90f3a56aee"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: DBDI Position. <br /></td></tr>
149 <tr class="separator:ga0367a8413c0a37d6c1de7b90f3a56aee"><td class="memSeparator" colspan="2"> </td></tr>
150 <tr class="memitem:ga0a3d58754927731758c53bd945ac35fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga0a3d58754927731758c53bd945ac35fe">ACTLR_DBDI_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga0367a8413c0a37d6c1de7b90f3a56aee">ACTLR_DBDI_Pos</a>)</td></tr>
151 <tr class="memdesc:ga0a3d58754927731758c53bd945ac35fe"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: DBDI Mask. <br /></td></tr>
152 <tr class="separator:ga0a3d58754927731758c53bd945ac35fe"><td class="memSeparator" colspan="2"> </td></tr>
153 <tr class="memitem:ga8c81a1e1522400322f215c52ca80d47d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga8c81a1e1522400322f215c52ca80d47d">ACTLR_BTDIS_Pos</a>   18U</td></tr>
154 <tr class="memdesc:ga8c81a1e1522400322f215c52ca80d47d"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: BTDIS Position. <br /></td></tr>
155 <tr class="separator:ga8c81a1e1522400322f215c52ca80d47d"><td class="memSeparator" colspan="2"> </td></tr>
156 <tr class="memitem:gad48e0a1c1e59e6721547b45f37baa48b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gad48e0a1c1e59e6721547b45f37baa48b">ACTLR_BTDIS_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga8c81a1e1522400322f215c52ca80d47d">ACTLR_BTDIS_Pos</a>)</td></tr>
157 <tr class="memdesc:gad48e0a1c1e59e6721547b45f37baa48b"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: BTDIS Mask. <br /></td></tr>
158 <tr class="separator:gad48e0a1c1e59e6721547b45f37baa48b"><td class="memSeparator" colspan="2"> </td></tr>
159 <tr class="memitem:ga4412a55ce52db3c5a4f035fcd0e350c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga4412a55ce52db3c5a4f035fcd0e350c6">ACTLR_RSDIS_Pos</a>   17U</td></tr>
160 <tr class="memdesc:ga4412a55ce52db3c5a4f035fcd0e350c6"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: RSDIS Position. <br /></td></tr>
161 <tr class="separator:ga4412a55ce52db3c5a4f035fcd0e350c6"><td class="memSeparator" colspan="2"> </td></tr>
162 <tr class="memitem:ga8487babc3514e2bb8f3d524e5f80d95f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga8487babc3514e2bb8f3d524e5f80d95f">ACTLR_RSDIS_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga4412a55ce52db3c5a4f035fcd0e350c6">ACTLR_RSDIS_Pos</a>)</td></tr>
163 <tr class="memdesc:ga8487babc3514e2bb8f3d524e5f80d95f"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: RSDIS Mask. <br /></td></tr>
164 <tr class="separator:ga8487babc3514e2bb8f3d524e5f80d95f"><td class="memSeparator" colspan="2"> </td></tr>
165 <tr class="memitem:ga120f5d653af52bd711c27c2495ce78f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga120f5d653af52bd711c27c2495ce78f6">ACTLR_BP_Pos</a>   15U</td></tr>
166 <tr class="memdesc:ga120f5d653af52bd711c27c2495ce78f6"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: BP Position. <br /></td></tr>
167 <tr class="separator:ga120f5d653af52bd711c27c2495ce78f6"><td class="memSeparator" colspan="2"> </td></tr>
168 <tr class="memitem:ga677211818d8a2c7b118115361fbef2e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga677211818d8a2c7b118115361fbef2e7">ACTLR_BP_Msk</a>   (3UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga120f5d653af52bd711c27c2495ce78f6">ACTLR_BP_Pos</a>)</td></tr>
169 <tr class="memdesc:ga677211818d8a2c7b118115361fbef2e7"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: BP Mask. <br /></td></tr>
170 <tr class="separator:ga677211818d8a2c7b118115361fbef2e7"><td class="memSeparator" colspan="2"> </td></tr>
171 <tr class="memitem:gaa9fe7651aa9bb48eea4f5301c69ee54d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gaa9fe7651aa9bb48eea4f5301c69ee54d">ACTLR_DDVM_Pos</a>   15U</td></tr>
172 <tr class="memdesc:gaa9fe7651aa9bb48eea4f5301c69ee54d"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: DDVM Position. <br /></td></tr>
173 <tr class="separator:gaa9fe7651aa9bb48eea4f5301c69ee54d"><td class="memSeparator" colspan="2"> </td></tr>
174 <tr class="memitem:ga4565f2632e5c4be5e1d3eb90fa6f2ac6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga4565f2632e5c4be5e1d3eb90fa6f2ac6">ACTLR_DDVM_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#gaa9fe7651aa9bb48eea4f5301c69ee54d">ACTLR_DDVM_Pos</a>)</td></tr>
175 <tr class="memdesc:ga4565f2632e5c4be5e1d3eb90fa6f2ac6"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: DDVM Mask. <br /></td></tr>
176 <tr class="separator:ga4565f2632e5c4be5e1d3eb90fa6f2ac6"><td class="memSeparator" colspan="2"> </td></tr>
177 <tr class="memitem:ga546f1f2bbf7344bad6522205257f17ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga546f1f2bbf7344bad6522205257f17ae">ACTLR_L1PCTL_Pos</a>   13U</td></tr>
178 <tr class="memdesc:ga546f1f2bbf7344bad6522205257f17ae"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: L1PCTL Position. <br /></td></tr>
179 <tr class="separator:ga546f1f2bbf7344bad6522205257f17ae"><td class="memSeparator" colspan="2"> </td></tr>
180 <tr class="memitem:gad701fa3ff69b89ba185b7482e81cb6fd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gad701fa3ff69b89ba185b7482e81cb6fd">ACTLR_L1PCTL_Msk</a>   (3UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga546f1f2bbf7344bad6522205257f17ae">ACTLR_L1PCTL_Pos</a>)</td></tr>
181 <tr class="memdesc:gad701fa3ff69b89ba185b7482e81cb6fd"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: L1PCTL Mask. <br /></td></tr>
182 <tr class="separator:gad701fa3ff69b89ba185b7482e81cb6fd"><td class="memSeparator" colspan="2"> </td></tr>
183 <tr class="memitem:gaf7a424f7f8c4f46592ce8f47f4bced44"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gaf7a424f7f8c4f46592ce8f47f4bced44">ACTLR_RADIS_Pos</a>   12U</td></tr>
184 <tr class="memdesc:gaf7a424f7f8c4f46592ce8f47f4bced44"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: RADIS Position. <br /></td></tr>
185 <tr class="separator:gaf7a424f7f8c4f46592ce8f47f4bced44"><td class="memSeparator" colspan="2"> </td></tr>
186 <tr class="memitem:gac6aea849e5320c0e93321d5d8b0c117c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gac6aea849e5320c0e93321d5d8b0c117c">ACTLR_RADIS_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#gaf7a424f7f8c4f46592ce8f47f4bced44">ACTLR_RADIS_Pos</a>)</td></tr>
187 <tr class="memdesc:gac6aea849e5320c0e93321d5d8b0c117c"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: RADIS Mask. <br /></td></tr>
188 <tr class="separator:gac6aea849e5320c0e93321d5d8b0c117c"><td class="memSeparator" colspan="2"> </td></tr>
189 <tr class="memitem:gaf8b306b854ecd78110cf944d414644a1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gaf8b306b854ecd78110cf944d414644a1">ACTLR_L1RADIS_Pos</a>   12U</td></tr>
190 <tr class="memdesc:gaf8b306b854ecd78110cf944d414644a1"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: L1RADIS Position. <br /></td></tr>
191 <tr class="separator:gaf8b306b854ecd78110cf944d414644a1"><td class="memSeparator" colspan="2"> </td></tr>
192 <tr class="memitem:ga6aafd83ca6c02f705def8edc8c064c04"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga6aafd83ca6c02f705def8edc8c064c04">ACTLR_L1RADIS_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#gaf8b306b854ecd78110cf944d414644a1">ACTLR_L1RADIS_Pos</a>)</td></tr>
193 <tr class="memdesc:ga6aafd83ca6c02f705def8edc8c064c04"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: L1RADIS Mask. <br /></td></tr>
194 <tr class="separator:ga6aafd83ca6c02f705def8edc8c064c04"><td class="memSeparator" colspan="2"> </td></tr>
195 <tr class="memitem:ga4ca2a9236b157d3f9405cf8c398897a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga4ca2a9236b157d3f9405cf8c398897a2">ACTLR_DWBST_Pos</a>   11U</td></tr>
196 <tr class="memdesc:ga4ca2a9236b157d3f9405cf8c398897a2"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: DWBST Position. <br /></td></tr>
197 <tr class="separator:ga4ca2a9236b157d3f9405cf8c398897a2"><td class="memSeparator" colspan="2"> </td></tr>
198 <tr class="memitem:gab948ab9af88a9357e2e383d948e9dc7e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gab948ab9af88a9357e2e383d948e9dc7e">ACTLR_DWBST_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga4ca2a9236b157d3f9405cf8c398897a2">ACTLR_DWBST_Pos</a>)</td></tr>
199 <tr class="memdesc:gab948ab9af88a9357e2e383d948e9dc7e"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: DWBST Mask. <br /></td></tr>
200 <tr class="separator:gab948ab9af88a9357e2e383d948e9dc7e"><td class="memSeparator" colspan="2"> </td></tr>
201 <tr class="memitem:ga505f33bbe45bbcaa9fcb738cb30daf4e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga505f33bbe45bbcaa9fcb738cb30daf4e">ACTLR_L2RADIS_Pos</a>   11U</td></tr>
202 <tr class="memdesc:ga505f33bbe45bbcaa9fcb738cb30daf4e"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: L2RADIS Position. <br /></td></tr>
203 <tr class="separator:ga505f33bbe45bbcaa9fcb738cb30daf4e"><td class="memSeparator" colspan="2"> </td></tr>
204 <tr class="memitem:gad84b20f4f5d1979bb000a14a582cad12"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gad84b20f4f5d1979bb000a14a582cad12">ACTLR_L2RADIS_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga505f33bbe45bbcaa9fcb738cb30daf4e">ACTLR_L2RADIS_Pos</a>)</td></tr>
205 <tr class="memdesc:gad84b20f4f5d1979bb000a14a582cad12"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: L2RADIS Mask. <br /></td></tr>
206 <tr class="separator:gad84b20f4f5d1979bb000a14a582cad12"><td class="memSeparator" colspan="2"> </td></tr>
207 <tr class="memitem:ga96eb411770c8e2b87f5e62b95e50ee02"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga96eb411770c8e2b87f5e62b95e50ee02">ACTLR_DODMBS_Pos</a>   10U</td></tr>
208 <tr class="memdesc:ga96eb411770c8e2b87f5e62b95e50ee02"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: DODMBS Position. <br /></td></tr>
209 <tr class="separator:ga96eb411770c8e2b87f5e62b95e50ee02"><td class="memSeparator" colspan="2"> </td></tr>
210 <tr class="memitem:ga88a85e6310334edb190a6e9298ae98b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga88a85e6310334edb190a6e9298ae98b7">ACTLR_DODMBS_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga96eb411770c8e2b87f5e62b95e50ee02">ACTLR_DODMBS_Pos</a>)</td></tr>
211 <tr class="memdesc:ga88a85e6310334edb190a6e9298ae98b7"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: DODMBS Mask. <br /></td></tr>
212 <tr class="separator:ga88a85e6310334edb190a6e9298ae98b7"><td class="memSeparator" colspan="2"> </td></tr>
213 <tr class="memitem:ga8300a65b41aa3f5c69c7cc713c847749"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga8300a65b41aa3f5c69c7cc713c847749">ACTLR_PARITY_Pos</a>   9U</td></tr>
214 <tr class="memdesc:ga8300a65b41aa3f5c69c7cc713c847749"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: PARITY Position. <br /></td></tr>
215 <tr class="separator:ga8300a65b41aa3f5c69c7cc713c847749"><td class="memSeparator" colspan="2"> </td></tr>
216 <tr class="memitem:gadec8e5d68791dc4749bf3f075a3559fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gadec8e5d68791dc4749bf3f075a3559fb">ACTLR_PARITY_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga8300a65b41aa3f5c69c7cc713c847749">ACTLR_PARITY_Pos</a>)</td></tr>
217 <tr class="memdesc:gadec8e5d68791dc4749bf3f075a3559fb"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: PARITY Mask. <br /></td></tr>
218 <tr class="separator:gadec8e5d68791dc4749bf3f075a3559fb"><td class="memSeparator" colspan="2"> </td></tr>
219 <tr class="memitem:ga633ee6b129f8668593687ab8537aeb7f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga633ee6b129f8668593687ab8537aeb7f">ACTLR_AOW_Pos</a>   8U</td></tr>
220 <tr class="memdesc:ga633ee6b129f8668593687ab8537aeb7f"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: AOW Position. <br /></td></tr>
221 <tr class="separator:ga633ee6b129f8668593687ab8537aeb7f"><td class="memSeparator" colspan="2"> </td></tr>
222 <tr class="memitem:ga5ca6754c31f90c7e5d1822dddfb4135c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga5ca6754c31f90c7e5d1822dddfb4135c">ACTLR_AOW_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga633ee6b129f8668593687ab8537aeb7f">ACTLR_AOW_Pos</a>)</td></tr>
223 <tr class="memdesc:ga5ca6754c31f90c7e5d1822dddfb4135c"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: AOW Mask. <br /></td></tr>
224 <tr class="separator:ga5ca6754c31f90c7e5d1822dddfb4135c"><td class="memSeparator" colspan="2"> </td></tr>
225 <tr class="memitem:ga17dcfbcdf5db82900354db5440699701"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga17dcfbcdf5db82900354db5440699701">ACTLR_EXCL_Pos</a>   7U</td></tr>
226 <tr class="memdesc:ga17dcfbcdf5db82900354db5440699701"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: EXCL Position. <br /></td></tr>
227 <tr class="separator:ga17dcfbcdf5db82900354db5440699701"><td class="memSeparator" colspan="2"> </td></tr>
228 <tr class="memitem:ga8b704419a7ed130ecbee00de9fd72d55"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga8b704419a7ed130ecbee00de9fd72d55">ACTLR_EXCL_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga17dcfbcdf5db82900354db5440699701">ACTLR_EXCL_Pos</a>)</td></tr>
229 <tr class="memdesc:ga8b704419a7ed130ecbee00de9fd72d55"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: EXCL Mask. <br /></td></tr>
230 <tr class="separator:ga8b704419a7ed130ecbee00de9fd72d55"><td class="memSeparator" colspan="2"> </td></tr>
231 <tr class="memitem:ga8cb19db067cca1e064189b27b1f1bcbf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga8cb19db067cca1e064189b27b1f1bcbf">ACTLR_SMP_Pos</a>   6U</td></tr>
232 <tr class="memdesc:ga8cb19db067cca1e064189b27b1f1bcbf"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: SMP Position. <br /></td></tr>
233 <tr class="separator:ga8cb19db067cca1e064189b27b1f1bcbf"><td class="memSeparator" colspan="2"> </td></tr>
234 <tr class="memitem:gac6dcc315f6c4527434b9b0e4106771d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gac6dcc315f6c4527434b9b0e4106771d8">ACTLR_SMP_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga8cb19db067cca1e064189b27b1f1bcbf">ACTLR_SMP_Pos</a>)</td></tr>
235 <tr class="memdesc:gac6dcc315f6c4527434b9b0e4106771d8"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: SMP Mask. <br /></td></tr>
236 <tr class="separator:gac6dcc315f6c4527434b9b0e4106771d8"><td class="memSeparator" colspan="2"> </td></tr>
237 <tr class="memitem:ga104112fe1d88dde49635e9b0f9530306"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga104112fe1d88dde49635e9b0f9530306">ACTLR_WFLZM_Pos</a>   3U</td></tr>
238 <tr class="memdesc:ga104112fe1d88dde49635e9b0f9530306"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: WFLZM Position. <br /></td></tr>
239 <tr class="separator:ga104112fe1d88dde49635e9b0f9530306"><td class="memSeparator" colspan="2"> </td></tr>
240 <tr class="memitem:gae5a89cb553773b10e86a9c826f11179f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gae5a89cb553773b10e86a9c826f11179f">ACTLR_WFLZM_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga104112fe1d88dde49635e9b0f9530306">ACTLR_WFLZM_Pos</a>)</td></tr>
241 <tr class="memdesc:gae5a89cb553773b10e86a9c826f11179f"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: WFLZM Mask. <br /></td></tr>
242 <tr class="separator:gae5a89cb553773b10e86a9c826f11179f"><td class="memSeparator" colspan="2"> </td></tr>
243 <tr class="memitem:ga65c3c81261a2aa26022f6bb967c4e56b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga65c3c81261a2aa26022f6bb967c4e56b">ACTLR_L1PE_Pos</a>   2U</td></tr>
244 <tr class="memdesc:ga65c3c81261a2aa26022f6bb967c4e56b"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: L1PE Position. <br /></td></tr>
245 <tr class="separator:ga65c3c81261a2aa26022f6bb967c4e56b"><td class="memSeparator" colspan="2"> </td></tr>
246 <tr class="memitem:ga969c20495fe3e50e8c2a73454688a674"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga969c20495fe3e50e8c2a73454688a674">ACTLR_L1PE_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga65c3c81261a2aa26022f6bb967c4e56b">ACTLR_L1PE_Pos</a>)</td></tr>
247 <tr class="memdesc:ga969c20495fe3e50e8c2a73454688a674"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: L1PE Mask. <br /></td></tr>
248 <tr class="separator:ga969c20495fe3e50e8c2a73454688a674"><td class="memSeparator" colspan="2"> </td></tr>
249 <tr class="memitem:ga89b1a661668534177bc9679149a692ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga89b1a661668534177bc9679149a692ce">ACTLR_FW_Pos</a>   0U</td></tr>
250 <tr class="memdesc:ga89b1a661668534177bc9679149a692ce"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: FW Position. <br /></td></tr>
251 <tr class="separator:ga89b1a661668534177bc9679149a692ce"><td class="memSeparator" colspan="2"> </td></tr>
252 <tr class="memitem:ga53ea0cfa2dd5cb51d9f9de21e4d2dbf1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga53ea0cfa2dd5cb51d9f9de21e4d2dbf1">ACTLR_FW_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga89b1a661668534177bc9679149a692ce">ACTLR_FW_Pos</a>)</td></tr>
253 <tr class="memdesc:ga53ea0cfa2dd5cb51d9f9de21e4d2dbf1"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: FW Mask. <br /></td></tr>
254 <tr class="separator:ga53ea0cfa2dd5cb51d9f9de21e4d2dbf1"><td class="memSeparator" colspan="2"> </td></tr>
256 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
257 <h2 class="groupheader">Macro Definition Documentation</h2>
258 <a id="ga5ca6754c31f90c7e5d1822dddfb4135c" name="ga5ca6754c31f90c7e5d1822dddfb4135c"></a>
259 <h2 class="memtitle"><span class="permalink"><a href="#ga5ca6754c31f90c7e5d1822dddfb4135c">◆ </a></span>ACTLR_AOW_Msk</h2>
261 <div class="memitem">
262 <div class="memproto">
263 <table class="memname">
265 <td class="memname">#define ACTLR_AOW_Msk   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga633ee6b129f8668593687ab8537aeb7f">ACTLR_AOW_Pos</a>)</td>
268 </div><div class="memdoc">
272 <a id="ga633ee6b129f8668593687ab8537aeb7f" name="ga633ee6b129f8668593687ab8537aeb7f"></a>
273 <h2 class="memtitle"><span class="permalink"><a href="#ga633ee6b129f8668593687ab8537aeb7f">◆ </a></span>ACTLR_AOW_Pos</h2>
275 <div class="memitem">
276 <div class="memproto">
277 <table class="memname">
279 <td class="memname">#define ACTLR_AOW_Pos   8U</td>
282 </div><div class="memdoc">
286 <a id="ga677211818d8a2c7b118115361fbef2e7" name="ga677211818d8a2c7b118115361fbef2e7"></a>
287 <h2 class="memtitle"><span class="permalink"><a href="#ga677211818d8a2c7b118115361fbef2e7">◆ </a></span>ACTLR_BP_Msk</h2>
289 <div class="memitem">
290 <div class="memproto">
291 <table class="memname">
293 <td class="memname">#define ACTLR_BP_Msk   (3UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga120f5d653af52bd711c27c2495ce78f6">ACTLR_BP_Pos</a>)</td>
296 </div><div class="memdoc">
300 <a id="ga120f5d653af52bd711c27c2495ce78f6" name="ga120f5d653af52bd711c27c2495ce78f6"></a>
301 <h2 class="memtitle"><span class="permalink"><a href="#ga120f5d653af52bd711c27c2495ce78f6">◆ </a></span>ACTLR_BP_Pos</h2>
303 <div class="memitem">
304 <div class="memproto">
305 <table class="memname">
307 <td class="memname">#define ACTLR_BP_Pos   15U</td>
310 </div><div class="memdoc">
314 <a id="gad48e0a1c1e59e6721547b45f37baa48b" name="gad48e0a1c1e59e6721547b45f37baa48b"></a>
315 <h2 class="memtitle"><span class="permalink"><a href="#gad48e0a1c1e59e6721547b45f37baa48b">◆ </a></span>ACTLR_BTDIS_Msk</h2>
317 <div class="memitem">
318 <div class="memproto">
319 <table class="memname">
321 <td class="memname">#define ACTLR_BTDIS_Msk   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga8c81a1e1522400322f215c52ca80d47d">ACTLR_BTDIS_Pos</a>)</td>
324 </div><div class="memdoc">
328 <a id="ga8c81a1e1522400322f215c52ca80d47d" name="ga8c81a1e1522400322f215c52ca80d47d"></a>
329 <h2 class="memtitle"><span class="permalink"><a href="#ga8c81a1e1522400322f215c52ca80d47d">◆ </a></span>ACTLR_BTDIS_Pos</h2>
331 <div class="memitem">
332 <div class="memproto">
333 <table class="memname">
335 <td class="memname">#define ACTLR_BTDIS_Pos   18U</td>
338 </div><div class="memdoc">
342 <a id="ga0a3d58754927731758c53bd945ac35fe" name="ga0a3d58754927731758c53bd945ac35fe"></a>
343 <h2 class="memtitle"><span class="permalink"><a href="#ga0a3d58754927731758c53bd945ac35fe">◆ </a></span>ACTLR_DBDI_Msk</h2>
345 <div class="memitem">
346 <div class="memproto">
347 <table class="memname">
349 <td class="memname">#define ACTLR_DBDI_Msk   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga0367a8413c0a37d6c1de7b90f3a56aee">ACTLR_DBDI_Pos</a>)</td>
352 </div><div class="memdoc">
356 <a id="ga0367a8413c0a37d6c1de7b90f3a56aee" name="ga0367a8413c0a37d6c1de7b90f3a56aee"></a>
357 <h2 class="memtitle"><span class="permalink"><a href="#ga0367a8413c0a37d6c1de7b90f3a56aee">◆ </a></span>ACTLR_DBDI_Pos</h2>
359 <div class="memitem">
360 <div class="memproto">
361 <table class="memname">
363 <td class="memname">#define ACTLR_DBDI_Pos   28U</td>
366 </div><div class="memdoc">
370 <a id="gaeee8e0fc7b28f2a405b234e7d2c7486e" name="gaeee8e0fc7b28f2a405b234e7d2c7486e"></a>
371 <h2 class="memtitle"><span class="permalink"><a href="#gaeee8e0fc7b28f2a405b234e7d2c7486e">◆ </a></span>ACTLR_DDI_Msk</h2>
373 <div class="memitem">
374 <div class="memproto">
375 <table class="memname">
377 <td class="memname">#define ACTLR_DDI_Msk   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga5468e93550ce28af7114cbc1e19474c0">ACTLR_DDI_Pos</a>)</td>
380 </div><div class="memdoc">
384 <a id="ga5468e93550ce28af7114cbc1e19474c0" name="ga5468e93550ce28af7114cbc1e19474c0"></a>
385 <h2 class="memtitle"><span class="permalink"><a href="#ga5468e93550ce28af7114cbc1e19474c0">◆ </a></span>ACTLR_DDI_Pos</h2>
387 <div class="memitem">
388 <div class="memproto">
389 <table class="memname">
391 <td class="memname">#define ACTLR_DDI_Pos   28U</td>
394 </div><div class="memdoc">
398 <a id="ga4565f2632e5c4be5e1d3eb90fa6f2ac6" name="ga4565f2632e5c4be5e1d3eb90fa6f2ac6"></a>
399 <h2 class="memtitle"><span class="permalink"><a href="#ga4565f2632e5c4be5e1d3eb90fa6f2ac6">◆ </a></span>ACTLR_DDVM_Msk</h2>
401 <div class="memitem">
402 <div class="memproto">
403 <table class="memname">
405 <td class="memname">#define ACTLR_DDVM_Msk   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#gaa9fe7651aa9bb48eea4f5301c69ee54d">ACTLR_DDVM_Pos</a>)</td>
408 </div><div class="memdoc">
412 <a id="gaa9fe7651aa9bb48eea4f5301c69ee54d" name="gaa9fe7651aa9bb48eea4f5301c69ee54d"></a>
413 <h2 class="memtitle"><span class="permalink"><a href="#gaa9fe7651aa9bb48eea4f5301c69ee54d">◆ </a></span>ACTLR_DDVM_Pos</h2>
415 <div class="memitem">
416 <div class="memproto">
417 <table class="memname">
419 <td class="memname">#define ACTLR_DDVM_Pos   15U</td>
422 </div><div class="memdoc">
426 <a id="ga88a85e6310334edb190a6e9298ae98b7" name="ga88a85e6310334edb190a6e9298ae98b7"></a>
427 <h2 class="memtitle"><span class="permalink"><a href="#ga88a85e6310334edb190a6e9298ae98b7">◆ </a></span>ACTLR_DODMBS_Msk</h2>
429 <div class="memitem">
430 <div class="memproto">
431 <table class="memname">
433 <td class="memname">#define ACTLR_DODMBS_Msk   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga96eb411770c8e2b87f5e62b95e50ee02">ACTLR_DODMBS_Pos</a>)</td>
436 </div><div class="memdoc">
440 <a id="ga96eb411770c8e2b87f5e62b95e50ee02" name="ga96eb411770c8e2b87f5e62b95e50ee02"></a>
441 <h2 class="memtitle"><span class="permalink"><a href="#ga96eb411770c8e2b87f5e62b95e50ee02">◆ </a></span>ACTLR_DODMBS_Pos</h2>
443 <div class="memitem">
444 <div class="memproto">
445 <table class="memname">
447 <td class="memname">#define ACTLR_DODMBS_Pos   10U</td>
450 </div><div class="memdoc">
454 <a id="gab948ab9af88a9357e2e383d948e9dc7e" name="gab948ab9af88a9357e2e383d948e9dc7e"></a>
455 <h2 class="memtitle"><span class="permalink"><a href="#gab948ab9af88a9357e2e383d948e9dc7e">◆ </a></span>ACTLR_DWBST_Msk</h2>
457 <div class="memitem">
458 <div class="memproto">
459 <table class="memname">
461 <td class="memname">#define ACTLR_DWBST_Msk   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga4ca2a9236b157d3f9405cf8c398897a2">ACTLR_DWBST_Pos</a>)</td>
464 </div><div class="memdoc">
468 <a id="ga4ca2a9236b157d3f9405cf8c398897a2" name="ga4ca2a9236b157d3f9405cf8c398897a2"></a>
469 <h2 class="memtitle"><span class="permalink"><a href="#ga4ca2a9236b157d3f9405cf8c398897a2">◆ </a></span>ACTLR_DWBST_Pos</h2>
471 <div class="memitem">
472 <div class="memproto">
473 <table class="memname">
475 <td class="memname">#define ACTLR_DWBST_Pos   11U</td>
478 </div><div class="memdoc">
482 <a id="ga8b704419a7ed130ecbee00de9fd72d55" name="ga8b704419a7ed130ecbee00de9fd72d55"></a>
483 <h2 class="memtitle"><span class="permalink"><a href="#ga8b704419a7ed130ecbee00de9fd72d55">◆ </a></span>ACTLR_EXCL_Msk</h2>
485 <div class="memitem">
486 <div class="memproto">
487 <table class="memname">
489 <td class="memname">#define ACTLR_EXCL_Msk   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga17dcfbcdf5db82900354db5440699701">ACTLR_EXCL_Pos</a>)</td>
492 </div><div class="memdoc">
496 <a id="ga17dcfbcdf5db82900354db5440699701" name="ga17dcfbcdf5db82900354db5440699701"></a>
497 <h2 class="memtitle"><span class="permalink"><a href="#ga17dcfbcdf5db82900354db5440699701">◆ </a></span>ACTLR_EXCL_Pos</h2>
499 <div class="memitem">
500 <div class="memproto">
501 <table class="memname">
503 <td class="memname">#define ACTLR_EXCL_Pos   7U</td>
506 </div><div class="memdoc">
510 <a id="ga53ea0cfa2dd5cb51d9f9de21e4d2dbf1" name="ga53ea0cfa2dd5cb51d9f9de21e4d2dbf1"></a>
511 <h2 class="memtitle"><span class="permalink"><a href="#ga53ea0cfa2dd5cb51d9f9de21e4d2dbf1">◆ </a></span>ACTLR_FW_Msk</h2>
513 <div class="memitem">
514 <div class="memproto">
515 <table class="memname">
517 <td class="memname">#define ACTLR_FW_Msk   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga89b1a661668534177bc9679149a692ce">ACTLR_FW_Pos</a>)</td>
520 </div><div class="memdoc">
524 <a id="ga89b1a661668534177bc9679149a692ce" name="ga89b1a661668534177bc9679149a692ce"></a>
525 <h2 class="memtitle"><span class="permalink"><a href="#ga89b1a661668534177bc9679149a692ce">◆ </a></span>ACTLR_FW_Pos</h2>
527 <div class="memitem">
528 <div class="memproto">
529 <table class="memname">
531 <td class="memname">#define ACTLR_FW_Pos   0U</td>
534 </div><div class="memdoc">
538 <a id="gad701fa3ff69b89ba185b7482e81cb6fd" name="gad701fa3ff69b89ba185b7482e81cb6fd"></a>
539 <h2 class="memtitle"><span class="permalink"><a href="#gad701fa3ff69b89ba185b7482e81cb6fd">◆ </a></span>ACTLR_L1PCTL_Msk</h2>
541 <div class="memitem">
542 <div class="memproto">
543 <table class="memname">
545 <td class="memname">#define ACTLR_L1PCTL_Msk   (3UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga546f1f2bbf7344bad6522205257f17ae">ACTLR_L1PCTL_Pos</a>)</td>
548 </div><div class="memdoc">
552 <a id="ga546f1f2bbf7344bad6522205257f17ae" name="ga546f1f2bbf7344bad6522205257f17ae"></a>
553 <h2 class="memtitle"><span class="permalink"><a href="#ga546f1f2bbf7344bad6522205257f17ae">◆ </a></span>ACTLR_L1PCTL_Pos</h2>
555 <div class="memitem">
556 <div class="memproto">
557 <table class="memname">
559 <td class="memname">#define ACTLR_L1PCTL_Pos   13U</td>
562 </div><div class="memdoc">
566 <a id="ga969c20495fe3e50e8c2a73454688a674" name="ga969c20495fe3e50e8c2a73454688a674"></a>
567 <h2 class="memtitle"><span class="permalink"><a href="#ga969c20495fe3e50e8c2a73454688a674">◆ </a></span>ACTLR_L1PE_Msk</h2>
569 <div class="memitem">
570 <div class="memproto">
571 <table class="memname">
573 <td class="memname">#define ACTLR_L1PE_Msk   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga65c3c81261a2aa26022f6bb967c4e56b">ACTLR_L1PE_Pos</a>)</td>
576 </div><div class="memdoc">
580 <a id="ga65c3c81261a2aa26022f6bb967c4e56b" name="ga65c3c81261a2aa26022f6bb967c4e56b"></a>
581 <h2 class="memtitle"><span class="permalink"><a href="#ga65c3c81261a2aa26022f6bb967c4e56b">◆ </a></span>ACTLR_L1PE_Pos</h2>
583 <div class="memitem">
584 <div class="memproto">
585 <table class="memname">
587 <td class="memname">#define ACTLR_L1PE_Pos   2U</td>
590 </div><div class="memdoc">
594 <a id="ga6aafd83ca6c02f705def8edc8c064c04" name="ga6aafd83ca6c02f705def8edc8c064c04"></a>
595 <h2 class="memtitle"><span class="permalink"><a href="#ga6aafd83ca6c02f705def8edc8c064c04">◆ </a></span>ACTLR_L1RADIS_Msk</h2>
597 <div class="memitem">
598 <div class="memproto">
599 <table class="memname">
601 <td class="memname">#define ACTLR_L1RADIS_Msk   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#gaf8b306b854ecd78110cf944d414644a1">ACTLR_L1RADIS_Pos</a>)</td>
604 </div><div class="memdoc">
608 <a id="gaf8b306b854ecd78110cf944d414644a1" name="gaf8b306b854ecd78110cf944d414644a1"></a>
609 <h2 class="memtitle"><span class="permalink"><a href="#gaf8b306b854ecd78110cf944d414644a1">◆ </a></span>ACTLR_L1RADIS_Pos</h2>
611 <div class="memitem">
612 <div class="memproto">
613 <table class="memname">
615 <td class="memname">#define ACTLR_L1RADIS_Pos   12U</td>
618 </div><div class="memdoc">
622 <a id="gad84b20f4f5d1979bb000a14a582cad12" name="gad84b20f4f5d1979bb000a14a582cad12"></a>
623 <h2 class="memtitle"><span class="permalink"><a href="#gad84b20f4f5d1979bb000a14a582cad12">◆ </a></span>ACTLR_L2RADIS_Msk</h2>
625 <div class="memitem">
626 <div class="memproto">
627 <table class="memname">
629 <td class="memname">#define ACTLR_L2RADIS_Msk   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga505f33bbe45bbcaa9fcb738cb30daf4e">ACTLR_L2RADIS_Pos</a>)</td>
632 </div><div class="memdoc">
636 <a id="ga505f33bbe45bbcaa9fcb738cb30daf4e" name="ga505f33bbe45bbcaa9fcb738cb30daf4e"></a>
637 <h2 class="memtitle"><span class="permalink"><a href="#ga505f33bbe45bbcaa9fcb738cb30daf4e">◆ </a></span>ACTLR_L2RADIS_Pos</h2>
639 <div class="memitem">
640 <div class="memproto">
641 <table class="memname">
643 <td class="memname">#define ACTLR_L2RADIS_Pos   11U</td>
646 </div><div class="memdoc">
650 <a id="gadec8e5d68791dc4749bf3f075a3559fb" name="gadec8e5d68791dc4749bf3f075a3559fb"></a>
651 <h2 class="memtitle"><span class="permalink"><a href="#gadec8e5d68791dc4749bf3f075a3559fb">◆ </a></span>ACTLR_PARITY_Msk</h2>
653 <div class="memitem">
654 <div class="memproto">
655 <table class="memname">
657 <td class="memname">#define ACTLR_PARITY_Msk   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga8300a65b41aa3f5c69c7cc713c847749">ACTLR_PARITY_Pos</a>)</td>
660 </div><div class="memdoc">
664 <a id="ga8300a65b41aa3f5c69c7cc713c847749" name="ga8300a65b41aa3f5c69c7cc713c847749"></a>
665 <h2 class="memtitle"><span class="permalink"><a href="#ga8300a65b41aa3f5c69c7cc713c847749">◆ </a></span>ACTLR_PARITY_Pos</h2>
667 <div class="memitem">
668 <div class="memproto">
669 <table class="memname">
671 <td class="memname">#define ACTLR_PARITY_Pos   9U</td>
674 </div><div class="memdoc">
678 <a id="gac6aea849e5320c0e93321d5d8b0c117c" name="gac6aea849e5320c0e93321d5d8b0c117c"></a>
679 <h2 class="memtitle"><span class="permalink"><a href="#gac6aea849e5320c0e93321d5d8b0c117c">◆ </a></span>ACTLR_RADIS_Msk</h2>
681 <div class="memitem">
682 <div class="memproto">
683 <table class="memname">
685 <td class="memname">#define ACTLR_RADIS_Msk   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#gaf7a424f7f8c4f46592ce8f47f4bced44">ACTLR_RADIS_Pos</a>)</td>
688 </div><div class="memdoc">
692 <a id="gaf7a424f7f8c4f46592ce8f47f4bced44" name="gaf7a424f7f8c4f46592ce8f47f4bced44"></a>
693 <h2 class="memtitle"><span class="permalink"><a href="#gaf7a424f7f8c4f46592ce8f47f4bced44">◆ </a></span>ACTLR_RADIS_Pos</h2>
695 <div class="memitem">
696 <div class="memproto">
697 <table class="memname">
699 <td class="memname">#define ACTLR_RADIS_Pos   12U</td>
702 </div><div class="memdoc">
706 <a id="ga8487babc3514e2bb8f3d524e5f80d95f" name="ga8487babc3514e2bb8f3d524e5f80d95f"></a>
707 <h2 class="memtitle"><span class="permalink"><a href="#ga8487babc3514e2bb8f3d524e5f80d95f">◆ </a></span>ACTLR_RSDIS_Msk</h2>
709 <div class="memitem">
710 <div class="memproto">
711 <table class="memname">
713 <td class="memname">#define ACTLR_RSDIS_Msk   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga4412a55ce52db3c5a4f035fcd0e350c6">ACTLR_RSDIS_Pos</a>)</td>
716 </div><div class="memdoc">
720 <a id="ga4412a55ce52db3c5a4f035fcd0e350c6" name="ga4412a55ce52db3c5a4f035fcd0e350c6"></a>
721 <h2 class="memtitle"><span class="permalink"><a href="#ga4412a55ce52db3c5a4f035fcd0e350c6">◆ </a></span>ACTLR_RSDIS_Pos</h2>
723 <div class="memitem">
724 <div class="memproto">
725 <table class="memname">
727 <td class="memname">#define ACTLR_RSDIS_Pos   17U</td>
730 </div><div class="memdoc">
734 <a id="gac6dcc315f6c4527434b9b0e4106771d8" name="gac6dcc315f6c4527434b9b0e4106771d8"></a>
735 <h2 class="memtitle"><span class="permalink"><a href="#gac6dcc315f6c4527434b9b0e4106771d8">◆ </a></span>ACTLR_SMP_Msk</h2>
737 <div class="memitem">
738 <div class="memproto">
739 <table class="memname">
741 <td class="memname">#define ACTLR_SMP_Msk   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga8cb19db067cca1e064189b27b1f1bcbf">ACTLR_SMP_Pos</a>)</td>
744 </div><div class="memdoc">
748 <a id="ga8cb19db067cca1e064189b27b1f1bcbf" name="ga8cb19db067cca1e064189b27b1f1bcbf"></a>
749 <h2 class="memtitle"><span class="permalink"><a href="#ga8cb19db067cca1e064189b27b1f1bcbf">◆ </a></span>ACTLR_SMP_Pos</h2>
751 <div class="memitem">
752 <div class="memproto">
753 <table class="memname">
755 <td class="memname">#define ACTLR_SMP_Pos   6U</td>
758 </div><div class="memdoc">
762 <a id="gae5a89cb553773b10e86a9c826f11179f" name="gae5a89cb553773b10e86a9c826f11179f"></a>
763 <h2 class="memtitle"><span class="permalink"><a href="#gae5a89cb553773b10e86a9c826f11179f">◆ </a></span>ACTLR_WFLZM_Msk</h2>
765 <div class="memitem">
766 <div class="memproto">
767 <table class="memname">
769 <td class="memname">#define ACTLR_WFLZM_Msk   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga104112fe1d88dde49635e9b0f9530306">ACTLR_WFLZM_Pos</a>)</td>
772 </div><div class="memdoc">
776 <a id="ga104112fe1d88dde49635e9b0f9530306" name="ga104112fe1d88dde49635e9b0f9530306"></a>
777 <h2 class="memtitle"><span class="permalink"><a href="#ga104112fe1d88dde49635e9b0f9530306">◆ </a></span>ACTLR_WFLZM_Pos</h2>
779 <div class="memitem">
780 <div class="memproto">
781 <table class="memname">
783 <td class="memname">#define ACTLR_WFLZM_Pos   3U</td>
786 </div><div class="memdoc">
790 </div><!-- contents -->
791 </div><!-- doc-content -->
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