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130 <div class="summary">
131 <a href="#define-members">Macros</a> </div>
132 <div class="headertitle"><div class="title">CPSR Bits<div class="ingroups"><a class="el" href="group__CMSIS__core__register.html">Core Register Access</a> » <a class="el" href="group__CMSIS__CPSR.html">Current Program Status Register (CPSR)</a></div></div></div>
134 <div class="contents">
136 <p>Bit position and mask macros.
137 <a href="#details">More...</a></p>
138 <table class="memberdecls">
139 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a>
140 Macros</h2></td></tr>
141 <tr class="memitem:gaaedc00ebe496885524daac4190742f84"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#gaaedc00ebe496885524daac4190742f84">CPSR_N_Pos</a>   31U</td></tr>
142 <tr class="memdesc:gaaedc00ebe496885524daac4190742f84"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: N Position. <br /></td></tr>
143 <tr class="separator:gaaedc00ebe496885524daac4190742f84"><td class="memSeparator" colspan="2"> </td></tr>
144 <tr class="memitem:ga6c4a636a3b5ec71e0f2eb021ac353544"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga6c4a636a3b5ec71e0f2eb021ac353544">CPSR_N_Msk</a>   (1UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#gaaedc00ebe496885524daac4190742f84">CPSR_N_Pos</a>)</td></tr>
145 <tr class="memdesc:ga6c4a636a3b5ec71e0f2eb021ac353544"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: N Mask. <br /></td></tr>
146 <tr class="separator:ga6c4a636a3b5ec71e0f2eb021ac353544"><td class="memSeparator" colspan="2"> </td></tr>
147 <tr class="memitem:ga18e9f21fcda9d385d23a4de0ef860cd4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga18e9f21fcda9d385d23a4de0ef860cd4">CPSR_Z_Pos</a>   30U</td></tr>
148 <tr class="memdesc:ga18e9f21fcda9d385d23a4de0ef860cd4"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: Z Position. <br /></td></tr>
149 <tr class="separator:ga18e9f21fcda9d385d23a4de0ef860cd4"><td class="memSeparator" colspan="2"> </td></tr>
150 <tr class="memitem:gab091112988009fb8360b01c79d993f67"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#gab091112988009fb8360b01c79d993f67">CPSR_Z_Msk</a>   (1UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#ga18e9f21fcda9d385d23a4de0ef860cd4">CPSR_Z_Pos</a>)</td></tr>
151 <tr class="memdesc:gab091112988009fb8360b01c79d993f67"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: Z Mask. <br /></td></tr>
152 <tr class="separator:gab091112988009fb8360b01c79d993f67"><td class="memSeparator" colspan="2"> </td></tr>
153 <tr class="memitem:ga8565df3cf054dc09506e1c0ea4790131"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga8565df3cf054dc09506e1c0ea4790131">CPSR_C_Pos</a>   29U</td></tr>
154 <tr class="memdesc:ga8565df3cf054dc09506e1c0ea4790131"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: C Position. <br /></td></tr>
155 <tr class="separator:ga8565df3cf054dc09506e1c0ea4790131"><td class="memSeparator" colspan="2"> </td></tr>
156 <tr class="memitem:ga3bc30b14b9b0bf113600eb882304244c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga3bc30b14b9b0bf113600eb882304244c">CPSR_C_Msk</a>   (1UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#ga8565df3cf054dc09506e1c0ea4790131">CPSR_C_Pos</a>)</td></tr>
157 <tr class="memdesc:ga3bc30b14b9b0bf113600eb882304244c"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: C Mask. <br /></td></tr>
158 <tr class="separator:ga3bc30b14b9b0bf113600eb882304244c"><td class="memSeparator" colspan="2"> </td></tr>
159 <tr class="memitem:ga5685fa5745113b4ff61181ee439bc2a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga5685fa5745113b4ff61181ee439bc2a5">CPSR_V_Pos</a>   28U</td></tr>
160 <tr class="memdesc:ga5685fa5745113b4ff61181ee439bc2a5"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: V Position. <br /></td></tr>
161 <tr class="separator:ga5685fa5745113b4ff61181ee439bc2a5"><td class="memSeparator" colspan="2"> </td></tr>
162 <tr class="memitem:ga9b9fe5c1da5e922cbff18215b70b4252"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga9b9fe5c1da5e922cbff18215b70b4252">CPSR_V_Msk</a>   (1UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#ga5685fa5745113b4ff61181ee439bc2a5">CPSR_V_Pos</a>)</td></tr>
163 <tr class="memdesc:ga9b9fe5c1da5e922cbff18215b70b4252"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: V Mask. <br /></td></tr>
164 <tr class="separator:ga9b9fe5c1da5e922cbff18215b70b4252"><td class="memSeparator" colspan="2"> </td></tr>
165 <tr class="memitem:ga84c8427c30fdce15f7191bd4f93d7ab7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga84c8427c30fdce15f7191bd4f93d7ab7">CPSR_Q_Pos</a>   27U</td></tr>
166 <tr class="memdesc:ga84c8427c30fdce15f7191bd4f93d7ab7"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: Q Position. <br /></td></tr>
167 <tr class="separator:ga84c8427c30fdce15f7191bd4f93d7ab7"><td class="memSeparator" colspan="2"> </td></tr>
168 <tr class="memitem:gaba36b1ac0438594afdc6eef220d2e146"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#gaba36b1ac0438594afdc6eef220d2e146">CPSR_Q_Msk</a>   (1UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#ga84c8427c30fdce15f7191bd4f93d7ab7">CPSR_Q_Pos</a>)</td></tr>
169 <tr class="memdesc:gaba36b1ac0438594afdc6eef220d2e146"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: Q Mask. <br /></td></tr>
170 <tr class="separator:gaba36b1ac0438594afdc6eef220d2e146"><td class="memSeparator" colspan="2"> </td></tr>
171 <tr class="memitem:ga450f3fff0642431fd3478a04b70c3d87"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga450f3fff0642431fd3478a04b70c3d87">CPSR_IT0_Pos</a>   25U</td></tr>
172 <tr class="memdesc:ga450f3fff0642431fd3478a04b70c3d87"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: IT0 Position. <br /></td></tr>
173 <tr class="separator:ga450f3fff0642431fd3478a04b70c3d87"><td class="memSeparator" colspan="2"> </td></tr>
174 <tr class="memitem:ga128366788d0f94d52fbe4610162c97e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga128366788d0f94d52fbe4610162c97e5">CPSR_IT0_Msk</a>   (3UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#ga450f3fff0642431fd3478a04b70c3d87">CPSR_IT0_Pos</a>)</td></tr>
175 <tr class="memdesc:ga128366788d0f94d52fbe4610162c97e5"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: IT0 Mask. <br /></td></tr>
176 <tr class="separator:ga128366788d0f94d52fbe4610162c97e5"><td class="memSeparator" colspan="2"> </td></tr>
177 <tr class="memitem:ga6b49ddfb770143a51aa682b56be2e990"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga6b49ddfb770143a51aa682b56be2e990">CPSR_J_Pos</a>   24U</td></tr>
178 <tr class="memdesc:ga6b49ddfb770143a51aa682b56be2e990"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: J Position. <br /></td></tr>
179 <tr class="separator:ga6b49ddfb770143a51aa682b56be2e990"><td class="memSeparator" colspan="2"> </td></tr>
180 <tr class="memitem:ga6b52a05ec2e95ade71b65090f19285c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga6b52a05ec2e95ade71b65090f19285c2">CPSR_J_Msk</a>   (1UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#ga6b49ddfb770143a51aa682b56be2e990">CPSR_J_Pos</a>)</td></tr>
181 <tr class="memdesc:ga6b52a05ec2e95ade71b65090f19285c2"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: J Mask. <br /></td></tr>
182 <tr class="separator:ga6b52a05ec2e95ade71b65090f19285c2"><td class="memSeparator" colspan="2"> </td></tr>
183 <tr class="memitem:ga37aa76465f6c6055395790e74169d760"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga37aa76465f6c6055395790e74169d760">CPSR_GE_Pos</a>   16U</td></tr>
184 <tr class="memdesc:ga37aa76465f6c6055395790e74169d760"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: GE Position. <br /></td></tr>
185 <tr class="separator:ga37aa76465f6c6055395790e74169d760"><td class="memSeparator" colspan="2"> </td></tr>
186 <tr class="memitem:ga9a3a6a87437892954cb37662ff27521a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga9a3a6a87437892954cb37662ff27521a">CPSR_GE_Msk</a>   (0xFUL << <a class="el" href="group__CMSIS__CPSR__BITS.html#ga37aa76465f6c6055395790e74169d760">CPSR_GE_Pos</a>)</td></tr>
187 <tr class="memdesc:ga9a3a6a87437892954cb37662ff27521a"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: GE Mask. <br /></td></tr>
188 <tr class="separator:ga9a3a6a87437892954cb37662ff27521a"><td class="memSeparator" colspan="2"> </td></tr>
189 <tr class="memitem:gaa2ab21d87052b439c06f058fb65036a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#gaa2ab21d87052b439c06f058fb65036a5">CPSR_IT1_Pos</a>   10U</td></tr>
190 <tr class="memdesc:gaa2ab21d87052b439c06f058fb65036a5"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: IT1 Position. <br /></td></tr>
191 <tr class="separator:gaa2ab21d87052b439c06f058fb65036a5"><td class="memSeparator" colspan="2"> </td></tr>
192 <tr class="memitem:ga791263c8a9707795b5824dae5485cd39"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga791263c8a9707795b5824dae5485cd39">CPSR_IT1_Msk</a>   (0x3FUL << <a class="el" href="group__CMSIS__CPSR__BITS.html#gaa2ab21d87052b439c06f058fb65036a5">CPSR_IT1_Pos</a>)</td></tr>
193 <tr class="memdesc:ga791263c8a9707795b5824dae5485cd39"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: IT1 Mask. <br /></td></tr>
194 <tr class="separator:ga791263c8a9707795b5824dae5485cd39"><td class="memSeparator" colspan="2"> </td></tr>
195 <tr class="memitem:ga6a5e065d9ea93489105c3d62c1d3c08f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga6a5e065d9ea93489105c3d62c1d3c08f">CPSR_E_Pos</a>   9U</td></tr>
196 <tr class="memdesc:ga6a5e065d9ea93489105c3d62c1d3c08f"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: E Position. <br /></td></tr>
197 <tr class="separator:ga6a5e065d9ea93489105c3d62c1d3c08f"><td class="memSeparator" colspan="2"> </td></tr>
198 <tr class="memitem:ga6661712dd33a50ce4a42e13bf72aa35b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga6661712dd33a50ce4a42e13bf72aa35b">CPSR_E_Msk</a>   (1UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#ga6a5e065d9ea93489105c3d62c1d3c08f">CPSR_E_Pos</a>)</td></tr>
199 <tr class="memdesc:ga6661712dd33a50ce4a42e13bf72aa35b"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: E Mask. <br /></td></tr>
200 <tr class="separator:ga6661712dd33a50ce4a42e13bf72aa35b"><td class="memSeparator" colspan="2"> </td></tr>
201 <tr class="memitem:ga6f8aa35ca07825d6b4498ae6e2ab616b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga6f8aa35ca07825d6b4498ae6e2ab616b">CPSR_A_Pos</a>   8U</td></tr>
202 <tr class="memdesc:ga6f8aa35ca07825d6b4498ae6e2ab616b"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: A Position. <br /></td></tr>
203 <tr class="separator:ga6f8aa35ca07825d6b4498ae6e2ab616b"><td class="memSeparator" colspan="2"> </td></tr>
204 <tr class="memitem:ga002803fa282333e0ead5c9b4cf748cb1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga002803fa282333e0ead5c9b4cf748cb1">CPSR_A_Msk</a>   (1UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#ga6f8aa35ca07825d6b4498ae6e2ab616b">CPSR_A_Pos</a>)</td></tr>
205 <tr class="memdesc:ga002803fa282333e0ead5c9b4cf748cb1"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: A Mask. <br /></td></tr>
206 <tr class="separator:ga002803fa282333e0ead5c9b4cf748cb1"><td class="memSeparator" colspan="2"> </td></tr>
207 <tr class="memitem:gad1d9be2f731f5400fc87076ce3495e59"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#gad1d9be2f731f5400fc87076ce3495e59">CPSR_I_Pos</a>   7U</td></tr>
208 <tr class="memdesc:gad1d9be2f731f5400fc87076ce3495e59"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: I Position. <br /></td></tr>
209 <tr class="separator:gad1d9be2f731f5400fc87076ce3495e59"><td class="memSeparator" colspan="2"> </td></tr>
210 <tr class="memitem:gad9abe93ba1179e254a70e325cb1a5834"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#gad9abe93ba1179e254a70e325cb1a5834">CPSR_I_Msk</a>   (1UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#gad1d9be2f731f5400fc87076ce3495e59">CPSR_I_Pos</a>)</td></tr>
211 <tr class="memdesc:gad9abe93ba1179e254a70e325cb1a5834"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: I Mask. <br /></td></tr>
212 <tr class="separator:gad9abe93ba1179e254a70e325cb1a5834"><td class="memSeparator" colspan="2"> </td></tr>
213 <tr class="memitem:ga5e9868fdea8e65374b25ddd2fde1bf62"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga5e9868fdea8e65374b25ddd2fde1bf62">CPSR_F_Pos</a>   6U</td></tr>
214 <tr class="memdesc:ga5e9868fdea8e65374b25ddd2fde1bf62"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: F Position. <br /></td></tr>
215 <tr class="separator:ga5e9868fdea8e65374b25ddd2fde1bf62"><td class="memSeparator" colspan="2"> </td></tr>
216 <tr class="memitem:ga4df09481ffd9dfb17823a8e9895b1566"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga4df09481ffd9dfb17823a8e9895b1566">CPSR_F_Msk</a>   (1UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#ga5e9868fdea8e65374b25ddd2fde1bf62">CPSR_F_Pos</a>)</td></tr>
217 <tr class="memdesc:ga4df09481ffd9dfb17823a8e9895b1566"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: F Mask. <br /></td></tr>
218 <tr class="separator:ga4df09481ffd9dfb17823a8e9895b1566"><td class="memSeparator" colspan="2"> </td></tr>
219 <tr class="memitem:gaa1134ff3e774b1354a43227b798a707c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#gaa1134ff3e774b1354a43227b798a707c">CPSR_T_Pos</a>   5U</td></tr>
220 <tr class="memdesc:gaa1134ff3e774b1354a43227b798a707c"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: T Position. <br /></td></tr>
221 <tr class="separator:gaa1134ff3e774b1354a43227b798a707c"><td class="memSeparator" colspan="2"> </td></tr>
222 <tr class="memitem:ga23ed422711cbd2f9a5dcbe6c05b2a720"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga23ed422711cbd2f9a5dcbe6c05b2a720">CPSR_T_Msk</a>   (1UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#gaa1134ff3e774b1354a43227b798a707c">CPSR_T_Pos</a>)</td></tr>
223 <tr class="memdesc:ga23ed422711cbd2f9a5dcbe6c05b2a720"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: T Mask. <br /></td></tr>
224 <tr class="separator:ga23ed422711cbd2f9a5dcbe6c05b2a720"><td class="memSeparator" colspan="2"> </td></tr>
225 <tr class="memitem:ga4e9e49c9a75cf3e7d696fc77de7d44d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga4e9e49c9a75cf3e7d696fc77de7d44d1">CPSR_M_Pos</a>   0U</td></tr>
226 <tr class="memdesc:ga4e9e49c9a75cf3e7d696fc77de7d44d1"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: M Position. <br /></td></tr>
227 <tr class="separator:ga4e9e49c9a75cf3e7d696fc77de7d44d1"><td class="memSeparator" colspan="2"> </td></tr>
228 <tr class="memitem:gadce47959b814f70f802a139250daa04c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#gadce47959b814f70f802a139250daa04c">CPSR_M_Msk</a>   (0x1FUL << <a class="el" href="group__CMSIS__CPSR__BITS.html#ga4e9e49c9a75cf3e7d696fc77de7d44d1">CPSR_M_Pos</a>)</td></tr>
229 <tr class="memdesc:gadce47959b814f70f802a139250daa04c"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: M Mask. <br /></td></tr>
230 <tr class="separator:gadce47959b814f70f802a139250daa04c"><td class="memSeparator" colspan="2"> </td></tr>
232 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
233 <h2 class="groupheader">Macro Definition Documentation</h2>
234 <a id="ga002803fa282333e0ead5c9b4cf748cb1" name="ga002803fa282333e0ead5c9b4cf748cb1"></a>
235 <h2 class="memtitle"><span class="permalink"><a href="#ga002803fa282333e0ead5c9b4cf748cb1">◆ </a></span>CPSR_A_Msk</h2>
237 <div class="memitem">
238 <div class="memproto">
239 <table class="memname">
241 <td class="memname">#define CPSR_A_Msk   (1UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#ga6f8aa35ca07825d6b4498ae6e2ab616b">CPSR_A_Pos</a>)</td>
244 </div><div class="memdoc">
248 <a id="ga6f8aa35ca07825d6b4498ae6e2ab616b" name="ga6f8aa35ca07825d6b4498ae6e2ab616b"></a>
249 <h2 class="memtitle"><span class="permalink"><a href="#ga6f8aa35ca07825d6b4498ae6e2ab616b">◆ </a></span>CPSR_A_Pos</h2>
251 <div class="memitem">
252 <div class="memproto">
253 <table class="memname">
255 <td class="memname">#define CPSR_A_Pos   8U</td>
258 </div><div class="memdoc">
262 <a id="ga3bc30b14b9b0bf113600eb882304244c" name="ga3bc30b14b9b0bf113600eb882304244c"></a>
263 <h2 class="memtitle"><span class="permalink"><a href="#ga3bc30b14b9b0bf113600eb882304244c">◆ </a></span>CPSR_C_Msk</h2>
265 <div class="memitem">
266 <div class="memproto">
267 <table class="memname">
269 <td class="memname">#define CPSR_C_Msk   (1UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#ga8565df3cf054dc09506e1c0ea4790131">CPSR_C_Pos</a>)</td>
272 </div><div class="memdoc">
276 <a id="ga8565df3cf054dc09506e1c0ea4790131" name="ga8565df3cf054dc09506e1c0ea4790131"></a>
277 <h2 class="memtitle"><span class="permalink"><a href="#ga8565df3cf054dc09506e1c0ea4790131">◆ </a></span>CPSR_C_Pos</h2>
279 <div class="memitem">
280 <div class="memproto">
281 <table class="memname">
283 <td class="memname">#define CPSR_C_Pos   29U</td>
286 </div><div class="memdoc">
290 <a id="ga6661712dd33a50ce4a42e13bf72aa35b" name="ga6661712dd33a50ce4a42e13bf72aa35b"></a>
291 <h2 class="memtitle"><span class="permalink"><a href="#ga6661712dd33a50ce4a42e13bf72aa35b">◆ </a></span>CPSR_E_Msk</h2>
293 <div class="memitem">
294 <div class="memproto">
295 <table class="memname">
297 <td class="memname">#define CPSR_E_Msk   (1UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#ga6a5e065d9ea93489105c3d62c1d3c08f">CPSR_E_Pos</a>)</td>
300 </div><div class="memdoc">
304 <a id="ga6a5e065d9ea93489105c3d62c1d3c08f" name="ga6a5e065d9ea93489105c3d62c1d3c08f"></a>
305 <h2 class="memtitle"><span class="permalink"><a href="#ga6a5e065d9ea93489105c3d62c1d3c08f">◆ </a></span>CPSR_E_Pos</h2>
307 <div class="memitem">
308 <div class="memproto">
309 <table class="memname">
311 <td class="memname">#define CPSR_E_Pos   9U</td>
314 </div><div class="memdoc">
318 <a id="ga4df09481ffd9dfb17823a8e9895b1566" name="ga4df09481ffd9dfb17823a8e9895b1566"></a>
319 <h2 class="memtitle"><span class="permalink"><a href="#ga4df09481ffd9dfb17823a8e9895b1566">◆ </a></span>CPSR_F_Msk</h2>
321 <div class="memitem">
322 <div class="memproto">
323 <table class="memname">
325 <td class="memname">#define CPSR_F_Msk   (1UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#ga5e9868fdea8e65374b25ddd2fde1bf62">CPSR_F_Pos</a>)</td>
328 </div><div class="memdoc">
332 <a id="ga5e9868fdea8e65374b25ddd2fde1bf62" name="ga5e9868fdea8e65374b25ddd2fde1bf62"></a>
333 <h2 class="memtitle"><span class="permalink"><a href="#ga5e9868fdea8e65374b25ddd2fde1bf62">◆ </a></span>CPSR_F_Pos</h2>
335 <div class="memitem">
336 <div class="memproto">
337 <table class="memname">
339 <td class="memname">#define CPSR_F_Pos   6U</td>
342 </div><div class="memdoc">
346 <a id="ga9a3a6a87437892954cb37662ff27521a" name="ga9a3a6a87437892954cb37662ff27521a"></a>
347 <h2 class="memtitle"><span class="permalink"><a href="#ga9a3a6a87437892954cb37662ff27521a">◆ </a></span>CPSR_GE_Msk</h2>
349 <div class="memitem">
350 <div class="memproto">
351 <table class="memname">
353 <td class="memname">#define CPSR_GE_Msk   (0xFUL << <a class="el" href="group__CMSIS__CPSR__BITS.html#ga37aa76465f6c6055395790e74169d760">CPSR_GE_Pos</a>)</td>
356 </div><div class="memdoc">
360 <a id="ga37aa76465f6c6055395790e74169d760" name="ga37aa76465f6c6055395790e74169d760"></a>
361 <h2 class="memtitle"><span class="permalink"><a href="#ga37aa76465f6c6055395790e74169d760">◆ </a></span>CPSR_GE_Pos</h2>
363 <div class="memitem">
364 <div class="memproto">
365 <table class="memname">
367 <td class="memname">#define CPSR_GE_Pos   16U</td>
370 </div><div class="memdoc">
374 <a id="gad9abe93ba1179e254a70e325cb1a5834" name="gad9abe93ba1179e254a70e325cb1a5834"></a>
375 <h2 class="memtitle"><span class="permalink"><a href="#gad9abe93ba1179e254a70e325cb1a5834">◆ </a></span>CPSR_I_Msk</h2>
377 <div class="memitem">
378 <div class="memproto">
379 <table class="memname">
381 <td class="memname">#define CPSR_I_Msk   (1UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#gad1d9be2f731f5400fc87076ce3495e59">CPSR_I_Pos</a>)</td>
384 </div><div class="memdoc">
388 <a id="gad1d9be2f731f5400fc87076ce3495e59" name="gad1d9be2f731f5400fc87076ce3495e59"></a>
389 <h2 class="memtitle"><span class="permalink"><a href="#gad1d9be2f731f5400fc87076ce3495e59">◆ </a></span>CPSR_I_Pos</h2>
391 <div class="memitem">
392 <div class="memproto">
393 <table class="memname">
395 <td class="memname">#define CPSR_I_Pos   7U</td>
398 </div><div class="memdoc">
402 <a id="ga128366788d0f94d52fbe4610162c97e5" name="ga128366788d0f94d52fbe4610162c97e5"></a>
403 <h2 class="memtitle"><span class="permalink"><a href="#ga128366788d0f94d52fbe4610162c97e5">◆ </a></span>CPSR_IT0_Msk</h2>
405 <div class="memitem">
406 <div class="memproto">
407 <table class="memname">
409 <td class="memname">#define CPSR_IT0_Msk   (3UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#ga450f3fff0642431fd3478a04b70c3d87">CPSR_IT0_Pos</a>)</td>
412 </div><div class="memdoc">
416 <a id="ga450f3fff0642431fd3478a04b70c3d87" name="ga450f3fff0642431fd3478a04b70c3d87"></a>
417 <h2 class="memtitle"><span class="permalink"><a href="#ga450f3fff0642431fd3478a04b70c3d87">◆ </a></span>CPSR_IT0_Pos</h2>
419 <div class="memitem">
420 <div class="memproto">
421 <table class="memname">
423 <td class="memname">#define CPSR_IT0_Pos   25U</td>
426 </div><div class="memdoc">
430 <a id="ga791263c8a9707795b5824dae5485cd39" name="ga791263c8a9707795b5824dae5485cd39"></a>
431 <h2 class="memtitle"><span class="permalink"><a href="#ga791263c8a9707795b5824dae5485cd39">◆ </a></span>CPSR_IT1_Msk</h2>
433 <div class="memitem">
434 <div class="memproto">
435 <table class="memname">
437 <td class="memname">#define CPSR_IT1_Msk   (0x3FUL << <a class="el" href="group__CMSIS__CPSR__BITS.html#gaa2ab21d87052b439c06f058fb65036a5">CPSR_IT1_Pos</a>)</td>
440 </div><div class="memdoc">
444 <a id="gaa2ab21d87052b439c06f058fb65036a5" name="gaa2ab21d87052b439c06f058fb65036a5"></a>
445 <h2 class="memtitle"><span class="permalink"><a href="#gaa2ab21d87052b439c06f058fb65036a5">◆ </a></span>CPSR_IT1_Pos</h2>
447 <div class="memitem">
448 <div class="memproto">
449 <table class="memname">
451 <td class="memname">#define CPSR_IT1_Pos   10U</td>
454 </div><div class="memdoc">
458 <a id="ga6b52a05ec2e95ade71b65090f19285c2" name="ga6b52a05ec2e95ade71b65090f19285c2"></a>
459 <h2 class="memtitle"><span class="permalink"><a href="#ga6b52a05ec2e95ade71b65090f19285c2">◆ </a></span>CPSR_J_Msk</h2>
461 <div class="memitem">
462 <div class="memproto">
463 <table class="memname">
465 <td class="memname">#define CPSR_J_Msk   (1UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#ga6b49ddfb770143a51aa682b56be2e990">CPSR_J_Pos</a>)</td>
468 </div><div class="memdoc">
472 <a id="ga6b49ddfb770143a51aa682b56be2e990" name="ga6b49ddfb770143a51aa682b56be2e990"></a>
473 <h2 class="memtitle"><span class="permalink"><a href="#ga6b49ddfb770143a51aa682b56be2e990">◆ </a></span>CPSR_J_Pos</h2>
475 <div class="memitem">
476 <div class="memproto">
477 <table class="memname">
479 <td class="memname">#define CPSR_J_Pos   24U</td>
482 </div><div class="memdoc">
486 <a id="gadce47959b814f70f802a139250daa04c" name="gadce47959b814f70f802a139250daa04c"></a>
487 <h2 class="memtitle"><span class="permalink"><a href="#gadce47959b814f70f802a139250daa04c">◆ </a></span>CPSR_M_Msk</h2>
489 <div class="memitem">
490 <div class="memproto">
491 <table class="memname">
493 <td class="memname">#define CPSR_M_Msk   (0x1FUL << <a class="el" href="group__CMSIS__CPSR__BITS.html#ga4e9e49c9a75cf3e7d696fc77de7d44d1">CPSR_M_Pos</a>)</td>
496 </div><div class="memdoc">
500 <a id="ga4e9e49c9a75cf3e7d696fc77de7d44d1" name="ga4e9e49c9a75cf3e7d696fc77de7d44d1"></a>
501 <h2 class="memtitle"><span class="permalink"><a href="#ga4e9e49c9a75cf3e7d696fc77de7d44d1">◆ </a></span>CPSR_M_Pos</h2>
503 <div class="memitem">
504 <div class="memproto">
505 <table class="memname">
507 <td class="memname">#define CPSR_M_Pos   0U</td>
510 </div><div class="memdoc">
514 <a id="ga6c4a636a3b5ec71e0f2eb021ac353544" name="ga6c4a636a3b5ec71e0f2eb021ac353544"></a>
515 <h2 class="memtitle"><span class="permalink"><a href="#ga6c4a636a3b5ec71e0f2eb021ac353544">◆ </a></span>CPSR_N_Msk</h2>
517 <div class="memitem">
518 <div class="memproto">
519 <table class="memname">
521 <td class="memname">#define CPSR_N_Msk   (1UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#gaaedc00ebe496885524daac4190742f84">CPSR_N_Pos</a>)</td>
524 </div><div class="memdoc">
528 <a id="gaaedc00ebe496885524daac4190742f84" name="gaaedc00ebe496885524daac4190742f84"></a>
529 <h2 class="memtitle"><span class="permalink"><a href="#gaaedc00ebe496885524daac4190742f84">◆ </a></span>CPSR_N_Pos</h2>
531 <div class="memitem">
532 <div class="memproto">
533 <table class="memname">
535 <td class="memname">#define CPSR_N_Pos   31U</td>
538 </div><div class="memdoc">
542 <a id="gaba36b1ac0438594afdc6eef220d2e146" name="gaba36b1ac0438594afdc6eef220d2e146"></a>
543 <h2 class="memtitle"><span class="permalink"><a href="#gaba36b1ac0438594afdc6eef220d2e146">◆ </a></span>CPSR_Q_Msk</h2>
545 <div class="memitem">
546 <div class="memproto">
547 <table class="memname">
549 <td class="memname">#define CPSR_Q_Msk   (1UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#ga84c8427c30fdce15f7191bd4f93d7ab7">CPSR_Q_Pos</a>)</td>
552 </div><div class="memdoc">
556 <a id="ga84c8427c30fdce15f7191bd4f93d7ab7" name="ga84c8427c30fdce15f7191bd4f93d7ab7"></a>
557 <h2 class="memtitle"><span class="permalink"><a href="#ga84c8427c30fdce15f7191bd4f93d7ab7">◆ </a></span>CPSR_Q_Pos</h2>
559 <div class="memitem">
560 <div class="memproto">
561 <table class="memname">
563 <td class="memname">#define CPSR_Q_Pos   27U</td>
566 </div><div class="memdoc">
570 <a id="ga23ed422711cbd2f9a5dcbe6c05b2a720" name="ga23ed422711cbd2f9a5dcbe6c05b2a720"></a>
571 <h2 class="memtitle"><span class="permalink"><a href="#ga23ed422711cbd2f9a5dcbe6c05b2a720">◆ </a></span>CPSR_T_Msk</h2>
573 <div class="memitem">
574 <div class="memproto">
575 <table class="memname">
577 <td class="memname">#define CPSR_T_Msk   (1UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#gaa1134ff3e774b1354a43227b798a707c">CPSR_T_Pos</a>)</td>
580 </div><div class="memdoc">
584 <a id="gaa1134ff3e774b1354a43227b798a707c" name="gaa1134ff3e774b1354a43227b798a707c"></a>
585 <h2 class="memtitle"><span class="permalink"><a href="#gaa1134ff3e774b1354a43227b798a707c">◆ </a></span>CPSR_T_Pos</h2>
587 <div class="memitem">
588 <div class="memproto">
589 <table class="memname">
591 <td class="memname">#define CPSR_T_Pos   5U</td>
594 </div><div class="memdoc">
598 <a id="ga9b9fe5c1da5e922cbff18215b70b4252" name="ga9b9fe5c1da5e922cbff18215b70b4252"></a>
599 <h2 class="memtitle"><span class="permalink"><a href="#ga9b9fe5c1da5e922cbff18215b70b4252">◆ </a></span>CPSR_V_Msk</h2>
601 <div class="memitem">
602 <div class="memproto">
603 <table class="memname">
605 <td class="memname">#define CPSR_V_Msk   (1UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#ga5685fa5745113b4ff61181ee439bc2a5">CPSR_V_Pos</a>)</td>
608 </div><div class="memdoc">
612 <a id="ga5685fa5745113b4ff61181ee439bc2a5" name="ga5685fa5745113b4ff61181ee439bc2a5"></a>
613 <h2 class="memtitle"><span class="permalink"><a href="#ga5685fa5745113b4ff61181ee439bc2a5">◆ </a></span>CPSR_V_Pos</h2>
615 <div class="memitem">
616 <div class="memproto">
617 <table class="memname">
619 <td class="memname">#define CPSR_V_Pos   28U</td>
622 </div><div class="memdoc">
626 <a id="gab091112988009fb8360b01c79d993f67" name="gab091112988009fb8360b01c79d993f67"></a>
627 <h2 class="memtitle"><span class="permalink"><a href="#gab091112988009fb8360b01c79d993f67">◆ </a></span>CPSR_Z_Msk</h2>
629 <div class="memitem">
630 <div class="memproto">
631 <table class="memname">
633 <td class="memname">#define CPSR_Z_Msk   (1UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#ga18e9f21fcda9d385d23a4de0ef860cd4">CPSR_Z_Pos</a>)</td>
636 </div><div class="memdoc">
640 <a id="ga18e9f21fcda9d385d23a4de0ef860cd4" name="ga18e9f21fcda9d385d23a4de0ef860cd4"></a>
641 <h2 class="memtitle"><span class="permalink"><a href="#ga18e9f21fcda9d385d23a4de0ef860cd4">◆ </a></span>CPSR_Z_Pos</h2>
643 <div class="memitem">
644 <div class="memproto">
645 <table class="memname">
647 <td class="memname">#define CPSR_Z_Pos   30U</td>
650 </div><div class="memdoc">
654 </div><!-- contents -->
655 </div><!-- doc-content -->
656 <!-- start footer part -->
657 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
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