1 /**************************************************************************************************/
2 /** \defgroup Core_Register_gr Core Register Access
3 \brief Functions to access the Cortex-M core registers.
5 The following functions provide access to Cortex-M core registers.
11 /**************************************************************************************************/
12 /** \brief Read the CONTROL register
14 The function reads the CONTROL register value using the instruction \b MRS.
16 The CONTROL register controls the stack used and the privilege level for software execution
17 when the processor is in thread mode and, if implemented, indicates whether the FPU state is
18 active. This register uses the following bits:
20 - \b CONTROL[2] [only Cortex-M4 and Cortex-M7]
25 - =0 In handler mode - MSP is selected. No alternate stack possible for handler mode.
26 - =0 In thread mode - Default stack pointer MSP is used.
27 - =1 In thread mode - Alternate stack pointer PSP is used.
29 - \b CONTROL[0] [not Cortex-M0]
30 - =0 In thread mode and privileged state.
31 - =1 In thread mode and user state.
33 \returns CONTROL register value
36 - The processor can be in user state or privileged state when running in thread mode.
37 - Exception handlers always run in privileged state.
38 - On reset, the processor is in thread mode with privileged access rights.
41 - \ref __set_CONTROL; CONTROL_Type
44 uint32_t __get_CONTROL(void);
47 /**************************************************************************************************/
48 /** \brief Set the CONTROL Register
50 The function sets the CONTROL register value using the instruction \b MSR.
52 The CONTROL register controls the stack used and the privilege level for software execution
53 when the processor is in thread mode and, if implemented, indicates whether the FPU state is
54 active. This register uses the following bits:
56 - \b CONTROL[2] [only Cortex-M4 and Cortex-M7]
61 - Writeable only when the processor is in thread mode and privileged state (CONTROL[0]=0).
62 - =0 In handler mode - MSP is selected. No alternate stack pointer possible for handler mode.
63 - =0 In thread mode - Default stack pointer MSP is used.
64 - =1 In thread mode - Alternate stack pointer PSP is used.
66 - \b CONTROL[0] [not writeable for Cortex-M0]
67 - Writeable only when the processor is in privileged state.
68 - Can be used to switch the processor to user state (thread mode).
69 - Once in user state, trigger an interrupt and change the state to privileged in the
70 exception handler (the only way).
71 - =0 In thread mode and privileged state.
72 - =1 In thread mode and user state.
75 \param [in] control CONTROL register value to set
78 - The processor can be in user state or privileged state when running in thread mode.
79 - Exception handlers always run in privileged state.
80 - On reset, the processor is in thread mode with privileged access rights.
83 - \ref __get_CONTROL; __set_PSP; __set_MSP; CONTROL_Type
86 void __set_CONTROL(uint32_t control);
89 /**************************************************************************************************/
90 /** \brief Read the IPSR register
92 The function reads the Interrupt Program Status Register (IPSR) using the instruction \b MRS.
94 The ISPR contains the exception type number of the current Interrupt Service Routine (ISR).
95 Each exception has an assocciated unique IRQn number. The following bits are used:
97 - \b ISR_NUMBER (IPSR[8:0])
107 - =12 Reserved for Debug
115 \returns ISPR register value
118 - This register is read-only.
121 - \ref __get_xPSR; IPSR_Type
125 uint32_t __get_IPSR(void);
128 /**************************************************************************************************/
129 /** \brief Read the APSR register
131 The function reads the Application Program Status Register (APSR) using the instruction \b MRS.
133 The APSR contains the current state of the condition flags from instructions executed previously.
134 The APSR is essential for controlling conditional branches. The following flags are used:
136 - \b N (APSR[31]) (Negative flag)
137 - =1 The instruction result has a negative value (when interpreted as signed integer).
138 - =0 The instruction result has a positive value or equal zero.
140 - \b Z (APSR[30]) (Zero flag)
141 - =1 The instruction result is zero. Or, after a compare instruction, when the two values
144 - \b C (APSR[29]) (Carry or borrow flag)
145 - =1 For unsigned additions, if an unsigned overflow occurred.
146 - =<i>inverse of borrow output status</i> For unsigned subtract operations.
148 - \b V (APSR[28]) (Overflow flag)
149 - =1 A signed overflow occurred (for signed additions or subtractions).
151 - \b Q (APSR[27]) (DSP overflow or saturation flag) [not Cortex-M0]
152 - This flag is a \em sticky flag. Saturating and certain mutliplying instructions can set the
153 flag, but cannot clear it.
154 - =1 When saturation or an overflow occurred.
156 - \b GE (APSR[19:16]) (Greater than or Equal flags) [not Cortex-M0]
157 - Can be set by the parallel add and subtract instructions.
158 - Are used by the <kbd>SEL</kbd> instruction to perform byte-based selection from two registers.
161 \returns APSR register value
164 - Some instructions update all flags; some instructions update a subset of the flags.
165 - If a flag is not updated, the original value is preserved.
166 - Conditional instructions that are not executed have no effect on the flags.
167 - The CMSIS does not provide a function to update this register.
170 - \ref __get_xPSR; APSR_Type
174 uint32_t __get_APSR(void);
177 /**************************************************************************************************/
178 /** \brief Read the xPSR register
180 The function reads the combined Program Status Register (xPSR) using the instruction \b MRS.
182 xPSR provides information about program execution and the APSR flags. It consists of the
184 \li Application Program Status Register (APSR)
185 \li Interrupt Program Status Register (IPSR)
186 \li Execution Program Status Register (EPSR)
188 In addition to the flags described in \ref __get_APSR and \ref __get_IPSR, the register provides
190 - \b IT (xPSR[26:25]) (If-Then condition instruction)
191 - Contains up to four instructions following an IT instruction.
192 - Each instruction in the block is conditional.
193 - The conditions for the instructions are either all the same, or some can be the inverse
196 - \b T (xPSR[24]) (Thumb bit)
197 - =1 Indicates that that the processor is in Thumb state.
198 - =0 Attempting to execute instructions when the T bit is 0 results in a fault or lockup.
199 - The conditions for the instructions are either all the same, or some can be the inverse
202 \returns xPSR register value
205 - The CMSIS does not provide functions that access EPSR.
208 - \ref __get_APSR; __get_IPSR; xPSR_Type
212 uint32_t __get_xPSR(void);
215 /**************************************************************************************************/
216 /** \brief Read the PSP register
218 The function reads the Program Status Pointer (PSP) value using the instruction \b MRS.
220 Physically two different stack pointers (SP) exist:
221 - The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when
222 running exception handlers (handler mode).
223 - The Process Stack Pointer (PSP), which can be used only in thread mode.
225 Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:
226 - =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded
227 from the first 32-bit word of the vector table from the program memory.
228 - =1 PSP is the current stack pointer. The initial value is undefined.
230 \returns PSP register value
233 - Only one of the two SPs is visible at a time.
234 - For many applications, the system can completely rely on the MSP.
235 - The PSP is normally used in designs with an OS where the stack memory for OS Kernel must
236 be separated from the application code.
239 - \ref __set_PSP; __get_MSP; __get_CONTROL
244 uint32_t __get_PSP(void);
247 /**************************************************************************************************/
248 /** \brief Set the PSP register
250 The function sets the Program Status Pointer (PSP) value using the instruction \b MSR.
252 Physically two different stack pointers (SP) exist:
253 - The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when
254 running exception handlers (handler mode).
255 - The Process Stack Pointer (PSP), which can be used only in thread mode.
257 Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:
258 - =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded
259 from the first 32-bit word of the vector table from the program memory.
260 - =1 PSP is the current stack pointer. The initial value is undefined.
262 \param [in] topOfProcStack PSP value to set
265 - Only one of the two SPs is visible at a time.
266 - For many applications, the system can completely rely on the MSP.
267 - The PSP is normally used in designs with an OS where the stack memory for OS Kernel must
268 be separated from the application code.
271 - \ref __get_PSP; __set_MSP; __set_CONTROL
274 void __set_PSP(uint32_t topOfProcStack);
277 /**************************************************************************************************/
278 /** \brief Read the MSP register
280 The function reads the Main Status Pointer (MSP) value using the instruction \b MRS.
282 Physically two different stack pointers (SP) exist:
283 - The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when
284 running exception handlers (handler mode).
285 - The Process Stack Pointer (PSP), which can be used only in thread mode.
287 Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:
288 - =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded
289 from the first 32-bit word of the vector table from the program memory.
290 - =1 PSP is the current stack pointer. The initial value is undefined.
292 \returns MSP Register value
295 - Only one of the two SPs is visible at a time.
296 - For many applications, the system can completely rely on the MSP.
297 - The PSP is normally used in designs with an OS where the stack memory for OS Kernel must
298 be separated from the application code.
301 - \ref __set_MSP; __get_PSP; __get_CONTROL
305 uint32_t __get_MSP(void);
308 /**************************************************************************************************/
309 /** \brief Set the MSP register
311 The function sets the Main Status Pointer (MSP) value using the instruction \b MSR.
313 Physically two different stack pointers (SP) exist:
314 - The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when
315 running exception handlers (handler mode).
316 - The Process Stack Pointer (PSP), which can be used only in thread mode.
318 Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:
319 - =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded
320 from the first 32-bit word of the vector table from the program memory.
321 - =1 PSP is the current stack pointer. The initial value is undefined.
323 \param [in] topOfMainStack MSP value to set
326 - Only one of the two SPs is visible at a time.
327 - For many applications, the system can completely rely on the MSP.
328 - The PSP is normally used in designs with an OS where the stack memory for OS Kernel must
329 be separated from the application code.
332 - \ref __get_MSP; __set_PSP; __set_CONTROL
336 void __set_MSP(uint32_t topOfMainStack);
339 /**************************************************************************************************/
340 /** \brief Read the PRIMASK register bit
342 The function reads the Priority Mask register (PRIMASK) value using the instruction \b MRS.
344 PRIMASK is a 1-bit-wide interrupt mask register. When set,
345 it blocks all interrupts apart from the non-maskable interrupt (NMI) and the hard fault exception.
346 The PRIMASK prevents activation of all exceptions with configurable priority.
348 \returns PRIMASK register value
350 - =1 prevents the activation of all exceptions with configurable priority
353 - \ref __set_PRIMASK; __get_BASEPRI; __get_FAULTMASK
357 uint32_t __get_PRIMASK(void);
360 /**************************************************************************************************/
361 /** \brief Set the Priority Mask bit
363 The function sets the Priority Mask register (PRIMASK) value using the instruction \b MSR.
365 PRIMASK is a 1-bit-wide interrupt mask register. When set,
366 it blocks all interrupts apart from the non-maskable interrupt (NMI) and the hard fault exception.
367 The PRIMASK prevents activation of all exceptions with configurable priority.
369 \param [in] priMask Priority Mask
371 - =1 prevents the activation of all exceptions with configurable priority
374 - When set, PRIMASK effectively changes the current priority level to 0.
375 This is the highest programmable level.
376 - When set and a fault occurs, the hard fault handler will be executed.
377 - Useful for temprorarily disabling all interrupts for timing critical tasks.
378 - Does not have the ability to mask BusFault or bypass MPU.
381 - \ref __get_PRIMASK; __set_BASEPRI; __set_FAULTMASK
385 void __set_PRIMASK(uint32_t priMask);
388 /**************************************************************************************************/
389 /** \brief Read the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]
391 The function returns the Base Priority Mask register (BASEPRI) using the instruction \b MRS.
393 BASEPRI defines the minimum priority for exception processing. When BASEPRI is set to a non-zero
394 value, it prevents the activation of all exceptions with the same or lower priority level as
397 \returns BASEPRI register value
400 - Not for Cortex-M0, Cortex-M0+, or SC000.
403 - \ref __set_BASEPRI; __set_BASEPRI_MAX; __get_FAULTMASK; __get_PRIMASK
407 uint32_t __get_BASEPRI(void);
410 /**************************************************************************************************/
411 /** \brief Set the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]
413 The function sets the Base Priority Mask register (BASEPRI) value using the instruction \b MSR.
415 BASEPRI defines the minimum priority for exception processing.
416 When BASEPRI is set to a non-zero value, it prevents the activation of all exceptions with the
417 same or lower priority level as the BASEPRI value.
419 \param [in] basePri BASEPRI value to set
422 - Not for Cortex-M0, Cortex-M0+, or SC000.
423 - Cannot be set in user state.
424 - Useful for changing the masking level or disabling the masking.
427 - \ref __get_BASEPRI; __set_BASEPRI_MAX; __set_FAULTMASK; __set_PRIMASK
431 void __set_BASEPRI(uint32_t basePri);
434 /**************************************************************************************************/
435 /** \brief Increase the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]
437 The function only increases the Base Priority Mask register (BASEPRI) value using the instruction \b MSR.
438 The value is set only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level.
440 BASEPRI defines the minimum priority for exception processing.
442 \param [in] basePri BASEPRI value to set
445 - Not for Cortex-M0, Cortex-M0+, or SC000.
446 - Cannot be set in user state.
447 - Useful for increasing the masking level.
448 - Has no effect when \em basePri is lower than the current value of BASEPRI.
449 - Use \ref __set_BASEPRI to lower the Base Priority Mask register.
452 - \ref __set_BASEPRI; __get_BASEPRI; __set_FAULTMASK; __set_PRIMASK
456 void __set_BASEPRI_MAX(uint32_t basePri);
459 /**************************************************************************************************/
460 /** \brief Read the FAULTMASK register [not for Cortex-M0, Cortex-M0+, or SC000]
462 The function reads the Fault Mask register (FAULTMASK) value using the instruction \b MRS.
464 FAULTMASK prevents activation of all exceptions except for the Non-Maskable Interrupt (NMI).
466 \returns FAULTMASK register value
469 - not for Cortex-M0, Cortex-M0+, or SC000.
470 - Is cleared automatically upon exiting the exception handler, except when returning
471 from the NMI handler.
474 - \ref __set_FAULTMASK; __get_BASEPRI; __get_PRIMASK
477 uint32_t __get_FAULTMASK(void);
480 /**************************************************************************************************/
481 /** \brief Set the FAULTMASK register [not for Cortex-M0, Cortex-M0+, or SC000]
483 The function sets the Fault Mask register (FAULTMASK) value using the instruction \b MSR.
485 FAULTMASK prevents activation of all exceptions except for Non-Maskable Interrupt (NMI).
486 FAULTMASK can be used to escalate a configurable fault handler (BusFault, usage fault, or
487 memory management fault) to hard fault level without invoking a hard fault. This allows the
488 fault handler to pretend to be the hard fault handler, whith the ability to:
489 -# <b>Mask BusFault</b> by setting the BFHFNMIGN in the Configuration Control register.
490 It can be used to test the bus system without causing a lockup.
491 -# <b>Bypass the MPU</b>, allowing accessing the MPU protected memory location without
492 reprogramming the MPU to just carry out a few transfers for fixing faults.
494 \param [in] faultMask FAULTMASK register value to set
497 - not for Cortex-M0, Cortex-M0+, or SC000.
498 - Is cleared automatically upon exiting the exception handler, except when returning
499 from the NMI handler.
500 - When set, it changes the effective current priority level to -1, so that even the hard
501 fault handler is blocked.
502 - Can be used by fault handlers to change their priority to -1 to have access to some
503 features for hard fault exceptions (see above).
504 - When set, lockups can still be caused by incorrect or undefined instructions, or by using
505 SVC in the wrong priority level.
508 - \ref __get_FAULTMASK; __set_BASEPRI; __set_PRIMASK
511 void __set_FAULTMASK(uint32_t faultMask);
514 /**************************************************************************************************/
515 /** \brief Read the FPSCR register [only Cortex-M4 and Cortex-M7]
517 The function reads the Floating-Point Status Control Register (FPSCR) value.
519 FPSCR provides all necessary User level controls of the floating-point system.
522 - FPSCR register value, when __FPU_PRESENT=1
523 - =0, when __FPU_PRESENT=0
526 - Only for Cortex-M4 and Cortex-M7.
533 uint32_t __get_FPSCR(void);
536 /**************************************************************************************************/
537 /** \brief Set the FPSC register [only for Cortex-M4 and Cortex-M7]
539 The function sets the Floating-Point Status Control Register (FPSCR) value.
541 FPSCR provides all necessary User level control of the floating-point system.
543 - \b N (FPSC[31]) (Negative flag)
544 - =1 The instruction result has a negative value (when interpreted as signed integer).
545 - =0 The instruction result has a positive value or equal zero.
547 - \b Z (FPSC[30]) (Zero flag)
548 - =1 The instruction result is zero. Or, after a compare instruction, when the two values
551 - \b C (FPSC[29]) (Carry or borrow flag)
552 - =1 For unsigned additions, if an unsigned overflow occurred.
553 - =<i>inverse of borrow output status</i> For unsigned subtract operations.
555 - \b V (FPSC[28]) (Overflow flag)
556 - =1 A signed overflow occurred (for signed additions or subtractions).
558 - \b AHP (FPSC[26]) (Alternative half-precision flag)
559 - =1 Alternative half-precision format selected.
560 - =0 IEEE half-precision format selected.
562 - \b DN (FPSC[25]) (Default NaN mode control flag)
563 - =1 Any operation involving one or more NaNs returns the Default NaN.
564 - =0 NaN operands propagate through to the output of a floating-point operation.
566 - \b FZ (FPSC[24]) (Flush-to-zero mode control flag)
567 - =1 Flush-to-zero mode enabled.
568 - =0 Flush-to-zero mode disabled. Behavior of the floating-point system is fully
569 compliant with the IEEE 754 standard.
571 - \b RMode (FPSC[23:22]) (Rounding Mode control flags)
572 - =0b00 Round to Nearest (RN) mode.
573 - =0b01 Round towards Plus Infinity (RP) mode.
574 - =0b10 Round towards Minus Infinity (RM) mode.
575 - =0b11 Round towards Zero (RZ) mode.
576 - The specified rounding mode is used by almost all floating-point instructions.
578 - \b IDC (FPSC[7]) (Input Denormal cumulative exception flags)
579 - See Cumulative exception bits (FPSC[4:0]).
581 - \b IXC (FPSC[4]) (Inexact cumulative exception flag)
582 - =1 Exception occurred.
583 - =0 Value has to be set explicitly.
584 - Flag is not cleared automatically.
586 - \b UFC (FPSC[3]) (Underflow cumulative exception flag)
587 - =1 Exception occurred.
588 - =0 Value has to be set explicitly.
589 - Flag is not cleared automatically.
591 - \b OFC (FPSC[2]) (Overflow cumulative exception flag)
592 - =1 Exception occurred.
593 - =0 Value has to be set explicitly.
594 - Flag is not cleared automatically.
596 - \b DZC (FPSC[1]) (Division by Zero cumulative exception flag)
597 - =1 Exception occurred.
598 - =0 Value has to be set explicitly.
599 - Flag is not cleared automatically.
601 - \b IOC (FPSC[0]) (Invalid Operation cumulative exception flag)
602 - =1 Exception occurred.
603 - =0 Value has to be set explicitly.
604 - Flag is not cleared automatically.
606 \param [in] fpscr FPSCR value to set
609 - Only for Cortex-M4 and Cortex-M7.
610 - The variable \b __FPU_PRESENT has to be set to 1.
616 void __set_FPSCR(uint32_t fpscr);
619 /**************************************************************************************************/
620 /** \brief Globally enables interrupts and configurable fault handlers
622 The function enables interrupts and all configurable fault handlers by clearing PRIMASK.
623 The function uses the instruction <b>CPSIE i</b>.
626 - Can be executed in privileged mode only.
629 - \ref __disable_irq; __set_BASEPRI; __set_CONTROL; __set_PRIMASK
631 void __enable_irq(void);
634 /**************************************************************************************************/
635 /** \brief Globally disables interrupts and configurable fault handlers
637 The function disables interrupts and all configurable fault handlers by setting PRIMASK.
638 The function uses the instruction <b>CPSID i</b>.
641 - Can be executed in privileged mode only.
642 - An interrupt can enter pending state even if it is disabled. Disabling an interrupt
643 only prevents the processor from taking that interrupt.
646 - \ref __enable_irq; __set_BASEPRI; __set_CONTROL; __set_PRIMASK
648 void __disable_irq(void);
651 /**************************************************************************************************/
652 /** \brief Enables interrupts and all fault handlers [not for Cortex-M0, Cortex-M0+, or SC000]
654 The function enables interrupts and all fault handlers by clearing FAULTMASK.
655 The function uses the instruction <b>CPSIE f</b>.
658 - not for Cortex-M0, Cortex-M0+, or SC000.
659 - Can be executed in privileged mode only.
662 - \ref __disable_fault_irq; __set_BASEPRI; __set_CONTROL; __set_FAULTMASK
664 void __enable_fault_irq(void);
667 /**************************************************************************************************/
668 /** \brief Disables interrupts and all fault handlers [not for Cortex-M0, Cortex-M0+, or SC000]
670 The function disables interrupts and all fault handlers by setting FAULTMASK.
671 The function uses the instruction <b>CPSID f</b>.
674 - not for Cortex-M0, Cortex-M0+, or SC000.
675 - Can be executed in privileged mode only.
676 - An interrupt can enter pending state even if it is disabled. Disabling an interrupt
677 only prevents the processor from taking that interrupt.
680 - \ref __enable_fault_irq; __set_BASEPRI; __set_CONTROL; __set_FAULTMASK
682 void __disable_fault_irq(void);
689 \brief Get Process Stack Pointer Limit
690 Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
691 Stack Pointer Limit register hence zero is returned always in non-secure
694 \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
695 \return PSPLIM Register value
696 \note Only availabe for Armv8-M Architecture.
698 uint32_t __get_PSPLIM(void);
701 \brief Set Process Stack Pointer Limit
702 Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
703 Stack Pointer Limit register hence the write is silently ignored in non-secure
706 \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
707 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
708 \note Only availabe for Armv8-M Architecture.
710 void __set_PSPLIM(uint32_t ProcStackPtrLimit);
713 \brief Get Main Stack Pointer Limit
714 Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
715 Stack Pointer Limit register hence zero is returned always in non-secure
718 \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
719 \return MSPLIM Register value
720 \note Only availabe for Armv8-M Architecture.
722 uint32_t __get_MSPLIM(void);
725 \brief Set Main Stack Pointer Limit
726 Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
727 Stack Pointer Limit register hence the write is silently ignored in non-secure
730 \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
731 \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
732 \note Only availabe for Armv8-M Architecture.
734 __set_MSPLIM(uint32_t MainStackPtrLimit);
740 /** @} */ /** end of Core_Register_gr **/
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