1 /**************************************************************************//**
3 * @brief CMSIS Cortex-A Core Peripheral Access Layer Header File
5 * @date 05. October 2023
6 ******************************************************************************/
8 * Copyright (c) 2009-2022 ARM Limited. All rights reserved.
10 * SPDX-License-Identifier: Apache-2.0
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
16 * www.apache.org/licenses/LICENSE-2.0
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
25 #ifndef __CORE_CA_H_GENERIC
26 #define __CORE_CA_H_GENERIC
28 #if defined ( __ICCARM__ )
29 #pragma system_include /* treat file as system include file for MISRA check */
30 #elif defined (__clang__)
31 #pragma clang system_header /* treat file as system include file */
38 /*******************************************************************************
40 ******************************************************************************/
42 /* CMSIS CA definitions */
43 #define __CA_CMSIS_VERSION_MAIN (1U) /*!< \brief [31:16] CMSIS-Core(A) main version */
44 #define __CA_CMSIS_VERSION_SUB (1U) /*!< \brief [15:0] CMSIS-Core(A) sub version */
45 #define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \
46 __CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS-Core(A) version number */
48 #if defined ( __CC_ARM )
49 #if defined (__TARGET_FPU_VFP)
50 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
53 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
60 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
61 #if defined (__ARM_FP)
62 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
65 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
72 #elif defined ( __ICCARM__ )
73 #if defined (__ARMVFP__)
74 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
77 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
84 #elif defined ( __TMS470__ )
85 #if defined __TI_VFP_SUPPORT__
86 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
89 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
96 #elif defined ( __GNUC__ )
97 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
98 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
101 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
102 #define __FPU_USED 0U
105 #define __FPU_USED 0U
108 #elif defined ( __TASKING__ )
109 #if defined (__FPU_VFP__)
110 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
111 #define __FPU_USED 1U
113 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
114 #define __FPU_USED 0U
117 #define __FPU_USED 0U
121 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
127 #endif /* __CORE_CA_H_GENERIC */
129 #ifndef __CMSIS_GENERIC
131 #ifndef __CORE_CA_H_DEPENDANT
132 #define __CORE_CA_H_DEPENDANT
134 #if defined ( __ICCARM__ )
135 #pragma system_include /* treat file as system include file for MISRA check */
136 #elif defined (__clang__)
137 #pragma clang system_header /* treat file as system include file */
144 /* check device defines and use defaults */
145 #if defined __CHECK_DEVICE_DEFINES
147 #define __CA_REV 0x0000U /*!< \brief Contains the core revision for a Cortex-A class device */
148 #warning "__CA_REV not defined in device header file; using default!"
151 #ifndef __FPU_PRESENT
152 #define __FPU_PRESENT 0U
153 #warning "__FPU_PRESENT not defined in device header file; using default!"
156 #ifndef __GIC_PRESENT
157 #define __GIC_PRESENT 1U
158 #warning "__GIC_PRESENT not defined in device header file; using default!"
161 #ifndef __TIM_PRESENT
162 #define __TIM_PRESENT 1U
163 #warning "__TIM_PRESENT not defined in device header file; using default!"
166 #ifndef __L2C_PRESENT
167 #define __L2C_PRESENT 0U
168 #warning "__L2C_PRESENT not defined in device header file; using default!"
172 /* IO definitions (access restrictions to peripheral registers) */
174 #define __I volatile /*!< \brief Defines 'read only' permissions */
176 #define __I volatile const /*!< \brief Defines 'read only' permissions */
178 #define __O volatile /*!< \brief Defines 'write only' permissions */
179 #define __IO volatile /*!< \brief Defines 'read / write' permissions */
181 /* following defines should be used for structure members */
182 #define __IM volatile const /*!< \brief Defines 'read only' structure member permissions */
183 #define __OM volatile /*!< \brief Defines 'write only' structure member permissions */
184 #define __IOM volatile /*!< \brief Defines 'read / write' structure member permissions */
185 #define RESERVED(N, T) T RESERVED##N; // placeholder struct members used for "reserved" areas
187 /*******************************************************************************
188 * Register Abstraction
189 Core Register contain:
192 - L2C-310 Cache Controller
193 - Generic Interrupt Controller Distributor
194 - Generic Interrupt Controller Interface
195 ******************************************************************************/
197 /* Core Register CPSR */
202 uint32_t M:5; /*!< \brief bit: 0.. 4 Mode field */
203 uint32_t T:1; /*!< \brief bit: 5 Thumb execution state bit */
204 uint32_t F:1; /*!< \brief bit: 6 FIQ mask bit */
205 uint32_t I:1; /*!< \brief bit: 7 IRQ mask bit */
206 uint32_t A:1; /*!< \brief bit: 8 Asynchronous abort mask bit */
207 uint32_t E:1; /*!< \brief bit: 9 Endianness execution state bit */
208 uint32_t IT1:6; /*!< \brief bit: 10..15 If-Then execution state bits 2-7 */
209 uint32_t GE:4; /*!< \brief bit: 16..19 Greater than or Equal flags */
210 RESERVED(0:4, uint32_t)
211 uint32_t J:1; /*!< \brief bit: 24 Jazelle bit */
212 uint32_t IT0:2; /*!< \brief bit: 25..26 If-Then execution state bits 0-1 */
213 uint32_t Q:1; /*!< \brief bit: 27 Saturation condition flag */
214 uint32_t V:1; /*!< \brief bit: 28 Overflow condition code flag */
215 uint32_t C:1; /*!< \brief bit: 29 Carry condition code flag */
216 uint32_t Z:1; /*!< \brief bit: 30 Zero condition code flag */
217 uint32_t N:1; /*!< \brief bit: 31 Negative condition code flag */
218 } b; /*!< \brief Structure used for bit access */
219 uint32_t w; /*!< \brief Type used for word access */
224 /* CPSR Register Definitions */
225 #define CPSR_N_Pos 31U /*!< \brief CPSR: N Position */
226 #define CPSR_N_Msk (1UL << CPSR_N_Pos) /*!< \brief CPSR: N Mask */
228 #define CPSR_Z_Pos 30U /*!< \brief CPSR: Z Position */
229 #define CPSR_Z_Msk (1UL << CPSR_Z_Pos) /*!< \brief CPSR: Z Mask */
231 #define CPSR_C_Pos 29U /*!< \brief CPSR: C Position */
232 #define CPSR_C_Msk (1UL << CPSR_C_Pos) /*!< \brief CPSR: C Mask */
234 #define CPSR_V_Pos 28U /*!< \brief CPSR: V Position */
235 #define CPSR_V_Msk (1UL << CPSR_V_Pos) /*!< \brief CPSR: V Mask */
237 #define CPSR_Q_Pos 27U /*!< \brief CPSR: Q Position */
238 #define CPSR_Q_Msk (1UL << CPSR_Q_Pos) /*!< \brief CPSR: Q Mask */
240 #define CPSR_IT0_Pos 25U /*!< \brief CPSR: IT0 Position */
241 #define CPSR_IT0_Msk (3UL << CPSR_IT0_Pos) /*!< \brief CPSR: IT0 Mask */
243 #define CPSR_J_Pos 24U /*!< \brief CPSR: J Position */
244 #define CPSR_J_Msk (1UL << CPSR_J_Pos) /*!< \brief CPSR: J Mask */
246 #define CPSR_GE_Pos 16U /*!< \brief CPSR: GE Position */
247 #define CPSR_GE_Msk (0xFUL << CPSR_GE_Pos) /*!< \brief CPSR: GE Mask */
249 #define CPSR_IT1_Pos 10U /*!< \brief CPSR: IT1 Position */
250 #define CPSR_IT1_Msk (0x3FUL << CPSR_IT1_Pos) /*!< \brief CPSR: IT1 Mask */
252 #define CPSR_E_Pos 9U /*!< \brief CPSR: E Position */
253 #define CPSR_E_Msk (1UL << CPSR_E_Pos) /*!< \brief CPSR: E Mask */
255 #define CPSR_A_Pos 8U /*!< \brief CPSR: A Position */
256 #define CPSR_A_Msk (1UL << CPSR_A_Pos) /*!< \brief CPSR: A Mask */
258 #define CPSR_I_Pos 7U /*!< \brief CPSR: I Position */
259 #define CPSR_I_Msk (1UL << CPSR_I_Pos) /*!< \brief CPSR: I Mask */
261 #define CPSR_F_Pos 6U /*!< \brief CPSR: F Position */
262 #define CPSR_F_Msk (1UL << CPSR_F_Pos) /*!< \brief CPSR: F Mask */
264 #define CPSR_T_Pos 5U /*!< \brief CPSR: T Position */
265 #define CPSR_T_Msk (1UL << CPSR_T_Pos) /*!< \brief CPSR: T Mask */
267 #define CPSR_M_Pos 0U /*!< \brief CPSR: M Position */
268 #define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /*!< \brief CPSR: M Mask */
270 #define CPSR_M_USR 0x10U /*!< \brief CPSR: M User mode (PL0) */
271 #define CPSR_M_FIQ 0x11U /*!< \brief CPSR: M Fast Interrupt mode (PL1) */
272 #define CPSR_M_IRQ 0x12U /*!< \brief CPSR: M Interrupt mode (PL1) */
273 #define CPSR_M_SVC 0x13U /*!< \brief CPSR: M Supervisor mode (PL1) */
274 #define CPSR_M_MON 0x16U /*!< \brief CPSR: M Monitor mode (PL1) */
275 #define CPSR_M_ABT 0x17U /*!< \brief CPSR: M Abort mode (PL1) */
276 #define CPSR_M_HYP 0x1AU /*!< \brief CPSR: M Hypervisor mode (PL2) */
277 #define CPSR_M_UND 0x1BU /*!< \brief CPSR: M Undefined mode (PL1) */
278 #define CPSR_M_SYS 0x1FU /*!< \brief CPSR: M System mode (PL1) */
280 /* CP15 Register SCTLR */
285 uint32_t M:1; /*!< \brief bit: 0 MMU enable */
286 uint32_t A:1; /*!< \brief bit: 1 Alignment check enable */
287 uint32_t C:1; /*!< \brief bit: 2 Cache enable */
288 RESERVED(0:2, uint32_t)
289 uint32_t CP15BEN:1; /*!< \brief bit: 5 CP15 barrier enable */
290 RESERVED(1:1, uint32_t)
291 uint32_t B:1; /*!< \brief bit: 7 Endianness model */
292 RESERVED(2:2, uint32_t)
293 uint32_t SW:1; /*!< \brief bit: 10 SWP and SWPB enable */
294 uint32_t Z:1; /*!< \brief bit: 11 Branch prediction enable */
295 uint32_t I:1; /*!< \brief bit: 12 Instruction cache enable */
296 uint32_t V:1; /*!< \brief bit: 13 Vectors bit */
297 uint32_t RR:1; /*!< \brief bit: 14 Round Robin select */
298 RESERVED(3:2, uint32_t)
299 uint32_t HA:1; /*!< \brief bit: 17 Hardware Access flag enable */
300 RESERVED(4:1, uint32_t)
301 uint32_t WXN:1; /*!< \brief bit: 19 Write permission implies XN */
302 uint32_t UWXN:1; /*!< \brief bit: 20 Unprivileged write permission implies PL1 XN */
303 uint32_t FI:1; /*!< \brief bit: 21 Fast interrupts configuration enable */
304 uint32_t U:1; /*!< \brief bit: 22 Alignment model */
305 RESERVED(5:1, uint32_t)
306 uint32_t VE:1; /*!< \brief bit: 24 Interrupt Vectors Enable */
307 uint32_t EE:1; /*!< \brief bit: 25 Exception Endianness */
308 RESERVED(6:1, uint32_t)
309 uint32_t NMFI:1; /*!< \brief bit: 27 Non-maskable FIQ (NMFI) support */
310 uint32_t TRE:1; /*!< \brief bit: 28 TEX remap enable. */
311 uint32_t AFE:1; /*!< \brief bit: 29 Access flag enable */
312 uint32_t TE:1; /*!< \brief bit: 30 Thumb Exception enable */
313 RESERVED(7:1, uint32_t)
314 } b; /*!< \brief Structure used for bit access */
315 uint32_t w; /*!< \brief Type used for word access */
318 #define SCTLR_TE_Pos 30U /*!< \brief SCTLR: TE Position */
319 #define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /*!< \brief SCTLR: TE Mask */
321 #define SCTLR_AFE_Pos 29U /*!< \brief SCTLR: AFE Position */
322 #define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /*!< \brief SCTLR: AFE Mask */
324 #define SCTLR_TRE_Pos 28U /*!< \brief SCTLR: TRE Position */
325 #define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /*!< \brief SCTLR: TRE Mask */
327 #define SCTLR_NMFI_Pos 27U /*!< \brief SCTLR: NMFI Position */
328 #define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) /*!< \brief SCTLR: NMFI Mask */
330 #define SCTLR_EE_Pos 25U /*!< \brief SCTLR: EE Position */
331 #define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /*!< \brief SCTLR: EE Mask */
333 #define SCTLR_VE_Pos 24U /*!< \brief SCTLR: VE Position */
334 #define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) /*!< \brief SCTLR: VE Mask */
336 #define SCTLR_U_Pos 22U /*!< \brief SCTLR: U Position */
337 #define SCTLR_U_Msk (1UL << SCTLR_U_Pos) /*!< \brief SCTLR: U Mask */
339 #define SCTLR_FI_Pos 21U /*!< \brief SCTLR: FI Position */
340 #define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) /*!< \brief SCTLR: FI Mask */
342 #define SCTLR_UWXN_Pos 20U /*!< \brief SCTLR: UWXN Position */
343 #define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /*!< \brief SCTLR: UWXN Mask */
345 #define SCTLR_WXN_Pos 19U /*!< \brief SCTLR: WXN Position */
346 #define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /*!< \brief SCTLR: WXN Mask */
348 #define SCTLR_HA_Pos 17U /*!< \brief SCTLR: HA Position */
349 #define SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) /*!< \brief SCTLR: HA Mask */
351 #define SCTLR_RR_Pos 14U /*!< \brief SCTLR: RR Position */
352 #define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) /*!< \brief SCTLR: RR Mask */
354 #define SCTLR_V_Pos 13U /*!< \brief SCTLR: V Position */
355 #define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /*!< \brief SCTLR: V Mask */
357 #define SCTLR_I_Pos 12U /*!< \brief SCTLR: I Position */
358 #define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /*!< \brief SCTLR: I Mask */
360 #define SCTLR_Z_Pos 11U /*!< \brief SCTLR: Z Position */
361 #define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) /*!< \brief SCTLR: Z Mask */
363 #define SCTLR_SW_Pos 10U /*!< \brief SCTLR: SW Position */
364 #define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) /*!< \brief SCTLR: SW Mask */
366 #define SCTLR_B_Pos 7U /*!< \brief SCTLR: B Position */
367 #define SCTLR_B_Msk (1UL << SCTLR_B_Pos) /*!< \brief SCTLR: B Mask */
369 #define SCTLR_CP15BEN_Pos 5U /*!< \brief SCTLR: CP15BEN Position */
370 #define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /*!< \brief SCTLR: CP15BEN Mask */
372 #define SCTLR_C_Pos 2U /*!< \brief SCTLR: C Position */
373 #define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /*!< \brief SCTLR: C Mask */
375 #define SCTLR_A_Pos 1U /*!< \brief SCTLR: A Position */
376 #define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /*!< \brief SCTLR: A Mask */
378 #define SCTLR_M_Pos 0U /*!< \brief SCTLR: M Position */
379 #define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /*!< \brief SCTLR: M Mask */
381 /* CP15 Register ACTLR */
384 #if __CORTEX_A == 5 || defined(DOXYGEN)
385 /** \brief Structure used for bit access on Cortex-A5 */
388 uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */
389 RESERVED(0:5, uint32_t)
390 uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */
391 uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */
392 RESERVED(1:2, uint32_t)
393 uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */
394 uint32_t DWBST:1; /*!< \brief bit: 11 AXI data write bursts to Normal memory */
395 uint32_t RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */
396 uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */
397 uint32_t BP:2; /*!< \brief bit:16..15 Branch prediction policy */
398 uint32_t RSDIS:1; /*!< \brief bit: 17 Disable return stack operation */
399 uint32_t BTDIS:1; /*!< \brief bit: 18 Disable indirect Branch Target Address Cache (BTAC) */
400 RESERVED(3:9, uint32_t)
401 uint32_t DBDI:1; /*!< \brief bit: 28 Disable branch dual issue */
402 RESERVED(7:3, uint32_t)
405 #if __CORTEX_A == 7 || defined(DOXYGEN)
406 /** \brief Structure used for bit access on Cortex-A7 */
409 RESERVED(0:6, uint32_t)
410 uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */
411 RESERVED(1:3, uint32_t)
412 uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */
413 uint32_t L2RADIS:1; /*!< \brief bit: 11 L2 Data Cache read-allocate mode disable */
414 uint32_t L1RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */
415 uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */
416 uint32_t DDVM:1; /*!< \brief bit: 15 Disable Distributed Virtual Memory (DVM) transactions */
417 RESERVED(3:12, uint32_t)
418 uint32_t DDI:1; /*!< \brief bit: 28 Disable dual issue */
419 RESERVED(7:3, uint32_t)
422 #if __CORTEX_A == 9 || defined(DOXYGEN)
423 /** \brief Structure used for bit access on Cortex-A9 */
426 uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */
427 RESERVED(0:1, uint32_t)
428 uint32_t L1PE:1; /*!< \brief bit: 2 Dside prefetch */
429 uint32_t WFLZM:1; /*!< \brief bit: 3 Cache and TLB maintenance broadcast */
430 RESERVED(1:2, uint32_t)
431 uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */
432 uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */
433 uint32_t AOW:1; /*!< \brief bit: 8 Enable allocation in one cache way only */
434 uint32_t PARITY:1; /*!< \brief bit: 9 Support for parity checking, if implemented */
435 RESERVED(7:22, uint32_t)
438 uint32_t w; /*!< \brief Type used for word access */
441 #define ACTLR_DDI_Pos 28U /*!< \brief ACTLR: DDI Position */
442 #define ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos) /*!< \brief ACTLR: DDI Mask */
444 #define ACTLR_DBDI_Pos 28U /*!< \brief ACTLR: DBDI Position */
445 #define ACTLR_DBDI_Msk (1UL << ACTLR_DBDI_Pos) /*!< \brief ACTLR: DBDI Mask */
447 #define ACTLR_BTDIS_Pos 18U /*!< \brief ACTLR: BTDIS Position */
448 #define ACTLR_BTDIS_Msk (1UL << ACTLR_BTDIS_Pos) /*!< \brief ACTLR: BTDIS Mask */
450 #define ACTLR_RSDIS_Pos 17U /*!< \brief ACTLR: RSDIS Position */
451 #define ACTLR_RSDIS_Msk (1UL << ACTLR_RSDIS_Pos) /*!< \brief ACTLR: RSDIS Mask */
453 #define ACTLR_BP_Pos 15U /*!< \brief ACTLR: BP Position */
454 #define ACTLR_BP_Msk (3UL << ACTLR_BP_Pos) /*!< \brief ACTLR: BP Mask */
456 #define ACTLR_DDVM_Pos 15U /*!< \brief ACTLR: DDVM Position */
457 #define ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos) /*!< \brief ACTLR: DDVM Mask */
459 #define ACTLR_L1PCTL_Pos 13U /*!< \brief ACTLR: L1PCTL Position */
460 #define ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos) /*!< \brief ACTLR: L1PCTL Mask */
462 #define ACTLR_RADIS_Pos 12U /*!< \brief ACTLR: RADIS Position */
463 #define ACTLR_RADIS_Msk (1UL << ACTLR_RADIS_Pos) /*!< \brief ACTLR: RADIS Mask */
465 #define ACTLR_L1RADIS_Pos 12U /*!< \brief ACTLR: L1RADIS Position */
466 #define ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos) /*!< \brief ACTLR: L1RADIS Mask */
468 #define ACTLR_DWBST_Pos 11U /*!< \brief ACTLR: DWBST Position */
469 #define ACTLR_DWBST_Msk (1UL << ACTLR_DWBST_Pos) /*!< \brief ACTLR: DWBST Mask */
471 #define ACTLR_L2RADIS_Pos 11U /*!< \brief ACTLR: L2RADIS Position */
472 #define ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos) /*!< \brief ACTLR: L2RADIS Mask */
474 #define ACTLR_DODMBS_Pos 10U /*!< \brief ACTLR: DODMBS Position */
475 #define ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos) /*!< \brief ACTLR: DODMBS Mask */
477 #define ACTLR_PARITY_Pos 9U /*!< \brief ACTLR: PARITY Position */
478 #define ACTLR_PARITY_Msk (1UL << ACTLR_PARITY_Pos) /*!< \brief ACTLR: PARITY Mask */
480 #define ACTLR_AOW_Pos 8U /*!< \brief ACTLR: AOW Position */
481 #define ACTLR_AOW_Msk (1UL << ACTLR_AOW_Pos) /*!< \brief ACTLR: AOW Mask */
483 #define ACTLR_EXCL_Pos 7U /*!< \brief ACTLR: EXCL Position */
484 #define ACTLR_EXCL_Msk (1UL << ACTLR_EXCL_Pos) /*!< \brief ACTLR: EXCL Mask */
486 #define ACTLR_SMP_Pos 6U /*!< \brief ACTLR: SMP Position */
487 #define ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos) /*!< \brief ACTLR: SMP Mask */
489 #define ACTLR_WFLZM_Pos 3U /*!< \brief ACTLR: WFLZM Position */
490 #define ACTLR_WFLZM_Msk (1UL << ACTLR_WFLZM_Pos) /*!< \brief ACTLR: WFLZM Mask */
492 #define ACTLR_L1PE_Pos 2U /*!< \brief ACTLR: L1PE Position */
493 #define ACTLR_L1PE_Msk (1UL << ACTLR_L1PE_Pos) /*!< \brief ACTLR: L1PE Mask */
495 #define ACTLR_FW_Pos 0U /*!< \brief ACTLR: FW Position */
496 #define ACTLR_FW_Msk (1UL << ACTLR_FW_Pos) /*!< \brief ACTLR: FW Mask */
498 /* CP15 Register CPACR */
503 uint32_t CP0:2; /*!< \brief bit: 0..1 Access rights for coprocessor 0 */
504 uint32_t CP1:2; /*!< \brief bit: 2..3 Access rights for coprocessor 1 */
505 uint32_t CP2:2; /*!< \brief bit: 4..5 Access rights for coprocessor 2 */
506 uint32_t CP3:2; /*!< \brief bit: 6..7 Access rights for coprocessor 3 */
507 uint32_t CP4:2; /*!< \brief bit: 8..9 Access rights for coprocessor 4 */
508 uint32_t CP5:2; /*!< \brief bit:10..11 Access rights for coprocessor 5 */
509 uint32_t CP6:2; /*!< \brief bit:12..13 Access rights for coprocessor 6 */
510 uint32_t CP7:2; /*!< \brief bit:14..15 Access rights for coprocessor 7 */
511 uint32_t CP8:2; /*!< \brief bit:16..17 Access rights for coprocessor 8 */
512 uint32_t CP9:2; /*!< \brief bit:18..19 Access rights for coprocessor 9 */
513 uint32_t CP10:2; /*!< \brief bit:20..21 Access rights for coprocessor 10 */
514 uint32_t CP11:2; /*!< \brief bit:22..23 Access rights for coprocessor 11 */
515 uint32_t CP12:2; /*!< \brief bit:24..25 Access rights for coprocessor 11 */
516 uint32_t CP13:2; /*!< \brief bit:26..27 Access rights for coprocessor 11 */
517 uint32_t TRCDIS:1; /*!< \brief bit: 28 Disable CP14 access to trace registers */
518 RESERVED(0:1, uint32_t)
519 uint32_t D32DIS:1; /*!< \brief bit: 30 Disable use of registers D16-D31 of the VFP register file */
520 uint32_t ASEDIS:1; /*!< \brief bit: 31 Disable Advanced SIMD Functionality */
521 } b; /*!< \brief Structure used for bit access */
522 uint32_t w; /*!< \brief Type used for word access */
525 #define CPACR_ASEDIS_Pos 31U /*!< \brief CPACR: ASEDIS Position */
526 #define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) /*!< \brief CPACR: ASEDIS Mask */
528 #define CPACR_D32DIS_Pos 30U /*!< \brief CPACR: D32DIS Position */
529 #define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */
531 #define CPACR_TRCDIS_Pos 28U /*!< \brief CPACR: D32DIS Position */
532 #define CPACR_TRCDIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */
534 #define CPACR_CP_Pos_(n) (n*2U) /*!< \brief CPACR: CPn Position */
535 #define CPACR_CP_Msk_(n) (3UL << CPACR_CP_Pos_(n)) /*!< \brief CPACR: CPn Mask */
537 #define CPACR_CP_NA 0U /*!< \brief CPACR CPn field: Access denied. */
538 #define CPACR_CP_PL1 1U /*!< \brief CPACR CPn field: Accessible from PL1 only. */
539 #define CPACR_CP_FA 3U /*!< \brief CPACR CPn field: Full access. */
541 /* CP15 Register DFSR */
546 uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */
547 uint32_t Domain:4; /*!< \brief bit: 4.. 7 Fault on which domain */
548 RESERVED(0:1, uint32_t)
549 uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */
550 uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */
551 uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */
552 uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
553 uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */
554 RESERVED(1:18, uint32_t)
555 } s; /*!< \brief Structure used for bit access in short format */
558 uint32_t STATUS:5; /*!< \brief bit: 0.. 5 Fault Status bits */
559 RESERVED(0:3, uint32_t)
560 uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */
561 RESERVED(1:1, uint32_t)
562 uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */
563 uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
564 uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */
565 RESERVED(2:18, uint32_t)
566 } l; /*!< \brief Structure used for bit access in long format */
567 uint32_t w; /*!< \brief Type used for word access */
570 #define DFSR_CM_Pos 13U /*!< \brief DFSR: CM Position */
571 #define DFSR_CM_Msk (1UL << DFSR_CM_Pos) /*!< \brief DFSR: CM Mask */
573 #define DFSR_Ext_Pos 12U /*!< \brief DFSR: Ext Position */
574 #define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) /*!< \brief DFSR: Ext Mask */
576 #define DFSR_WnR_Pos 11U /*!< \brief DFSR: WnR Position */
577 #define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) /*!< \brief DFSR: WnR Mask */
579 #define DFSR_FS1_Pos 10U /*!< \brief DFSR: FS1 Position */
580 #define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /*!< \brief DFSR: FS1 Mask */
582 #define DFSR_LPAE_Pos 9U /*!< \brief DFSR: LPAE Position */
583 #define DFSR_LPAE_Msk (1UL << DFSR_LPAE_Pos) /*!< \brief DFSR: LPAE Mask */
585 #define DFSR_Domain_Pos 4U /*!< \brief DFSR: Domain Position */
586 #define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /*!< \brief DFSR: Domain Mask */
588 #define DFSR_FS0_Pos 0U /*!< \brief DFSR: FS0 Position */
589 #define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /*!< \brief DFSR: FS0 Mask */
591 #define DFSR_STATUS_Pos 0U /*!< \brief DFSR: STATUS Position */
592 #define DFSR_STATUS_Msk (0x3FUL << DFSR_STATUS_Pos) /*!< \brief DFSR: STATUS Mask */
594 /* CP15 Register IFSR */
599 uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */
600 RESERVED(0:5, uint32_t)
601 uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */
602 uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */
603 RESERVED(1:1, uint32_t)
604 uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
605 RESERVED(2:19, uint32_t)
606 } s; /*!< \brief Structure used for bit access in short format */
609 uint32_t STATUS:6; /*!< \brief bit: 0.. 5 Fault Status bits */
610 RESERVED(0:3, uint32_t)
611 uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */
612 RESERVED(1:2, uint32_t)
613 uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
614 RESERVED(2:19, uint32_t)
615 } l; /*!< \brief Structure used for bit access in long format */
616 uint32_t w; /*!< \brief Type used for word access */
619 #define IFSR_ExT_Pos 12U /*!< \brief IFSR: ExT Position */
620 #define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) /*!< \brief IFSR: ExT Mask */
622 #define IFSR_FS1_Pos 10U /*!< \brief IFSR: FS1 Position */
623 #define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /*!< \brief IFSR: FS1 Mask */
625 #define IFSR_LPAE_Pos 9U /*!< \brief IFSR: LPAE Position */
626 #define IFSR_LPAE_Msk (0x1UL << IFSR_LPAE_Pos) /*!< \brief IFSR: LPAE Mask */
628 #define IFSR_FS0_Pos 0U /*!< \brief IFSR: FS0 Position */
629 #define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /*!< \brief IFSR: FS0 Mask */
631 #define IFSR_STATUS_Pos 0U /*!< \brief IFSR: STATUS Position */
632 #define IFSR_STATUS_Msk (0x3FUL << IFSR_STATUS_Pos) /*!< \brief IFSR: STATUS Mask */
634 /* CP15 Register ISR */
639 RESERVED(0:6, uint32_t)
640 uint32_t F:1; /*!< \brief bit: 6 FIQ pending bit */
641 uint32_t I:1; /*!< \brief bit: 7 IRQ pending bit */
642 uint32_t A:1; /*!< \brief bit: 8 External abort pending bit */
643 RESERVED(1:23, uint32_t)
644 } b; /*!< \brief Structure used for bit access */
645 uint32_t w; /*!< \brief Type used for word access */
648 #define ISR_A_Pos 13U /*!< \brief ISR: A Position */
649 #define ISR_A_Msk (1UL << ISR_A_Pos) /*!< \brief ISR: A Mask */
651 #define ISR_I_Pos 12U /*!< \brief ISR: I Position */
652 #define ISR_I_Msk (1UL << ISR_I_Pos) /*!< \brief ISR: I Mask */
654 #define ISR_F_Pos 11U /*!< \brief ISR: F Position */
655 #define ISR_F_Msk (1UL << ISR_F_Pos) /*!< \brief ISR: F Mask */
658 #define DACR_D_Pos_(n) (2U*n) /*!< \brief DACR: Dn Position */
659 #define DACR_D_Msk_(n) (3UL << DACR_D_Pos_(n)) /*!< \brief DACR: Dn Mask */
660 #define DACR_Dn_NOACCESS 0U /*!< \brief DACR Dn field: No access */
661 #define DACR_Dn_CLIENT 1U /*!< \brief DACR Dn field: Client */
662 #define DACR_Dn_MANAGER 3U /*!< \brief DACR Dn field: Manager */
665 \brief Mask and shift a bit field value for use in a register bit range.
666 \param [in] field Name of the register bit field.
667 \param [in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
668 \return Masked and shifted value.
670 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
673 \brief Mask and shift a register value to extract a bit filed value.
674 \param [in] field Name of the register bit field.
675 \param [in] value Value of register. This parameter is interpreted as an uint32_t type.
676 \return Masked and shifted bit field value.
678 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
682 \brief Union type to access the L2C_310 Cache Controller.
684 #if (defined(__L2C_PRESENT) && (__L2C_PRESENT == 1U)) || \
688 __IM uint32_t CACHE_ID; /*!< \brief Offset: 0x0000 (R/ ) Cache ID Register */
689 __IM uint32_t CACHE_TYPE; /*!< \brief Offset: 0x0004 (R/ ) Cache Type Register */
690 RESERVED(0[0x3e], uint32_t)
691 __IOM uint32_t CONTROL; /*!< \brief Offset: 0x0100 (R/W) Control Register */
692 __IOM uint32_t AUX_CNT; /*!< \brief Offset: 0x0104 (R/W) Auxiliary Control */
693 RESERVED(1[0x3e], uint32_t)
694 __IOM uint32_t EVENT_CONTROL; /*!< \brief Offset: 0x0200 (R/W) Event Counter Control */
695 __IOM uint32_t EVENT_COUNTER1_CONF; /*!< \brief Offset: 0x0204 (R/W) Event Counter 1 Configuration */
696 __IOM uint32_t EVENT_COUNTER0_CONF; /*!< \brief Offset: 0x0208 (R/W) Event Counter 1 Configuration */
697 RESERVED(2[0x2], uint32_t)
698 __IOM uint32_t INTERRUPT_MASK; /*!< \brief Offset: 0x0214 (R/W) Interrupt Mask */
699 __IM uint32_t MASKED_INT_STATUS; /*!< \brief Offset: 0x0218 (R/ ) Masked Interrupt Status */
700 __IM uint32_t RAW_INT_STATUS; /*!< \brief Offset: 0x021c (R/ ) Raw Interrupt Status */
701 __OM uint32_t INTERRUPT_CLEAR; /*!< \brief Offset: 0x0220 ( /W) Interrupt Clear */
702 RESERVED(3[0x143], uint32_t)
703 __IOM uint32_t CACHE_SYNC; /*!< \brief Offset: 0x0730 (R/W) Cache Sync */
704 RESERVED(4[0xf], uint32_t)
705 __IOM uint32_t INV_LINE_PA; /*!< \brief Offset: 0x0770 (R/W) Invalidate Line By PA */
706 RESERVED(6[2], uint32_t)
707 __IOM uint32_t INV_WAY; /*!< \brief Offset: 0x077c (R/W) Invalidate by Way */
708 RESERVED(5[0xc], uint32_t)
709 __IOM uint32_t CLEAN_LINE_PA; /*!< \brief Offset: 0x07b0 (R/W) Clean Line by PA */
710 RESERVED(7[1], uint32_t)
711 __IOM uint32_t CLEAN_LINE_INDEX_WAY; /*!< \brief Offset: 0x07b8 (R/W) Clean Line by Index/Way */
712 __IOM uint32_t CLEAN_WAY; /*!< \brief Offset: 0x07bc (R/W) Clean by Way */
713 RESERVED(8[0xc], uint32_t)
714 __IOM uint32_t CLEAN_INV_LINE_PA; /*!< \brief Offset: 0x07f0 (R/W) Clean and Invalidate Line by PA */
715 RESERVED(9[1], uint32_t)
716 __IOM uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< \brief Offset: 0x07f8 (R/W) Clean and Invalidate Line by Index/Way */
717 __IOM uint32_t CLEAN_INV_WAY; /*!< \brief Offset: 0x07fc (R/W) Clean and Invalidate by Way */
718 RESERVED(10[0x40], uint32_t)
719 __IOM uint32_t DATA_LOCK_0_WAY; /*!< \brief Offset: 0x0900 (R/W) Data Lockdown 0 by Way */
720 __IOM uint32_t INST_LOCK_0_WAY; /*!< \brief Offset: 0x0904 (R/W) Instruction Lockdown 0 by Way */
721 __IOM uint32_t DATA_LOCK_1_WAY; /*!< \brief Offset: 0x0908 (R/W) Data Lockdown 1 by Way */
722 __IOM uint32_t INST_LOCK_1_WAY; /*!< \brief Offset: 0x090c (R/W) Instruction Lockdown 1 by Way */
723 __IOM uint32_t DATA_LOCK_2_WAY; /*!< \brief Offset: 0x0910 (R/W) Data Lockdown 2 by Way */
724 __IOM uint32_t INST_LOCK_2_WAY; /*!< \brief Offset: 0x0914 (R/W) Instruction Lockdown 2 by Way */
725 __IOM uint32_t DATA_LOCK_3_WAY; /*!< \brief Offset: 0x0918 (R/W) Data Lockdown 3 by Way */
726 __IOM uint32_t INST_LOCK_3_WAY; /*!< \brief Offset: 0x091c (R/W) Instruction Lockdown 3 by Way */
727 __IOM uint32_t DATA_LOCK_4_WAY; /*!< \brief Offset: 0x0920 (R/W) Data Lockdown 4 by Way */
728 __IOM uint32_t INST_LOCK_4_WAY; /*!< \brief Offset: 0x0924 (R/W) Instruction Lockdown 4 by Way */
729 __IOM uint32_t DATA_LOCK_5_WAY; /*!< \brief Offset: 0x0928 (R/W) Data Lockdown 5 by Way */
730 __IOM uint32_t INST_LOCK_5_WAY; /*!< \brief Offset: 0x092c (R/W) Instruction Lockdown 5 by Way */
731 __IOM uint32_t DATA_LOCK_6_WAY; /*!< \brief Offset: 0x0930 (R/W) Data Lockdown 5 by Way */
732 __IOM uint32_t INST_LOCK_6_WAY; /*!< \brief Offset: 0x0934 (R/W) Instruction Lockdown 5 by Way */
733 __IOM uint32_t DATA_LOCK_7_WAY; /*!< \brief Offset: 0x0938 (R/W) Data Lockdown 6 by Way */
734 __IOM uint32_t INST_LOCK_7_WAY; /*!< \brief Offset: 0x093c (R/W) Instruction Lockdown 6 by Way */
735 RESERVED(11[0x4], uint32_t)
736 __IOM uint32_t LOCK_LINE_EN; /*!< \brief Offset: 0x0950 (R/W) Lockdown by Line Enable */
737 __IOM uint32_t UNLOCK_ALL_BY_WAY; /*!< \brief Offset: 0x0954 (R/W) Unlock All Lines by Way */
738 RESERVED(12[0xaa], uint32_t)
739 __IOM uint32_t ADDRESS_FILTER_START; /*!< \brief Offset: 0x0c00 (R/W) Address Filtering Start */
740 __IOM uint32_t ADDRESS_FILTER_END; /*!< \brief Offset: 0x0c04 (R/W) Address Filtering End */
741 RESERVED(13[0xce], uint32_t)
742 __IOM uint32_t DEBUG_CONTROL; /*!< \brief Offset: 0x0f40 (R/W) Debug Control Register */
745 #define L2C_310 ((L2C_310_TypeDef *)L2C_310_BASE) /*!< \brief L2C_310 register set access pointer */
748 #if (defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U)) || \
751 /** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD)
755 __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) Distributor Control Register */
756 __IM uint32_t TYPER; /*!< \brief Offset: 0x004 (R/ ) Interrupt Controller Type Register */
757 __IM uint32_t IIDR; /*!< \brief Offset: 0x008 (R/ ) Distributor Implementer Identification Register */
758 RESERVED(0, uint32_t)
759 __IOM uint32_t STATUSR; /*!< \brief Offset: 0x010 (R/W) Error Reporting Status Register, optional */
760 RESERVED(1[11], uint32_t)
761 __OM uint32_t SETSPI_NSR; /*!< \brief Offset: 0x040 ( /W) Set SPI Register */
762 RESERVED(2, uint32_t)
763 __OM uint32_t CLRSPI_NSR; /*!< \brief Offset: 0x048 ( /W) Clear SPI Register */
764 RESERVED(3, uint32_t)
765 __OM uint32_t SETSPI_SR; /*!< \brief Offset: 0x050 ( /W) Set SPI, Secure Register */
766 RESERVED(4, uint32_t)
767 __OM uint32_t CLRSPI_SR; /*!< \brief Offset: 0x058 ( /W) Clear SPI, Secure Register */
768 RESERVED(5[9], uint32_t)
769 __IOM uint32_t IGROUPR[32]; /*!< \brief Offset: 0x080 (R/W) Interrupt Group Registers */
770 __IOM uint32_t ISENABLER[32]; /*!< \brief Offset: 0x100 (R/W) Interrupt Set-Enable Registers */
771 __IOM uint32_t ICENABLER[32]; /*!< \brief Offset: 0x180 (R/W) Interrupt Clear-Enable Registers */
772 __IOM uint32_t ISPENDR[32]; /*!< \brief Offset: 0x200 (R/W) Interrupt Set-Pending Registers */
773 __IOM uint32_t ICPENDR[32]; /*!< \brief Offset: 0x280 (R/W) Interrupt Clear-Pending Registers */
774 __IOM uint32_t ISACTIVER[32]; /*!< \brief Offset: 0x300 (R/W) Interrupt Set-Active Registers */
775 __IOM uint32_t ICACTIVER[32]; /*!< \brief Offset: 0x380 (R/W) Interrupt Clear-Active Registers */
776 __IOM uint32_t IPRIORITYR[255]; /*!< \brief Offset: 0x400 (R/W) Interrupt Priority Registers */
777 RESERVED(6, uint32_t)
778 __IOM uint32_t ITARGETSR[255]; /*!< \brief Offset: 0x800 (R/W) Interrupt Targets Registers */
779 RESERVED(7, uint32_t)
780 __IOM uint32_t ICFGR[64]; /*!< \brief Offset: 0xC00 (R/W) Interrupt Configuration Registers */
781 __IOM uint32_t IGRPMODR[32]; /*!< \brief Offset: 0xD00 (R/W) Interrupt Group Modifier Registers */
782 RESERVED(8[32], uint32_t)
783 __IOM uint32_t NSACR[64]; /*!< \brief Offset: 0xE00 (R/W) Non-secure Access Control Registers */
784 __OM uint32_t SGIR; /*!< \brief Offset: 0xF00 ( /W) Software Generated Interrupt Register */
785 RESERVED(9[3], uint32_t)
786 __IOM uint32_t CPENDSGIR[4]; /*!< \brief Offset: 0xF10 (R/W) SGI Clear-Pending Registers */
787 __IOM uint32_t SPENDSGIR[4]; /*!< \brief Offset: 0xF20 (R/W) SGI Set-Pending Registers */
788 RESERVED(10[5236], uint32_t)
789 __IOM uint64_t IROUTER[988]; /*!< \brief Offset: 0x6100(R/W) Interrupt Routing Registers */
790 } GICDistributor_Type;
792 #define GICDistributor ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE ) /*!< \brief GIC Distributor register set access pointer */
794 /* GICDistributor CTLR Register */
795 #define GICDistributor_CTLR_EnableGrp0_Pos 0U /*!< GICDistributor CTLR: EnableGrp0 Position */
796 #define GICDistributor_CTLR_EnableGrp0_Msk (0x1U /*<< GICDistributor_CTLR_EnableGrp0_Pos*/) /*!< GICDistributor CTLR: EnableGrp0 Mask */
797 #define GICDistributor_CTLR_EnableGrp0(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_CTLR_EnableGrp0_Pos*/)) & GICDistributor_CTLR_EnableGrp0_Msk)
799 #define GICDistributor_CTLR_EnableGrp1_Pos 1U /*!< GICDistributor CTLR: EnableGrp1 Position */
800 #define GICDistributor_CTLR_EnableGrp1_Msk (0x1U << GICDistributor_CTLR_EnableGrp1_Pos) /*!< GICDistributor CTLR: EnableGrp1 Mask */
801 #define GICDistributor_CTLR_EnableGrp1(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_EnableGrp1_Pos)) & GICDistributor_CTLR_EnableGrp1_Msk)
803 #define GICDistributor_CTLR_ARE_Pos 4U /*!< GICDistributor CTLR: ARE Position */
804 #define GICDistributor_CTLR_ARE_Msk (0x1U << GICDistributor_CTLR_ARE_Pos) /*!< GICDistributor CTLR: ARE Mask */
805 #define GICDistributor_CTLR_ARE(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_ARE_Pos)) & GICDistributor_CTLR_ARE_Msk)
807 #define GICDistributor_CTLR_DC_Pos 6U /*!< GICDistributor CTLR: DC Position */
808 #define GICDistributor_CTLR_DC_Msk (0x1U << GICDistributor_CTLR_DC_Pos) /*!< GICDistributor CTLR: DC Mask */
809 #define GICDistributor_CTLR_DC(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_DC_Pos)) & GICDistributor_CTLR_DC_Msk)
811 #define GICDistributor_CTLR_EINWF_Pos 7U /*!< GICDistributor CTLR: EINWF Position */
812 #define GICDistributor_CTLR_EINWF_Msk (0x1U << GICDistributor_CTLR_EINWF_Pos) /*!< GICDistributor CTLR: EINWF Mask */
813 #define GICDistributor_CTLR_EINWF(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_EINWF_Pos)) & GICDistributor_CTLR_EINWF_Msk)
815 #define GICDistributor_CTLR_RWP_Pos 31U /*!< GICDistributor CTLR: RWP Position */
816 #define GICDistributor_CTLR_RWP_Msk (0x1U << GICDistributor_CTLR_RWP_Pos) /*!< GICDistributor CTLR: RWP Mask */
817 #define GICDistributor_CTLR_RWP(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_RWP_Pos)) & GICDistributor_CTLR_RWP_Msk)
819 /* GICDistributor TYPER Register */
820 #define GICDistributor_TYPER_ITLinesNumber_Pos 0U /*!< GICDistributor TYPER: ITLinesNumber Position */
821 #define GICDistributor_TYPER_ITLinesNumber_Msk (0x1FU /*<< GICDistributor_TYPER_ITLinesNumber_Pos*/) /*!< GICDistributor TYPER: ITLinesNumber Mask */
822 #define GICDistributor_TYPER_ITLinesNumber(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_TYPER_ITLinesNumber_Pos*/)) & GICDistributor_CTLR_ITLinesNumber_Msk)
824 #define GICDistributor_TYPER_CPUNumber_Pos 5U /*!< GICDistributor TYPER: CPUNumber Position */
825 #define GICDistributor_TYPER_CPUNumber_Msk (0x7U << GICDistributor_TYPER_CPUNumber_Pos) /*!< GICDistributor TYPER: CPUNumber Mask */
826 #define GICDistributor_TYPER_CPUNumber(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_TYPER_CPUNumber_Pos)) & GICDistributor_TYPER_CPUNumber_Msk)
828 #define GICDistributor_TYPER_SecurityExtn_Pos 10U /*!< GICDistributor TYPER: SecurityExtn Position */
829 #define GICDistributor_TYPER_SecurityExtn_Msk (0x1U << GICDistributor_TYPER_SecurityExtn_Pos) /*!< GICDistributor TYPER: SecurityExtn Mask */
830 #define GICDistributor_TYPER_SecurityExtn(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_TYPER_SecurityExtn_Pos)) & GICDistributor_TYPER_SecurityExtn_Msk)
832 #define GICDistributor_TYPER_LSPI_Pos 11U /*!< GICDistributor TYPER: LSPI Position */
833 #define GICDistributor_TYPER_LSPI_Msk (0x1FU << GICDistributor_TYPER_LSPI_Pos) /*!< GICDistributor TYPER: LSPI Mask */
834 #define GICDistributor_TYPER_LSPI(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_TYPER_LSPI_Pos)) & GICDistributor_TYPER_LSPI_Msk)
836 /* GICDistributor IIDR Register */
837 #define GICDistributor_IIDR_Implementer_Pos 0U /*!< GICDistributor IIDR: Implementer Position */
838 #define GICDistributor_IIDR_Implementer_Msk (0xFFFU /*<< GICDistributor_IIDR_Implementer_Pos*/) /*!< GICDistributor IIDR: Implementer Mask */
839 #define GICDistributor_IIDR_Implementer(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_IIDR_Implementer_Pos*/)) & GICDistributor_IIDR_Implementer_Msk)
841 #define GICDistributor_IIDR_Revision_Pos 12U /*!< GICDistributor IIDR: Revision Position */
842 #define GICDistributor_IIDR_Revision_Msk (0xFU << GICDistributor_IIDR_Revision_Pos) /*!< GICDistributor IIDR: Revision Mask */
843 #define GICDistributor_IIDR_Revision(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_IIDR_Revision_Pos)) & GICDistributor_IIDR_Revision_Msk)
845 #define GICDistributor_IIDR_Variant_Pos 16U /*!< GICDistributor IIDR: Variant Position */
846 #define GICDistributor_IIDR_Variant_Msk (0xFU << GICDistributor_IIDR_Variant_Pos) /*!< GICDistributor IIDR: Variant Mask */
847 #define GICDistributor_IIDR_Variant(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_IIDR_Variant_Pos)) & GICDistributor_IIDR_Variant_Msk)
849 #define GICDistributor_IIDR_ProductID_Pos 24U /*!< GICDistributor IIDR: ProductID Position */
850 #define GICDistributor_IIDR_ProductID_Msk (0xFFU << GICDistributor_IIDR_ProductID_Pos) /*!< GICDistributor IIDR: ProductID Mask */
851 #define GICDistributor_IIDR_ProductID(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_IIDR_ProductID_Pos)) & GICDistributor_IIDR_ProductID_Msk)
853 /* GICDistributor STATUSR Register */
854 #define GICDistributor_STATUSR_RRD_Pos 0U /*!< GICDistributor STATUSR: RRD Position */
855 #define GICDistributor_STATUSR_RRD_Msk (0x1U /*<< GICDistributor_STATUSR_RRD_Pos*/) /*!< GICDistributor STATUSR: RRD Mask */
856 #define GICDistributor_STATUSR_RRD(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_STATUSR_RRD_Pos*/)) & GICDistributor_STATUSR_RRD_Msk)
858 #define GICDistributor_STATUSR_WRD_Pos 1U /*!< GICDistributor STATUSR: WRD Position */
859 #define GICDistributor_STATUSR_WRD_Msk (0x1U << GICDistributor_STATUSR_WRD_Pos) /*!< GICDistributor STATUSR: WRD Mask */
860 #define GICDistributor_STATUSR_WRD(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_STATUSR_WRD_Pos)) & GICDistributor_STATUSR_WRD_Msk)
862 #define GICDistributor_STATUSR_RWOD_Pos 2U /*!< GICDistributor STATUSR: RWOD Position */
863 #define GICDistributor_STATUSR_RWOD_Msk (0x1U << GICDistributor_STATUSR_RWOD_Pos) /*!< GICDistributor STATUSR: RWOD Mask */
864 #define GICDistributor_STATUSR_RWOD(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_STATUSR_RWOD_Pos)) & GICDistributor_STATUSR_RWOD_Msk)
866 #define GICDistributor_STATUSR_WROD_Pos 3U /*!< GICDistributor STATUSR: WROD Position */
867 #define GICDistributor_STATUSR_WROD_Msk (0x1U << GICDistributor_STATUSR_WROD_Pos) /*!< GICDistributor STATUSR: WROD Mask */
868 #define GICDistributor_STATUSR_WROD(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_STATUSR_WROD_Pos)) & GICDistributor_STATUSR_WROD_Msk)
870 /* GICDistributor SETSPI_NSR Register */
871 #define GICDistributor_SETSPI_NSR_INTID_Pos 0U /*!< GICDistributor SETSPI_NSR: INTID Position */
872 #define GICDistributor_SETSPI_NSR_INTID_Msk (0x3FFU /*<< GICDistributor_SETSPI_NSR_INTID_Pos*/) /*!< GICDistributor SETSPI_NSR: INTID Mask */
873 #define GICDistributor_SETSPI_NSR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_SETSPI_NSR_INTID_Pos*/)) & GICDistributor_SETSPI_NSR_INTID_Msk)
875 /* GICDistributor CLRSPI_NSR Register */
876 #define GICDistributor_CLRSPI_NSR_INTID_Pos 0U /*!< GICDistributor CLRSPI_NSR: INTID Position */
877 #define GICDistributor_CLRSPI_NSR_INTID_Msk (0x3FFU /*<< GICDistributor_CLRSPI_NSR_INTID_Pos*/) /*!< GICDistributor CLRSPI_NSR: INTID Mask */
878 #define GICDistributor_CLRSPI_NSR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_CLRSPI_NSR_INTID_Pos*/)) & GICDistributor_CLRSPI_NSR_INTID_Msk)
880 /* GICDistributor SETSPI_SR Register */
881 #define GICDistributor_SETSPI_SR_INTID_Pos 0U /*!< GICDistributor SETSPI_SR: INTID Position */
882 #define GICDistributor_SETSPI_SR_INTID_Msk (0x3FFU /*<< GICDistributor_SETSPI_SR_INTID_Pos*/) /*!< GICDistributor SETSPI_SR: INTID Mask */
883 #define GICDistributor_SETSPI_SR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_SETSPI_SR_INTID_Pos*/)) & GICDistributor_SETSPI_SR_INTID_Msk)
885 /* GICDistributor CLRSPI_SR Register */
886 #define GICDistributor_CLRSPI_SR_INTID_Pos 0U /*!< GICDistributor CLRSPI_SR: INTID Position */
887 #define GICDistributor_CLRSPI_SR_INTID_Msk (0x3FFU /*<< GICDistributor_CLRSPI_SR_INTID_Pos*/) /*!< GICDistributor CLRSPI_SR: INTID Mask */
888 #define GICDistributor_CLRSPI_SR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_CLRSPI_SR_INTID_Pos*/)) & GICDistributor_CLRSPI_SR_INTID_Msk)
890 /* GICDistributor ITARGETSR Register */
891 #define GICDistributor_ITARGETSR_CPU0_Pos 0U /*!< GICDistributor ITARGETSR: CPU0 Position */
892 #define GICDistributor_ITARGETSR_CPU0_Msk (0x1U /*<< GICDistributor_ITARGETSR_CPU0_Pos*/) /*!< GICDistributor ITARGETSR: CPU0 Mask */
893 #define GICDistributor_ITARGETSR_CPU0(x) (((uint8_t)(((uint8_t)(x)) /*<< GICDistributor_ITARGETSR_CPU0_Pos*/)) & GICDistributor_ITARGETSR_CPU0_Msk)
895 #define GICDistributor_ITARGETSR_CPU1_Pos 1U /*!< GICDistributor ITARGETSR: CPU1 Position */
896 #define GICDistributor_ITARGETSR_CPU1_Msk (0x1U << GICDistributor_ITARGETSR_CPU1_Pos) /*!< GICDistributor ITARGETSR: CPU1 Mask */
897 #define GICDistributor_ITARGETSR_CPU1(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU1_Pos)) & GICDistributor_ITARGETSR_CPU1_Msk)
899 #define GICDistributor_ITARGETSR_CPU2_Pos 2U /*!< GICDistributor ITARGETSR: CPU2 Position */
900 #define GICDistributor_ITARGETSR_CPU2_Msk (0x1U << GICDistributor_ITARGETSR_CPU2_Pos) /*!< GICDistributor ITARGETSR: CPU2 Mask */
901 #define GICDistributor_ITARGETSR_CPU2(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU2_Pos)) & GICDistributor_ITARGETSR_CPU2_Msk)
903 #define GICDistributor_ITARGETSR_CPU3_Pos 3U /*!< GICDistributor ITARGETSR: CPU3 Position */
904 #define GICDistributor_ITARGETSR_CPU3_Msk (0x1U << GICDistributor_ITARGETSR_CPU3_Pos) /*!< GICDistributor ITARGETSR: CPU3 Mask */
905 #define GICDistributor_ITARGETSR_CPU3(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU3_Pos)) & GICDistributor_ITARGETSR_CPU3_Msk)
907 #define GICDistributor_ITARGETSR_CPU4_Pos 4U /*!< GICDistributor ITARGETSR: CPU4 Position */
908 #define GICDistributor_ITARGETSR_CPU4_Msk (0x1U << GICDistributor_ITARGETSR_CPU4_Pos) /*!< GICDistributor ITARGETSR: CPU4 Mask */
909 #define GICDistributor_ITARGETSR_CPU4(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU4_Pos)) & GICDistributor_ITARGETSR_CPU4_Msk)
911 #define GICDistributor_ITARGETSR_CPU5_Pos 5U /*!< GICDistributor ITARGETSR: CPU5 Position */
912 #define GICDistributor_ITARGETSR_CPU5_Msk (0x1U << GICDistributor_ITARGETSR_CPU5_Pos) /*!< GICDistributor ITARGETSR: CPU5 Mask */
913 #define GICDistributor_ITARGETSR_CPU5(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU5_Pos)) & GICDistributor_ITARGETSR_CPU5_Msk)
915 #define GICDistributor_ITARGETSR_CPU6_Pos 6U /*!< GICDistributor ITARGETSR: CPU6 Position */
916 #define GICDistributor_ITARGETSR_CPU6_Msk (0x1U << GICDistributor_ITARGETSR_CPU6_Pos) /*!< GICDistributor ITARGETSR: CPU6 Mask */
917 #define GICDistributor_ITARGETSR_CPU6(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU6_Pos)) & GICDistributor_ITARGETSR_CPU6_Msk)
919 #define GICDistributor_ITARGETSR_CPU7_Pos 7U /*!< GICDistributor ITARGETSR: CPU7 Position */
920 #define GICDistributor_ITARGETSR_CPU7_Msk (0x1U << GICDistributor_ITARGETSR_CPU7_Pos) /*!< GICDistributor ITARGETSR: CPU7 Mask */
921 #define GICDistributor_ITARGETSR_CPU7(x) (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU7_Pos)) & GICDistributor_ITARGETSR_CPU7_Msk)
923 /* GICDistributor SGIR Register */
924 #define GICDistributor_SGIR_INTID_Pos 0U /*!< GICDistributor SGIR: INTID Position */
925 #define GICDistributor_SGIR_INTID_Msk (0x7U /*<< GICDistributor_SGIR_INTID_Pos*/) /*!< GICDistributor SGIR: INTID Mask */
926 #define GICDistributor_SGIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_SGIR_INTID_Pos*/)) & GICDistributor_SGIR_INTID_Msk)
928 #define GICDistributor_SGIR_NSATT_Pos 15U /*!< GICDistributor SGIR: NSATT Position */
929 #define GICDistributor_SGIR_NSATT_Msk (0x1U << GICDistributor_SGIR_NSATT_Pos) /*!< GICDistributor SGIR: NSATT Mask */
930 #define GICDistributor_SGIR_NSATT(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_SGIR_NSATT_Pos)) & GICDistributor_SGIR_NSATT_Msk)
932 #define GICDistributor_SGIR_CPUTargetList_Pos 16U /*!< GICDistributor SGIR: CPUTargetList Position */
933 #define GICDistributor_SGIR_CPUTargetList_Msk (0xFFU << GICDistributor_SGIR_CPUTargetList_Pos) /*!< GICDistributor SGIR: CPUTargetList Mask */
934 #define GICDistributor_SGIR_CPUTargetList(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_SGIR_CPUTargetList_Pos)) & GICDistributor_SGIR_CPUTargetList_Msk)
936 #define GICDistributor_SGIR_TargetFilterList_Pos 24U /*!< GICDistributor SGIR: TargetFilterList Position */
937 #define GICDistributor_SGIR_TargetFilterList_Msk (0x3U << GICDistributor_SGIR_TargetFilterList_Pos) /*!< GICDistributor SGIR: TargetFilterList Mask */
938 #define GICDistributor_SGIR_TargetFilterList(x) (((uint32_t)(((uint32_t)(x)) << GICDistributor_SGIR_TargetFilterList_Pos)) & GICDistributor_SGIR_TargetFilterList_Msk)
940 /* GICDistributor IROUTER Register */
941 #define GICDistributor_IROUTER_Aff0_Pos 0UL /*!< GICDistributor IROUTER: Aff0 Position */
942 #define GICDistributor_IROUTER_Aff0_Msk (0xFFUL /*<< GICDistributor_IROUTER_Aff0_Pos*/) /*!< GICDistributor IROUTER: Aff0 Mask */
943 #define GICDistributor_IROUTER_Aff0(x) (((uint64_t)(((uint64_t)(x)) /*<< GICDistributor_IROUTER_Aff0_Pos*/)) & GICDistributor_IROUTER_Aff0_Msk)
945 #define GICDistributor_IROUTER_Aff1_Pos 8UL /*!< GICDistributor IROUTER: Aff1 Position */
946 #define GICDistributor_IROUTER_Aff1_Msk (0xFFUL << GICDistributor_IROUTER_Aff1_Pos) /*!< GICDistributor IROUTER: Aff1 Mask */
947 #define GICDistributor_IROUTER_Aff1(x) (((uint64_t)(((uint64_t)(x)) << GICDistributor_IROUTER_Aff1_Pos)) & GICDistributor_IROUTER_Aff1_Msk)
949 #define GICDistributor_IROUTER_Aff2_Pos 16UL /*!< GICDistributor IROUTER: Aff2 Position */
950 #define GICDistributor_IROUTER_Aff2_Msk (0xFFUL << GICDistributor_IROUTER_Aff2_Pos) /*!< GICDistributor IROUTER: Aff2 Mask */
951 #define GICDistributor_IROUTER_Aff2(x) (((uint64_t)(((uint64_t)(x)) << GICDistributor_IROUTER_Aff2_Pos)) & GICDistributor_IROUTER_Aff2_Msk)
953 #define GICDistributor_IROUTER_IRM_Pos 31UL /*!< GICDistributor IROUTER: IRM Position */
954 #define GICDistributor_IROUTER_IRM_Msk (0xFFUL << GICDistributor_IROUTER_IRM_Pos) /*!< GICDistributor IROUTER: IRM Mask */
955 #define GICDistributor_IROUTER_IRM(x) (((uint64_t)(((uint64_t)(x)) << GICDistributor_IROUTER_IRM_Pos)) & GICDistributor_IROUTER_IRM_Msk)
957 #define GICDistributor_IROUTER_Aff3_Pos 32UL /*!< GICDistributor IROUTER: Aff3 Position */
958 #define GICDistributor_IROUTER_Aff3_Msk (0xFFUL << GICDistributor_IROUTER_Aff3_Pos) /*!< GICDistributor IROUTER: Aff3 Mask */
959 #define GICDistributor_IROUTER_Aff3(x) (((uint64_t)(((uint64_t)(x)) << GICDistributor_IROUTER_Aff3_Pos)) & GICDistributor_IROUTER_Aff3_Msk)
963 /** \brief Structure type to access the Generic Interrupt Controller Interface (GICC)
967 __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) CPU Interface Control Register */
968 __IOM uint32_t PMR; /*!< \brief Offset: 0x004 (R/W) Interrupt Priority Mask Register */
969 __IOM uint32_t BPR; /*!< \brief Offset: 0x008 (R/W) Binary Point Register */
970 __IM uint32_t IAR; /*!< \brief Offset: 0x00C (R/ ) Interrupt Acknowledge Register */
971 __OM uint32_t EOIR; /*!< \brief Offset: 0x010 ( /W) End Of Interrupt Register */
972 __IM uint32_t RPR; /*!< \brief Offset: 0x014 (R/ ) Running Priority Register */
973 __IM uint32_t HPPIR; /*!< \brief Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register */
974 __IOM uint32_t ABPR; /*!< \brief Offset: 0x01C (R/W) Aliased Binary Point Register */
975 __IM uint32_t AIAR; /*!< \brief Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register */
976 __OM uint32_t AEOIR; /*!< \brief Offset: 0x024 ( /W) Aliased End Of Interrupt Register */
977 __IM uint32_t AHPPIR; /*!< \brief Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register */
978 __IOM uint32_t STATUSR; /*!< \brief Offset: 0x02C (R/W) Error Reporting Status Register, optional */
979 RESERVED(1[40], uint32_t)
980 __IOM uint32_t APR[4]; /*!< \brief Offset: 0x0D0 (R/W) Active Priority Register */
981 __IOM uint32_t NSAPR[4]; /*!< \brief Offset: 0x0E0 (R/W) Non-secure Active Priority Register */
982 RESERVED(2[3], uint32_t)
983 __IM uint32_t IIDR; /*!< \brief Offset: 0x0FC (R/ ) CPU Interface Identification Register */
984 RESERVED(3[960], uint32_t)
985 __OM uint32_t DIR; /*!< \brief Offset: 0x1000( /W) Deactivate Interrupt Register */
988 #define GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE ) /*!< \brief GIC Interface register set access pointer */
990 /* GICInterface CTLR Register */
991 #define GICInterface_CTLR_Enable_Pos 0U /*!< PTIM CTLR: Enable Position */
992 #define GICInterface_CTLR_Enable_Msk (0x1U /*<< GICInterface_CTLR_Enable_Pos*/) /*!< PTIM CTLR: Enable Mask */
993 #define GICInterface_CTLR_Enable(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_CTLR_Enable_Pos*/)) & GICInterface_CTLR_Enable_Msk)
995 /* GICInterface PMR Register */
996 #define GICInterface_PMR_Priority_Pos 0U /*!< PTIM PMR: Priority Position */
997 #define GICInterface_PMR_Priority_Msk (0xFFU /*<< GICInterface_PMR_Priority_Pos*/) /*!< PTIM PMR: Priority Mask */
998 #define GICInterface_PMR_Priority(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_PMR_Priority_Pos*/)) & GICInterface_PMR_Priority_Msk)
1000 /* GICInterface BPR Register */
1001 #define GICInterface_BPR_Binary_Point_Pos 0U /*!< PTIM BPR: Binary_Point Position */
1002 #define GICInterface_BPR_Binary_Point_Msk (0x7U /*<< GICInterface_BPR_Binary_Point_Pos*/) /*!< PTIM BPR: Binary_Point Mask */
1003 #define GICInterface_BPR_Binary_Point(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_BPR_Binary_Point_Pos*/)) & GICInterface_BPR_Binary_Point_Msk)
1005 /* GICInterface IAR Register */
1006 #define GICInterface_IAR_INTID_Pos 0U /*!< PTIM IAR: INTID Position */
1007 #define GICInterface_IAR_INTID_Msk (0xFFFFFFU /*<< GICInterface_IAR_INTID_Pos*/) /*!< PTIM IAR: INTID Mask */
1008 #define GICInterface_IAR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_IAR_INTID_Pos*/)) & GICInterface_IAR_INTID_Msk)
1010 /* GICInterface EOIR Register */
1011 #define GICInterface_EOIR_INTID_Pos 0U /*!< PTIM EOIR: INTID Position */
1012 #define GICInterface_EOIR_INTID_Msk (0xFFFFFFU /*<< GICInterface_EOIR_INTID_Pos*/) /*!< PTIM EOIR: INTID Mask */
1013 #define GICInterface_EOIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_EOIR_INTID_Pos*/)) & GICInterface_EOIR_INTID_Msk)
1015 /* GICInterface RPR Register */
1016 #define GICInterface_RPR_INTID_Pos 0U /*!< PTIM RPR: INTID Position */
1017 #define GICInterface_RPR_INTID_Msk (0xFFU /*<< GICInterface_RPR_INTID_Pos*/) /*!< PTIM RPR: INTID Mask */
1018 #define GICInterface_RPR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_RPR_INTID_Pos*/)) & GICInterface_RPR_INTID_Msk)
1020 /* GICInterface HPPIR Register */
1021 #define GICInterface_HPPIR_INTID_Pos 0U /*!< PTIM HPPIR: INTID Position */
1022 #define GICInterface_HPPIR_INTID_Msk (0xFFFFFFU /*<< GICInterface_HPPIR_INTID_Pos*/) /*!< PTIM HPPIR: INTID Mask */
1023 #define GICInterface_HPPIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_HPPIR_INTID_Pos*/)) & GICInterface_HPPIR_INTID_Msk)
1025 /* GICInterface ABPR Register */
1026 #define GICInterface_ABPR_Binary_Point_Pos 0U /*!< PTIM ABPR: Binary_Point Position */
1027 #define GICInterface_ABPR_Binary_Point_Msk (0x7U /*<< GICInterface_ABPR_Binary_Point_Pos*/) /*!< PTIM ABPR: Binary_Point Mask */
1028 #define GICInterface_ABPR_Binary_Point(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_ABPR_Binary_Point_Pos*/)) & GICInterface_ABPR_Binary_Point_Msk)
1030 /* GICInterface AIAR Register */
1031 #define GICInterface_AIAR_INTID_Pos 0U /*!< PTIM AIAR: INTID Position */
1032 #define GICInterface_AIAR_INTID_Msk (0xFFFFFFU /*<< GICInterface_AIAR_INTID_Pos*/) /*!< PTIM AIAR: INTID Mask */
1033 #define GICInterface_AIAR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_AIAR_INTID_Pos*/)) & GICInterface_AIAR_INTID_Msk)
1035 /* GICInterface AEOIR Register */
1036 #define GICInterface_AEOIR_INTID_Pos 0U /*!< PTIM AEOIR: INTID Position */
1037 #define GICInterface_AEOIR_INTID_Msk (0xFFFFFFU /*<< GICInterface_AEOIR_INTID_Pos*/) /*!< PTIM AEOIR: INTID Mask */
1038 #define GICInterface_AEOIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_AEOIR_INTID_Pos*/)) & GICInterface_AEOIR_INTID_Msk)
1040 /* GICInterface AHPPIR Register */
1041 #define GICInterface_AHPPIR_INTID_Pos 0U /*!< PTIM AHPPIR: INTID Position */
1042 #define GICInterface_AHPPIR_INTID_Msk (0xFFFFFFU /*<< GICInterface_AHPPIR_INTID_Pos*/) /*!< PTIM AHPPIR: INTID Mask */
1043 #define GICInterface_AHPPIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_AHPPIR_INTID_Pos*/)) & GICInterface_AHPPIR_INTID_Msk)
1045 /* GICInterface STATUSR Register */
1046 #define GICInterface_STATUSR_RRD_Pos 0U /*!< GICInterface STATUSR: RRD Position */
1047 #define GICInterface_STATUSR_RRD_Msk (0x1U /*<< GICInterface_STATUSR_RRD_Pos*/) /*!< GICInterface STATUSR: RRD Mask */
1048 #define GICInterface_STATUSR_RRD(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_STATUSR_RRD_Pos*/)) & GICInterface_STATUSR_RRD_Msk)
1050 #define GICInterface_STATUSR_WRD_Pos 1U /*!< GICInterface STATUSR: WRD Position */
1051 #define GICInterface_STATUSR_WRD_Msk (0x1U << GICInterface_STATUSR_WRD_Pos) /*!< GICInterface STATUSR: WRD Mask */
1052 #define GICInterface_STATUSR_WRD(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_STATUSR_WRD_Pos)) & GICInterface_STATUSR_WRD_Msk)
1054 #define GICInterface_STATUSR_RWOD_Pos 2U /*!< GICInterface STATUSR: RWOD Position */
1055 #define GICInterface_STATUSR_RWOD_Msk (0x1U << GICInterface_STATUSR_RWOD_Pos) /*!< GICInterface STATUSR: RWOD Mask */
1056 #define GICInterface_STATUSR_RWOD(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_STATUSR_RWOD_Pos)) & GICInterface_STATUSR_RWOD_Msk)
1058 #define GICInterface_STATUSR_WROD_Pos 3U /*!< GICInterface STATUSR: WROD Position */
1059 #define GICInterface_STATUSR_WROD_Msk (0x1U << GICInterface_STATUSR_WROD_Pos) /*!< GICInterface STATUSR: WROD Mask */
1060 #define GICInterface_STATUSR_WROD(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_STATUSR_WROD_Pos)) & GICInterface_STATUSR_WROD_Msk)
1062 #define GICInterface_STATUSR_ASV_Pos 4U /*!< GICInterface STATUSR: ASV Position */
1063 #define GICInterface_STATUSR_ASV_Msk (0x1U << GICInterface_STATUSR_ASV_Pos) /*!< GICInterface STATUSR: ASV Mask */
1064 #define GICInterface_STATUSR_ASV(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_STATUSR_ASV_Pos)) & GICInterface_STATUSR_ASV_Msk)
1066 /* GICInterface IIDR Register */
1067 #define GICInterface_IIDR_Implementer_Pos 0U /*!< GICInterface IIDR: Implementer Position */
1068 #define GICInterface_IIDR_Implementer_Msk (0xFFFU /*<< GICInterface_IIDR_Implementer_Pos*/) /*!< GICInterface IIDR: Implementer Mask */
1069 #define GICInterface_IIDR_Implementer(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_IIDR_Implementer_Pos*/)) & GICInterface_IIDR_Implementer_Msk)
1071 #define GICInterface_IIDR_Revision_Pos 12U /*!< GICInterface IIDR: Revision Position */
1072 #define GICInterface_IIDR_Revision_Msk (0xFU << GICInterface_IIDR_Revision_Pos) /*!< GICInterface IIDR: Revision Mask */
1073 #define GICInterface_IIDR_Revision(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_IIDR_Revision_Pos)) & GICInterface_IIDR_Revision_Msk)
1075 #define GICInterface_IIDR_Arch_version_Pos 16U /*!< GICInterface IIDR: Arch_version Position */
1076 #define GICInterface_IIDR_Arch_version_Msk (0xFU << GICInterface_IIDR_Arch_version_Pos) /*!< GICInterface IIDR: Arch_version Mask */
1077 #define GICInterface_IIDR_Arch_version(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_IIDR_Arch_version_Pos)) & GICInterface_IIDR_Arch_version_Msk)
1079 #define GICInterface_IIDR_ProductID_Pos 20U /*!< GICInterface IIDR: ProductID Position */
1080 #define GICInterface_IIDR_ProductID_Msk (0xFFFU << GICInterface_IIDR_ProductID_Pos) /*!< GICInterface IIDR: ProductID Mask */
1081 #define GICInterface_IIDR_ProductID(x) (((uint32_t)(((uint32_t)(x)) << GICInterface_IIDR_ProductID_Pos)) & GICInterface_IIDR_ProductID_Msk)
1083 /* GICInterface DIR Register */
1084 #define GICInterface_DIR_INTID_Pos 0U /*!< PTIM DIR: INTID Position */
1085 #define GICInterface_DIR_INTID_Msk (0xFFFFFFU /*<< GICInterface_DIR_INTID_Pos*/) /*!< PTIM DIR: INTID Mask */
1086 #define GICInterface_DIR_INTID(x) (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_DIR_INTID_Pos*/)) & GICInterface_DIR_INTID_Msk)
1087 #endif /* (__GIC_PRESENT == 1U) || defined(DOXYGEN) */
1089 #if (defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \
1091 #if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN)
1092 /** \brief Structure type to access the Private Timer
1096 __IOM uint32_t LOAD; //!< \brief Offset: 0x000 (R/W) Private Timer Load Register
1097 __IOM uint32_t COUNTER; //!< \brief Offset: 0x004 (R/W) Private Timer Counter Register
1098 __IOM uint32_t CONTROL; //!< \brief Offset: 0x008 (R/W) Private Timer Control Register
1099 __IOM uint32_t ISR; //!< \brief Offset: 0x00C (R/W) Private Timer Interrupt Status Register
1100 RESERVED(0[4], uint32_t)
1101 __IOM uint32_t WLOAD; //!< \brief Offset: 0x020 (R/W) Watchdog Load Register
1102 __IOM uint32_t WCOUNTER; //!< \brief Offset: 0x024 (R/W) Watchdog Counter Register
1103 __IOM uint32_t WCONTROL; //!< \brief Offset: 0x028 (R/W) Watchdog Control Register
1104 __IOM uint32_t WISR; //!< \brief Offset: 0x02C (R/W) Watchdog Interrupt Status Register
1105 __IOM uint32_t WRESET; //!< \brief Offset: 0x030 (R/W) Watchdog Reset Status Register
1106 __OM uint32_t WDISABLE; //!< \brief Offset: 0x034 ( /W) Watchdog Disable Register
1108 #define PTIM ((Timer_Type *) TIMER_BASE ) /*!< \brief Timer register struct */
1110 /* PTIM Control Register */
1111 #define PTIM_CONTROL_Enable_Pos 0U /*!< PTIM CONTROL: Enable Position */
1112 #define PTIM_CONTROL_Enable_Msk (0x1U /*<< PTIM_CONTROL_Enable_Pos*/) /*!< PTIM CONTROL: Enable Mask */
1113 #define PTIM_CONTROL_Enable(x) (((uint32_t)(((uint32_t)(x)) /*<< PTIM_CONTROL_Enable_Pos*/)) & PTIM_CONTROL_Enable_Msk)
1115 #define PTIM_CONTROL_AutoReload_Pos 1U /*!< PTIM CONTROL: Auto Reload Position */
1116 #define PTIM_CONTROL_AutoReload_Msk (0x1U << PTIM_CONTROL_AutoReload_Pos) /*!< PTIM CONTROL: Auto Reload Mask */
1117 #define PTIM_CONTROL_AutoReload(x) (((uint32_t)(((uint32_t)(x)) << PTIM_CONTROL_AutoReload_Pos)) & PTIM_CONTROL_AutoReload_Msk)
1119 #define PTIM_CONTROL_IRQenable_Pos 2U /*!< PTIM CONTROL: IRQ Enabel Position */
1120 #define PTIM_CONTROL_IRQenable_Msk (0x1U << PTIM_CONTROL_IRQenable_Pos) /*!< PTIM CONTROL: IRQ Enabel Mask */
1121 #define PTIM_CONTROL_IRQenable(x) (((uint32_t)(((uint32_t)(x)) << PTIM_CONTROL_IRQenable_Pos)) & PTIM_CONTROL_IRQenable_Msk)
1123 #define PTIM_CONTROL_Prescaler_Pos 8U /*!< PTIM CONTROL: Prescaler Position */
1124 #define PTIM_CONTROL_Prescaler_Msk (0xFFU << PTIM_CONTROL_Prescaler_Pos) /*!< PTIM CONTROL: Prescaler Mask */
1125 #define PTIM_CONTROL_Prescaler(x) (((uint32_t)(((uint32_t)(x)) << PTIM_CONTROL_Prescaler_Pos)) & PTIM_CONTROL_Prescaler_Msk)
1127 /* WCONTROL Watchdog Control Register */
1128 #define PTIM_WCONTROL_Enable_Pos 0U /*!< PTIM WCONTROL: Enable Position */
1129 #define PTIM_WCONTROL_Enable_Msk (0x1U /*<< PTIM_WCONTROL_Enable_Pos*/) /*!< PTIM WCONTROL: Enable Mask */
1130 #define PTIM_WCONTROL_Enable(x) (((uint32_t)(((uint32_t)(x)) /*<< PTIM_WCONTROL_Enable_Pos*/)) & PTIM_WCONTROL_Enable_Msk)
1132 #define PTIM_WCONTROL_AutoReload_Pos 1U /*!< PTIM WCONTROL: Auto Reload Position */
1133 #define PTIM_WCONTROL_AutoReload_Msk (0x1U << PTIM_WCONTROL_AutoReload_Pos) /*!< PTIM WCONTROL: Auto Reload Mask */
1134 #define PTIM_WCONTROL_AutoReload(x) (((uint32_t)(((uint32_t)(x)) << PTIM_WCONTROL_AutoReload_Pos)) & PTIM_WCONTROL_AutoReload_Msk)
1136 #define PTIM_WCONTROL_IRQenable_Pos 2U /*!< PTIM WCONTROL: IRQ Enable Position */
1137 #define PTIM_WCONTROL_IRQenable_Msk (0x1U << PTIM_WCONTROL_IRQenable_Pos) /*!< PTIM WCONTROL: IRQ Enable Mask */
1138 #define PTIM_WCONTROL_IRQenable(x) (((uint32_t)(((uint32_t)(x)) << PTIM_WCONTROL_IRQenable_Pos)) & PTIM_WCONTROL_IRQenable_Msk)
1140 #define PTIM_WCONTROL_Mode_Pos 3U /*!< PTIM WCONTROL: Watchdog Mode Position */
1141 #define PTIM_WCONTROL_Mode_Msk (0x1U << PTIM_WCONTROL_Mode_Pos) /*!< PTIM WCONTROL: Watchdog Mode Mask */
1142 #define PTIM_WCONTROL_Mode(x) (((uint32_t)(((uint32_t)(x)) << PTIM_WCONTROL_Mode_Pos)) & PTIM_WCONTROL_Mode_Msk)
1144 #define PTIM_WCONTROL_Presacler_Pos 8U /*!< PTIM WCONTROL: Prescaler Position */
1145 #define PTIM_WCONTROL_Presacler_Msk (0xFFU << PTIM_WCONTROL_Presacler_Pos) /*!< PTIM WCONTROL: Prescaler Mask */
1146 #define PTIM_WCONTROL_Presacler(x) (((uint32_t)(((uint32_t)(x)) << PTIM_WCONTROL_Presacler_Pos)) & PTIM_WCONTROL_Presacler_Msk)
1148 /* WISR Watchdog Interrupt Status Register */
1149 #define PTIM_WISR_EventFlag_Pos 0U /*!< PTIM WISR: Event Flag Position */
1150 #define PTIM_WISR_EventFlag_Msk (0x1U /*<< PTIM_WISR_EventFlag_Pos*/) /*!< PTIM WISR: Event Flag Mask */
1151 #define PTIM_WISR_EventFlag(x) (((uint32_t)(((uint32_t)(x)) /*<< PTIM_WISR_EventFlag_Pos*/)) & PTIM_WISR_EventFlag_Msk)
1153 /* WRESET Watchdog Reset Status */
1154 #define PTIM_WRESET_ResetFlag_Pos 0U /*!< PTIM WRESET: Reset Flag Position */
1155 #define PTIM_WRESET_ResetFlag_Msk (0x1U /*<< PTIM_WRESET_ResetFlag_Pos*/) /*!< PTIM WRESET: Reset Flag Mask */
1156 #define PTIM_WRESET_ResetFlag(x) (((uint32_t)(((uint32_t)(x)) /*<< PTIM_WRESET_ResetFlag_Pos*/)) & PTIM_WRESET_ResetFlag_Msk)
1158 #endif /* ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN) */
1159 #endif /* (__TIM_PRESENT == 1U) || defined(DOXYGEN) */
1161 /*******************************************************************************
1162 * Hardware Abstraction Layer
1163 Core Function Interface contains:
1164 - L1 Cache Functions
1165 - L2C-310 Cache Controller Functions
1166 - PL1 Timer Functions
1169 ******************************************************************************/
1171 /* ########################## L1 Cache functions ################################# */
1173 /** \brief Enable Caches by setting I and C bits in SCTLR register.
1175 __STATIC_FORCEINLINE void L1C_EnableCaches(void) {
1176 __set_SCTLR( __get_SCTLR() | SCTLR_I_Msk | SCTLR_C_Msk);
1180 /** \brief Disable Caches by clearing I and C bits in SCTLR register.
1182 __STATIC_FORCEINLINE void L1C_DisableCaches(void) {
1183 __set_SCTLR( __get_SCTLR() & (~SCTLR_I_Msk) & (~SCTLR_C_Msk));
1187 /** \brief Enable Branch Prediction by setting Z bit in SCTLR register.
1189 __STATIC_FORCEINLINE void L1C_EnableBTAC(void) {
1190 __set_SCTLR( __get_SCTLR() | SCTLR_Z_Msk);
1194 /** \brief Disable Branch Prediction by clearing Z bit in SCTLR register.
1196 __STATIC_FORCEINLINE void L1C_DisableBTAC(void) {
1197 __set_SCTLR( __get_SCTLR() & (~SCTLR_Z_Msk));
1201 /** \brief Invalidate entire branch predictor array
1203 __STATIC_FORCEINLINE void L1C_InvalidateBTAC(void) {
1205 __DSB(); //ensure completion of the invalidation
1206 __ISB(); //ensure instruction fetch path sees new state
1209 /** \brief Clean instruction cache line by address.
1210 * \param [in] va Pointer to instructions to clear the cache for.
1212 __STATIC_FORCEINLINE void L1C_InvalidateICacheMVA(void *va) {
1213 __set_ICIMVAC((uint32_t)va);
1214 __DSB(); //ensure completion of the invalidation
1215 __ISB(); //ensure instruction fetch path sees new I cache state
1218 /** \brief Invalidate the whole instruction cache
1220 __STATIC_FORCEINLINE void L1C_InvalidateICacheAll(void) {
1222 __DSB(); //ensure completion of the invalidation
1223 __ISB(); //ensure instruction fetch path sees new I cache state
1226 /** \brief Clean data cache line by address.
1227 * \param [in] va Pointer to data to clear the cache for.
1229 __STATIC_FORCEINLINE void L1C_CleanDCacheMVA(void *va) {
1230 __set_DCCMVAC((uint32_t)va);
1231 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
1234 /** \brief Invalidate data cache line by address.
1235 * \param [in] va Pointer to data to invalidate the cache for.
1237 __STATIC_FORCEINLINE void L1C_InvalidateDCacheMVA(void *va) {
1238 __set_DCIMVAC((uint32_t)va);
1239 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
1242 /** \brief Clean and Invalidate data cache by address.
1243 * \param [in] va Pointer to data to invalidate the cache for.
1245 __STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheMVA(void *va) {
1246 __set_DCCIMVAC((uint32_t)va);
1247 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
1250 /** \brief Calculate log2 rounded up
1261 * \param [in] n input value parameter
1264 __STATIC_FORCEINLINE uint8_t __log2_up(uint32_t n)
1276 if (n & 1U) { log++; }
1280 /** \brief Apply cache maintenance to given cache level.
1281 * \param [in] level cache level to be maintained
1282 * \param [in] maint 0 - invalidate, 1 - clean, otherwise - invalidate and clean
1284 __STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint)
1291 uint32_t log2_linesize;
1292 uint8_t log2_num_ways;
1294 Dummy = level << 1U;
1295 /* set csselr, select ccsidr register */
1296 __set_CSSELR(Dummy);
1297 /* get current ccsidr register */
1298 ccsidr = __get_CCSIDR();
1299 num_sets = ((ccsidr & 0x0FFFE000U) >> 13U) + 1U;
1300 num_ways = ((ccsidr & 0x00001FF8U) >> 3U) + 1U;
1301 log2_linesize = (ccsidr & 0x00000007U) + 2U + 2U;
1302 log2_num_ways = __log2_up(num_ways);
1303 if (log2_num_ways > 32U) {
1304 return; // FATAL ERROR
1306 shift_way = 32U - log2_num_ways;
1307 for(int32_t way = num_ways-1; way >= 0; way--)
1309 for(int32_t set = num_sets-1; set >= 0; set--)
1311 Dummy = (level << 1U) | (((uint32_t)set) << log2_linesize) | (((uint32_t)way) << shift_way);
1314 case 0U: __set_DCISW(Dummy); break;
1315 case 1U: __set_DCCSW(Dummy); break;
1316 default: __set_DCCISW(Dummy); break;
1323 /** \brief Clean and Invalidate the entire data or unified cache
1324 * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
1325 * \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean
1327 __STATIC_FORCEINLINE void L1C_CleanInvalidateCache(uint32_t op) {
1329 uint32_t cache_type;
1330 clidr = __get_CLIDR();
1331 for(uint32_t i = 0U; i<7U; i++)
1333 cache_type = (clidr >> i*3U) & 0x7UL;
1334 if ((cache_type >= 2U) && (cache_type <= 4U))
1336 __L1C_MaintainDCacheSetWay(i, op);
1341 /** \brief Clean and Invalidate the entire data or unified cache
1342 * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
1343 * \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean
1344 * \deprecated Use generic L1C_CleanInvalidateCache instead.
1347 __STATIC_FORCEINLINE void __L1C_CleanInvalidateCache(uint32_t op) {
1348 L1C_CleanInvalidateCache(op);
1351 /** \brief Invalidate the whole data cache.
1353 __STATIC_FORCEINLINE void L1C_InvalidateDCacheAll(void) {
1354 L1C_CleanInvalidateCache(0);
1357 /** \brief Clean the whole data cache.
1359 __STATIC_FORCEINLINE void L1C_CleanDCacheAll(void) {
1360 L1C_CleanInvalidateCache(1);
1363 /** \brief Clean and invalidate the whole data cache.
1365 __STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheAll(void) {
1366 L1C_CleanInvalidateCache(2);
1369 /* ########################## L2 Cache functions ################################# */
1370 #if (defined(__L2C_PRESENT) && (__L2C_PRESENT == 1U)) || \
1372 /** \brief Cache Sync operation by writing CACHE_SYNC register.
1374 __STATIC_INLINE void L2C_Sync(void)
1376 L2C_310->CACHE_SYNC = 0x0;
1379 /** \brief Read cache controller cache ID from CACHE_ID register.
1380 * \return L2C_310_TypeDef::CACHE_ID
1382 __STATIC_INLINE int L2C_GetID (void)
1384 return L2C_310->CACHE_ID;
1387 /** \brief Read cache controller cache type from CACHE_TYPE register.
1388 * \return L2C_310_TypeDef::CACHE_TYPE
1390 __STATIC_INLINE int L2C_GetType (void)
1392 return L2C_310->CACHE_TYPE;
1395 /** \brief Invalidate all cache by way
1397 __STATIC_INLINE void L2C_InvAllByWay (void)
1401 if (L2C_310->AUX_CNT & (1U << 16U)) {
1407 L2C_310->INV_WAY = (1U << assoc) - 1U;
1408 while(L2C_310->INV_WAY & ((1U << assoc) - 1U)); //poll invalidate
1413 /** \brief Clean and Invalidate all cache by way
1415 __STATIC_INLINE void L2C_CleanInvAllByWay (void)
1419 if (L2C_310->AUX_CNT & (1U << 16U)) {
1425 L2C_310->CLEAN_INV_WAY = (1U << assoc) - 1U;
1426 while(L2C_310->CLEAN_INV_WAY & ((1U << assoc) - 1U)); //poll invalidate
1431 /** \brief Enable Level 2 Cache
1433 __STATIC_INLINE void L2C_Enable(void)
1435 L2C_310->CONTROL = 0;
1436 L2C_310->INTERRUPT_CLEAR = 0x000001FFuL;
1437 L2C_310->DEBUG_CONTROL = 0;
1438 L2C_310->DATA_LOCK_0_WAY = 0;
1439 L2C_310->CACHE_SYNC = 0;
1440 L2C_310->CONTROL = 0x01;
1444 /** \brief Disable Level 2 Cache
1446 __STATIC_INLINE void L2C_Disable(void)
1448 L2C_310->CONTROL = 0x00;
1452 /** \brief Invalidate cache by physical address
1453 * \param [in] pa Pointer to data to invalidate cache for.
1455 __STATIC_INLINE void L2C_InvPa (void *pa)
1457 L2C_310->INV_LINE_PA = (unsigned int)pa;
1461 /** \brief Clean cache by physical address
1462 * \param [in] pa Pointer to data to invalidate cache for.
1464 __STATIC_INLINE void L2C_CleanPa (void *pa)
1466 L2C_310->CLEAN_LINE_PA = (unsigned int)pa;
1470 /** \brief Clean and invalidate cache by physical address
1471 * \param [in] pa Pointer to data to invalidate cache for.
1473 __STATIC_INLINE void L2C_CleanInvPa (void *pa)
1475 L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa;
1480 /* ########################## GIC functions ###################################### */
1481 #if (defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U)) || \
1484 /** \brief Enable the interrupt distributor using the GIC's CTLR register.
1486 __STATIC_INLINE void GIC_EnableDistributor(void)
1488 GICDistributor->CTLR |= 1U;
1491 /** \brief Disable the interrupt distributor using the GIC's CTLR register.
1493 __STATIC_INLINE void GIC_DisableDistributor(void)
1495 GICDistributor->CTLR &=~1U;
1498 /** \brief Read the GIC's TYPER register.
1499 * \return GICDistributor_Type::TYPER
1501 __STATIC_INLINE uint32_t GIC_DistributorInfo(void)
1503 return (GICDistributor->TYPER);
1506 /** \brief Reads the GIC's IIDR register.
1507 * \return GICDistributor_Type::IIDR
1509 __STATIC_INLINE uint32_t GIC_DistributorImplementer(void)
1511 return (GICDistributor->IIDR);
1514 /** \brief Sets the GIC's ITARGETSR register for the given interrupt.
1515 * \param [in] IRQn Interrupt to be configured.
1516 * \param [in] cpu_target CPU interfaces to assign this interrupt to.
1518 __STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
1520 uint32_t mask = GICDistributor->ITARGETSR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U));
1521 GICDistributor->ITARGETSR[IRQn / 4U] = mask | ((cpu_target & 0xFFUL) << ((IRQn % 4U) * 8U));
1524 /** \brief Read the GIC's ITARGETSR register.
1525 * \param [in] IRQn Interrupt to acquire the configuration for.
1526 * \return GICDistributor_Type::ITARGETSR
1528 __STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn)
1530 return (GICDistributor->ITARGETSR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
1533 /** \brief Enable the CPU's interrupt interface.
1535 __STATIC_INLINE void GIC_EnableInterface(void)
1537 GICInterface->CTLR |= 1U; //enable interface
1540 /** \brief Disable the CPU's interrupt interface.
1542 __STATIC_INLINE void GIC_DisableInterface(void)
1544 GICInterface->CTLR &=~1U; //disable distributor
1547 /** \brief Read the CPU's IAR register.
1548 * \return GICInterface_Type::IAR
1550 __STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void)
1552 return (IRQn_Type)(GICInterface->IAR);
1555 /** \brief Writes the given interrupt number to the CPU's EOIR register.
1556 * \param [in] IRQn The interrupt to be signaled as finished.
1558 __STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn)
1560 GICInterface->EOIR = IRQn;
1563 /** \brief Enables the given interrupt using GIC's ISENABLER register.
1564 * \param [in] IRQn The interrupt to be enabled.
1566 __STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn)
1568 GICDistributor->ISENABLER[IRQn / 32U] = 1U << (IRQn % 32U);
1571 /** \brief Get interrupt enable status using GIC's ISENABLER register.
1572 * \param [in] IRQn The interrupt to be queried.
1573 * \return 0 - interrupt is not enabled, 1 - interrupt is enabled.
1575 __STATIC_INLINE uint32_t GIC_GetEnableIRQ(IRQn_Type IRQn)
1577 return (GICDistributor->ISENABLER[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
1580 /** \brief Disables the given interrupt using GIC's ICENABLER register.
1581 * \param [in] IRQn The interrupt to be disabled.
1583 __STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn)
1585 GICDistributor->ICENABLER[IRQn / 32U] = 1U << (IRQn % 32U);
1588 /** \brief Get interrupt pending status from GIC's ISPENDR register.
1589 * \param [in] IRQn The interrupt to be queried.
1590 * \return 0 - interrupt is not pending, 1 - interrupt is pendig.
1592 __STATIC_INLINE uint32_t GIC_GetPendingIRQ(IRQn_Type IRQn)
1597 pend = (GICDistributor->ISPENDR[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
1599 // INTID 0-15 Software Generated Interrupt
1600 pend = (GICDistributor->SPENDSGIR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
1601 // No CPU identification offered
1612 /** \brief Sets the given interrupt as pending using GIC's ISPENDR register.
1613 * \param [in] IRQn The interrupt to be enabled.
1615 __STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn)
1618 GICDistributor->ISPENDR[IRQn / 32U] = 1U << (IRQn % 32U);
1620 // INTID 0-15 Software Generated Interrupt
1621 // Forward the interrupt to the CPU interface that requested it
1622 GICDistributor->SGIR = (IRQn | 0x02000000U);
1626 /** \brief Clears the given interrupt from being pending using GIC's ICPENDR register.
1627 * \param [in] IRQn The interrupt to be enabled.
1629 __STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn)
1632 GICDistributor->ICPENDR[IRQn / 32U] = 1U << (IRQn % 32U);
1634 // INTID 0-15 Software Generated Interrupt
1635 GICDistributor->CPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U);
1639 /** \brief Sets the interrupt configuration using GIC's ICFGR register.
1640 * \param [in] IRQn The interrupt to be configured.
1641 * \param [in] int_config Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1)
1642 * Bit 1: 0 - level sensitive, 1 - edge triggered
1644 __STATIC_INLINE void GIC_SetConfiguration(IRQn_Type IRQn, uint32_t int_config)
1646 uint32_t icfgr = GICDistributor->ICFGR[IRQn / 16U]; /* read current register content */
1647 uint32_t shift = (IRQn % 16U) << 1U; /* calculate shift value */
1649 int_config &= 3U; /* only 2 bits are valid */
1650 icfgr &= (~(3U << shift)); /* clear bits to change */
1651 icfgr |= ( int_config << shift); /* set new configuration */
1653 GICDistributor->ICFGR[IRQn / 16U] = icfgr; /* write new register content */
1656 /** \brief Get the interrupt configuration from the GIC's ICFGR register.
1657 * \param [in] IRQn Interrupt to acquire the configuration for.
1658 * \return Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1)
1659 * Bit 1: 0 - level sensitive, 1 - edge triggered
1661 __STATIC_INLINE uint32_t GIC_GetConfiguration(IRQn_Type IRQn)
1663 return (GICDistributor->ICFGR[IRQn / 16U] >> ((IRQn % 16U) >> 1U));
1666 /** \brief Set the priority for the given interrupt in the GIC's IPRIORITYR register.
1667 * \param [in] IRQn The interrupt to be configured.
1668 * \param [in] priority The priority for the interrupt, lower values denote higher priorities.
1670 __STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1672 uint32_t mask = GICDistributor->IPRIORITYR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U));
1673 GICDistributor->IPRIORITYR[IRQn / 4U] = mask | ((priority & 0xFFUL) << ((IRQn % 4U) * 8U));
1676 /** \brief Read the current interrupt priority from GIC's IPRIORITYR register.
1677 * \param [in] IRQn The interrupt to be queried.
1679 __STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)
1681 return (GICDistributor->IPRIORITYR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
1684 /** \brief Set the interrupt priority mask using CPU's PMR register.
1685 * \param [in] priority Priority mask to be set.
1687 __STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority)
1689 GICInterface->PMR = priority & 0xFFUL; //set priority mask
1692 /** \brief Read the current interrupt priority mask from CPU's PMR register.
1693 * \result GICInterface_Type::PMR
1695 __STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void)
1697 return GICInterface->PMR;
1700 /** \brief Configures the group priority and subpriority split point using CPU's BPR register.
1701 * \param [in] binary_point Amount of bits used as subpriority.
1703 __STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point)
1705 GICInterface->BPR = binary_point & 7U; //set binary point
1708 /** \brief Read the current group priority and subpriority split point from CPU's BPR register.
1709 * \return GICInterface_Type::BPR
1711 __STATIC_INLINE uint32_t GIC_GetBinaryPoint(void)
1713 return GICInterface->BPR;
1716 /** \brief Get the status for a given interrupt.
1717 * \param [in] IRQn The interrupt to get status for.
1718 * \return 0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active
1720 __STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
1722 uint32_t pending, active;
1724 active = ((GICDistributor->ISACTIVER[IRQn / 32U]) >> (IRQn % 32U)) & 1UL;
1725 pending = ((GICDistributor->ISPENDR[IRQn / 32U]) >> (IRQn % 32U)) & 1UL;
1727 return ((active<<1U) | pending);
1730 /** \brief Generate a software interrupt using GIC's SGIR register.
1731 * \param [in] IRQn Software interrupt to be generated.
1732 * \param [in] target_list List of CPUs the software interrupt should be forwarded to.
1733 * \param [in] filter_list Filter to be applied to determine interrupt receivers.
1735 __STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
1737 GICDistributor->SGIR = ((filter_list & 3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (IRQn & 0x0FUL);
1740 /** \brief Get the interrupt number of the highest interrupt pending from CPU's HPPIR register.
1741 * \return GICInterface_Type::HPPIR
1743 __STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void)
1745 return GICInterface->HPPIR;
1748 /** \brief Provides information about the implementer and revision of the CPU interface.
1749 * \return GICInterface_Type::IIDR
1751 __STATIC_INLINE uint32_t GIC_GetInterfaceId(void)
1753 return GICInterface->IIDR;
1756 /** \brief Set the interrupt group from the GIC's IGROUPR register.
1757 * \param [in] IRQn The interrupt to be queried.
1758 * \param [in] group Interrupt group number: 0 - Group 0, 1 - Group 1
1760 __STATIC_INLINE void GIC_SetGroup(IRQn_Type IRQn, uint32_t group)
1762 uint32_t igroupr = GICDistributor->IGROUPR[IRQn / 32U];
1763 uint32_t shift = (IRQn % 32U);
1765 igroupr &= (~(1U << shift));
1766 igroupr |= ( (group & 1U) << shift);
1768 GICDistributor->IGROUPR[IRQn / 32U] = igroupr;
1770 #define GIC_SetSecurity GIC_SetGroup
1772 /** \brief Get the interrupt group from the GIC's IGROUPR register.
1773 * \param [in] IRQn The interrupt to be queried.
1774 * \return 0 - Group 0, 1 - Group 1
1776 __STATIC_INLINE uint32_t GIC_GetGroup(IRQn_Type IRQn)
1778 return (GICDistributor->IGROUPR[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
1780 #define GIC_GetSecurity GIC_GetGroup
1782 /** \brief Initialize the interrupt distributor.
1784 __STATIC_INLINE void GIC_DistInit(void)
1787 uint32_t num_irq = 0U;
1788 uint32_t priority_field;
1790 //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0,
1791 //configuring all of the interrupts as Secure.
1793 //Disable interrupt forwarding
1794 GIC_DisableDistributor();
1795 //Get the maximum number of interrupts that the GIC supports
1796 num_irq = 32U * ((GIC_DistributorInfo() & 0x1FU) + 1U);
1798 /* Priority level is implementation defined.
1799 To determine the number of priority bits implemented write 0xFF to an IPRIORITYR
1800 priority field and read back the value stored.*/
1801 GIC_SetPriority((IRQn_Type)0U, 0xFFU);
1802 priority_field = GIC_GetPriority((IRQn_Type)0U);
1804 for (i = 32U; i < num_irq; i++)
1806 //Disable the SPI interrupt
1807 GIC_DisableIRQ((IRQn_Type)i);
1808 //Set level-sensitive (and N-N model)
1809 GIC_SetConfiguration((IRQn_Type)i, 0U);
1811 GIC_SetPriority((IRQn_Type)i, priority_field/2U);
1812 //Set target list to CPU0
1813 GIC_SetTarget((IRQn_Type)i, 1U);
1815 //Enable distributor
1816 GIC_EnableDistributor();
1819 /** \brief Initialize the CPU's interrupt interface
1821 __STATIC_INLINE void GIC_CPUInterfaceInit(void)
1824 uint32_t priority_field;
1826 //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0,
1827 //configuring all of the interrupts as Secure.
1829 //Disable interrupt forwarding
1830 GIC_DisableInterface();
1832 /* Priority level is implementation defined.
1833 To determine the number of priority bits implemented write 0xFF to an IPRIORITYR
1834 priority field and read back the value stored.*/
1835 GIC_SetPriority((IRQn_Type)0U, 0xFFU);
1836 priority_field = GIC_GetPriority((IRQn_Type)0U);
1839 for (i = 0U; i < 32U; i++)
1842 //Set level-sensitive (and N-N model) for PPI
1843 GIC_SetConfiguration((IRQn_Type)i, 0U);
1845 //Disable SGI and PPI interrupts
1846 GIC_DisableIRQ((IRQn_Type)i);
1848 GIC_SetPriority((IRQn_Type)i, priority_field/2U);
1851 GIC_EnableInterface();
1852 //Set binary point to 0
1853 GIC_SetBinaryPoint(0U);
1855 GIC_SetInterfacePriorityMask(0xFFU);
1858 /** \brief Initialize and enable the GIC
1860 __STATIC_INLINE void GIC_Enable(void)
1863 GIC_CPUInterfaceInit(); //per CPU
1867 /* ########################## Generic Timer functions ############################ */
1868 #if (defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \
1871 /* PL1 Physical Timer */
1872 #if (__CORTEX_A == 7U) || defined(DOXYGEN)
1874 /** \brief Physical Timer Control register */
1879 uint32_t ENABLE:1; /*!< \brief bit: 0 Enables the timer. */
1880 uint32_t IMASK:1; /*!< \brief bit: 1 Timer output signal mask bit. */
1881 uint32_t ISTATUS:1; /*!< \brief bit: 2 The status of the timer. */
1882 RESERVED(0:29, uint32_t)
1883 } b; /*!< \brief Structure used for bit access */
1884 uint32_t w; /*!< \brief Type used for word access */
1887 /** \brief Configures the frequency the timer shall run at.
1888 * \param [in] value The timer frequency in Hz.
1890 __STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value)
1892 __set_CNTFRQ(value);
1896 /** \brief Sets the reset value of the timer.
1897 * \param [in] value The value the timer is loaded with.
1899 __STATIC_INLINE void PL1_SetLoadValue(uint32_t value)
1901 __set_CNTP_TVAL(value);
1905 /** \brief Get the current counter value.
1906 * \return Current counter value.
1908 __STATIC_INLINE uint32_t PL1_GetCurrentValue(void)
1910 return(__get_CNTP_TVAL());
1913 /** \brief Get the current physical counter value.
1914 * \return Current physical counter value.
1916 __STATIC_INLINE uint64_t PL1_GetCurrentPhysicalValue(void)
1918 return(__get_CNTPCT());
1921 /** \brief Set the physical compare value.
1922 * \param [in] value New physical timer compare value.
1924 __STATIC_INLINE void PL1_SetPhysicalCompareValue(uint64_t value)
1926 __set_CNTP_CVAL(value);
1930 /** \brief Get the physical compare value.
1931 * \return Physical compare value.
1933 __STATIC_INLINE uint64_t PL1_GetPhysicalCompareValue(void)
1935 return(__get_CNTP_CVAL());
1938 /** \brief Configure the timer by setting the control value.
1939 * \param [in] value New timer control value.
1941 __STATIC_INLINE void PL1_SetControl(uint32_t value)
1943 __set_CNTP_CTL(value);
1947 /** \brief Get the control value.
1948 * \return Control value.
1950 __STATIC_INLINE uint32_t PL1_GetControl(void)
1952 return(__get_CNTP_CTL());
1957 #if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN)
1958 /** \brief Set the load value to timers LOAD register.
1959 * \param [in] value The load value to be set.
1961 __STATIC_INLINE void PTIM_SetLoadValue(uint32_t value)
1966 /** \brief Get the load value from timers LOAD register.
1967 * \return Timer_Type::LOAD
1969 __STATIC_INLINE uint32_t PTIM_GetLoadValue(void)
1974 /** \brief Set current counter value from its COUNTER register.
1976 __STATIC_INLINE void PTIM_SetCurrentValue(uint32_t value)
1978 PTIM->COUNTER = value;
1981 /** \brief Get current counter value from timers COUNTER register.
1982 * \result Timer_Type::COUNTER
1984 __STATIC_INLINE uint32_t PTIM_GetCurrentValue(void)
1986 return(PTIM->COUNTER);
1989 /** \brief Configure the timer using its CONTROL register.
1990 * \param [in] value The new configuration value to be set.
1992 __STATIC_INLINE void PTIM_SetControl(uint32_t value)
1994 PTIM->CONTROL = value;
1997 /** ref Timer_Type::CONTROL Get the current timer configuration from its CONTROL register.
1998 * \return Timer_Type::CONTROL
2000 __STATIC_INLINE uint32_t PTIM_GetControl(void)
2002 return(PTIM->CONTROL);
2005 /** ref Timer_Type::CONTROL Get the event flag in timers ISR register.
2006 * \return 0 - flag is not set, 1- flag is set
2008 __STATIC_INLINE uint32_t PTIM_GetEventFlag(void)
2010 return (PTIM->ISR & 1UL);
2013 /** ref Timer_Type::CONTROL Clears the event flag in timers ISR register.
2015 __STATIC_INLINE void PTIM_ClearEventFlag(void)
2022 /* ########################## MMU functions ###################################### */
2024 #define SECTION_DESCRIPTOR (0x2)
2025 #define SECTION_MASK (0xFFFFFFFC)
2027 #define SECTION_TEXCB_MASK (0xFFFF8FF3)
2028 #define SECTION_B_SHIFT (2)
2029 #define SECTION_C_SHIFT (3)
2030 #define SECTION_TEX0_SHIFT (12)
2031 #define SECTION_TEX1_SHIFT (13)
2032 #define SECTION_TEX2_SHIFT (14)
2034 #define SECTION_XN_MASK (0xFFFFFFEF)
2035 #define SECTION_XN_SHIFT (4)
2037 #define SECTION_DOMAIN_MASK (0xFFFFFE1F)
2038 #define SECTION_DOMAIN_SHIFT (5)
2040 #define SECTION_P_MASK (0xFFFFFDFF)
2041 #define SECTION_P_SHIFT (9)
2043 #define SECTION_AP_MASK (0xFFFF73FF)
2044 #define SECTION_AP_SHIFT (10)
2045 #define SECTION_AP2_SHIFT (15)
2047 #define SECTION_S_MASK (0xFFFEFFFF)
2048 #define SECTION_S_SHIFT (16)
2050 #define SECTION_NG_MASK (0xFFFDFFFF)
2051 #define SECTION_NG_SHIFT (17)
2053 #define SECTION_NS_MASK (0xFFF7FFFF)
2054 #define SECTION_NS_SHIFT (19)
2056 #define PAGE_L1_DESCRIPTOR (0x1)
2057 #define PAGE_L1_MASK (0xFFFFFFFC)
2059 #define PAGE_L2_4K_DESC (0x2)
2060 #define PAGE_L2_4K_MASK (0xFFFFFFFD)
2062 #define PAGE_L2_64K_DESC (0x1)
2063 #define PAGE_L2_64K_MASK (0xFFFFFFFC)
2065 #define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
2066 #define PAGE_4K_B_SHIFT (2)
2067 #define PAGE_4K_C_SHIFT (3)
2068 #define PAGE_4K_TEX0_SHIFT (6)
2069 #define PAGE_4K_TEX1_SHIFT (7)
2070 #define PAGE_4K_TEX2_SHIFT (8)
2072 #define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
2073 #define PAGE_64K_B_SHIFT (2)
2074 #define PAGE_64K_C_SHIFT (3)
2075 #define PAGE_64K_TEX0_SHIFT (12)
2076 #define PAGE_64K_TEX1_SHIFT (13)
2077 #define PAGE_64K_TEX2_SHIFT (14)
2079 #define PAGE_TEXCB_MASK (0xFFFF8FF3)
2080 #define PAGE_B_SHIFT (2)
2081 #define PAGE_C_SHIFT (3)
2082 #define PAGE_TEX_SHIFT (12)
2084 #define PAGE_XN_4K_MASK (0xFFFFFFFE)
2085 #define PAGE_XN_4K_SHIFT (0)
2086 #define PAGE_XN_64K_MASK (0xFFFF7FFF)
2087 #define PAGE_XN_64K_SHIFT (15)
2089 #define PAGE_DOMAIN_MASK (0xFFFFFE1F)
2090 #define PAGE_DOMAIN_SHIFT (5)
2092 #define PAGE_P_MASK (0xFFFFFDFF)
2093 #define PAGE_P_SHIFT (9)
2095 #define PAGE_AP_MASK (0xFFFFFDCF)
2096 #define PAGE_AP_SHIFT (4)
2097 #define PAGE_AP2_SHIFT (9)
2099 #define PAGE_S_MASK (0xFFFFFBFF)
2100 #define PAGE_S_SHIFT (10)
2102 #define PAGE_NG_MASK (0xFFFFF7FF)
2103 #define PAGE_NG_SHIFT (11)
2105 #define PAGE_NS_MASK (0xFFFFFFF7)
2106 #define PAGE_NS_SHIFT (3)
2108 #define OFFSET_1M (0x00100000)
2109 #define OFFSET_64K (0x00010000)
2110 #define OFFSET_4K (0x00001000)
2112 #define DESCRIPTOR_FAULT (0x00000000)
2114 /* Attributes enumerations */
2116 /* Region size attributes */
2122 } mmu_region_size_Type;
2124 /* Region type attributes */
2134 /* Region cacheability attributes */
2141 } mmu_cacheability_Type;
2143 /* Region parity check attributes */
2148 } mmu_ecc_check_Type;
2150 /* Region execution attributes */
2157 /* Region global attributes */
2164 /* Region shareability attributes */
2171 /* Region security attributes */
2178 /* Region access attributes */
2186 /* Memory Region definition */
2187 typedef struct RegionStruct {
2188 mmu_region_size_Type rg_t;
2189 mmu_memory_Type mem_t;
2191 mmu_cacheability_Type inner_norm_t;
2192 mmu_cacheability_Type outer_norm_t;
2193 mmu_ecc_check_Type e_t;
2194 mmu_execute_Type xn_t;
2195 mmu_global_Type g_t;
2196 mmu_secure_Type sec_t;
2197 mmu_access_Type priv_t;
2198 mmu_access_Type user_t;
2199 mmu_shared_Type sh_t;
2201 } mmu_region_attributes_Type;
2203 //Following macros define the descriptors and attributes
2204 //Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0
2205 #define section_normal(descriptor_l1, region) region.rg_t = SECTION; \
2206 region.domain = 0x0; \
2207 region.e_t = ECC_DISABLED; \
2208 region.g_t = GLOBAL; \
2209 region.inner_norm_t = WB_WA; \
2210 region.outer_norm_t = WB_WA; \
2211 region.mem_t = NORMAL; \
2212 region.sec_t = SECURE; \
2213 region.xn_t = EXECUTE; \
2214 region.priv_t = RW; \
2215 region.user_t = RW; \
2216 region.sh_t = NON_SHARED; \
2217 MMU_GetSectionDescriptor(&descriptor_l1, region);
2219 //Sect_Normal_NC. Outer & inner non-cacheable, non-shareable, executable, rw, domain 0
2220 #define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \
2221 region.domain = 0x0; \
2222 region.e_t = ECC_DISABLED; \
2223 region.g_t = GLOBAL; \
2224 region.inner_norm_t = NON_CACHEABLE; \
2225 region.outer_norm_t = NON_CACHEABLE; \
2226 region.mem_t = NORMAL; \
2227 region.sec_t = SECURE; \
2228 region.xn_t = EXECUTE; \
2229 region.priv_t = RW; \
2230 region.user_t = RW; \
2231 region.sh_t = NON_SHARED; \
2232 MMU_GetSectionDescriptor(&descriptor_l1, region);
2234 //Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0
2235 #define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \
2236 region.domain = 0x0; \
2237 region.e_t = ECC_DISABLED; \
2238 region.g_t = GLOBAL; \
2239 region.inner_norm_t = WB_WA; \
2240 region.outer_norm_t = WB_WA; \
2241 region.mem_t = NORMAL; \
2242 region.sec_t = SECURE; \
2243 region.xn_t = EXECUTE; \
2244 region.priv_t = READ; \
2245 region.user_t = READ; \
2246 region.sh_t = NON_SHARED; \
2247 MMU_GetSectionDescriptor(&descriptor_l1, region);
2249 //Sect_Normal_RO. Sect_Normal_Cod, but not executable
2250 #define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \
2251 region.domain = 0x0; \
2252 region.e_t = ECC_DISABLED; \
2253 region.g_t = GLOBAL; \
2254 region.inner_norm_t = WB_WA; \
2255 region.outer_norm_t = WB_WA; \
2256 region.mem_t = NORMAL; \
2257 region.sec_t = SECURE; \
2258 region.xn_t = NON_EXECUTE; \
2259 region.priv_t = READ; \
2260 region.user_t = READ; \
2261 region.sh_t = NON_SHARED; \
2262 MMU_GetSectionDescriptor(&descriptor_l1, region);
2264 //Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable
2265 #define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \
2266 region.domain = 0x0; \
2267 region.e_t = ECC_DISABLED; \
2268 region.g_t = GLOBAL; \
2269 region.inner_norm_t = WB_WA; \
2270 region.outer_norm_t = WB_WA; \
2271 region.mem_t = NORMAL; \
2272 region.sec_t = SECURE; \
2273 region.xn_t = NON_EXECUTE; \
2274 region.priv_t = RW; \
2275 region.user_t = RW; \
2276 region.sh_t = NON_SHARED; \
2277 MMU_GetSectionDescriptor(&descriptor_l1, region);
2278 //Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
2279 #define section_so(descriptor_l1, region) region.rg_t = SECTION; \
2280 region.domain = 0x0; \
2281 region.e_t = ECC_DISABLED; \
2282 region.g_t = GLOBAL; \
2283 region.inner_norm_t = NON_CACHEABLE; \
2284 region.outer_norm_t = NON_CACHEABLE; \
2285 region.mem_t = STRONGLY_ORDERED; \
2286 region.sec_t = SECURE; \
2287 region.xn_t = NON_EXECUTE; \
2288 region.priv_t = RW; \
2289 region.user_t = RW; \
2290 region.sh_t = NON_SHARED; \
2291 MMU_GetSectionDescriptor(&descriptor_l1, region);
2293 //Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0
2294 #define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \
2295 region.domain = 0x0; \
2296 region.e_t = ECC_DISABLED; \
2297 region.g_t = GLOBAL; \
2298 region.inner_norm_t = NON_CACHEABLE; \
2299 region.outer_norm_t = NON_CACHEABLE; \
2300 region.mem_t = STRONGLY_ORDERED; \
2301 region.sec_t = SECURE; \
2302 region.xn_t = NON_EXECUTE; \
2303 region.priv_t = READ; \
2304 region.user_t = READ; \
2305 region.sh_t = NON_SHARED; \
2306 MMU_GetSectionDescriptor(&descriptor_l1, region);
2308 //Sect_Device_RW. Sect_Device_RO, but writeable
2309 #define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \
2310 region.domain = 0x0; \
2311 region.e_t = ECC_DISABLED; \
2312 region.g_t = GLOBAL; \
2313 region.inner_norm_t = NON_CACHEABLE; \
2314 region.outer_norm_t = NON_CACHEABLE; \
2315 region.mem_t = STRONGLY_ORDERED; \
2316 region.sec_t = SECURE; \
2317 region.xn_t = NON_EXECUTE; \
2318 region.priv_t = RW; \
2319 region.user_t = RW; \
2320 region.sh_t = NON_SHARED; \
2321 MMU_GetSectionDescriptor(&descriptor_l1, region);
2322 //Page_4k_Device_RW. Shared device, not executable, rw, domain 0
2323 #define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \
2324 region.domain = 0x0; \
2325 region.e_t = ECC_DISABLED; \
2326 region.g_t = GLOBAL; \
2327 region.inner_norm_t = NON_CACHEABLE; \
2328 region.outer_norm_t = NON_CACHEABLE; \
2329 region.mem_t = SHARED_DEVICE; \
2330 region.sec_t = SECURE; \
2331 region.xn_t = NON_EXECUTE; \
2332 region.priv_t = RW; \
2333 region.user_t = RW; \
2334 region.sh_t = NON_SHARED; \
2335 MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
2337 //Page_64k_Device_RW. Shared device, not executable, rw, domain 0
2338 #define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \
2339 region.domain = 0x0; \
2340 region.e_t = ECC_DISABLED; \
2341 region.g_t = GLOBAL; \
2342 region.inner_norm_t = NON_CACHEABLE; \
2343 region.outer_norm_t = NON_CACHEABLE; \
2344 region.mem_t = SHARED_DEVICE; \
2345 region.sec_t = SECURE; \
2346 region.xn_t = NON_EXECUTE; \
2347 region.priv_t = RW; \
2348 region.user_t = RW; \
2349 region.sh_t = NON_SHARED; \
2350 MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
2352 /** \brief Set section execution-never attribute
2354 \param [out] descriptor_l1 L1 descriptor.
2355 \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
2359 __STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn)
2361 *descriptor_l1 &= SECTION_XN_MASK;
2362 *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
2366 /** \brief Set section domain
2368 \param [out] descriptor_l1 L1 descriptor.
2369 \param [in] domain Section domain
2373 __STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain)
2375 *descriptor_l1 &= SECTION_DOMAIN_MASK;
2376 *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
2380 /** \brief Set section parity check
2382 \param [out] descriptor_l1 L1 descriptor.
2383 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
2387 __STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
2389 *descriptor_l1 &= SECTION_P_MASK;
2390 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
2394 /** \brief Set section access privileges
2396 \param [out] descriptor_l1 L1 descriptor.
2397 \param [in] user User Level Access: NO_ACCESS, RW, READ
2398 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
2399 \param [in] afe Access flag enable
2403 __STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
2407 if (afe == 0) { //full access
2408 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
2409 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
2410 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
2411 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
2412 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
2413 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
2416 else { //Simplified access
2417 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
2418 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
2419 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
2420 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
2423 *descriptor_l1 &= SECTION_AP_MASK;
2424 *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
2425 *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
2430 /** \brief Set section shareability
2432 \param [out] descriptor_l1 L1 descriptor.
2433 \param [in] s_bit Section shareability: NON_SHARED, SHARED
2437 __STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
2439 *descriptor_l1 &= SECTION_S_MASK;
2440 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
2444 /** \brief Set section Global attribute
2446 \param [out] descriptor_l1 L1 descriptor.
2447 \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
2451 __STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit)
2453 *descriptor_l1 &= SECTION_NG_MASK;
2454 *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
2458 /** \brief Set section Security attribute
2460 \param [out] descriptor_l1 L1 descriptor.
2461 \param [in] s_bit Section Security attribute: SECURE, NON_SECURE
2465 __STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
2467 *descriptor_l1 &= SECTION_NS_MASK;
2468 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
2472 /* Page 4k or 64k */
2473 /** \brief Set 4k/64k page execution-never attribute
2475 \param [out] descriptor_l2 L2 descriptor.
2476 \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
2477 \param [in] page Page size: PAGE_4k, PAGE_64k,
2481 __STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
2483 if (page == PAGE_4k)
2485 *descriptor_l2 &= PAGE_XN_4K_MASK;
2486 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
2490 *descriptor_l2 &= PAGE_XN_64K_MASK;
2491 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
2496 /** \brief Set 4k/64k page domain
2498 \param [out] descriptor_l1 L1 descriptor.
2499 \param [in] domain Page domain
2503 __STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain)
2505 *descriptor_l1 &= PAGE_DOMAIN_MASK;
2506 *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
2510 /** \brief Set 4k/64k page parity check
2512 \param [out] descriptor_l1 L1 descriptor.
2513 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
2517 __STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
2519 *descriptor_l1 &= SECTION_P_MASK;
2520 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
2524 /** \brief Set 4k/64k page access privileges
2526 \param [out] descriptor_l2 L2 descriptor.
2527 \param [in] user User Level Access: NO_ACCESS, RW, READ
2528 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
2529 \param [in] afe Access flag enable
2533 __STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
2537 if (afe == 0) { //full access
2538 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
2539 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
2540 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
2541 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
2542 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
2543 else if ((priv == READ) && (user == READ)) { ap = 0x6; }
2546 else { //Simplified access
2547 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
2548 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
2549 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
2550 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
2553 *descriptor_l2 &= PAGE_AP_MASK;
2554 *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
2555 *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
2560 /** \brief Set 4k/64k page shareability
2562 \param [out] descriptor_l2 L2 descriptor.
2563 \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
2567 __STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
2569 *descriptor_l2 &= PAGE_S_MASK;
2570 *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
2574 /** \brief Set 4k/64k page Global attribute
2576 \param [out] descriptor_l2 L2 descriptor.
2577 \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
2581 __STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit)
2583 *descriptor_l2 &= PAGE_NG_MASK;
2584 *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
2588 /** \brief Set 4k/64k page Security attribute
2590 \param [out] descriptor_l1 L1 descriptor.
2591 \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
2595 __STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
2597 *descriptor_l1 &= PAGE_NS_MASK;
2598 *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
2602 /** \brief Set Section memory attributes
2604 \param [out] descriptor_l1 L1 descriptor.
2605 \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
2606 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
2607 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
2611 __STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
2613 *descriptor_l1 &= SECTION_TEXCB_MASK;
2615 if (STRONGLY_ORDERED == mem)
2619 else if (SHARED_DEVICE == mem)
2621 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
2623 else if (NON_SHARED_DEVICE == mem)
2625 *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
2627 else if (NORMAL == mem)
2629 *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
2635 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
2638 *descriptor_l1 |= 1 << SECTION_C_SHIFT;
2641 *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
2649 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
2652 *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
2655 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
2662 /** \brief Set 4k/64k page memory attributes
2664 \param [out] descriptor_l2 L2 descriptor.
2665 \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
2666 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
2667 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
2668 \param [in] page Page size
2672 __STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
2674 *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
2676 if (page == PAGE_64k)
2679 MMU_MemorySection(descriptor_l2, mem, outer, inner);
2683 if (STRONGLY_ORDERED == mem)
2687 else if (SHARED_DEVICE == mem)
2689 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
2691 else if (NON_SHARED_DEVICE == mem)
2693 *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
2695 else if (NORMAL == mem)
2697 *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
2703 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
2706 *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
2709 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
2717 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
2720 *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
2723 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
2732 /** \brief Create a L1 section descriptor
2734 \param [out] descriptor L1 descriptor
2735 \param [in] reg Section attributes
2739 __STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
2743 MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
2744 MMU_XNSection(descriptor,reg.xn_t);
2745 MMU_DomainSection(descriptor, reg.domain);
2746 MMU_PSection(descriptor, reg.e_t);
2747 MMU_APSection(descriptor, reg.user_t, reg.priv_t, 1);
2748 MMU_SharedSection(descriptor,reg.sh_t);
2749 MMU_GlobalSection(descriptor,reg.g_t);
2750 MMU_SecureSection(descriptor,reg.sec_t);
2751 *descriptor &= SECTION_MASK;
2752 *descriptor |= SECTION_DESCRIPTOR;
2758 /** \brief Create a L1 and L2 4k/64k page descriptor
2760 \param [out] descriptor L1 descriptor
2761 \param [out] descriptor2 L2 descriptor
2762 \param [in] reg 4k/64k page attributes
2766 __STATIC_INLINE int MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
2774 MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
2775 MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k);
2776 MMU_DomainPage(descriptor, reg.domain);
2777 MMU_PPage(descriptor, reg.e_t);
2778 MMU_APPage(descriptor2, reg.user_t, reg.priv_t, 1);
2779 MMU_SharedPage(descriptor2,reg.sh_t);
2780 MMU_GlobalPage(descriptor2,reg.g_t);
2781 MMU_SecurePage(descriptor,reg.sec_t);
2782 *descriptor &= PAGE_L1_MASK;
2783 *descriptor |= PAGE_L1_DESCRIPTOR;
2784 *descriptor2 &= PAGE_L2_4K_MASK;
2785 *descriptor2 |= PAGE_L2_4K_DESC;
2789 MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
2790 MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k);
2791 MMU_DomainPage(descriptor, reg.domain);
2792 MMU_PPage(descriptor, reg.e_t);
2793 MMU_APPage(descriptor2, reg.user_t, reg.priv_t, 1);
2794 MMU_SharedPage(descriptor2,reg.sh_t);
2795 MMU_GlobalPage(descriptor2,reg.g_t);
2796 MMU_SecurePage(descriptor,reg.sec_t);
2797 *descriptor &= PAGE_L1_MASK;
2798 *descriptor |= PAGE_L1_DESCRIPTOR;
2799 *descriptor2 &= PAGE_L2_64K_MASK;
2800 *descriptor2 |= PAGE_L2_64K_DESC;
2811 /** \brief Create a 1MB Section
2813 \param [in] ttb Translation table base address
2814 \param [in] base_address Section base address
2815 \param [in] count Number of sections to create
2816 \param [in] descriptor_l1 L1 descriptor (region attributes)
2819 __STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
2825 offset = base_address >> 20;
2826 entry = (base_address & 0xFFF00000) | descriptor_l1;
2831 for (i = 0; i < count; i++ )
2839 /** \brief Create a 4k page entry
2841 \param [in] ttb L1 table base address
2842 \param [in] base_address 4k base address
2843 \param [in] count Number of 4k pages to create
2844 \param [in] descriptor_l1 L1 descriptor (region attributes)
2845 \param [in] ttb_l2 L2 table base address
2846 \param [in] descriptor_l2 L2 descriptor (region attributes)
2849 __STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
2852 uint32_t offset, offset2;
2853 uint32_t entry, entry2;
2856 offset = base_address >> 20;
2857 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
2864 offset2 = (base_address & 0xff000) >> 12;
2866 entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
2867 for (i = 0; i < count; i++ )
2871 entry2 += OFFSET_4K;
2875 /** \brief Create a 64k page entry
2877 \param [in] ttb L1 table base address
2878 \param [in] base_address 64k base address
2879 \param [in] count Number of 64k pages to create
2880 \param [in] descriptor_l1 L1 descriptor (region attributes)
2881 \param [in] ttb_l2 L2 table base address
2882 \param [in] descriptor_l2 L2 descriptor (region attributes)
2885 __STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
2887 uint32_t offset, offset2;
2888 uint32_t entry, entry2;
2892 offset = base_address >> 20;
2893 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
2900 offset2 = (base_address & 0xff000) >> 12;
2902 entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
2903 for (i = 0; i < count; i++ )
2906 for (j = 0; j < 16; j++)
2911 entry2 += OFFSET_64K;
2915 /** \brief Enable MMU
2917 __STATIC_INLINE void MMU_Enable(void)
2919 // Set M bit 0 to enable the MMU
2920 // Set AFE bit to enable simplified access permissions model
2921 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
2922 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
2926 /** \brief Disable MMU
2928 __STATIC_INLINE void MMU_Disable(void)
2930 // Clear M bit 0 to disable the MMU
2931 __set_SCTLR( __get_SCTLR() & ~1);
2935 /** \brief Invalidate entire unified TLB
2938 __STATIC_INLINE void MMU_InvalidateTLB(void)
2941 __DSB(); //ensure completion of the invalidation
2942 __ISB(); //ensure instruction fetch path sees new state
2950 #endif /* __CORE_CA_H_DEPENDANT */
2952 #endif /* __CMSIS_GENERIC */
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