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128 <a href="#func-members">Functions</a> </div>
129 <div class="headertitle"><div class="title">Intrinsic Functions for CPU Instructions</div></div>
131 <div class="contents">
133 <p>Functions that generate specific Cortex-M CPU Instructions.
134 <a href="#details">More...</a></p>
135 <table class="memberdecls">
136 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a>
137 Functions</h2></td></tr>
138 <tr class="memitem:ga92f5621626711931da71eaa8bf301af7"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga92f5621626711931da71eaa8bf301af7">__BKPT</a> (uint8_t value)</td></tr>
139 <tr class="memdesc:ga92f5621626711931da71eaa8bf301af7"><td class="mdescLeft"> </td><td class="mdescRight">Set Breakpoint. <br /></td></tr>
140 <tr class="separator:ga92f5621626711931da71eaa8bf301af7"><td class="memSeparator" colspan="2"> </td></tr>
141 <tr class="memitem:ga354c5ac8870cc3dfb823367af9c4b412"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga354c5ac8870cc3dfb823367af9c4b412">__CLREX</a> (void)</td></tr>
142 <tr class="memdesc:ga354c5ac8870cc3dfb823367af9c4b412"><td class="mdescLeft"> </td><td class="mdescRight">Remove the exclusive lock [not for Cortex-M0, Cortex-M0+, or SC000]. <br /></td></tr>
143 <tr class="separator:ga354c5ac8870cc3dfb823367af9c4b412"><td class="memSeparator" colspan="2"> </td></tr>
144 <tr class="memitem:ga90884c591ac5d73d6069334eba9d6c02"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga90884c591ac5d73d6069334eba9d6c02">__CLZ</a> (uint32_t value)</td></tr>
145 <tr class="memdesc:ga90884c591ac5d73d6069334eba9d6c02"><td class="mdescLeft"> </td><td class="mdescRight">Count leading zeros. <br /></td></tr>
146 <tr class="separator:ga90884c591ac5d73d6069334eba9d6c02"><td class="memSeparator" colspan="2"> </td></tr>
147 <tr class="memitem:gab1c9b393641dc2d397b3408fdbe72b96"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gab1c9b393641dc2d397b3408fdbe72b96">__DMB</a> (void)</td></tr>
148 <tr class="memdesc:gab1c9b393641dc2d397b3408fdbe72b96"><td class="mdescLeft"> </td><td class="mdescRight">Data Memory Barrier. <br /></td></tr>
149 <tr class="separator:gab1c9b393641dc2d397b3408fdbe72b96"><td class="memSeparator" colspan="2"> </td></tr>
150 <tr class="memitem:gacb2a8ca6eae1ba4b31161578b720c199"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gacb2a8ca6eae1ba4b31161578b720c199">__DSB</a> (void)</td></tr>
151 <tr class="memdesc:gacb2a8ca6eae1ba4b31161578b720c199"><td class="mdescLeft"> </td><td class="mdescRight">Data Synchronization Barrier. <br /></td></tr>
152 <tr class="separator:gacb2a8ca6eae1ba4b31161578b720c199"><td class="memSeparator" colspan="2"> </td></tr>
153 <tr class="memitem:ga93c09b4709394d81977300d5f84950e5"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga93c09b4709394d81977300d5f84950e5">__ISB</a> (void)</td></tr>
154 <tr class="memdesc:ga93c09b4709394d81977300d5f84950e5"><td class="mdescLeft"> </td><td class="mdescRight">Instruction Synchronization Barrier. <br /></td></tr>
155 <tr class="separator:ga93c09b4709394d81977300d5f84950e5"><td class="memSeparator" colspan="2"> </td></tr>
156 <tr class="memitem:ga22a24f416b65c2f5a82d9f1162d9394d"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga22a24f416b65c2f5a82d9f1162d9394d">__LDA</a> (volatile uint32_t *ptr)</td></tr>
157 <tr class="memdesc:ga22a24f416b65c2f5a82d9f1162d9394d"><td class="mdescLeft"> </td><td class="mdescRight">Load-Acquire (32 bit) <br /></td></tr>
158 <tr class="separator:ga22a24f416b65c2f5a82d9f1162d9394d"><td class="memSeparator" colspan="2"> </td></tr>
159 <tr class="memitem:ga263b9b2d9c06d731022873acddb6aa3f"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga263b9b2d9c06d731022873acddb6aa3f">__LDAB</a> (volatile uint8_t *ptr)</td></tr>
160 <tr class="memdesc:ga263b9b2d9c06d731022873acddb6aa3f"><td class="mdescLeft"> </td><td class="mdescRight">Load-Acquire (8 bit) <br /></td></tr>
161 <tr class="separator:ga263b9b2d9c06d731022873acddb6aa3f"><td class="memSeparator" colspan="2"> </td></tr>
162 <tr class="memitem:ga3c74d923529f664eda099d1b2668b3c1"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga3c74d923529f664eda099d1b2668b3c1">__LDAEX</a> (volatile uint32_t *ptr)</td></tr>
163 <tr class="memdesc:ga3c74d923529f664eda099d1b2668b3c1"><td class="mdescLeft"> </td><td class="mdescRight">Load-Acquire Exclusive (32 bit) <br /></td></tr>
164 <tr class="separator:ga3c74d923529f664eda099d1b2668b3c1"><td class="memSeparator" colspan="2"> </td></tr>
165 <tr class="memitem:ga513beada40cdd7123281f22482603bcc"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga513beada40cdd7123281f22482603bcc">__LDAEXB</a> (volatile uint32_t *ptr)</td></tr>
166 <tr class="memdesc:ga513beada40cdd7123281f22482603bcc"><td class="mdescLeft"> </td><td class="mdescRight">Load-Acquire Exclusive (8 bit) <br /></td></tr>
167 <tr class="separator:ga513beada40cdd7123281f22482603bcc"><td class="memSeparator" colspan="2"> </td></tr>
168 <tr class="memitem:ga426b61640fc68f21b21ae4dc2726f3b4"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga426b61640fc68f21b21ae4dc2726f3b4">__LDAEXH</a> (volatile uint32_t *ptr)</td></tr>
169 <tr class="memdesc:ga426b61640fc68f21b21ae4dc2726f3b4"><td class="mdescLeft"> </td><td class="mdescRight">Load-Acquire Exclusive (16 bit) <br /></td></tr>
170 <tr class="separator:ga426b61640fc68f21b21ae4dc2726f3b4"><td class="memSeparator" colspan="2"> </td></tr>
171 <tr class="memitem:ga5810ac0b87a37e321c2f909cd3860499"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga5810ac0b87a37e321c2f909cd3860499">__LDAH</a> (volatile uint16_t *ptr)</td></tr>
172 <tr class="memdesc:ga5810ac0b87a37e321c2f909cd3860499"><td class="mdescLeft"> </td><td class="mdescRight">Load-Acquire (16 bit) <br /></td></tr>
173 <tr class="separator:ga5810ac0b87a37e321c2f909cd3860499"><td class="memSeparator" colspan="2"> </td></tr>
174 <tr class="memitem:ga9464d75db32846aa8295c3c3adfacb41"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga9464d75db32846aa8295c3c3adfacb41">__LDRBT</a> (uint8_t ptr)</td></tr>
175 <tr class="memdesc:ga9464d75db32846aa8295c3c3adfacb41"><td class="mdescLeft"> </td><td class="mdescRight">LDRT Unprivileged (8 bit) <br /></td></tr>
176 <tr class="separator:ga9464d75db32846aa8295c3c3adfacb41"><td class="memSeparator" colspan="2"> </td></tr>
177 <tr class="memitem:ga9e3ac13d8dcf4331176b624cf6234a7e"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga9e3ac13d8dcf4331176b624cf6234a7e">__LDREXB</a> (volatile uint8_t *addr)</td></tr>
178 <tr class="memdesc:ga9e3ac13d8dcf4331176b624cf6234a7e"><td class="mdescLeft"> </td><td class="mdescRight">LDR Exclusive (8 bit) [not for Cortex-M0, Cortex-M0+, or SC000]. <br /></td></tr>
179 <tr class="separator:ga9e3ac13d8dcf4331176b624cf6234a7e"><td class="memSeparator" colspan="2"> </td></tr>
180 <tr class="memitem:ga9feffc093d6f68b120d592a7a0d45a15"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga9feffc093d6f68b120d592a7a0d45a15">__LDREXH</a> (volatile uint16_t *addr)</td></tr>
181 <tr class="memdesc:ga9feffc093d6f68b120d592a7a0d45a15"><td class="mdescLeft"> </td><td class="mdescRight">LDR Exclusive (16 bit) [not for Cortex-M0, Cortex-M0+, or SC000]. <br /></td></tr>
182 <tr class="separator:ga9feffc093d6f68b120d592a7a0d45a15"><td class="memSeparator" colspan="2"> </td></tr>
183 <tr class="memitem:gabd78840a0f2464905b7cec791ebc6a4c"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gabd78840a0f2464905b7cec791ebc6a4c">__LDREXW</a> (volatile uint32_t *addr)</td></tr>
184 <tr class="memdesc:gabd78840a0f2464905b7cec791ebc6a4c"><td class="mdescLeft"> </td><td class="mdescRight">LDR Exclusive (32 bit) [not for Cortex-M0, Cortex-M0+, or SC000]. <br /></td></tr>
185 <tr class="separator:gabd78840a0f2464905b7cec791ebc6a4c"><td class="memSeparator" colspan="2"> </td></tr>
186 <tr class="memitem:gaa762b8bc5634ce38cb14d62a6b2aee32"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gaa762b8bc5634ce38cb14d62a6b2aee32">__LDRHT</a> (uint16_t ptr)</td></tr>
187 <tr class="memdesc:gaa762b8bc5634ce38cb14d62a6b2aee32"><td class="mdescLeft"> </td><td class="mdescRight">LDRT Unprivileged (16 bit) <br /></td></tr>
188 <tr class="separator:gaa762b8bc5634ce38cb14d62a6b2aee32"><td class="memSeparator" colspan="2"> </td></tr>
189 <tr class="memitem:ga616504f5da979ba8a073d428d6e8d5c7"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga616504f5da979ba8a073d428d6e8d5c7">__LDRT</a> (uint32_t ptr)</td></tr>
190 <tr class="memdesc:ga616504f5da979ba8a073d428d6e8d5c7"><td class="mdescLeft"> </td><td class="mdescRight">LDRT Unprivileged (32 bit) <br /></td></tr>
191 <tr class="separator:ga616504f5da979ba8a073d428d6e8d5c7"><td class="memSeparator" colspan="2"> </td></tr>
192 <tr class="memitem:gac71fad9f0a91980fecafcb450ee0a63e"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gac71fad9f0a91980fecafcb450ee0a63e">__NOP</a> (void)</td></tr>
193 <tr class="memdesc:gac71fad9f0a91980fecafcb450ee0a63e"><td class="mdescLeft"> </td><td class="mdescRight">No Operation. <br /></td></tr>
194 <tr class="separator:gac71fad9f0a91980fecafcb450ee0a63e"><td class="memSeparator" colspan="2"> </td></tr>
195 <tr class="memitem:gad6f9f297f6b91a995ee199fbc796b863"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gad6f9f297f6b91a995ee199fbc796b863">__RBIT</a> (uint32_t value)</td></tr>
196 <tr class="memdesc:gad6f9f297f6b91a995ee199fbc796b863"><td class="mdescLeft"> </td><td class="mdescRight">Reverse bit order of value. <br /></td></tr>
197 <tr class="separator:gad6f9f297f6b91a995ee199fbc796b863"><td class="memSeparator" colspan="2"> </td></tr>
198 <tr class="memitem:ga4717abc17af5ba29b1e4c055e0a0d9b8"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga4717abc17af5ba29b1e4c055e0a0d9b8">__REV</a> (uint32_t value)</td></tr>
199 <tr class="memdesc:ga4717abc17af5ba29b1e4c055e0a0d9b8"><td class="mdescLeft"> </td><td class="mdescRight">Reverse byte order (32 bit) <br /></td></tr>
200 <tr class="separator:ga4717abc17af5ba29b1e4c055e0a0d9b8"><td class="memSeparator" colspan="2"> </td></tr>
201 <tr class="memitem:gaeef6f853b6df3a365c838ee5b49a7a26"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gaeef6f853b6df3a365c838ee5b49a7a26">__REV16</a> (uint32_t value)</td></tr>
202 <tr class="memdesc:gaeef6f853b6df3a365c838ee5b49a7a26"><td class="mdescLeft"> </td><td class="mdescRight">Reverse byte order (16 bit) <br /></td></tr>
203 <tr class="separator:gaeef6f853b6df3a365c838ee5b49a7a26"><td class="memSeparator" colspan="2"> </td></tr>
204 <tr class="memitem:ga211618c03a0bf3264a7b22ad626d4f0a"><td class="memItemLeft" align="right" valign="top">int16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga211618c03a0bf3264a7b22ad626d4f0a">__REVSH</a> (int16_t value)</td></tr>
205 <tr class="memdesc:ga211618c03a0bf3264a7b22ad626d4f0a"><td class="mdescLeft"> </td><td class="mdescRight">Reverse byte order (16 bit) <br /></td></tr>
206 <tr class="separator:ga211618c03a0bf3264a7b22ad626d4f0a"><td class="memSeparator" colspan="2"> </td></tr>
207 <tr class="memitem:gaf66beb577bb9d90424c3d1d7f684c024"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gaf66beb577bb9d90424c3d1d7f684c024">__ROR</a> (uint32_t value, uint32_t shift)</td></tr>
208 <tr class="memdesc:gaf66beb577bb9d90424c3d1d7f684c024"><td class="mdescLeft"> </td><td class="mdescRight">Rotate a value right by a number of bits. <br /></td></tr>
209 <tr class="separator:gaf66beb577bb9d90424c3d1d7f684c024"><td class="memSeparator" colspan="2"> </td></tr>
210 <tr class="memitem:gac09134f1bf9c49db07282001afcc9380"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gac09134f1bf9c49db07282001afcc9380">__RRX</a> (uint32_t value)</td></tr>
211 <tr class="memdesc:gac09134f1bf9c49db07282001afcc9380"><td class="mdescLeft"> </td><td class="mdescRight">Rotate Right with Extend (32 bit) <br /></td></tr>
212 <tr class="separator:gac09134f1bf9c49db07282001afcc9380"><td class="memSeparator" colspan="2"> </td></tr>
213 <tr class="memitem:ga3c34da7eb16496ae2668a5b95fa441e7"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga3c34da7eb16496ae2668a5b95fa441e7">__SEV</a> (void)</td></tr>
214 <tr class="memdesc:ga3c34da7eb16496ae2668a5b95fa441e7"><td class="mdescLeft"> </td><td class="mdescRight">Send Event. <br /></td></tr>
215 <tr class="separator:ga3c34da7eb16496ae2668a5b95fa441e7"><td class="memSeparator" colspan="2"> </td></tr>
216 <tr class="memitem:ga8cfeb5ffe0e49ec6b29dafdde92e5118"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga8cfeb5ffe0e49ec6b29dafdde92e5118">__SSAT</a> (int32_t value, uint32_t sat)</td></tr>
217 <tr class="memdesc:ga8cfeb5ffe0e49ec6b29dafdde92e5118"><td class="mdescLeft"> </td><td class="mdescRight">Signed Saturate. <br /></td></tr>
218 <tr class="separator:ga8cfeb5ffe0e49ec6b29dafdde92e5118"><td class="memSeparator" colspan="2"> </td></tr>
219 <tr class="memitem:ga5429d7083fb8d30c43cecd3a861e1672"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga5429d7083fb8d30c43cecd3a861e1672">__STL</a> (uint32_t value, volatile uint32_t *ptr)</td></tr>
220 <tr class="memdesc:ga5429d7083fb8d30c43cecd3a861e1672"><td class="mdescLeft"> </td><td class="mdescRight">Store-Release (32 bit) <br /></td></tr>
221 <tr class="separator:ga5429d7083fb8d30c43cecd3a861e1672"><td class="memSeparator" colspan="2"> </td></tr>
222 <tr class="memitem:gace025d3a1f85d2ab9bae7288838d6bc8"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gace025d3a1f85d2ab9bae7288838d6bc8">__STLB</a> (uint8_t value, volatile uint8_t *ptr)</td></tr>
223 <tr class="memdesc:gace025d3a1f85d2ab9bae7288838d6bc8"><td class="mdescLeft"> </td><td class="mdescRight">Store-Release (8 bit) <br /></td></tr>
224 <tr class="separator:gace025d3a1f85d2ab9bae7288838d6bc8"><td class="memSeparator" colspan="2"> </td></tr>
225 <tr class="memitem:gae7f955b91595cfd82a03e4b437c59afe"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gae7f955b91595cfd82a03e4b437c59afe">__STLEX</a> (uint32_t value, volatile uint32_t *ptr)</td></tr>
226 <tr class="memdesc:gae7f955b91595cfd82a03e4b437c59afe"><td class="mdescLeft"> </td><td class="mdescRight">Store-Release Exclusive (32 bit) <br /></td></tr>
227 <tr class="separator:gae7f955b91595cfd82a03e4b437c59afe"><td class="memSeparator" colspan="2"> </td></tr>
228 <tr class="memitem:ga590724a32a229978536fbbbd6cc82536"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga590724a32a229978536fbbbd6cc82536">__STLEXB</a> (uint8_t value, volatile uint8_t *ptr)</td></tr>
229 <tr class="memdesc:ga590724a32a229978536fbbbd6cc82536"><td class="mdescLeft"> </td><td class="mdescRight">Store-Release Exclusive (8 bit) <br /></td></tr>
230 <tr class="separator:ga590724a32a229978536fbbbd6cc82536"><td class="memSeparator" colspan="2"> </td></tr>
231 <tr class="memitem:ga047c3bebca3d0ae348ab8370a046301d"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga047c3bebca3d0ae348ab8370a046301d">__STLEXH</a> (uint16_t value, volatile uint16_t *ptr)</td></tr>
232 <tr class="memdesc:ga047c3bebca3d0ae348ab8370a046301d"><td class="mdescLeft"> </td><td class="mdescRight">Store-Release Exclusive (16 bit) <br /></td></tr>
233 <tr class="separator:ga047c3bebca3d0ae348ab8370a046301d"><td class="memSeparator" colspan="2"> </td></tr>
234 <tr class="memitem:ga25691650de536f9b248b15f6dc4a3e70"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga25691650de536f9b248b15f6dc4a3e70">__STLH</a> (uint16_t value, volatile uint16_t *ptr)</td></tr>
235 <tr class="memdesc:ga25691650de536f9b248b15f6dc4a3e70"><td class="mdescLeft"> </td><td class="mdescRight">Store-Release (16 bit) <br /></td></tr>
236 <tr class="separator:ga25691650de536f9b248b15f6dc4a3e70"><td class="memSeparator" colspan="2"> </td></tr>
237 <tr class="memitem:gad41aa59c92c0a165b7f98428d3320cd5"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gad41aa59c92c0a165b7f98428d3320cd5">__STRBT</a> (uint8_t value, uint8_t ptr)</td></tr>
238 <tr class="memdesc:gad41aa59c92c0a165b7f98428d3320cd5"><td class="mdescLeft"> </td><td class="mdescRight">STRT Unprivileged (8 bit) <br /></td></tr>
239 <tr class="separator:gad41aa59c92c0a165b7f98428d3320cd5"><td class="memSeparator" colspan="2"> </td></tr>
240 <tr class="memitem:gaab6482d1f59f59e2b6b7efc1af391c99"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gaab6482d1f59f59e2b6b7efc1af391c99">__STREXB</a> (uint8_t value, volatile uint8_t *addr)</td></tr>
241 <tr class="memdesc:gaab6482d1f59f59e2b6b7efc1af391c99"><td class="mdescLeft"> </td><td class="mdescRight">STR Exclusive (8 bit) [not for Cortex-M0, Cortex-M0+, or SC000]. <br /></td></tr>
242 <tr class="separator:gaab6482d1f59f59e2b6b7efc1af391c99"><td class="memSeparator" colspan="2"> </td></tr>
243 <tr class="memitem:ga0a354bdf71caa52f081a4a54e84c8d2a"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga0a354bdf71caa52f081a4a54e84c8d2a">__STREXH</a> (uint16_t value, volatile uint16_t *addr)</td></tr>
244 <tr class="memdesc:ga0a354bdf71caa52f081a4a54e84c8d2a"><td class="mdescLeft"> </td><td class="mdescRight">STR Exclusive (16 bit) [not for Cortex-M0, Cortex-M0+, or SC000]. <br /></td></tr>
245 <tr class="separator:ga0a354bdf71caa52f081a4a54e84c8d2a"><td class="memSeparator" colspan="2"> </td></tr>
246 <tr class="memitem:ga335deaaa7991490e1450cb7d1e4c5197"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga335deaaa7991490e1450cb7d1e4c5197">__STREXW</a> (uint32_t value, volatile uint32_t *addr)</td></tr>
247 <tr class="memdesc:ga335deaaa7991490e1450cb7d1e4c5197"><td class="mdescLeft"> </td><td class="mdescRight">STR Exclusive (32 bit) [not for Cortex-M0, Cortex-M0+, or SC000]. <br /></td></tr>
248 <tr class="separator:ga335deaaa7991490e1450cb7d1e4c5197"><td class="memSeparator" colspan="2"> </td></tr>
249 <tr class="memitem:ga2b5d93b8e461755b1072a03df3f1722e"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga2b5d93b8e461755b1072a03df3f1722e">__STRHT</a> (uint16_t value, uint16_t ptr)</td></tr>
250 <tr class="memdesc:ga2b5d93b8e461755b1072a03df3f1722e"><td class="mdescLeft"> </td><td class="mdescRight">STRT Unprivileged (16 bit) <br /></td></tr>
251 <tr class="separator:ga2b5d93b8e461755b1072a03df3f1722e"><td class="memSeparator" colspan="2"> </td></tr>
252 <tr class="memitem:ga625bc4ac0b1d50de9bcd13d9f050030e"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga625bc4ac0b1d50de9bcd13d9f050030e">__STRT</a> (uint32_t value, uint32_t ptr)</td></tr>
253 <tr class="memdesc:ga625bc4ac0b1d50de9bcd13d9f050030e"><td class="mdescLeft"> </td><td class="mdescRight">STRT Unprivileged (32 bit) <br /></td></tr>
254 <tr class="separator:ga625bc4ac0b1d50de9bcd13d9f050030e"><td class="memSeparator" colspan="2"> </td></tr>
255 <tr class="memitem:ga9ba87371aebd17dd6244ed3458b29b5d"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga9ba87371aebd17dd6244ed3458b29b5d">__USAT</a> (int32_t value, uint32_t sat)</td></tr>
256 <tr class="memdesc:ga9ba87371aebd17dd6244ed3458b29b5d"><td class="mdescLeft"> </td><td class="mdescRight">Unsigned Saturate. <br /></td></tr>
257 <tr class="separator:ga9ba87371aebd17dd6244ed3458b29b5d"><td class="memSeparator" colspan="2"> </td></tr>
258 <tr class="memitem:gad3efec76c3bfa2b8528ded530386c563"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gad3efec76c3bfa2b8528ded530386c563">__WFE</a> (void)</td></tr>
259 <tr class="memdesc:gad3efec76c3bfa2b8528ded530386c563"><td class="mdescLeft"> </td><td class="mdescRight">Wait For Event. <br /></td></tr>
260 <tr class="separator:gad3efec76c3bfa2b8528ded530386c563"><td class="memSeparator" colspan="2"> </td></tr>
261 <tr class="memitem:gaed91dfbf3d7d7b7fba8d912fcbeaad88"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gaed91dfbf3d7d7b7fba8d912fcbeaad88">__WFI</a> (void)</td></tr>
262 <tr class="memdesc:gaed91dfbf3d7d7b7fba8d912fcbeaad88"><td class="mdescLeft"> </td><td class="mdescRight">Wait For Interrupt. <br /></td></tr>
263 <tr class="separator:gaed91dfbf3d7d7b7fba8d912fcbeaad88"><td class="memSeparator" colspan="2"> </td></tr>
265 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
266 <p>Functions that generate specific Cortex-M CPU Instructions. </p>
267 <p>The following functions generate specific Cortex-M instructions that cannot be directly accessed by the C/C++ Compiler. Refer to the <a class="el" href="index.html#ref_man_sec">Cortex-M Generic User Guides</a> for detailed information about these Cortex-M instructions.</p>
268 <dl class="section note"><dt>Note</dt><dd>When using the <b>Arm Compiler Version 5 Toolchain</b> the following <a class="el" href="group__intrinsic__CPU__gr.html">Intrinsic Functions for CPU Instructions</a> are implemented using the Embedded Assembler. As the Embedded Assembler may cause side effects (Refer to <b>Arm Compiler v5.xx User Guide - Using the Inline and Embedded Assemblers of the Arm Compiler</b> for more information) it is possible to disable the following intrinsic functions and therefore the usage of the Embedded Assembler with the <b><em>define __NO_EMBEDDED_ASM</em></b>:<ul>
269 <li><a class="el" href="group__intrinsic__CPU__gr.html#gaeef6f853b6df3a365c838ee5b49a7a26">__REV16</a></li>
270 <li><a class="el" href="group__intrinsic__CPU__gr.html#ga211618c03a0bf3264a7b22ad626d4f0a">__REVSH</a></li>
271 <li><a class="el" href="group__intrinsic__CPU__gr.html#gac09134f1bf9c49db07282001afcc9380">__RRX</a> </li>
274 <h2 class="groupheader">Function Documentation</h2>
275 <a id="ga92f5621626711931da71eaa8bf301af7" name="ga92f5621626711931da71eaa8bf301af7"></a>
276 <h2 class="memtitle"><span class="permalink"><a href="#ga92f5621626711931da71eaa8bf301af7">◆ </a></span>__BKPT()</h2>
278 <div class="memitem">
279 <div class="memproto">
280 <table class="memname">
282 <td class="memname">void __BKPT </td>
284 <td class="paramtype">uint8_t </td>
285 <td class="paramname"><em>value</em></td><td>)</td>
289 </div><div class="memdoc">
291 <p>Set Breakpoint. </p>
292 <p>This function causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached.</p>
293 <dl class="params"><dt>Parameters</dt><dd>
294 <table class="params">
295 <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>is ignored by the processor. If required, a debugger can use it to obtain additional information about the breakpoint. </td></tr>
302 <a id="ga354c5ac8870cc3dfb823367af9c4b412" name="ga354c5ac8870cc3dfb823367af9c4b412"></a>
303 <h2 class="memtitle"><span class="permalink"><a href="#ga354c5ac8870cc3dfb823367af9c4b412">◆ </a></span>__CLREX()</h2>
305 <div class="memitem">
306 <div class="memproto">
307 <table class="memname">
309 <td class="memname">void __CLREX </td>
311 <td class="paramtype">void </td>
312 <td class="paramname"></td><td>)</td>
316 </div><div class="memdoc">
318 <p>Remove the exclusive lock [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
319 <p>This function removes the exclusive lock which is created by LDREX [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
323 <a id="ga90884c591ac5d73d6069334eba9d6c02" name="ga90884c591ac5d73d6069334eba9d6c02"></a>
324 <h2 class="memtitle"><span class="permalink"><a href="#ga90884c591ac5d73d6069334eba9d6c02">◆ </a></span>__CLZ()</h2>
326 <div class="memitem">
327 <div class="memproto">
328 <table class="memname">
330 <td class="memname">uint8_t __CLZ </td>
332 <td class="paramtype">uint32_t </td>
333 <td class="paramname"><em>value</em></td><td>)</td>
337 </div><div class="memdoc">
339 <p>Count leading zeros. </p>
340 <p>This function counts the number of leading zeros of a data value.</p>
341 <p>On Armv6-M (Cortex-M0, Cortex-M0+, and SC000) this function is not available as a core instruction instruction and thus __CLZ is implemented in software.</p>
342 <dl class="params"><dt>Parameters</dt><dd>
343 <table class="params">
344 <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to count the leading zeros </td></tr>
348 <dl class="section return"><dt>Returns</dt><dd>number of leading zeros in value </dd></dl>
352 <a id="gab1c9b393641dc2d397b3408fdbe72b96" name="gab1c9b393641dc2d397b3408fdbe72b96"></a>
353 <h2 class="memtitle"><span class="permalink"><a href="#gab1c9b393641dc2d397b3408fdbe72b96">◆ </a></span>__DMB()</h2>
355 <div class="memitem">
356 <div class="memproto">
357 <table class="memname">
359 <td class="memname">void __DMB </td>
361 <td class="paramtype">void </td>
362 <td class="paramname"></td><td>)</td>
366 </div><div class="memdoc">
368 <p>Data Memory Barrier. </p>
369 <p>This function ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. </p>
373 <a id="gacb2a8ca6eae1ba4b31161578b720c199" name="gacb2a8ca6eae1ba4b31161578b720c199"></a>
374 <h2 class="memtitle"><span class="permalink"><a href="#gacb2a8ca6eae1ba4b31161578b720c199">◆ </a></span>__DSB()</h2>
376 <div class="memitem">
377 <div class="memproto">
378 <table class="memname">
380 <td class="memname">void __DSB </td>
382 <td class="paramtype">void </td>
383 <td class="paramname"></td><td>)</td>
387 </div><div class="memdoc">
389 <p>Data Synchronization Barrier. </p>
390 <p>This function acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. </p>
394 <a id="ga93c09b4709394d81977300d5f84950e5" name="ga93c09b4709394d81977300d5f84950e5"></a>
395 <h2 class="memtitle"><span class="permalink"><a href="#ga93c09b4709394d81977300d5f84950e5">◆ </a></span>__ISB()</h2>
397 <div class="memitem">
398 <div class="memproto">
399 <table class="memname">
401 <td class="memname">void __ISB </td>
403 <td class="paramtype">void </td>
404 <td class="paramname"></td><td>)</td>
408 </div><div class="memdoc">
410 <p>Instruction Synchronization Barrier. </p>
411 <p>Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. </p>
415 <a id="ga22a24f416b65c2f5a82d9f1162d9394d" name="ga22a24f416b65c2f5a82d9f1162d9394d"></a>
416 <h2 class="memtitle"><span class="permalink"><a href="#ga22a24f416b65c2f5a82d9f1162d9394d">◆ </a></span>__LDA()</h2>
418 <div class="memitem">
419 <div class="memproto">
420 <table class="memname">
422 <td class="memname">uint32_t __LDA </td>
424 <td class="paramtype">volatile uint32_t * </td>
425 <td class="paramname"><em>ptr</em></td><td>)</td>
429 </div><div class="memdoc">
431 <p>Load-Acquire (32 bit) </p>
432 <p>Executes a LDA instruction for 32 bit values. </p><dl class="params"><dt>Parameters</dt><dd>
433 <table class="params">
434 <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to data </td></tr>
438 <dl class="section return"><dt>Returns</dt><dd>value of type uint32_t at (*ptr) </dd></dl>
439 <dl class="section note"><dt>Note</dt><dd>Only available for Armv8-M Architecture. </dd></dl>
443 <a id="ga263b9b2d9c06d731022873acddb6aa3f" name="ga263b9b2d9c06d731022873acddb6aa3f"></a>
444 <h2 class="memtitle"><span class="permalink"><a href="#ga263b9b2d9c06d731022873acddb6aa3f">◆ </a></span>__LDAB()</h2>
446 <div class="memitem">
447 <div class="memproto">
448 <table class="memname">
450 <td class="memname">uint8_t __LDAB </td>
452 <td class="paramtype">volatile uint8_t * </td>
453 <td class="paramname"><em>ptr</em></td><td>)</td>
457 </div><div class="memdoc">
459 <p>Load-Acquire (8 bit) </p>
460 <p>Executes a LDAB instruction for 8 bit value. </p><dl class="params"><dt>Parameters</dt><dd>
461 <table class="params">
462 <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to data </td></tr>
466 <dl class="section return"><dt>Returns</dt><dd>value of type uint8_t at (*ptr) </dd></dl>
467 <dl class="section note"><dt>Note</dt><dd>Only available for Armv8-M Architecture. </dd></dl>
471 <a id="ga3c74d923529f664eda099d1b2668b3c1" name="ga3c74d923529f664eda099d1b2668b3c1"></a>
472 <h2 class="memtitle"><span class="permalink"><a href="#ga3c74d923529f664eda099d1b2668b3c1">◆ </a></span>__LDAEX()</h2>
474 <div class="memitem">
475 <div class="memproto">
476 <table class="memname">
478 <td class="memname">uint32_t __LDAEX </td>
480 <td class="paramtype">volatile uint32_t * </td>
481 <td class="paramname"><em>ptr</em></td><td>)</td>
485 </div><div class="memdoc">
487 <p>Load-Acquire Exclusive (32 bit) </p>
488 <p>Executes a LDA exclusive instruction for 32 bit values. </p><dl class="params"><dt>Parameters</dt><dd>
489 <table class="params">
490 <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to data </td></tr>
494 <dl class="section return"><dt>Returns</dt><dd>value of type uint32_t at (*ptr) </dd></dl>
495 <dl class="section note"><dt>Note</dt><dd>Only available for Armv8-M Architecture. </dd></dl>
499 <a id="ga513beada40cdd7123281f22482603bcc" name="ga513beada40cdd7123281f22482603bcc"></a>
500 <h2 class="memtitle"><span class="permalink"><a href="#ga513beada40cdd7123281f22482603bcc">◆ </a></span>__LDAEXB()</h2>
502 <div class="memitem">
503 <div class="memproto">
504 <table class="memname">
506 <td class="memname">uint8_t __LDAEXB </td>
508 <td class="paramtype">volatile uint32_t * </td>
509 <td class="paramname"><em>ptr</em></td><td>)</td>
513 </div><div class="memdoc">
515 <p>Load-Acquire Exclusive (8 bit) </p>
516 <p>Executes a LDAB exclusive instruction for 8 bit value. </p><dl class="params"><dt>Parameters</dt><dd>
517 <table class="params">
518 <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to data </td></tr>
522 <dl class="section return"><dt>Returns</dt><dd>value of type uint8_t at (*ptr) </dd></dl>
523 <dl class="section note"><dt>Note</dt><dd>Only available for Armv8-M Architecture. </dd></dl>
527 <a id="ga426b61640fc68f21b21ae4dc2726f3b4" name="ga426b61640fc68f21b21ae4dc2726f3b4"></a>
528 <h2 class="memtitle"><span class="permalink"><a href="#ga426b61640fc68f21b21ae4dc2726f3b4">◆ </a></span>__LDAEXH()</h2>
530 <div class="memitem">
531 <div class="memproto">
532 <table class="memname">
534 <td class="memname">uint16_t __LDAEXH </td>
536 <td class="paramtype">volatile uint32_t * </td>
537 <td class="paramname"><em>ptr</em></td><td>)</td>
541 </div><div class="memdoc">
543 <p>Load-Acquire Exclusive (16 bit) </p>
544 <p>Executes a LDAH exclusive instruction for 16 bit values. </p><dl class="params"><dt>Parameters</dt><dd>
545 <table class="params">
546 <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to data </td></tr>
550 <dl class="section return"><dt>Returns</dt><dd>value of type uint16_t at (*ptr) </dd></dl>
551 <dl class="section note"><dt>Note</dt><dd>Only available for Armv8-M Architecture. </dd></dl>
555 <a id="ga5810ac0b87a37e321c2f909cd3860499" name="ga5810ac0b87a37e321c2f909cd3860499"></a>
556 <h2 class="memtitle"><span class="permalink"><a href="#ga5810ac0b87a37e321c2f909cd3860499">◆ </a></span>__LDAH()</h2>
558 <div class="memitem">
559 <div class="memproto">
560 <table class="memname">
562 <td class="memname">uint16_t __LDAH </td>
564 <td class="paramtype">volatile uint16_t * </td>
565 <td class="paramname"><em>ptr</em></td><td>)</td>
569 </div><div class="memdoc">
571 <p>Load-Acquire (16 bit) </p>
572 <p>Executes a LDAH instruction for 16 bit values. </p><dl class="params"><dt>Parameters</dt><dd>
573 <table class="params">
574 <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to data </td></tr>
578 <dl class="section return"><dt>Returns</dt><dd>value of type uint16_t at (*ptr) </dd></dl>
579 <dl class="section note"><dt>Note</dt><dd>Only available for Armv8-M Architecture. </dd></dl>
583 <a id="ga9464d75db32846aa8295c3c3adfacb41" name="ga9464d75db32846aa8295c3c3adfacb41"></a>
584 <h2 class="memtitle"><span class="permalink"><a href="#ga9464d75db32846aa8295c3c3adfacb41">◆ </a></span>__LDRBT()</h2>
586 <div class="memitem">
587 <div class="memproto">
588 <table class="memname">
590 <td class="memname">uint8_t __LDRBT </td>
592 <td class="paramtype">uint8_t </td>
593 <td class="paramname"><em>ptr</em></td><td>)</td>
597 </div><div class="memdoc">
599 <p>LDRT Unprivileged (8 bit) </p>
600 <p>This function executed an Unprivileged LDRT command for 8 bit value.</p>
601 <dl class="params"><dt>Parameters</dt><dd>
602 <table class="params">
603 <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to data </td></tr>
607 <dl class="section return"><dt>Returns</dt><dd>value of type uint8_t at (*ptr) </dd></dl>
611 <a id="ga9e3ac13d8dcf4331176b624cf6234a7e" name="ga9e3ac13d8dcf4331176b624cf6234a7e"></a>
612 <h2 class="memtitle"><span class="permalink"><a href="#ga9e3ac13d8dcf4331176b624cf6234a7e">◆ </a></span>__LDREXB()</h2>
614 <div class="memitem">
615 <div class="memproto">
616 <table class="memname">
618 <td class="memname">uint8_t __LDREXB </td>
620 <td class="paramtype">volatile uint8_t * </td>
621 <td class="paramname"><em>addr</em></td><td>)</td>
625 </div><div class="memdoc">
627 <p>LDR Exclusive (8 bit) [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
628 <p>This function executed an exclusive LDR command for 8 bit value [not for Cortex-M0, Cortex-M0+, or SC000].</p>
629 <dl class="params"><dt>Parameters</dt><dd>
630 <table class="params">
631 <tr><td class="paramdir">[in]</td><td class="paramname">*addr</td><td>Pointer to data </td></tr>
635 <dl class="section return"><dt>Returns</dt><dd>value of type uint8_t at (*addr) </dd></dl>
639 <a id="ga9feffc093d6f68b120d592a7a0d45a15" name="ga9feffc093d6f68b120d592a7a0d45a15"></a>
640 <h2 class="memtitle"><span class="permalink"><a href="#ga9feffc093d6f68b120d592a7a0d45a15">◆ </a></span>__LDREXH()</h2>
642 <div class="memitem">
643 <div class="memproto">
644 <table class="memname">
646 <td class="memname">uint16_t __LDREXH </td>
648 <td class="paramtype">volatile uint16_t * </td>
649 <td class="paramname"><em>addr</em></td><td>)</td>
653 </div><div class="memdoc">
655 <p>LDR Exclusive (16 bit) [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
656 <p>This function executed an exclusive LDR command for 16 bit values [not for Cortex-M0, Cortex-M0+, or SC000].</p>
657 <dl class="params"><dt>Parameters</dt><dd>
658 <table class="params">
659 <tr><td class="paramdir">[in]</td><td class="paramname">*addr</td><td>Pointer to data </td></tr>
663 <dl class="section return"><dt>Returns</dt><dd>value of type uint16_t at (*addr) </dd></dl>
667 <a id="gabd78840a0f2464905b7cec791ebc6a4c" name="gabd78840a0f2464905b7cec791ebc6a4c"></a>
668 <h2 class="memtitle"><span class="permalink"><a href="#gabd78840a0f2464905b7cec791ebc6a4c">◆ </a></span>__LDREXW()</h2>
670 <div class="memitem">
671 <div class="memproto">
672 <table class="memname">
674 <td class="memname">uint32_t __LDREXW </td>
676 <td class="paramtype">volatile uint32_t * </td>
677 <td class="paramname"><em>addr</em></td><td>)</td>
681 </div><div class="memdoc">
683 <p>LDR Exclusive (32 bit) [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
684 <p>This function executed an exclusive LDR command for 32 bit values [not for Cortex-M0, Cortex-M0+, or SC000].</p>
685 <dl class="params"><dt>Parameters</dt><dd>
686 <table class="params">
687 <tr><td class="paramdir">[in]</td><td class="paramname">*addr</td><td>Pointer to data </td></tr>
691 <dl class="section return"><dt>Returns</dt><dd>value of type uint32_t at (*addr) </dd></dl>
695 <a id="gaa762b8bc5634ce38cb14d62a6b2aee32" name="gaa762b8bc5634ce38cb14d62a6b2aee32"></a>
696 <h2 class="memtitle"><span class="permalink"><a href="#gaa762b8bc5634ce38cb14d62a6b2aee32">◆ </a></span>__LDRHT()</h2>
698 <div class="memitem">
699 <div class="memproto">
700 <table class="memname">
702 <td class="memname">uint16_t __LDRHT </td>
704 <td class="paramtype">uint16_t </td>
705 <td class="paramname"><em>ptr</em></td><td>)</td>
709 </div><div class="memdoc">
711 <p>LDRT Unprivileged (16 bit) </p>
712 <p>This function executed an Unprivileged LDRT command for 16 bit values.</p>
713 <dl class="params"><dt>Parameters</dt><dd>
714 <table class="params">
715 <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to data </td></tr>
719 <dl class="section return"><dt>Returns</dt><dd>value of type uint16_t at (*ptr) </dd></dl>
723 <a id="ga616504f5da979ba8a073d428d6e8d5c7" name="ga616504f5da979ba8a073d428d6e8d5c7"></a>
724 <h2 class="memtitle"><span class="permalink"><a href="#ga616504f5da979ba8a073d428d6e8d5c7">◆ </a></span>__LDRT()</h2>
726 <div class="memitem">
727 <div class="memproto">
728 <table class="memname">
730 <td class="memname">uint32_t __LDRT </td>
732 <td class="paramtype">uint32_t </td>
733 <td class="paramname"><em>ptr</em></td><td>)</td>
737 </div><div class="memdoc">
739 <p>LDRT Unprivileged (32 bit) </p>
740 <p>This function executed an Unprivileged LDRT command for 32 bit values.</p>
741 <dl class="params"><dt>Parameters</dt><dd>
742 <table class="params">
743 <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to data </td></tr>
747 <dl class="section return"><dt>Returns</dt><dd>value of type uint32_t at (*ptr) </dd></dl>
751 <a id="gac71fad9f0a91980fecafcb450ee0a63e" name="gac71fad9f0a91980fecafcb450ee0a63e"></a>
752 <h2 class="memtitle"><span class="permalink"><a href="#gac71fad9f0a91980fecafcb450ee0a63e">◆ </a></span>__NOP()</h2>
754 <div class="memitem">
755 <div class="memproto">
756 <table class="memname">
758 <td class="memname">void __NOP </td>
760 <td class="paramtype">void </td>
761 <td class="paramname"></td><td>)</td>
765 </div><div class="memdoc">
767 <p>No Operation. </p>
768 <p>This function does nothing. This instruction can be used for code alignment purposes. </p>
772 <a id="gad6f9f297f6b91a995ee199fbc796b863" name="gad6f9f297f6b91a995ee199fbc796b863"></a>
773 <h2 class="memtitle"><span class="permalink"><a href="#gad6f9f297f6b91a995ee199fbc796b863">◆ </a></span>__RBIT()</h2>
775 <div class="memitem">
776 <div class="memproto">
777 <table class="memname">
779 <td class="memname">uint32_t __RBIT </td>
781 <td class="paramtype">uint32_t </td>
782 <td class="paramname"><em>value</em></td><td>)</td>
786 </div><div class="memdoc">
788 <p>Reverse bit order of value. </p>
789 <dl class="params"><dt>Parameters</dt><dd>
790 <table class="params">
791 <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr>
795 <dl class="section return"><dt>Returns</dt><dd>Reversed value </dd></dl>
799 <a id="ga4717abc17af5ba29b1e4c055e0a0d9b8" name="ga4717abc17af5ba29b1e4c055e0a0d9b8"></a>
800 <h2 class="memtitle"><span class="permalink"><a href="#ga4717abc17af5ba29b1e4c055e0a0d9b8">◆ </a></span>__REV()</h2>
802 <div class="memitem">
803 <div class="memproto">
804 <table class="memname">
806 <td class="memname">uint32_t __REV </td>
808 <td class="paramtype">uint32_t </td>
809 <td class="paramname"><em>value</em></td><td>)</td>
813 </div><div class="memdoc">
815 <p>Reverse byte order (32 bit) </p>
816 <p>Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. </p><dl class="params"><dt>Parameters</dt><dd>
817 <table class="params">
818 <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr>
822 <dl class="section return"><dt>Returns</dt><dd>Reversed value </dd></dl>
826 <a id="gaeef6f853b6df3a365c838ee5b49a7a26" name="gaeef6f853b6df3a365c838ee5b49a7a26"></a>
827 <h2 class="memtitle"><span class="permalink"><a href="#gaeef6f853b6df3a365c838ee5b49a7a26">◆ </a></span>__REV16()</h2>
829 <div class="memitem">
830 <div class="memproto">
831 <table class="memname">
833 <td class="memname">uint32_t __REV16 </td>
835 <td class="paramtype">uint32_t </td>
836 <td class="paramname"><em>value</em></td><td>)</td>
840 </div><div class="memdoc">
842 <p>Reverse byte order (16 bit) </p>
843 <p>Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. </p><dl class="params"><dt>Parameters</dt><dd>
844 <table class="params">
845 <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr>
849 <dl class="section return"><dt>Returns</dt><dd>Reversed value </dd></dl>
853 <a id="ga211618c03a0bf3264a7b22ad626d4f0a" name="ga211618c03a0bf3264a7b22ad626d4f0a"></a>
854 <h2 class="memtitle"><span class="permalink"><a href="#ga211618c03a0bf3264a7b22ad626d4f0a">◆ </a></span>__REVSH()</h2>
856 <div class="memitem">
857 <div class="memproto">
858 <table class="memname">
860 <td class="memname">int16_t __REVSH </td>
862 <td class="paramtype">int16_t </td>
863 <td class="paramname"><em>value</em></td><td>)</td>
867 </div><div class="memdoc">
869 <p>Reverse byte order (16 bit) </p>
870 <p>Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. </p><dl class="params"><dt>Parameters</dt><dd>
871 <table class="params">
872 <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr>
876 <dl class="section return"><dt>Returns</dt><dd>Reversed value </dd></dl>
880 <a id="gaf66beb577bb9d90424c3d1d7f684c024" name="gaf66beb577bb9d90424c3d1d7f684c024"></a>
881 <h2 class="memtitle"><span class="permalink"><a href="#gaf66beb577bb9d90424c3d1d7f684c024">◆ </a></span>__ROR()</h2>
883 <div class="memitem">
884 <div class="memproto">
885 <table class="memname">
887 <td class="memname">uint32_t __ROR </td>
889 <td class="paramtype">uint32_t </td>
890 <td class="paramname"><em>value</em>, </td>
893 <td class="paramkey"></td>
895 <td class="paramtype">uint32_t </td>
896 <td class="paramname"><em>shift</em> </td>
904 </div><div class="memdoc">
906 <p>Rotate a value right by a number of bits. </p>
907 <p>This function rotates a value right by a specified number of bits.</p>
908 <dl class="params"><dt>Parameters</dt><dd>
909 <table class="params">
910 <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to be shifted right </td></tr>
911 <tr><td class="paramdir">[in]</td><td class="paramname">shift</td><td>Number of bits in the range [1..31] </td></tr>
915 <dl class="section return"><dt>Returns</dt><dd>Rotated value </dd></dl>
919 <a id="gac09134f1bf9c49db07282001afcc9380" name="gac09134f1bf9c49db07282001afcc9380"></a>
920 <h2 class="memtitle"><span class="permalink"><a href="#gac09134f1bf9c49db07282001afcc9380">◆ </a></span>__RRX()</h2>
922 <div class="memitem">
923 <div class="memproto">
924 <table class="memname">
926 <td class="memname">uint32_t __RRX </td>
928 <td class="paramtype">uint32_t </td>
929 <td class="paramname"><em>value</em></td><td>)</td>
933 </div><div class="memdoc">
935 <p>Rotate Right with Extend (32 bit) </p>
936 <p>This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.</p>
937 <dl class="params"><dt>Parameters</dt><dd>
938 <table class="params">
939 <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to rotate </td></tr>
943 <dl class="section return"><dt>Returns</dt><dd>Rotated value </dd></dl>
947 <a id="ga3c34da7eb16496ae2668a5b95fa441e7" name="ga3c34da7eb16496ae2668a5b95fa441e7"></a>
948 <h2 class="memtitle"><span class="permalink"><a href="#ga3c34da7eb16496ae2668a5b95fa441e7">◆ </a></span>__SEV()</h2>
950 <div class="memitem">
951 <div class="memproto">
952 <table class="memname">
954 <td class="memname">void __SEV </td>
956 <td class="paramtype">void </td>
957 <td class="paramname"></td><td>)</td>
961 </div><div class="memdoc">
964 <p>Send Event is a hint instruction. It causes an event to be signaled to the CPU. </p>
968 <a id="ga8cfeb5ffe0e49ec6b29dafdde92e5118" name="ga8cfeb5ffe0e49ec6b29dafdde92e5118"></a>
969 <h2 class="memtitle"><span class="permalink"><a href="#ga8cfeb5ffe0e49ec6b29dafdde92e5118">◆ </a></span>__SSAT()</h2>
971 <div class="memitem">
972 <div class="memproto">
973 <table class="memname">
975 <td class="memname">int32_t __SSAT </td>
977 <td class="paramtype">int32_t </td>
978 <td class="paramname"><em>value</em>, </td>
981 <td class="paramkey"></td>
983 <td class="paramtype">uint32_t </td>
984 <td class="paramname"><em>sat</em> </td>
992 </div><div class="memdoc">
994 <p>Signed Saturate. </p>
995 <p>This function saturates a signed value. The Q bit is set if saturation occurs [not for Cortex-M0, Cortex-M0+, or SC000].</p>
996 <p>On Armv6-M (Cortex-M0, Cortex-M0+, and SC000) this function is not available as a core instruction instruction and thus __SSAT is implemented in software.</p>
997 <dl class="params"><dt>Parameters</dt><dd>
998 <table class="params">
999 <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to be saturated </td></tr>
1000 <tr><td class="paramdir">[in]</td><td class="paramname">sat</td><td>Bit position to saturate to [1..32] </td></tr>
1004 <dl class="section return"><dt>Returns</dt><dd>Saturated value </dd></dl>
1008 <a id="ga5429d7083fb8d30c43cecd3a861e1672" name="ga5429d7083fb8d30c43cecd3a861e1672"></a>
1009 <h2 class="memtitle"><span class="permalink"><a href="#ga5429d7083fb8d30c43cecd3a861e1672">◆ </a></span>__STL()</h2>
1011 <div class="memitem">
1012 <div class="memproto">
1013 <table class="memname">
1015 <td class="memname">void __STL </td>
1017 <td class="paramtype">uint32_t </td>
1018 <td class="paramname"><em>value</em>, </td>
1021 <td class="paramkey"></td>
1023 <td class="paramtype">volatile uint32_t * </td>
1024 <td class="paramname"><em>ptr</em> </td>
1032 </div><div class="memdoc">
1034 <p>Store-Release (32 bit) </p>
1035 <p>Executes a STL instruction for 32 bit values. </p><dl class="params"><dt>Parameters</dt><dd>
1036 <table class="params">
1037 <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr>
1038 <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to location </td></tr>
1042 <dl class="section note"><dt>Note</dt><dd>Only available for Armv8-M Architecture. </dd></dl>
1046 <a id="gace025d3a1f85d2ab9bae7288838d6bc8" name="gace025d3a1f85d2ab9bae7288838d6bc8"></a>
1047 <h2 class="memtitle"><span class="permalink"><a href="#gace025d3a1f85d2ab9bae7288838d6bc8">◆ </a></span>__STLB()</h2>
1049 <div class="memitem">
1050 <div class="memproto">
1051 <table class="memname">
1053 <td class="memname">void __STLB </td>
1055 <td class="paramtype">uint8_t </td>
1056 <td class="paramname"><em>value</em>, </td>
1059 <td class="paramkey"></td>
1061 <td class="paramtype">volatile uint8_t * </td>
1062 <td class="paramname"><em>ptr</em> </td>
1070 </div><div class="memdoc">
1072 <p>Store-Release (8 bit) </p>
1073 <p>Executes a STLB instruction for 8 bit values. </p><dl class="params"><dt>Parameters</dt><dd>
1074 <table class="params">
1075 <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr>
1076 <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to location </td></tr>
1080 <dl class="section note"><dt>Note</dt><dd>Only available for Armv8-M Architecture. </dd></dl>
1084 <a id="gae7f955b91595cfd82a03e4b437c59afe" name="gae7f955b91595cfd82a03e4b437c59afe"></a>
1085 <h2 class="memtitle"><span class="permalink"><a href="#gae7f955b91595cfd82a03e4b437c59afe">◆ </a></span>__STLEX()</h2>
1087 <div class="memitem">
1088 <div class="memproto">
1089 <table class="memname">
1091 <td class="memname">uint32_t __STLEX </td>
1093 <td class="paramtype">uint32_t </td>
1094 <td class="paramname"><em>value</em>, </td>
1097 <td class="paramkey"></td>
1099 <td class="paramtype">volatile uint32_t * </td>
1100 <td class="paramname"><em>ptr</em> </td>
1108 </div><div class="memdoc">
1110 <p>Store-Release Exclusive (32 bit) </p>
1111 <p>Executes a STL exclusive instruction for 32 bit values. </p><dl class="params"><dt>Parameters</dt><dd>
1112 <table class="params">
1113 <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr>
1114 <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to location </td></tr>
1118 <dl class="section return"><dt>Returns</dt><dd>0 Function succeeded </dd>
1120 1 Function failed </dd></dl>
1121 <dl class="section note"><dt>Note</dt><dd>Only available for Armv8-M Architecture. </dd></dl>
1125 <a id="ga590724a32a229978536fbbbd6cc82536" name="ga590724a32a229978536fbbbd6cc82536"></a>
1126 <h2 class="memtitle"><span class="permalink"><a href="#ga590724a32a229978536fbbbd6cc82536">◆ </a></span>__STLEXB()</h2>
1128 <div class="memitem">
1129 <div class="memproto">
1130 <table class="memname">
1132 <td class="memname">uint32_t __STLEXB </td>
1134 <td class="paramtype">uint8_t </td>
1135 <td class="paramname"><em>value</em>, </td>
1138 <td class="paramkey"></td>
1140 <td class="paramtype">volatile uint8_t * </td>
1141 <td class="paramname"><em>ptr</em> </td>
1149 </div><div class="memdoc">
1151 <p>Store-Release Exclusive (8 bit) </p>
1152 <p>Executes a STLB exclusive instruction for 8 bit values. </p><dl class="params"><dt>Parameters</dt><dd>
1153 <table class="params">
1154 <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr>
1155 <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to location </td></tr>
1159 <dl class="section return"><dt>Returns</dt><dd>0 Function succeeded </dd>
1161 1 Function failed </dd></dl>
1162 <dl class="section note"><dt>Note</dt><dd>Only available for Armv8-M Architecture. </dd></dl>
1166 <a id="ga047c3bebca3d0ae348ab8370a046301d" name="ga047c3bebca3d0ae348ab8370a046301d"></a>
1167 <h2 class="memtitle"><span class="permalink"><a href="#ga047c3bebca3d0ae348ab8370a046301d">◆ </a></span>__STLEXH()</h2>
1169 <div class="memitem">
1170 <div class="memproto">
1171 <table class="memname">
1173 <td class="memname">uint32_t __STLEXH </td>
1175 <td class="paramtype">uint16_t </td>
1176 <td class="paramname"><em>value</em>, </td>
1179 <td class="paramkey"></td>
1181 <td class="paramtype">volatile uint16_t * </td>
1182 <td class="paramname"><em>ptr</em> </td>
1190 </div><div class="memdoc">
1192 <p>Store-Release Exclusive (16 bit) </p>
1193 <p>Executes a STLH exclusive instruction for 16 bit values. </p><dl class="params"><dt>Parameters</dt><dd>
1194 <table class="params">
1195 <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr>
1196 <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to location </td></tr>
1200 <dl class="section return"><dt>Returns</dt><dd>0 Function succeeded </dd>
1202 1 Function failed </dd></dl>
1203 <dl class="section note"><dt>Note</dt><dd>Only available for Armv8-M Architecture. </dd></dl>
1207 <a id="ga25691650de536f9b248b15f6dc4a3e70" name="ga25691650de536f9b248b15f6dc4a3e70"></a>
1208 <h2 class="memtitle"><span class="permalink"><a href="#ga25691650de536f9b248b15f6dc4a3e70">◆ </a></span>__STLH()</h2>
1210 <div class="memitem">
1211 <div class="memproto">
1212 <table class="memname">
1214 <td class="memname">void __STLH </td>
1216 <td class="paramtype">uint16_t </td>
1217 <td class="paramname"><em>value</em>, </td>
1220 <td class="paramkey"></td>
1222 <td class="paramtype">volatile uint16_t * </td>
1223 <td class="paramname"><em>ptr</em> </td>
1231 </div><div class="memdoc">
1233 <p>Store-Release (16 bit) </p>
1234 <p>Executes a STLH instruction for 16 bit values. </p><dl class="params"><dt>Parameters</dt><dd>
1235 <table class="params">
1236 <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr>
1237 <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to location </td></tr>
1241 <dl class="section note"><dt>Note</dt><dd>Only available for Armv8-M Architecture. </dd></dl>
1245 <a id="gad41aa59c92c0a165b7f98428d3320cd5" name="gad41aa59c92c0a165b7f98428d3320cd5"></a>
1246 <h2 class="memtitle"><span class="permalink"><a href="#gad41aa59c92c0a165b7f98428d3320cd5">◆ </a></span>__STRBT()</h2>
1248 <div class="memitem">
1249 <div class="memproto">
1250 <table class="memname">
1252 <td class="memname">void __STRBT </td>
1254 <td class="paramtype">uint8_t </td>
1255 <td class="paramname"><em>value</em>, </td>
1258 <td class="paramkey"></td>
1260 <td class="paramtype">uint8_t </td>
1261 <td class="paramname"><em>ptr</em> </td>
1269 </div><div class="memdoc">
1271 <p>STRT Unprivileged (8 bit) </p>
1272 <p>This function executed an Unprivileged STRT command for 8 bit values.</p>
1273 <dl class="params"><dt>Parameters</dt><dd>
1274 <table class="params">
1275 <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr>
1276 <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to location </td></tr>
1283 <a id="gaab6482d1f59f59e2b6b7efc1af391c99" name="gaab6482d1f59f59e2b6b7efc1af391c99"></a>
1284 <h2 class="memtitle"><span class="permalink"><a href="#gaab6482d1f59f59e2b6b7efc1af391c99">◆ </a></span>__STREXB()</h2>
1286 <div class="memitem">
1287 <div class="memproto">
1288 <table class="memname">
1290 <td class="memname">uint32_t __STREXB </td>
1292 <td class="paramtype">uint8_t </td>
1293 <td class="paramname"><em>value</em>, </td>
1296 <td class="paramkey"></td>
1298 <td class="paramtype">volatile uint8_t * </td>
1299 <td class="paramname"><em>addr</em> </td>
1307 </div><div class="memdoc">
1309 <p>STR Exclusive (8 bit) [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
1310 <p>This function executed an exclusive STR command for 8 bit values [not for Cortex-M0, Cortex-M0+, or SC000].</p>
1311 <dl class="params"><dt>Parameters</dt><dd>
1312 <table class="params">
1313 <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr>
1314 <tr><td class="paramdir">[in]</td><td class="paramname">*addr</td><td>Pointer to location </td></tr>
1318 <dl class="section return"><dt>Returns</dt><dd>0 Function succeeded </dd>
1320 1 Function failed </dd></dl>
1324 <a id="ga0a354bdf71caa52f081a4a54e84c8d2a" name="ga0a354bdf71caa52f081a4a54e84c8d2a"></a>
1325 <h2 class="memtitle"><span class="permalink"><a href="#ga0a354bdf71caa52f081a4a54e84c8d2a">◆ </a></span>__STREXH()</h2>
1327 <div class="memitem">
1328 <div class="memproto">
1329 <table class="memname">
1331 <td class="memname">uint32_t __STREXH </td>
1333 <td class="paramtype">uint16_t </td>
1334 <td class="paramname"><em>value</em>, </td>
1337 <td class="paramkey"></td>
1339 <td class="paramtype">volatile uint16_t * </td>
1340 <td class="paramname"><em>addr</em> </td>
1348 </div><div class="memdoc">
1350 <p>STR Exclusive (16 bit) [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
1351 <p>This function executed an exclusive STR command for 16 bit values [not for Cortex-M0, Cortex-M0+, or SC000].</p>
1352 <dl class="params"><dt>Parameters</dt><dd>
1353 <table class="params">
1354 <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr>
1355 <tr><td class="paramdir">[in]</td><td class="paramname">*addr</td><td>Pointer to location </td></tr>
1359 <dl class="section return"><dt>Returns</dt><dd>0 Function succeeded </dd>
1361 1 Function failed </dd></dl>
1365 <a id="ga335deaaa7991490e1450cb7d1e4c5197" name="ga335deaaa7991490e1450cb7d1e4c5197"></a>
1366 <h2 class="memtitle"><span class="permalink"><a href="#ga335deaaa7991490e1450cb7d1e4c5197">◆ </a></span>__STREXW()</h2>
1368 <div class="memitem">
1369 <div class="memproto">
1370 <table class="memname">
1372 <td class="memname">uint32_t __STREXW </td>
1374 <td class="paramtype">uint32_t </td>
1375 <td class="paramname"><em>value</em>, </td>
1378 <td class="paramkey"></td>
1380 <td class="paramtype">volatile uint32_t * </td>
1381 <td class="paramname"><em>addr</em> </td>
1389 </div><div class="memdoc">
1391 <p>STR Exclusive (32 bit) [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
1392 <p>This function executed an exclusive STR command for 32 bit values [not for Cortex-M0, Cortex-M0+, or SC000].</p>
1393 <dl class="params"><dt>Parameters</dt><dd>
1394 <table class="params">
1395 <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr>
1396 <tr><td class="paramdir">[in]</td><td class="paramname">*addr</td><td>Pointer to location </td></tr>
1400 <dl class="section return"><dt>Returns</dt><dd>0 Function succeeded </dd>
1402 1 Function failed </dd></dl>
1406 <a id="ga2b5d93b8e461755b1072a03df3f1722e" name="ga2b5d93b8e461755b1072a03df3f1722e"></a>
1407 <h2 class="memtitle"><span class="permalink"><a href="#ga2b5d93b8e461755b1072a03df3f1722e">◆ </a></span>__STRHT()</h2>
1409 <div class="memitem">
1410 <div class="memproto">
1411 <table class="memname">
1413 <td class="memname">void __STRHT </td>
1415 <td class="paramtype">uint16_t </td>
1416 <td class="paramname"><em>value</em>, </td>
1419 <td class="paramkey"></td>
1421 <td class="paramtype">uint16_t </td>
1422 <td class="paramname"><em>ptr</em> </td>
1430 </div><div class="memdoc">
1432 <p>STRT Unprivileged (16 bit) </p>
1433 <p>This function executed an Unprivileged STRT command for 16 bit values.</p>
1434 <dl class="params"><dt>Parameters</dt><dd>
1435 <table class="params">
1436 <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr>
1437 <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to location </td></tr>
1444 <a id="ga625bc4ac0b1d50de9bcd13d9f050030e" name="ga625bc4ac0b1d50de9bcd13d9f050030e"></a>
1445 <h2 class="memtitle"><span class="permalink"><a href="#ga625bc4ac0b1d50de9bcd13d9f050030e">◆ </a></span>__STRT()</h2>
1447 <div class="memitem">
1448 <div class="memproto">
1449 <table class="memname">
1451 <td class="memname">void __STRT </td>
1453 <td class="paramtype">uint32_t </td>
1454 <td class="paramname"><em>value</em>, </td>
1457 <td class="paramkey"></td>
1459 <td class="paramtype">uint32_t </td>
1460 <td class="paramname"><em>ptr</em> </td>
1468 </div><div class="memdoc">
1470 <p>STRT Unprivileged (32 bit) </p>
1471 <p>This function executed an Unprivileged STRT command for 32 bit values.</p>
1472 <dl class="params"><dt>Parameters</dt><dd>
1473 <table class="params">
1474 <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr>
1475 <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to location </td></tr>
1482 <a id="ga9ba87371aebd17dd6244ed3458b29b5d" name="ga9ba87371aebd17dd6244ed3458b29b5d"></a>
1483 <h2 class="memtitle"><span class="permalink"><a href="#ga9ba87371aebd17dd6244ed3458b29b5d">◆ </a></span>__USAT()</h2>
1485 <div class="memitem">
1486 <div class="memproto">
1487 <table class="memname">
1489 <td class="memname">uint32_t __USAT </td>
1491 <td class="paramtype">int32_t </td>
1492 <td class="paramname"><em>value</em>, </td>
1495 <td class="paramkey"></td>
1497 <td class="paramtype">uint32_t </td>
1498 <td class="paramname"><em>sat</em> </td>
1506 </div><div class="memdoc">
1508 <p>Unsigned Saturate. </p>
1509 <p>This function saturates an unsigned value. The Q bit is set if saturation occurs [not for Cortex-M0, Cortex-M0+, or SC000].</p>
1510 <p>On Armv6-M (Cortex-M0, Cortex-M0+, and SC000) this function is not available as a core instruction instruction and thus __USAT is implemented in software.</p>
1511 <dl class="params"><dt>Parameters</dt><dd>
1512 <table class="params">
1513 <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to be saturated </td></tr>
1514 <tr><td class="paramdir">[in]</td><td class="paramname">sat</td><td>Bit position to saturate to [0..31] </td></tr>
1518 <dl class="section return"><dt>Returns</dt><dd>Saturated value </dd></dl>
1522 <a id="gad3efec76c3bfa2b8528ded530386c563" name="gad3efec76c3bfa2b8528ded530386c563"></a>
1523 <h2 class="memtitle"><span class="permalink"><a href="#gad3efec76c3bfa2b8528ded530386c563">◆ </a></span>__WFE()</h2>
1525 <div class="memitem">
1526 <div class="memproto">
1527 <table class="memname">
1529 <td class="memname">void __WFE </td>
1531 <td class="paramtype">void </td>
1532 <td class="paramname"></td><td>)</td>
1536 </div><div class="memdoc">
1538 <p>Wait For Event. </p>
1539 <p>Wait For Event is a hint instruction that permits the processor to enter a low-power state until an events occurs: </p><ul>
1540 <li>If the <b>event register is 0</b>, then WFE suspends execution until one of the following events occurs:<ul>
1541 <li>An exception, unless masked by the exception mask registers or the current priority level.</li>
1542 <li>An exception enters the Pending state, if SEVONPEND in the System Control Register is set.</li>
1543 <li>A Debug Entry request, if Debug is enabled.</li>
1544 <li>An event signaled by a peripheral or another processor in a multiprocessor system using the SEV instruction.</li>
1549 <li>If the <b>event register is 1</b>, then WFE clears it to 0 and returns immediately. </li>
1554 <a id="gaed91dfbf3d7d7b7fba8d912fcbeaad88" name="gaed91dfbf3d7d7b7fba8d912fcbeaad88"></a>
1555 <h2 class="memtitle"><span class="permalink"><a href="#gaed91dfbf3d7d7b7fba8d912fcbeaad88">◆ </a></span>__WFI()</h2>
1557 <div class="memitem">
1558 <div class="memproto">
1559 <table class="memname">
1561 <td class="memname">void __WFI </td>
1563 <td class="paramtype">void </td>
1564 <td class="paramname"></td><td>)</td>
1568 </div><div class="memdoc">
1570 <p>Wait For Interrupt. </p>
1571 <p>WFI is a hint instruction that suspends execution until one of the following events occurs:</p><ul>
1572 <li>A non-masked interrupt occurs and is taken.</li>
1573 <li>An interrupt masked by PRIMASK becomes pending.</li>
1574 <li>A Debug Entry request. </li>
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