begriffs open source - cmsis/blob - main/Core/group__mpu__defines.html

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 127   <div class="summary">
 128 <a href="#define-members">Macros</a>  </div>
 129   <div class="headertitle"><div class="title">Define values<div class="ingroups"><a class="el" href="group__mpu__functions.html">MPU Functions for Armv6-M/v7-M</a></div></div></div>
 130 </div><!--header-->
 131 <div class="contents">
 132
 133 <p>Define values for MPU region setup.
 134 <a href="#details">More...</a></p>
 135 <table class="memberdecls">
 136 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a>
 137 Macros</h2></td></tr>
 138 <tr class="memitem:ga71d41084e984be70a23cb640fd89d1e2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__defines.html#ga71d41084e984be70a23cb640fd89d1e2">ARM_MPU_ACCESS_xxx</a></td></tr>
 139 <tr class="memdesc:ga71d41084e984be70a23cb640fd89d1e2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Values for MPU region access attributes (in RASR field)  <br /></td></tr>
 140 <tr class="separator:ga71d41084e984be70a23cb640fd89d1e2"><td class="memSeparator" colspan="2">&#160;</td></tr>
 141 <tr class="memitem:gabc4788126d7798469cb862a08d3050cc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__defines.html#gabc4788126d7798469cb862a08d3050cc">ARM_MPU_AP_xxx</a></td></tr>
 142 <tr class="memdesc:gabc4788126d7798469cb862a08d3050cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Values for MPU region access permissions (in RASR field)  <br /></td></tr>
 143 <tr class="separator:gabc4788126d7798469cb862a08d3050cc"><td class="memSeparator" colspan="2">&#160;</td></tr>
 144 <tr class="memitem:gab23596306119e7831847bd9683de3934"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__defines.html#gab23596306119e7831847bd9683de3934">ARM_MPU_CACHEP_xxx</a></td></tr>
 145 <tr class="memdesc:gab23596306119e7831847bd9683de3934"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cache policy values for MPU region access attributes (in RASR field)  <br /></td></tr>
 146 <tr class="separator:gab23596306119e7831847bd9683de3934"><td class="memSeparator" colspan="2">&#160;</td></tr>
 147 <tr class="memitem:gadb0a92c0928c113120567e85ff1ba05c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__defines.html#gadb0a92c0928c113120567e85ff1ba05c">ARM_MPU_REGION_SIZE_xxx</a></td></tr>
 148 <tr class="memdesc:gadb0a92c0928c113120567e85ff1ba05c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Size values of a MPU region (in RASR field)  <br /></td></tr>
 149 <tr class="separator:gadb0a92c0928c113120567e85ff1ba05c"><td class="memSeparator" colspan="2">&#160;</td></tr>
 150 </table>
 151 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
 152 <p>Define values for MPU region setup. </p>
 153 <p><br  />
 154 </p>
 155 <p>The following define values are used with <a class="el" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a> to setup the <a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">RASR</a> value field in the MPU region.</p>
 156 <dl class="section see"><dt>See also</dt><dd><a class="el" href="structARM__MPU__Region__t.html" title="Setup information of a single MPU Region.">ARM_MPU_Region_t</a>, <a class="el" href="group__mpu__functions.html#ga16931f9ad84d7289e8218e169ae6db5d">ARM_MPU_SetRegion</a>, <a class="el" href="group__mpu__functions.html#ga042ba1a6a1a58795231459ac0410b809">ARM_MPU_SetRegionEx</a>. </dd></dl>
 157 <h2 class="groupheader">Macro Definition Documentation</h2>
 158 <a id="ga71d41084e984be70a23cb640fd89d1e2" name="ga71d41084e984be70a23cb640fd89d1e2"></a>
 159 <h2 class="memtitle"><span class="permalink"><a href="#ga71d41084e984be70a23cb640fd89d1e2">&#9670;&#160;</a></span>ARM_MPU_ACCESS_xxx</h2>
 160
 161 <div class="memitem">
 162 <div class="memproto">
 163       <table class="memname">
 164         <tr>
 165           <td class="memname">#define ARM_MPU_ACCESS_xxx</td>
 166         </tr>
 167       </table>
 168 </div><div class="memdoc">
 169
 170 <p>Values for MPU region access attributes (in RASR field) </p>
 171 <p>The following define values are used to compose the access attributes for an MPU region: </p><table class="markdownTable">
 172 <tr class="markdownTableHead">
 173 <th class="markdownTableHeadLeft">#define   </th><th class="markdownTableHeadLeft">TEX   </th><th class="markdownTableHeadLeft">Shareable   </th><th class="markdownTableHeadLeft">Cacheable   </th><th class="markdownTableHeadLeft">Bufferable   </th><th class="markdownTableHeadLeft">Description    </th></tr>
 174 <tr class="markdownTableRowOdd">
 175 <td class="markdownTableBodyLeft">ARM_MPU_ACCESS_ORDERED   </td><td class="markdownTableBodyLeft">000b   </td><td class="markdownTableBodyLeft">1   </td><td class="markdownTableBodyLeft">0   </td><td class="markdownTableBodyLeft">0   </td><td class="markdownTableBodyLeft">Strongly ordered memory    </td></tr>
 176 <tr class="markdownTableRowEven">
 177 <td class="markdownTableBodyLeft">ARM_MPU_ACCESS_DEVICE(S)   </td><td class="markdownTableBodyLeft">0s0b   </td><td class="markdownTableBodyLeft">S   </td><td class="markdownTableBodyLeft">0   </td><td class="markdownTableBodyLeft">S   </td><td class="markdownTableBodyLeft">Memory mapped peripheral device, shared (S=1) or non-shared (S=0)    </td></tr>
 178 <tr class="markdownTableRowOdd">
 179 <td class="markdownTableBodyLeft">ARM_MPU_ACCESS_NORMAL(O,I,S)   </td><td class="markdownTableBodyLeft">1BBb   </td><td class="markdownTableBodyLeft">S   </td><td class="markdownTableBodyLeft">A   </td><td class="markdownTableBodyLeft">A   </td><td class="markdownTableBodyLeft">Normal memory, with outer/inner cache policy (O/I=<a class="el" href="group__mpu__defines.html#gab23596306119e7831847bd9683de3934">ARM_MPU_CACHEP_xxx</a>, shared (S=1) or non-share (S=0)   </td></tr>
 180 </table>
 181
 182 </div>
 183 </div>
 184 <a id="gabc4788126d7798469cb862a08d3050cc" name="gabc4788126d7798469cb862a08d3050cc"></a>
 185 <h2 class="memtitle"><span class="permalink"><a href="#gabc4788126d7798469cb862a08d3050cc">&#9670;&#160;</a></span>ARM_MPU_AP_xxx</h2>
 186
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 189       <table class="memname">
 190         <tr>
 191           <td class="memname">#define ARM_MPU_AP_xxx</td>
 192         </tr>
 193       </table>
 194 </div><div class="memdoc">
 195
 196 <p>Values for MPU region access permissions (in RASR field) </p>
 197 <p>The following define values are used to compose the access permission for an MPU region: </p><table class="markdownTable">
 198 <tr class="markdownTableHead">
 199 <th class="markdownTableHeadLeft">#define   </th><th class="markdownTableHeadLeft">Value   </th><th class="markdownTableHeadLeft">Access permissions    </th></tr>
 200 <tr class="markdownTableRowOdd">
 201 <td class="markdownTableBodyLeft">ARM_MPU_AP_NONE   </td><td class="markdownTableBodyLeft">0x0U   </td><td class="markdownTableBodyLeft">None: any access generates a permission fault.    </td></tr>
 202 <tr class="markdownTableRowEven">
 203 <td class="markdownTableBodyLeft">ARM_MPU_AP_PRIV   </td><td class="markdownTableBodyLeft">0x1U   </td><td class="markdownTableBodyLeft">Privileged Read/Write: privileged access only; any unprivileged access generates a permission fault.    </td></tr>
 204 <tr class="markdownTableRowOdd">
 205 <td class="markdownTableBodyLeft">ARM_MPU_AP_URO   </td><td class="markdownTableBodyLeft">0x2U   </td><td class="markdownTableBodyLeft">Privileged Read/Write; Unprivileged Read-only: any unprivileged write generates a permission fault.    </td></tr>
 206 <tr class="markdownTableRowEven">
 207 <td class="markdownTableBodyLeft">ARM_MPU_AP_FULL   </td><td class="markdownTableBodyLeft">0x3U   </td><td class="markdownTableBodyLeft">Privileged Read/Write. Unprivileged Read/Write: full access, permission faults are never generated.    </td></tr>
 208 <tr class="markdownTableRowOdd">
 209 <td class="markdownTableBodyLeft">ARM_MPU_AP_PRO   </td><td class="markdownTableBodyLeft">0x5U   </td><td class="markdownTableBodyLeft">Privileged Read-only: any unprivileged access or privileged write generates a permission fault.    </td></tr>
 210 <tr class="markdownTableRowEven">
 211 <td class="markdownTableBodyLeft">ARM_MPU_AP_RO   </td><td class="markdownTableBodyLeft">0x6U   </td><td class="markdownTableBodyLeft">Privileged and Unprivileged Read-only: any write generates a permission fault.   </td></tr>
 212 </table>
 213
 214 </div>
 215 </div>
 216 <a id="gab23596306119e7831847bd9683de3934" name="gab23596306119e7831847bd9683de3934"></a>
 217 <h2 class="memtitle"><span class="permalink"><a href="#gab23596306119e7831847bd9683de3934">&#9670;&#160;</a></span>ARM_MPU_CACHEP_xxx</h2>
 218
 219 <div class="memitem">
 220 <div class="memproto">
 221       <table class="memname">
 222         <tr>
 223           <td class="memname">#define ARM_MPU_CACHEP_xxx</td>
 224         </tr>
 225       </table>
 226 </div><div class="memdoc">
 227
 228 <p>Cache policy values for MPU region access attributes (in RASR field) </p>
 229 <p>The following define values are used to compose the cacheability flags within the access attributes for an MPU region: </p><table class="markdownTable">
 230 <tr class="markdownTableHead">
 231 <th class="markdownTableHeadLeft">#define   </th><th class="markdownTableHeadLeft">Value   </th><th class="markdownTableHeadLeft">Cacheability policy    </th></tr>
 232 <tr class="markdownTableRowOdd">
 233 <td class="markdownTableBodyLeft">ARM_MPU_CACHEP_NOCACHE   </td><td class="markdownTableBodyLeft">00b   </td><td class="markdownTableBodyLeft">Non-cacheable    </td></tr>
 234 <tr class="markdownTableRowEven">
 235 <td class="markdownTableBodyLeft">ARM_MPU_CACHEP_WB_WRA   </td><td class="markdownTableBodyLeft">01b   </td><td class="markdownTableBodyLeft">Write-back, write and read allocate    </td></tr>
 236 <tr class="markdownTableRowOdd">
 237 <td class="markdownTableBodyLeft">ARM_MPU_CACHEP_WT_NWA   </td><td class="markdownTableBodyLeft">10b   </td><td class="markdownTableBodyLeft">Write-through, no write allocate    </td></tr>
 238 <tr class="markdownTableRowEven">
 239 <td class="markdownTableBodyLeft">ARM_MPU_CACHEP_WB_NWA   </td><td class="markdownTableBodyLeft">11b   </td><td class="markdownTableBodyLeft">Write-back, no write allocate   </td></tr>
 240 </table>
 241
 242 </div>
 243 </div>
 244 <a id="gadb0a92c0928c113120567e85ff1ba05c" name="gadb0a92c0928c113120567e85ff1ba05c"></a>
 245 <h2 class="memtitle"><span class="permalink"><a href="#gadb0a92c0928c113120567e85ff1ba05c">&#9670;&#160;</a></span>ARM_MPU_REGION_SIZE_xxx</h2>
 246
 247 <div class="memitem">
 248 <div class="memproto">
 249       <table class="memname">
 250         <tr>
 251           <td class="memname">#define ARM_MPU_REGION_SIZE_xxx</td>
 252         </tr>
 253       </table>
 254 </div><div class="memdoc">
 255
 256 <p>Size values of a MPU region (in RASR field) </p>
 257 <p>The following define values are used to compose the size information for an MPU region:</p>
 258 <table class="markdownTable">
 259 <tr class="markdownTableHead">
 260 <th class="markdownTableHeadLeft">#define   </th><th class="markdownTableHeadLeft">Value   </th><th class="markdownTableHeadLeft">Description    </th></tr>
 261 <tr class="markdownTableRowOdd">
 262 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_32B   </td><td class="markdownTableBodyLeft">0x04U   </td><td class="markdownTableBodyLeft">Region size 32 Bytes    </td></tr>
 263 <tr class="markdownTableRowEven">
 264 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_64B   </td><td class="markdownTableBodyLeft">0x05U   </td><td class="markdownTableBodyLeft">Region size 64 Bytes    </td></tr>
 265 <tr class="markdownTableRowOdd">
 266 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_128B   </td><td class="markdownTableBodyLeft">0x06U   </td><td class="markdownTableBodyLeft">Region size 128 Bytes    </td></tr>
 267 <tr class="markdownTableRowEven">
 268 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_256B   </td><td class="markdownTableBodyLeft">0x07U   </td><td class="markdownTableBodyLeft">Region size 256 Bytes    </td></tr>
 269 <tr class="markdownTableRowOdd">
 270 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_512B   </td><td class="markdownTableBodyLeft">0x08U   </td><td class="markdownTableBodyLeft">Region size 512 Bytes    </td></tr>
 271 <tr class="markdownTableRowEven">
 272 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_1KB   </td><td class="markdownTableBodyLeft">0x09U   </td><td class="markdownTableBodyLeft">Region size 1 KByte    </td></tr>
 273 <tr class="markdownTableRowOdd">
 274 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_2KB   </td><td class="markdownTableBodyLeft">0x0AU   </td><td class="markdownTableBodyLeft">Region size 2 KBytes    </td></tr>
 275 <tr class="markdownTableRowEven">
 276 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_4KB   </td><td class="markdownTableBodyLeft">0x0BU   </td><td class="markdownTableBodyLeft">Region size 4 KBytes    </td></tr>
 277 <tr class="markdownTableRowOdd">
 278 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_8KB   </td><td class="markdownTableBodyLeft">0x0CU   </td><td class="markdownTableBodyLeft">Region size 8 KBytes    </td></tr>
 279 <tr class="markdownTableRowEven">
 280 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_16KB   </td><td class="markdownTableBodyLeft">0x0DU   </td><td class="markdownTableBodyLeft">Region size 16 KBytes    </td></tr>
 281 <tr class="markdownTableRowOdd">
 282 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_32KB   </td><td class="markdownTableBodyLeft">0x0EU   </td><td class="markdownTableBodyLeft">Region size 32 KBytes    </td></tr>
 283 <tr class="markdownTableRowEven">
 284 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_64KB   </td><td class="markdownTableBodyLeft">0x0FU   </td><td class="markdownTableBodyLeft">Region size 64 KBytes    </td></tr>
 285 <tr class="markdownTableRowOdd">
 286 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_128KB   </td><td class="markdownTableBodyLeft">0x10U   </td><td class="markdownTableBodyLeft">Region size 128 KBytes    </td></tr>
 287 <tr class="markdownTableRowEven">
 288 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_256KB   </td><td class="markdownTableBodyLeft">0x11U   </td><td class="markdownTableBodyLeft">Region size 256 KBytes    </td></tr>
 289 <tr class="markdownTableRowOdd">
 290 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_512KB   </td><td class="markdownTableBodyLeft">0x12U   </td><td class="markdownTableBodyLeft">Region size 512 KBytes    </td></tr>
 291 <tr class="markdownTableRowEven">
 292 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_1MB   </td><td class="markdownTableBodyLeft">0x13U   </td><td class="markdownTableBodyLeft">Region size 1 MByte    </td></tr>
 293 <tr class="markdownTableRowOdd">
 294 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_2MB   </td><td class="markdownTableBodyLeft">0x14U   </td><td class="markdownTableBodyLeft">Region size 2 MBytes    </td></tr>
 295 <tr class="markdownTableRowEven">
 296 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_4MB   </td><td class="markdownTableBodyLeft">0x15U   </td><td class="markdownTableBodyLeft">Region size 4 MBytes    </td></tr>
 297 <tr class="markdownTableRowOdd">
 298 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_8MB   </td><td class="markdownTableBodyLeft">0x16U   </td><td class="markdownTableBodyLeft">Region size 8 MBytes    </td></tr>
 299 <tr class="markdownTableRowEven">
 300 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_16MB   </td><td class="markdownTableBodyLeft">0x17U   </td><td class="markdownTableBodyLeft">Region size 16 MBytes    </td></tr>
 301 <tr class="markdownTableRowOdd">
 302 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_32MB   </td><td class="markdownTableBodyLeft">0x18U   </td><td class="markdownTableBodyLeft">Region size 32 MBytes    </td></tr>
 303 <tr class="markdownTableRowEven">
 304 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_64MB   </td><td class="markdownTableBodyLeft">0x19U   </td><td class="markdownTableBodyLeft">Region size 64 MBytes    </td></tr>
 305 <tr class="markdownTableRowOdd">
 306 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_128MB   </td><td class="markdownTableBodyLeft">0x1AU   </td><td class="markdownTableBodyLeft">Region size 128 MBytes    </td></tr>
 307 <tr class="markdownTableRowEven">
 308 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_256MB   </td><td class="markdownTableBodyLeft">0x1BU   </td><td class="markdownTableBodyLeft">Region size 256 MBytes    </td></tr>
 309 <tr class="markdownTableRowOdd">
 310 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_512MB   </td><td class="markdownTableBodyLeft">0x1CU   </td><td class="markdownTableBodyLeft">Region size 512 MBytes    </td></tr>
 311 <tr class="markdownTableRowEven">
 312 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_1GB   </td><td class="markdownTableBodyLeft">0x1DU   </td><td class="markdownTableBodyLeft">Region size 1 GByte    </td></tr>
 313 <tr class="markdownTableRowOdd">
 314 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_2GB   </td><td class="markdownTableBodyLeft">0x1EU   </td><td class="markdownTableBodyLeft">Region size 2 GBytes    </td></tr>
 315 <tr class="markdownTableRowEven">
 316 <td class="markdownTableBodyLeft">ARM_MPU_REGION_SIZE_4GB   </td><td class="markdownTableBodyLeft">0x1FU   </td><td class="markdownTableBodyLeft">Region size 4 GBytes   </td></tr>
 317 </table>
 318
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