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  43    <div id="projectname">CMSIS-Core (Cortex-M)
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  52    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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 127   <div class="headertitle"><div class="title">Overview </div></div>
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 129 <div class="contents">
 130 <div class="textblock"><p><a class="anchor" id="mainpage"></a> The <b>CMSIS-Core (Cortex-M)</b> component implements the basic run-time system for Arm Cortex-M devices and gives the user access to the processor core and the device peripherals.</p>
 131 <p>In detail it defines:</p>
 132 <ul>
 133 <li><b>Hardware Abstraction Layer (HAL)</b> for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.</li>
 134 <li><b>System exception names</b> to interface to system exceptions without having compatibility issues.</li>
 135 <li><b>Methods to organize header files</b> that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.</li>
 136 <li><b>Methods for system initialization</b> to be used by each MCU vendor. For example, the standardized <code><a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2" title="Function to Initialize the system.">SystemInit()</a></code> function is essential for configuring the clock system of the device.</li>
 137 <li><b>Intrinsic functions</b> used to generate CPU instructions that are not supported by standard C functions.</li>
 138 <li>A variable to determine the <b>system clock frequency</b> which simplifies the setup the SysTick timer.</li>
 139 </ul>
 140 <p>The following sections provide details about the CMSIS-Core (Cortex-M):</p>
 141 <ul>
 142 <li><a class="el" href="using_pg.html">Using CMSIS-Core</a> explains the project setup and shows a simple program example. </li>
 143 <li><a class="el" href="using_TrustZone_pg.html">Using TrustZone&reg; for Armv8-M</a> describes how to use the security extensions available in the Armv8-M architecture. </li>
 144 <li><a class="el" href="cmsis_core_files.html">CMSIS-Core Files</a> describes the files of the CMSIS-Core (Cortex-M) in detail and explains how to adapt template files provided by Arm to silicon vendor devices.</li>
 145 <li><a class="el" href="coreMISRA_Exceptions_pg.html">MISRA-C Deviations</a> describes the violations to the MISRA standard.</li>
 146 <li><a href="modules.html"><b>API Reference</b></a> describes the features and functions of the <a class="el" href="device_h_pg.html">Device Header File &lt;Device.h&gt;</a> in detail.</li>
 147 <li><a href="annotated.html"><b>Data Structures</b></a> describe the data structures of the <a class="el" href="device_h_pg.html">Device Header File &lt;Device.h&gt;</a> in detail.</li>
 148 </ul>
 149 <h1><a class="anchor" id="autotoc_md0"></a>
 150 Access to CMSIS-Core (Cortex-M)</h1>
 151 <p>CMSIS-Core is actively maintained in the <a href="https://github.com/ARM-software/CMSIS_6"><b>CMSIS 6 GitHub repository</b></a> and released as part of the <a href="../General/cmsis_pack.html"><b>CMSIS Software Pack</b></a>.</p>
 152 <p>The following directories and files relevant to CMSIS-Core (Cortex-M) are present in the <b>ARM::CMSIS</b> Pack:</p>
 153 <table class="markdownTable">
 154 <tr class="markdownTableHead">
 155 <th class="markdownTableHeadLeft">Directory   </th><th class="markdownTableHeadLeft">Content    </th></tr>
 156 <tr class="markdownTableRowOdd">
 157 <td class="markdownTableBodyLeft">📂 CMSIS   </td><td class="markdownTableBodyLeft">CMSIS Base software components folder    </td></tr>
 158 <tr class="markdownTableRowEven">
 159 <td class="markdownTableBodyLeft">┣ 📂 Documentation/html/Core   </td><td class="markdownTableBodyLeft">A local copy of this CMSIS-Core (M) documentation    </td></tr>
 160 <tr class="markdownTableRowOdd">
 161 <td class="markdownTableBodyLeft">┗ 📂 Core   </td><td class="markdownTableBodyLeft">CMSIS-Core files    </td></tr>
 162 <tr class="markdownTableRowEven">
 163 <td class="markdownTableBodyLeft">&emsp;&#160; ┣ 📂 Include   </td><td class="markdownTableBodyLeft"><a class="el" href="cmsis_core_files.html#cmsis_processor_files">CMSIS-Core Processor Files</a>.    </td></tr>
 164 <tr class="markdownTableRowOdd">
 165 <td class="markdownTableBodyLeft">&emsp;&emsp;&#160; ┗ 📂 m-profile   </td><td class="markdownTableBodyLeft">Header files specific for Arm M-Profile.<br  />
 166  See <a class="el" href="cmsis_core_files.html#cmsis_compiler_files">CMSIS-Core Compiler Files</a> and <a class="el" href="cmsis_core_files.html#cmsis_feature_files">CMSIS-Core Architecture Feature Files</a>.    </td></tr>
 167 <tr class="markdownTableRowEven">
 168 <td class="markdownTableBodyLeft">&emsp;&#160; ┗ 📂 Template   </td><td class="markdownTableBodyLeft"><a class="el" href="cmsis_device_files.html#cmsis_template_files">Device Template Files</a>   </td></tr>
 169 </table>
 170 <h1><a class="anchor" id="ref_v6-v8M"></a>
 171 Processor Support</h1>
 172 <p>CMSIS-Core supports the complete range of <a href="https://www.arm.com/products/silicon-ip-cpu?families=cortex-m&amp;showall=true">Cortex-M processors</a>.</p>
 173 <p><a class="anchor" id="ref_man_sec"></a><b>Cortex-M Generic User Guides</b></p>
 174 <p>Following Cortex-M Device Generic User Guides contain the programmers model and detailed information about the core peripherals:</p>
 175 <ul>
 176 <li><a href="https://developer.arm.com/documentation/dui0497/latest/">Cortex-M0 Devices Generic User Guide (Armv6-M architecture)</a></li>
 177 <li><a href="https://developer.arm.com/documentation/dui0662/latest/">Cortex-M0+ Devices Generic User Guide (Armv6-M architecture)</a></li>
 178 <li><a href="https://developer.arm.com/documentation/dui0552/latest/">Cortex-M3 Devices Generic User Guide (Armv7-M architecture)</a></li>
 179 <li><a href="https://developer.arm.com/documentation/dui0553/latest/">Cortex-M4 Devices Generic User Guide (Armv7-M architecture)</a></li>
 180 <li><a href="https://developer.arm.com/documentation/dui0646/latest/">Cortex-M7 Devices Generic User Guide (Armv7-M architecture)</a></li>
 181 <li><a href="https://developer.arm.com/documentation/dui1095/latest/">Cortex-M23 Devices Generic User Guide (Armv8-M architecture)</a></li>
 182 <li><a href="https://developer.arm.com/documentation/100235/latest/">Cortex-M33 Devices Generic User Guide (Armv8-M architecture)</a></li>
 183 <li><a href="https://developer.arm.com/documentation/102776/latest/">Cortex-M52 Devices Generic User Guide (Armv8.1-M architecture)</a></li>
 184 <li><a href="https://developer.arm.com/documentation/101273/latest/">Cortex-M55 Devices Generic User Guide (Armv8.1-M architecture)</a></li>
 185 <li><a href="https://developer.arm.com/documentation/101928/latest/">Cortex-M85 Devices Generic User Guide (Armv8.1-M architecture)</a></li>
 186 </ul>
 187 <p>CMSIS-Core also supports the following Cortex-M processor variants:</p>
 188 <ul>
 189 <li><a href="https://developer.arm.com/Processors/Cortex-M1">Cortex-M1</a> is a processor designed specifically for implementation in FPGAs (Armv6-M architecture).</li>
 190 <li><a href="https://developer.arm.com/Processors/SecurCore%20SC000">SecurCore SC000</a> is designed specifically for smartcard and security applications (Armv6-M architecture).</li>
 191 <li><a href="https://developer.arm.com/Processors/SecurCore%20SC300">SecurCore SC300</a> is designed specifically for smartcard and security applications (Armv7-M architecture).</li>
 192 <li><a href="https://developer.arm.com/Processors/Cortex-M35P">Cortex-M35P</a> is a tamper resistant Cortex-M processor with optional software isolation using TrustZone for Armv8-M.</li>
 193 <li><a href="https://www.armchina.com/mountain?infoId=160">STAR-MC1</a> is a variant of Armv8-M with TrustZone designed by Arm China.</li>
 194 </ul>
 195 <p><a class="anchor" id="ARMv8M"></a><b>Armv8-M and Armv8.1-M Architecture</b></p>
 196 <p>Armv8-M introduces two profiles <b>baseline</b> (for power and area constrained applications) and <b>mainline</b> (full-featured with optional SIMD, floating-point, and co-processor extensions). Both Armv8-M profiles and Armv8.1-M are supported by CMSIS.</p>
 197 <p>The Armv8-M architecture is described in the <a href="https://developer.arm.com/documentation/ddi0553/latest/">Armv8-M Architecture Reference Manual</a>.</p>
 198 <p>The Armv8.1-M architecture further extends Armv8-M with Helium (the so called M-Profile Vector Extension (MVE)), as well as further instruction set and debug extensions.</p>
 199 <p>More information about Armv8.1-M architecture is available under <a href="https://developer.arm.com/Architectures/Helium">Arm Helium technology</a>.</p>
 200 <h1><a class="anchor" id="tested_tools_sec"></a>
 201 Tested and Verified Toolchains</h1>
 202 <p>The <a class="el" href="cmsis_core_files.html">CMSIS-Core Files</a> delivered with this CMSIS-Core release have been tested and verified with the following toolchains:</p>
 203 <ul>
 204 <li>Arm Compiler for Embedded 6.22</li>
 205 <li>IAR C/C++ Compiler for Arm 9.40</li>
 206 <li>GNU Arm Embedded Toolchain 13.2.1</li>
 207 <li>LLVM/Clang 18.3.1 </li>
 208 </ul>
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